VLSI - Automation...

Install gdata google python module in Ubuntu

noreply@blogger.com (Unknown) — Sat, 13 Feb 2016 09:47:00 +0000

Install gdata google python module in Ubuntu

python-gdata deb

After a long time am publishing the new post…

Am started a new mini project which upload a photo to picassa.google.com using python code. Am searching python API on the internet. I found a code. But when i run the code it shows error like 'did not find "gdata" module'. So am searching how to install python-gdata module in ubuntu. After my searching these term i found the solution simply…

First of all what is python-gdata?
python-gdata – Google Data Python client library

Distribution: Ubuntu 12.04.2 LTS

Repository: Ubuntu Universe i386

Package name: python-gdata

Package version: 2.0.14-2

Package architecture: all

Package type: deb

Binary package: python-gdata_2.0.14-2_all.deb

Source package: python-gdata

Installed size: 2,93 MB

Download size: 447,12 KB
The GData (Google data) APIs provide a simple protocol for reading and writing data on the web.
Each of the following Google services provides a Google data API:
* Base
* Blogger
* Calendar
* Code Search
* Contacts
* Document List
* Google Apps Provisioning
* Notebook
* Picasa Web Albums
* Spreadsheets
* YouTube
The Google data Python client library provides a library and source
code that make it easy to access data through Google data APIs.

Install how to???

1. First we need to update the linux index, so that run the following code first:

# sudo apt-get update

When i run the above code it will update the repositories and index.
2. Install python-gdata deb package by simply running these code:

# sudo apt-get install python-gdata

This command will download the python-gdata module succesfully.

VLSI : What is finfet?

noreply@blogger.com (Unknown) — Sun, 10 Jan 2016 13:14:00 +0000

FinFET

FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or "3D" transistor used in the design of modern processors. As in earlier, planar designs, it is built on an SOI (silicon on insulator) substrate. However, FinFET designs also use a conducting channel that rises above the level of the insulator, creating a thin silicon structure, shaped like a fin, which is called a gate electrode. This fin-shaped electrode allows multiple gates to operate on a single transistor.

This type of multi-gate process extends Moore's law, allowing semiconductor manufacturers to create CPUs and memory modules that are smaller, perform faster, and consume less energy. Intel began releasing FinFET CPU technology in 2012 with its 22-nm Ivy Bridge processors.

source: http://www.computerhope.com/jargon/f/finfet.htm

Physical Design Flow I:Netlist In & Floorplanning

noreply@blogger.com (Unknown) — Sun, 18 Oct 2015 10:30:00 +0000

Netlist In
The first stage in physical design flow is reading in the netlist and the constraints to your tool of choice. Let us see what kinds of files we are dealing with here. I have used both Cadence and Synopsys tools extensively, so those are what I will base my examples on. However, every tool uses pretty much the same flow and even the same format files.

Gate Level Netlist
Once you choose a process and a library, a synthesis tool will translate your RTL into a collection of interconnected logic gates that define the logic. The most common format is verilog. I had seen some VHDL and EDIF designs when I started my career, but I have only really worked with Verilog files.
Standard Cell Library
In digital design, you have a ready made standard cell library which will be used for synthesis and subsequent layouts. Your netlist will have instantiation of these cells. For digital layout, you need layout and timing abstracts for these cells.
- Layout Model – An abstract model of the standard cell layout is used instead of the complete layout. This will have PINs defined, so as to facilitate automatic routing by the tool as per your netlist. Synopsys tool ICCompiler use “FRAM” views as a PnR abstract. FRAM view is a cell view that has only the PINs and metal and via blockages defined. This makes sure that the interconnection between the PINs can be routed automatically and that the routing tool will not route over existing metal/via areas thus ruling out any shorts. Cadence EDI tools use LEF views, which again has only the PINs and Obstructions (blockages) defined. LEF is an ascii file, so go ahead and have a read.
- Timing Model – Tools also need a timing model in the form of a .lib file. ICC takes a .db file, which is generated from a .lib. This liberty format file will have timing numbers for the various arcs in a cell, generally in a look up model. Please note that .libs may also have cell power information.
Technology File
The rules pertaining to the process you have selected should also be given to the PnR tool. This includes metal widths, spacing, via definitions etc. ICC takes a milkyway techfile format, while EDI tools take a technology LEF file.
Timing Constraints
SDC files define the timing constraints of your design. You will have the clock definitions, false paths, any input and output delay constraints etc.

These inputs once read in, will get you started with your database.

VEDA IIT: Recruitment test 2015: Trainee in all specializations of VLSI(LD/PD/AD/CL)

noreply@blogger.com (Unknown) — Sun, 24 May 2015 14:22:00 +0000

All India Recruitment test for Engineer Trainee in all specializations of VLSI(LD/PD/AD/CL), Embedded System Design and User Experience(UX) are announced.
Apply by June 01, 2015 (on line at www.vedaiit.org)
Recruitment test on June 06, 2015

application:

http://vedaiit.org/application/VedaIITAutomation_2/codevalidate.php

http://vedaiit.org/#course_module

perl tutor : How to modify your @INC include path - What to do when Perl modules aren't in their normal locations

noreply@blogger.com (Unknown) — Sun, 18 Jan 2015 09:09:00 +0000

The final thing to remember is that if this message comes back with an error, it doesn't exactly mean that this module isn't installed on the current system, it just means that the module isn't in your @INC include path.

perl tutor : How to modify your @INC include path - What to do when Perl modules aren't in their normal locations

When you have root access to a Unix server, it's pretty easy to install Perl modules in their proper locations, and forget about them. But if you don't have root access and you need to install your Perl modules in non-standard directories, how will you get your programs to find your modules?

In this article we'll demonstrate how to use the use lib statement in your Perl programs to include the non-standard location of your Perl modules into Perl's @INC search list.

Perl modules - use and require examples (with root access)

If you're lucky enough to have root access to your Unix server, it's easy to install Perl modules into their default locations. Once they're installed in their default locations, you just include the modules into your Perl/CGI programs with a "use" or "require" statement like this:

use "LWP.pm";

or this:

require "LWP.pm";

Include Perl modules when you don't have root access ...

If you don't have access to the root password on your Unix server, or you're not allowed to add Perl modules to the Perl installation directories, what can you do? (Note: This problem usually arises when you're renting web space on somebody else's web server, and they don't have the module installed that you need -- a fairly common occurrence.)

In cases like this, the thing to do is to install the Perl module yourself into a directory where you do have write permission. For instance, if my name is George, and my HOME directory is /home/george, I might install my Perl modules into a directory named /home/george/modules. If you follow the installation instructions for Perl modules, this is very easy to do.

Assuming that goes okay and you now have the module installed in /home/george/modules, how do you get your Perl/CGI programs to find the module? Fortunately, that too is easy. All you have to do is modify your Perl/CGI program slightly to tell the program where else it should look for modules.

For instance, if the people that host my web site didn't have the CGI.pm module available, I'd install it in /home/george/modules. Then I'd modify my Perl/CGI program to find the module by adding this line near the top of my Perl programs:

use lib '/home/george/modules';

This simple line of code tells your Perl program to add this directory to it's @INC search directory. @INC contains the list of directories Perl searches when looking for modules. The use lib command is the easiest way I know to modify @INC.

Tech Buzz: To Create Any New File showing in right click menu in Linux

noreply@blogger.com (Unknown) — Tue, 14 Jan 2014 03:18:00 +0000

This should enable scripts when right clicking on a folder or a file.

Create New File not showing in right click menu
open gedit with sudo gedit
when the blank document is open in gedit press "file" then "save as"
store the blank file in the /home/username/Template folder, save it as "Empty File"
Now Reboot to reload nautilus
This should enable "New Document" > "Empty file" when right clicking in folder/on desktop

I am trying to get scripts showing on desktop right click, if i manage i will post an update.
I Hope my answer helped you out

option show up on right clicking in the desktop in Ubuntu ... How to make it appear?

Tech Update : All about Haswell - microarchitecture- the 22nm process

noreply@blogger.com (Unknown) — Tue, 24 Sep 2013 17:44:00 +0000

Haswell is the codename for a processor microarchitecture developed by
Intel as the successor to the Ivy Bridge architecture. It uses the 22
nm process. Intel officially announced CPUs with this
microarchitecture on June 4, 2013 at Computex Taipei 2013. With
Haswell, Intel introduced a low-power processor designed for
convertible or 'hybrid' Ultrabooks, having the Y suffix. Intel
demonstrated a working Haswell chip at the 2011 Intel Developer Forum.

Courtesy: http://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29

VEDA IIT Recruitment Test - 5-Oct-2013

noreply@blogger.com (Unknown) — Sat, 21 Sep 2013 05:18:00 +0000

	Recruitment Test for VLSI Physical Design/Logical Design and Embedded System Design

Entrance Test: 5-Oct-2013

Last Date for receiving applications: 1-Oct-2013

*DD for Rs. 300/- should be drawn in favor of VEDA Institute of Information Technology Pvt. Ltd. before applying

Click here to apply

Modal papers please go through vedaiit.blogspot.com

Graphic Data System II

noreply@blogger.com (Unknown) — Mon, 17 Dec 2012 09:13:00 +0000

GDS II is a database file format which is the de facto industry
standard for data exchange of integrated circuit or IC layout artwork.
It is a binary file format representing planar geometric shapes, text
labels, and other information about the layout in hierarchical form.
The data can be used to reconstruct all or part of the artwork to be
used in sharing layouts, transferring artwork between different tools,
or creating photo masks. Initially, GDS II was designed as a format
used to control integrated circuit photo mask plotting. Despite its
limited set of features and low data density, it became the industry
conventional format for transfer of IC layout data between design
tools of different vendors, all of which operated with proprietary
data formats. It was originally developed by Calma for its layout
design software, "Graphic Data System" ("GDS") and "GDS II". Now the
format is owned by Cadence Design Systems.

GDS II files are usually the final output product of the IC design
cycle and are given to IC foundries for IC fabrication. GDS II files
were originally placed on magnetic tapes. This moment was fittingly
called tape out though it is not the original root of the term.
Objects contained in a GDS II file are grouped by assigning numeric
attributes to them including "layer number", "datatype" or "texttype".
While these attributes were designed to correspond to the "layers of
material" used in manufacturing an integrated circuit, their meaning
rapidly became more abstract to reflect the way that the physical
layout is designed. As of October 2004, many EDA software vendors have
begun to support a new format, OASIS, which may replace GDS I

source:http://www.layouteditor.net/wiki/GDSII

VEDA IIT Recruitment Test - 26th May 2012

noreply@blogger.com (Unknown) — Thu, 03 May 2012 18:27:00 +0000

'VEDA IIT Recruitment Test' is scheduled on 26^th May 2012 . Apply online at www.vedaiit.com before 23^rd May 2012

VEDA IIT Recruitment Test Details:

Exam Date : *Entrance Test will be conducted on 26^th May 2012

Exam Time : 10:00 A.M

Exam Duration : 3 Hours

Last Date to Apply: DD for Rs.300/- should be drawn in favor of VEDA Institute of Information Technology Pvt. Ltd., Hyderabad should reach VEDA IIT by 23^rd May 2012

How to Apply : Please visit www.vedaiit.com and click on 'Apply for Jobs'

Venue : VEDA IIT, Plot No. 90,

Annapurna Studios/ VEDA Lane,

Road No 2, Banjara Hills,

Hyderabad

Phone: + 91 40 3061 5555

JNTUH ,hyderabad kukatpalli.

Syllabus : 1. Digital Design & Micro Processors

2. C Programming

3. Aptitude

http://www.vedaiit.com/applicationformwinter.htm

Recruitment of Engineer Trainees in VLSI Design (Logic/Physical) and Embedded System Design at VEDAIIT for March 2012

noreply@blogger.com (Unknown) — Sun, 04 Mar 2012 03:57:00 +0000

Application for Recruitment of Engineer Trainees in VLSI Design (Logic/Physical) and Embedded System Design

please click here for more information and for apply online

http://www.vedaiit.com/applicationformrt.htm

DD for Rs.300/- should be drawn in favor of VEDA Institute of Information Technology Pvt. Ltd., Hyderabad should reach VEDA IIT by 15th Mar 2012

*Short listed candidates will be called for a written test

*Hall Tickets will be dispatched from 14th Mar 2012 on wards

*Entrance Test will be conducted on 17th Mar 2012

*DD's should be sent to the following address.

VEDA IIT, Road. No:2,

Annapurna Studio Lane

Banjara Hills, Hyderabad –34

*Write your Name, Program applying for, Registration Number, address and Contact Number on the reverse of DD.

for syllabus click here....

Test Pattern & Syllabus

http://www.vedaiit.com/testpattern_syllabus.htm

VLSI Terminology: Definition of process technology

noreply@blogger.com (Unknown) — Mon, 23 Jan 2012 17:24:00 +0000

Definition of: process technology

With regard to digital integrated circuits, process technology refers to the particular method used to make silicon chips. The driving force behind the manufacture of integrated circuits is miniaturization, and process technology boils down to the size of the finished transistor and other components. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they require and the cooler the chip runs (given equal numbers of transistors).

Measured in Nanometers
The size of the features (the elements that make up the structures on a chip) used to be measured in micrometers. A 3 µm process technology, also called a "technology node" and "process node," referred to a silicon chip with features three micrometers in size. Today, features are measured in nanometers. A 45 nm process technology refers to features 45 nm or 0.45 µm in size.

Elements Measured
Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

An Example of Progress
Consider that the process technology of the first 486 chip in 1989 was one micron (1,000 nanometers). By 2003, the state-of-the-art decreased to 90 nm ("90 nano"). In 15 years, feature sizes were reduced by slightly less than one millionth of a meter. What may seem like a minuscule, microscopic change to the casual observer took thousands of man years and billions of dollars worth of research and development. Note the huge variance in semiconductor feature sizes starting in the 1950s (see chart below).

Chips Are Nanotechnology
Intel introduced 45 nm processors in 2008. To understand how tiny 45 nanometers is, it would take two thousand 45 nm objects laid side-by-side to equal the thickness of one human hair.

In 2010, 32 nm chips were introduced, and feature sizes as low as 11 nm are expected in the future. For some time, chips have been in the realm of nanotechnology, which refers to elements 100 nanometers and smaller.

Definition of: feature size

noreply@blogger.com (Unknown) — Mon, 23 Jan 2012 17:15:00 +0000

Definition of: feature size

The size of the elements on a chip, which is designated by the "DRAM half pitch." The smallest feature size is generally smaller than the feature size for a technology generation (technology node). For example, the 180 nm technology generation will have gate lengths smaller than 180 nm.

Definition of: DRAM half pitch

The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch had been reduced to 130 nm (.13 micron). By 2006, it had shrunk to 65 nm (.065 micron).

source :http://www.pcmag.com/encyclopedia_term/0,2542,t=feature+size&i=43075,00.asp

Integrated circuits: Generations

noreply@blogger.com (Unknown) — Mon, 23 Jan 2012 17:04:00 +0000

SSI, MSI and LSI

The first integrated circuits contained only a few transistors. Called "small-scale integration" (SSI), digital circuits containing transistors numbering in the tens provided a few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips TAA320 had as few as two transistors. The term Large Scale Integration was first used by IBM scientist Rolf Landauer when describing the theoretical concept[citation needed], from there came the terms for SSI, MSI, VLSI, and ULSI.

VLSI

The final step in the development process, starting in the 1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009.

Multiple developments were required to achieve this increased density. Manufacturers moved to smaller design rules and cleaner fabrication facilities, so that they could make chips with more transistors and maintain adequate yield. The path of process improvements was summarized by the International Technology Roadmap for Semiconductors (ITRS). Design tools improved enough to make it practical to finish these designs in a reasonable time. The more energy efficient CMOS replaced NMOS and PMOS, avoiding a prohibitive increase in power consumption. Better texts such as the landmark textbook by Mead and Conway helped schools educate more designers, among other factors.

In 1986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor mark in 2005

ULSI, WSI, SOC and 3D-IC

To reflect further growth of the complexity, the term ULSI that stands for "ultra-large-scale integration" was proposed for chips of complexity of more than 1 million transistors.

Wafer-scale integration (WSI) is a system of building very-large integrated circuits that uses an entire silicon wafer to produce a single "super-chip". Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers. The name is taken from the term Very-Large-Scale Integration, the current state of the art when WSI was being developed.

A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components needed for a computer or other system are included on a single chip. The design of such a device can be complex and costly, and building disparate components on a single piece of silicon may compromise the efficiency of some elements. However, these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budget: because signals among the components are kept on-die, much less power is required (see Packaging).

A three-dimensional integrated circuit (3D-IC) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit. Communication between layers uses on-die signaling, so power consumption is much lower than in equivalent separate circuits. Judicious use of short vertical wires can substantially reduce overall wire length for faster operation.

AWK :The for statement

noreply@blogger.com (Unknown) — Sun, 08 Jan 2012 19:24:00 +0000

The `for` Statement

The for statement makes it more convenient to count iterations of a loop. The general form of the for statement looks like this:

for (initialization; condition; increment)   body

This statement starts by executing initialization. Then, as long as condition is true, it repeatedly executes body and then increment. Typically initialization sets a variable to either zero or one, increment adds 1 to it, and condition compares it against the desired number of iterations.

Here is an example of a for statement:

awk '{ for (i = 1; i <= 3; i++)           print $i }'

This prints the first three fields of each input record, one field per line.

In the for statement, body stands for any statement, but initialization, condition and increment are just expressions. You cannot set more than one variable in the initialization part unless you use a multiple assignment statement such as x = y = 0, which is possible only if all the initial values are equal. (But you can initialize additional variables by writing their assignments as separate statements preceding the forloop.)

awk '{ for (i =j= 1; i <= 3; i++)

{if (j <2){

j++;

print $i

}

The same is true of the increment part; to increment additional variables, you must write separate statements at the end of the loop. The C compound expression, using C's comma operator, would be useful in this context, but it is not supported in awk.

Most often, increment is an increment expression, as in the example above. But this is not required; it can be any expression whatever. For example, this statement prints all the powers of 2 between 1 and 100:

for (i = 1; i <= 100; i *= 2)   print i

Any of the three expressions in the parentheses following the for may be omitted if there is nothing to be done there. Thus, `for (;x > 0;)' is equivalent to `while (x > 0)'. If the condition is omitted, it is treated as true, effectively yielding an infinite loop (i.e., a loop that will never terminate).

In most cases, a for loop is an abbreviation for a while loop, as shown here:

initialization while (condition) {   body   increment }

source:http://www.staff.science.uu.nl/~oostr102/docs/nawk/nawk_toc.html#TOC77

Definition of Metastability...

noreply@blogger.com (Unknown) — Mon, 02 Jan 2012 18:10:00 +0000

source:
		Definition of Metastability :
		Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. In the figure below Tsu is the setup time and Th is the hold time. Whenever the input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs.



		When a flip-flop is in metastable state, its output oscillate between '0' and '1' as shown in the figure below (here the flip-flop output settles down to '0') . How long it takes to settle down, depends on the technology of the flip-flop.



		If we look deep inside of the flip-flop we see that the quasi-stable state is reached when the flip-flop setup and hold times are violated. Assuming the use of a positive edge triggered "D" type flip-flop, when the rising edge of the flip-flop clock occurs at a point in time when the D input to the flip-flop is causing its master latch to transition, the flip-flop is highly likely to end up in a quasi-stable state. This rising clock causes the master latch to try to capture its current value while the slave latch is opened allowing the Q output to follow the "latched" value of the master. The most perfectly "caught" quasi-stable state (on the very top of the hill) results in the longest time required for the flip-flop to resolve itself to one of the stable states.



		How long does it stay in this state?
		The relative stability of states shown in the figure above shows that the logic 0 and logic 1 states (being at the base of the hill) are much more stable than the somewhat stable state at the top of the hill. In theory, a flip-flop in this quasi-stable hilltop state could remain there indefinitely but in reality it won't. Just as the slightest air current would eventually cause a ball on the illustrated hill to roll down one side or the other, thermal and induced noise will jostle the state of the flip-flop causing it to move from the quasi-stable state into either the logic 0 or logic 1 state.



		What are the cases in which metastability occurs?
		As we have seen that whenever setup and hold violation time occurs, metastability occurs, so we have to see when signals violate this timing requirement:

		When the input signal is an asynchronous signal. When the clock skew/slew is too much (rise and fall time are more than the tolerable values). When interfacing two domains operating at two different frequencies or at the same frequency but with different phase. When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)

		What is MTBF?
		MTBF is Mean time between failure, what does that mean? Well MTBF gives us information on how often a particular element will fail or in other words, it gives the average time interval between two successive failures. The figure below shows a typical MTBF of a flip-flop and also it gives the MTBF equation. I am not looking here to derive MTBF equation :-)
















		Normally,

		We can use a metastable hardened flip-flop Cascade two or three D-Flip-Flops (two or three stages synchronizer).

		METASTABILITY REFERENCES

		http://www-s.ti.com/sc/psheets/sdya006/sdya006.pdf Thomas J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Vol. C-32. No. 12, December 1983, pp.1207-1209. Lindsay Kleeman and Antonio Cantoni, "On the Unavoidability of Metastable Behavior in Digital Systems", IEEE Transactions on Computers, Vol. C-36. No. 1, January 1987, pp.109-112. Lindsay Kleeman and Antonio Cantoni, "Can Redundancy and Masking Improve the Performance of Synchronizers?", IEEE Transactions on Computers, Vol. C-35, No. 7, July 1986, pp.643-646. Cypress Semiconductor, "Are Your PLDs Metastable?, Fax ID: 6403, May 1992, Revised March 6,1997. http://www.cypress.com/pld/pldappnotes.html#pldmeta http://www.xilinx.com/apps/xapp.htm M. Valencia, M. J. Bellido, J. L. Huertas, A. J. Acosta, and S. Sanchez-Solano, "Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Transactions on Computers, 44(12):1456-1461, December 1995

Setup and hold times of an flip-flop

noreply@blogger.com (Unknown) — Mon, 02 Jan 2012 17:58:00 +0000

Setup and hold times

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.

Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.

To summarize: Setup time -> Clock flank -> Hold time.

The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time (t_su) and the hold time (t_h) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.

Propagation delay

Another important timing value for a flip-flop (F/F) is the clock-to-output delay (common symbol in data sheets: t_CO) or propagation delay (t_P), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (t_PHL) is sometimes different from the time for a low-to-high transition (t_PLH).

When cascading F/Fs which share the same clock (as in a shift register), it is important to ensure that the t_CO of a preceding F/F is longer than the hold time (t_h) of the following flip-flop, so data present at the input of the succeeding F/F is properly "shifted in" following the active edge of the clock. This relationship between t_CO and t_h is normally guaranteed if the F/Fs are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum t_su + t_h.

source:http://en.wikipedia.org/wiki/Flip-flop_(electronics)

SETUP TIME & HOLD TIME EQUATIONS for Flip Flop

noreply@blogger.com (Unknown) — Sun, 01 Jan 2012 17:17:00 +0000

SETUP TIME & HOLD TIME EQUATIONS

This section derives the equation for valid input window for a flip-flop to avoid set up and hold time violations.

Assume tskew = 0, and FF2 is processing IN1, and FF1 is processing IN2,

IN2 should not reach FF2 before thold of FF2 to avoid Meta stability at FF2,

Hold time -> tCQ (FF1) + tcomb > thold (FF2)--- Eq.1

At the same time, IN2 should reach FF2 before setup time of FF2,

Setup time -> tCQ (FF1) + tcomb < tclk - tsetup (FF2)--- Eq.2

If tskew != 0, equations will be modified in the following way,

Hold time -> tCQ (FF1) + tcomb > thold (FF2) + tskew --- Eq.3

Setup time -> tCQ (FF1) + tcomb < tclk + tskew - tsetup (FF2) --- Eq.4

In Eq.3, skew is added to hold time, becomes effective hold time. In Eq.4, skew is added to clock period, becomes effective period or you can think, effective set up time is decreased by skew. This discussion is just for the purpose of our understanding. From equations, positive skew is good for setup time and bad for hold time.

Transient response of a simple RC circuit

noreply@blogger.com (Unknown) — Thu, 15 Dec 2011 17:14:00 +0000

Transient response of a simple RC circuit

The switch is closed at time=0. After the switch is closed, the
voltage on the capacitor changes from its initial value to a value
that aproaches Vb in an exponential manner.

The following equations describe the voltage change with regard to time.

Vc(t) = Vb + (Vc(0) - Vb)e^(-t/T)
T = RC
Where:

C Is the value of the capacitor in farads.
e is 2.718 (you knew that, right? :-) )
R Is the value of the resistor in ohms.
t Is the time in seconds after the switch is closed.
T Is actually Tau, but that's not in ASCII
It is the time constant, the product of R and C
Vb Is the voltage supplied by the voltage source.
In this case, the battery symbol represents an ideal
voltage source.
Vc(t) Is the voltage across the capacitor at the specified time.

The GDSII Stream Format

noreply@blogger.com (Unknown) — Thu, 15 Dec 2011 17:11:00 +0000

> GDS = Graphic Database System

Initially, GDSII was designed as a format used to control integrated
circuit photomask plotting. Despite its limited set of features and
low data density, it became the industry conventional format for
transfer of IC layout data between design tools of different vendors,
all of which operated with proprietary data formats.
It was originally developed by Calma for its layout design software,
"Graphic Data System" ("GDS") and "GDSII". Now the format is owned by
Cadence Design Systems.
GDS II files are usually the final output product of the IC design
cycle and are given to IC foundries for IC fabrication. GDS II files
were originally placed on magnetic tapes. This moment was fittingly
called tape out though it is not the original root of the term.
Objects contained in a GDSII file are grouped by assigning numeric
attributes to them including a "layer number", "datatype" or
"texttype". While these attributes were designed to correspond to the
"layers of material" used in manufacturing an integrated circuit,
their meaning rapidly became more abstract to reflect the way that the
physical layout is designed.
As of October 2004, many EDA software vendors have begun to support a
new format, OASIS, which may replace GDSII.

source:http://en.wikipedia.org/wiki/GDSII

9 Powerful Awk Built-in Functions for Numeric

noreply@blogger.com (Unknown) — Fri, 09 Dec 2011 16:48:00 +0000

9 Powerful Awk Built-in Functions for Numeric

awk also has lot of built-in functions for numeric, string, input, and ouput operations. Awk has the following three types of high level built-in function categories.

Built-in functions for numeric operations
Built-in functions for String operations
Built-in functions for Input Output operations

In this article, we will review awk Numeric built-in functions.

1. Awk int(n) Function

int() function gives you the integer part of the given argument. This produces the lowest integer part of given n. n is any number with or with out floating point. If you give the whole number as an argument, this function returns the same. For floating point number, it truncates.

Example

 $ awk 'BEGIN{ print int(3.534); print int(4); print int(-5.223); print int(-5); }' 3 4 -5 -5

2. Awk log(n) Function

log() function provides natural logarithmic of given argument n. log() returns logarithm value only when n is positive number. If you give any invalid number (even negative) it throws an error.

Example

 $ awk 'BEGIN{ print log(12); print log(0); print log(1); print log(-1); }' 2.48491 -inf 0 nan

In the above output you can identify that log(0) is infinity which was shown as -inf, and log(-1) gives you the error nan (Not a Number)

3. Awk sqrt(n) Function

sqrt function gives the positive square root for the given integer n. This function also accepts the positive number, and it returns nan error if you give the negative number as an argument.

Example

 $ awk 'BEGIN{ print sqrt(16); print sqrt(0); print sqrt(-12); }' 4 0 nan

4. Awk exp(n) Function

exp function provides e to the power of n.

Example

 $ awk 'BEGIN{ print exp(123434346); print exp(0); print exp(-12); }' inf 1 6.14421e-06

In the above output, for exp(1234346), it gives you the output infinity, because this is out of range.

5. Awk sin(n) Function

sin() function gives sine value of n, with n in radians.

Example

 $ awk 'BEGIN { print sin(90); print sin(45); }' 0.893997 0.850904

6. Awk cos(n) Function

cos() returns cosine value of n, with n in radians.

Example

 $ awk 'BEGIN { print cos(90); print cos(45); }' -0.448074 0.525322

7. Awk atan2(m,n) Function

This function gives you the arc-tangent of m/n in radians.

Example

 $ awk 'BEGIN { print atan2(30,45);  }' 0.588003

8. Awk rand() Function

rand() is used to generate the random number between 0 and 1. It never return 0 and 1. It always returns the value between 0 and 1. Numbers are random with in one awk run, but predictable from run to run. Awk uses some algorithm to generate the random numbers. Since this algorithm is fixed, the numbers are repeatable.

Example

The following example generates 1000 random numbers between 0 to 100 and shows how often each number was used

 $cat rand.awk BEGIN { while(i<1000) { 	n = int(rand()*100); 	rnd[n]++; 	i++; } for(i=0;i<=100;i++) { 	print i,"Occured", rnd[i], "times"; } } $

Pasted some of the output of the above script here.

 $awk -f rand.awk 0 Occured 6 times 1 Occured 16 times 2 Occured 12 times 3 Occured 6 times 4 Occured 13 times 5 Occured 13 times 6 Occured 8 times 7 Occured 7 times 8 Occured 16 times 9 Occured 9 times 10 Occured 6 times 11 Occured 9 times 12 Occured 17 times 13 Occured 12 times

From the above output, sure that rand() function can generate repeatable numbers very often.

9. Awk srand(n) Function

srand() is used to initialize the random generation with the given argument n. So that whenever the program execution starts, it starts generating the number from n. If no argument is given, it uses the time of the day to generate the seed.

Example. Generate 5 random number starting from 5 to 50

 $cat srand.awk BEGIN { #initialize the seed with 5. srand(5); # Totally I want to generate 5 numbers. total=5; #maximum number is 50. max=50; count=0; while(count < total) { 	rnd = int(rand() * max); 	if ( array[rnd] == 0 ) { 		count++; 		array[rnd]++; 	} } for ( i=5; i<=max; i++) { 	if ( array[i] ) 		print i; } }

In this srand.awk, using rand() function, generate the number and multiply with max value to produce the number with the max of 50, and check if the generated random number is already exist in the array, if it does not exist, increment its index and as well as increment loop count. so that it generates 5 number like this and finally in the for loop from minimum number to maximum, and prints the index only which has the value.

Here is the output of the above script

 $ awk -f  srand.awk 9 15 26 37 39

Synopsys Acquires Magma Design Automation

noreply@blogger.com (Unknown) — Sun, 04 Dec 2011 06:22:00 +0000

Well...... Finally the predicted is happening ! EDA major Synopsys is acquiringMagma Design Automation.
Here is the press release: Synopsys to Acquire Magma Design Automation
http://synopsys.mediaroom.com/index.php?s=43&item=982

Physical Design: Routing

noreply@blogger.com (Unknown) — Mon, 28 Nov 2011 17:42:00 +0000

Routing

Routing flow is shown in the Figure (1).

Figure (1) Routing flow [1]

Routing is the process of creating physical connections based on logical connectivity. Signal pins are connected by routing metal interconnects. Routed metal paths must meet timing, clock skew, max trans/cap requirements and also physical DRC requirements.

In grid based routing system each metal layer has its own tracks and preferred routing direction which are defined in a unified cell in the standard cell library.

There are four steps of routing operations:

1. Global routing
2. Track assignment
3. Detail routing
4. Search and repair

Global Route assigns nets to specific metal layers and global routing cells. Global route tries to avoid congested global cells while minimizing detours. Global route also avoids pre-routed P/G, placement blockages and routing blockages.

Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at once.

Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as "SBox". Detail route traverses the whole design box by box until entire routing pass is complete.

Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox sizes.

Reference

[1] Astro User Guide, Version X-2005.09, September 2005

Expressions, Operators and Operands in Verilog HDL

noreply@blogger.com (Unknown) — Mon, 28 Nov 2011 17:30:00 +0000

Verilog HDL: Expressions, Operators and Operands

Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. 'expressions,, 'operators' and 'operands' form the basis of Verilog dataflow modeling.

Arithmetic:

                            *       ---> Multiplication
                            /        ---> Division
                           +        ---> Addition
                           -         ---> Subtraction
                           %       ---> Modulo
                         **        ---> Power or exponent

Logical:

                           !         ---> logical negation (one operand)
                       &&       ---> logical AND
                           ||         ---> logical OR

Relational:

                          >        ---> greater than

< ---> lesser than

>= ---> gretaer than or equal to

<= ---> less than or equal to

Equality:

                          ==      ---> equality
                          !=       ---> inequality
                       ===       ---> case equality
                        !==       ---> case inequality

Bitwise:

                          ~        ---> bitwise negation (one operand)
                         &        ---> bitwise AND
                          |          ---> bitwise OR
                         ^         ---> bitwise XOR
             ^~ or ~^         ---> bitwise XNOR

Reduction:

                         &          ---> reduction and (one operand)
                       ~&         ---> reduction NAND
                          |            ---> reduction OR
                        ~|            ---> reduction NOR
                         ^           ---> reduction XOR
              ^~ or ~^          ---> reduction XNOR

Shift:

                       >>           ---> right shift
                      <<            ---> left shift
                    >>>            ---> arithmetic right shift
                    <<<            ---> arithmetic left shift

Concatenation:

                          { }       ---> any number operand

Eg:

       A= 1'b1, B=2'b00, C =2'b10, D=3'b110
       Y={B,C}                                                 //result y is 4'b0010
         Y={A,B,C,D,3'b001}                           //y=11'b10010110001
         Y={A,B[0],C[1]}                                   //Y=3'b101

Replication:

                       {{ }}        ---> any number operand

Eg :-
           reg A;
           reg [1:0] B,C;
           reg [2:0] D;
          A=11b1; B=2'b00; C=2'b10; D=3'b110;

          Y={4{A}}                                             //result y is 4'b1111
          Y={4{A} , 2{B}}                                 //y=8'b11110000
          Y={4{A},2{B},C}                                //y=8'b1111000010

Conditional:

                          ?: (three operands)

Data Types in Verilog HDL

noreply@blogger.com (Unknown) — Mon, 28 Nov 2011 16:59:00 +0000

Verilog HDL: Data Types

Value Set:
---> Four values to model the functionality

---> Eight strengths of real hardware

Value level--------- Condition in hardware circuits

            0 ------------- > Logic zero, false condition
            1 ------------- > Logic one, true condition
            X ------------ > Unknown logic value
            Z ------------- > High impedance ,floating state

Nets:

Represent connection between hardware elements ; is a datatype; not a keyword
Nets are declared primarily with the keyword 'wire'
Default value is 'z'
Exception : 'trireg' net,which defaults to x

Eg:

           wire a;
           wire b,c;
           wire d=1'b0     //Net d is fixed to logic value zero at declaration

Register:

Represent data storage element
Retain value until another value is placed onto them
Keyword is 'reg'

Eg:

reg reset; //declare a variable reset that can hold its value

Registers can also be declared as signed variables

Eg:

reg signed[63:0] ; //64 bit signed value

Vectors:

Nets or reg (multiple bit widths) data types can be declared as vectors

Default is scalar (1-bit)

Eg :

wire a; //scalar net variable;default

wire [7:0] bus; //8 bit bus

wire [31:0] bus A,bus B,bus C; //3 buses of 32 bit width

reg clock; //scalar register; default

reg [0:40] virtual_addr; //vector register. Virtual address 41 bits wide

// 0:always MSB ; 40:always LSB

Vector Part Select:
It is possible to address bits or parts of vectors.

Eg:

busA[7] //bit 7 of vector bus A

bus[2:0] //three LSBs of vector bus

virtual_addr[0:1] //two MSBs of vector virtual_addr

Variable Vector Part Select:

Eg:

reg[255:0] data 1; //Little endian notation

byte = data1[31-:8]; //starting bit=31,width=8=>data[31:24]

byte = data[24+:8]; //starting bit =24, width=8=>data[31:24]

Integer:

Default width is the host machine word size

Eg:

integer counter; //general purpose variable used as a counter

Real:

Can be in decimal notation(eg: 3.14)
Can be in scientific notation(eg: 3e6)
No range declaration possible
Default value is zero

Eg:

real delta; //define a real variable

Time:

A special time register data type is used in verilog to store simulation time
Width is application specific ;but atleast 64 bits
The system function '$time' is invoked to get the current simulation time
The simulation time is measured in terms of simulation seconds

Eg :

time save_sim_time; //define a time variable save_sim_time

initial save_sim_time= $time; //save the current simulation time

Arrays:

Allowed for reg, integer, time, real, realtime and vector
Multidimensional arrays are also allowed
Arrays are accessed by []

Eg:

integer count[0:7] ; //an array of 8 count variables

reg bool[31:0] ; //array of 32 one-bit Boolean register variables

time chk_point[1:100]; //array of 100 time checkpoint variables

reg [4:0] port_id[0:7]; //array of 8 port_ids; each port_id is 5 bits wide

Memories:

Memories are modeled as a one-dimensional array of registers
Each word can be one or more bits

Eg :

reg memory_1_bit[0:1023]; //memory memory_1_bit with 1K 1-bit words

reg[7:0] memory_byte[0:1023]; //memory memory_byte with 1K 8-bit words(bytes)

memory_byte[511] //fetches 1 byte word whose address is 511

Parameters:

Constant definitions

Eg:

parameter part_id =5; //defines a constant port_id

parameter cache_line_width=256; //constant defines width of cache line

parameter signed [15:0] width; //fixed sign and range for parameter width

VLSI - Automation...

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Setup and hold times of an flip-flop

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SETUP TIME & HOLD TIME EQUATIONS for Flip Flop

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The GDSII Stream Format

9 Powerful Awk Built-in Functions for Numeric

9 Powerful Awk Built-in Functions for Numeric

1. Awk int(n) Function

Example

2. Awk log(n) Function

Example

3. Awk sqrt(n) Function

Example

4. Awk exp(n) Function

Example

5. Awk sin(n) Function

Example

6. Awk cos(n) Function

Example

7. Awk atan2(m,n) Function

Example

8. Awk rand() Function

Example

9. Awk srand(n) Function

Example. Generate 5 random number starting from 5 to 50

Synopsys Acquires Magma Design Automation

Physical Design: Routing

Routing

Expressions, Operators and Operands in Verilog HDL

Verilog HDL: Expressions, Operators and Operands

Data Types in Verilog HDL

Verilog HDL: Data Types

The `for` Statement