VLSI-Simplified

Few simple VHDL codes

2014-08-10T22:28:00.004-07:00

Combinational circuits

1. Unsigned 8-bit adder.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder is

port(A,B : in std_logic_vector(7 downto 0);

SUM : out std_logic_vector(7 downto 0));

end adder;

architecture archi of adder is

begin

SUM <= A + B;

end archi;

2. Unsigned 8-bit subtractor.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity subtr is

port(A,B : in std_logic_vector(7 downto 0);

RES : out std_logic_vector(7 downto 0));

end subtr;

architecture archi of subtr is

begin

RES <= A - B;

end archi;

3. Unsigned 8-bit adder with carry in.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder is

port(A,B : in std_logic_vector(7 downto 0);

CI : in std_logic;

SUM : out std_logic_vector(7 downto 0));

end adder;

architecture archi of adder is

begin

SUM <= A + B + CI;

end archi;

4. Decoder 1:8

library ieee;

use ieee.std_logic_1164.all;

entity dec is

port (sel: in std_logic_vector (2 downto 0);

res: out std_logic_vector (7 downto 0));

end dec;

architecture archi of dec is

begin

res <= "00000001" when sel = "000" else

"00000010" when sel = "001" else

"00000100" when sel = "010" else

"00001000" when sel = "011" else

"00010000" when sel = "100" else

"00100000" when sel = "101" else

"01000000" when sel = "110" else

"10000000";

end archi;

5.Priority encoder 1:9

library ieee;

use ieee.std_logic_1164.all;

entity priority is

port ( sel : in std_logic_vector (7 downto 0);

code :out std_logic_vector (2 downto 0));

end priority;

architecture archi of priority is

begin

code <= "000" when sel(0) = '1' else

"001" when sel(1) = '1' else

"010" when sel(2) = '1' else

"011" when sel(3) = '1' else

"100" when sel(4) = '1' else

"101" when sel(5) = '1' else

"110" when sel(6) = '1' else

"111" when sel(7) = '1' else

"---";

end archi;

6. 8-bit Comparator (>,=):

Following is the VHDL code for an unsigned 8-bit greater or equal

comparator.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity compar is

port(A,B : in std_logic_vector(7 downto 0);

CMP : out std_logic);

end compar;

architecture archi of compar is

begin

CMP <= '1' when A >= B

else '0';

end archi;

7. Different ways of writing same logic : Multiplexer

1. Mux using 'with'

library ieee;

use ieee.std_logic_1164.all;

entity mux1 is

port (

din_0 :in std_logic;-- Mux first input

din_1 :in std_logic;-- Mux Second input

sel :in std_logic;-- Select input

mux_out :out std_logic -- Mux output

);

end entity;

architecture behavior of mux_using_with is

begin

with (sel) select

mux_out <= din_0 when '0',

din_1 when others;

end architecture;

2. Mux using 'when'

library ieee;

     use ieee.std_logic_1164.all;

 entity mux2 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

         mux_out :out std_logic -- Mux output

);

 end entity;

 architecture behavior of mux_using_when is

 begin

     mux_out <= din_0 when (sel = '0') else

                din_1;

 end architecture;

3. Mux using 'if'

library ieee;

    use ieee.std_logic_1164.all;

 entity mux3 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

         mux_out :out std_logic -- Mux output

);

 end entity;

 architecture behavior of mux_using_if is

 begin

     MUX:

     process (sel, din_0, din_1) begin

        if (sel = '0') then

             mux_out <= din_0;

         else

             mux_out <= din_1;

         end if;

     end process;

end architecture;

4. Mux using 'if'

library ieee;

    use ieee.std_logic_1164.all;

entity mux4 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

        mux_out :out std_logic -- Mux output

);

 end entity;

architecture behavior of mux_using_case is

 begin

     MUX:

     process (sel, din_0, din_1) begin

         case sel is

             when '0'    => mux_out <= din_0;

             when others => mux_out <= din_1;

         end case;

     end process;

 end architecture;

8. parity generator: 4-bit


Behavioral model

entity PARITY is

port(V: in BIT_VECTOR(3 downto 0);

   EVEN:out BIT);

end PARITY;

architecture PARITY_BEHAVIORAL of PARITY is

begin

process(V)

variable NR_1: NATURAL;

begin

NR_1:=0;

for I in 3 downto 0 loop

if V(I)='1' then

NR_1:=NR_1+1;

end if;

end loop;

if NR_1 mod 2 = 0 then

EVEN <= '1' after 2.5 ns;

else

EVEN <= '0' after 2.5 ns;

end if;

end process;

end PARITY_BEHAVIORAL;

is Kuchcinski (LTH)

Structural model



use WORK.all;

architecture PARITY_STRUCTURAL of PARITY is

component XOR_GATE

port(X,Y: in BIT; Z: out BIT);

end component;

component INV

generic(DEL: TIME);

port(X: in BIT; Z: out BIT);

end component;

signal T1, T2, T3: BIT;

begin

XOR1: XOR_GATE portmap (V(0), V(1), T1);

XOR2: XOR_GATE portmap (V(2), V(3), T2);

XOR3: XOR_GATE portmap (T1, T2, T3);

INV1: INV

generic map (0.5 ns)

port map (T3, EVEN);

end PRITY_STRUCTURAL;

Sequential circuits

1. D-latch


library ieee;

    use ieee.std_logic_1164.all;

 entity dlatch_reset is

    port (   data  :in  std_logic;-- Data input

            en    :in  std_logic;-- Enable input

            reset :in  std_logic;-- Reset input

            q     :out std_logic -- Q output

        );

 end entity;

architecture rtl of dlatch_reset is

begin

     process (en, reset, data) begin

         if (reset = '0') then

               q <= '0';

         elsif (en = '1') then

         q <= data;

        end if;

    end process;

 end architecture;
2. Up-counter: 8-bit

library ieee;

    use ieee.std_logic_1164.all;

     use ieee.std_logic_unsigned.all;

entity up_counter is

   port (

      cout   :out std_logic_vector (7 downto 0); -- Output of the counter

       enable :in  std_logic;                     -- Enable counting

       clk    :in  std_logic;                     -- Input clock

      reset  :in  std_logic                      -- Input reset

     );

end entity;

architecture rtl of up_counter is

    signal count :std_logic_vector (7 downto 0);

begin

     process (clk, reset) begin

         if (reset = '1') then

            count <= (others=>'0');

         elsif (rising_edge(clk)) then

            if (enable = '1') then

                count <= count + 1;

            end if;

       end if;

   end process;

    cout <= count;

end architecture;
2. Up-down counter: 8-bit

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
 entity up_down_counter is
   port (
     cout    :out std_logic_vector (7 downto 0);
     up_down :in  std_logic;                   -- up_down control for counter
     clk     :in  std_logic;                   -- Input clock
     reset   :in  std_logic                    -- Input reset
   );
 end entity;
 architecture rtl of up_down_counter is
     signal count :std_logic_vector (7 downto 0);
 begin
     process (clk, reset) begin
         if (reset = '1') then
             count <= (others=>'0');
         elsif (rising_edge(clk)) then
            if (up_down = '1') then
                count <= count + 1;
             else
                 count <= count - 1;
             end if;
         end if;
     end process;
     cout <= count;
 end architecture;




All the best for further coding with this background !

Verification in VLSI

2014-06-06T23:38:00.000-07:00

General view:

• Verification : an unavoidable effort.

• It never gives result but gives assurity of correct result.

• A mother testing food before serving to baby.

IEEE definition:

“Confirmation by examination and provisions of objective evidence that specified requirements have been fulfilled.”

Verification in VLSI Field:

• 70% of the total efforts in ASIC cycle

• Number of verification engineer is twice the number of RTL design engineer

• Test benches makes up 80% of the total code volume.

(Bug: Pantium bug costs to nearly 4.75 million dollar.)

Impact of Incomplete Verification

• Costly re-spin(s)

• Companies may miss out market window

• Large companies can have reputation at stake

– e.g. Pentium Bug

• Smaller companies can have hard to recover financial implications

• For start-ups, their existence itself can be at stake!

Verification Techniques

• Simulation

• Formal Verification (comparison)

• Static Timing Analysis

Simulator:

Simulator makes a computing model of the

circuit, executes the model for a set of

input signals (stimuli, patterns, or vector),

and verifies the output signals.

Formal Verification

• Can be used to verify a design against a reference design as it progresses through the different levels of abstraction

• Verifies functionality without test vectors•

• obtaining a complete FSM description of the system.

• FSM (Discrete functions) can be represented conveniently by BDDs (binary decision diagram) and its extension MDDs (multi-valued decision diagram)

Static Timing Analysis

• Inputs: – Netlist, library models of the cells and constraints (clock period, skew, setup and hold time…)

• Outputs:– Delay through the combinational logic

• Basic concepts:

– Look for the longest topological path

– Discard it if it is false

Verification Languages

•“e”

• Vera

• Suger

• System – C

• System – Verilog Language

• verilog

VERIFICATION REUSE

• verification consuming 60-80% of the manpower on complex chip projects

• improving verification productivity is an economic necessity Verification reuse directly addresses higher productivity

• all components be built and packaged uniformly.

• efficient integration of reusable, plug-and play verification components

Getting started with VHDL codes

2013-11-20T23:19:00.000-08:00

To code in any Hardware description language, one must know the digital design aspects. Let's start with a the simplest circuit - a Full adder. Following figure shows its logic-gate implementation.

The VHDL Code can be constructed either by following its functionality or by looking at its structure in above circuit.(Behavioural/ Data flow modelling & Structural modelling respectively)

Sample Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_adder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           sum : out STD_LOGIC;
           carry : out STD_LOGIC);
end F_adder;
architecture Behavioral of F_adder is
begin
sum <= (a xor b) xor cin;
carry <= (a and b)or (cin and (a xor b));
end Behavioral;

Functional Simulation Result:

Post-route Simulation results:

Note: These simulation results are drawn by using Xilinx ISE design suit.

Get introduced with VLSI world

2013-11-20T02:46:00.000-08:00

Historically, numerous events witness the evolution of current VLSI technology. In early 1930s, Lilienfield & Heil discussed on the theoretical development of forerunners of today's Field effect transistor (FET). Few years later in 1947, John Bardeen, Walter Brattain and William Schokley at Bell laboratories built the first working point contact transistor (Nobel Prize in Physics in 1956). This development marked the practical beginning of microelectronic industry.

Figure 1.1 First trnsister (point contact) in the world built by John Bardeen, Walter Brattain and William Schokley at Bell laboratories on December 16, 1947.

In 1958, Jack Kylby built the first integrated circuit flip flop at Texas Instruments. The work of Kylby has marked the beginning of so called VLSI design. In the following years the field was booming with developments one after another.In 1963, Frank Wanlass at Fairchild described the first CMOS logic gate (nMOS and pMOS). Till 1970s, the processes using n-MOS became dominant. Gradually, power consumption became a major issue & because of the advantage of CMOS, it was widely adapted.

1.1. Issues & Trends in digital design

The term digital has become a part of our everyday life, because of the way these digital circuits have spread almost all areas of our lives. The technology used to build digital hardware has developed dramatically over last four decades. The logic circuits that were built earlier used bulky components whereas today's circuits are extremely small & efficient. Many integrated circuits of today contain more than 1 million transistors. The methods of designing integrated circuits have changed from conventional iterative methods at breadboard level to sophisticated software tools. Although previous technologies had limited scope to explore but they opened the door for the information processing revolution in this field.

1.1.1. Moore’s law

The lowest level of digital design is the device physics & IC manufacturing process. This level is mainly responsible the advances in speed & density of the IC. The effects of these advances are summarised in Moore’s law. It states that, “The number of transistors per square inch in an IC doubles every 18 months”. It is worth noting that, with each doubling of density the speed is also increasing.

Figure 1.2 Increasing transistor densities

1.1.2. Size & complexity of integrated circuits:

Integrated circuits can be classified in terms of number of potential devices used in the design of the circuit. It is summarised in Table 1.1

Table 1.1: classification of Integrated circuits by device count

Nomenclature	Approximate development duration	Active device count	Typical functions/ applied to build-
SSI (small-scale integration)	early 60s	1-100	Gates, op-amps
MSI (medium-scale integration)	late 60s	100-1000	Registers, filters
LSI (large-scale integration)	early 70s	1000-100,000	Microprocessors, A/D
VLSI (very large-scale integration)	early 80s	100000-1000000	Memories, computers, signal processors
ULSI (ultra large-scale integration)	late 80 onwards	>= 1000000	Increasing the current chip densities

1.1.3. Digital hardware

The digital circuits are called so, because of the way in which information is represented as electronic signals corresponding to particular digits. The advent of integrated circuits made it possible to accommodate number of transistors & ultimately the entire circuit on a single chip. Now a-days there are number of chips available in the market ranging from very simple chips with low functionality to extremely complex one. For example, a digital electronic system may require a microprocessor for some arithmetic operations, a memory storage for preserving some outputs, some interfacing chips etc. it may also be needed to design & built a logic circuit from scratch. Such all hardware components can be broadly categorised in three groups- full custom / standard chips, semi custom ICs & programmable logic devices.

Numbers of chips are available that have some commonly used fix logic circuit which can not be changed so can also be called as full custom chips. Generally standard chips contain a small circuit with few transistors & can perform a simple function. The designer needs to select appropriate chips to build a bigger circuit. But having such number of chips on a PCB increases the size of total circuit.(Examples: 74XX series chips)

In some situations it is required to design an application oriented chip for better performance. In this case, usually the required logic circuit is designed first, and then with the help of a suitable technology is used to implement it. Finally the chip is manufactured through a foundry. This approach is called as semi custom design. As such chips are intended for a specific application, they are also called as Application specific integrated circuit (ASIC). As custom chips require a large amount of design efforts, the cost for its production is too high.

Examples: microprocessors, memory chips.

Programmable logic device is a general purpose chip for implementing logic designs at hardware level. In contrast to the standard chips which have fixed functionality, it is possible to realise the logic circuits directly configured by the end user. The PLDs have a very general structure of programmable switches that can be configured in many different ways. Most types of PLDs are reprogrammable & corrections can be made in the design without any risk.

Examples: PLA, PAL, CPLD, FPGA.

Important terms:

1. Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit.

2. IC- Integrated circuit is a collection of one or more gates fabricated on a single silicon chip.

3. Wafer- is a thin slice of semiconductor material on which semiconductor devices are made. Also called a slice or substrate.

4. Chip- is a small piece of semiconductor material upon which miniaturised electronic circuits can be built.

5. Die- is an individual circuit or subsystem that is one of several identical chips that are produced after dicing up a wafer.

6. HDL- hardware description language- a language which allows structure & function of a digital circuit to be specified/ modeled.

7. PLD- programmable logic devices- the chip with a very general structure of programmable switches that allow the internal circuitry of the chip to be configured in many different ways.

References:

1. www.wikipedia.org

2. ULSI semiconductor technology atlas : by- Chih- Hang Tung, Georgr T T Sheng et all , Wiley pub