VLSI Digest

Why there is a massive chip shortage in the semiconductor industry?

2021-04-07T01:17:00.003-07:00

Potential factors like economic disruption due to COVID-19, working from home, wafer yield issues, and shortage for 200 mm wafer capacities in foundries are some of the potential reasons why we are seeing a sudden surge in demand and a severe shortage in supply.
Over the last 30 years, silicon wafer size has grown from 1-inch to 300 mm wafer size (which is 11.8 times larger than 1 inch). 300 mm wafers are invariably used for manufacturing leading-edge silicon IC’s, but this doesn’t benefit many customers.
The reason being these design companies don’t see much profitability in lower node technologies and hence they want to continue with their current fab.
200 mm (8-inch in diameter) fabs are older facilities that manufacture chips at mature nodes (350 nm to 90 nm), whereas 300 mm fabs are used for manufacturing chips designed on lower nodes (65 nm and below), but it is not restricted just to lower nodes.
Moving design from one fab to another incur huge cost.
Since many people are working from home, there is a huge demand for computers, tablets, TV, Wi-Fi, Bluetooth, and many automotive electronics. And the current fab capacity limit is making it difficult to meet the supply request.
The semiconductor industry is at a critical juncture where the demand from general household and partner companies is shooting up with a huge potential for revenue generation in 2021 (at least 12% growth), but at the same time, the supply chain is in the spotlight restricted by limited capability and lower investment.

Tcl Programming Language | Lecture 1 | Basics

2021-04-06T12:07:00.002-07:00

Micron Rules and Lambda Design rules

2021-04-04T11:27:00.006-07:00

Micron Rules: This specifies the layout constraints such as minimum feature sizes and minimum feature separations in terms of absolute dimensions.

Lambda Rules: This specifies the layout constraints in terms of a single parameter (𝝀) and thus allows linear and proportional scaling of all geometrical constraints.
Example:- Minimum Poly width: 4𝝀

Types of element?

2020-09-08T09:30:00.001-07:00

1. Active and Passive element:

Active devices are the one which generates (or) amplify (or) rectify any signals (Voltage source, Current source, Diode, Transistor, DIAC, SCR, Op-Amp, etc)

Rest all devices are called a passive device (R, L, C, Transformer).

Note: Amplification here is in terms of the power signal and hence transformer cannot be put under the category of the active device as the power is constant in both the primary and secondary side of the transformer (I1V1 = I2V2).

2. Linear and Non-Linear:

Linear devices are the one which obeys the law of superposition and homogeneity.

(Or) To put this simply, any straight line passing through the origin is called a linear element (R, L, C).

Non-linear element examples are diode, SCR, DIAC, etc.

3. Bilateral and Unilateral:

Any bilateral element (e.g. R, DIAC) will have similar characteristics in the 1st and 3rd quadrant of the graph else it will be a unilateral element (e.g. Diode).

4. Time-Variant and Time-Invariant

5. Lumped and Distributed

Let's understand these concepts on a graph (I vs V):-

Latch-Up Effect?

2020-09-08T08:22:00.005-07:00

As can be seen in the above snapshot, resistance connected to the bases of NPN transistors and collectors of the PNP transistors greatly influences both ESD and Latch-Up effect in the layout. Furthermore, latch-up is sensitive to layout and hence most often solved at the layout level when doing the physical implementation of the design.

What is latch-up?
Latch-up is the creation of low impedance path between the power supply rails (e.g. vdd to gnd in the above case). It is caused when the parasitic BJT structures within an IC are triggered when a current/voltage is applied as stimulus in the input, output or I/O pin.

Sometime it also happen that the latch-up occur only while the pulse stimulus is connected to the IC and returns back to normal level once the stimulus is removed. Such an effect is called temporary (or) transient latch-up.

While a true latch-up is a one which remains even after the stimulus is removed. In such scenarios to remove the low impedance path between the power rails, a power supply shutdown is required.

How does it occur?
Latch-up is a regenerative process that occur when a pnpn structure (aka silicon controlled rectifier (SCR)) is formed. It is composed of parasitic npn and pnp transistor.

To avoid latch-up:

Vpnpn <= Vs (Sustaining Voltage)
Injecting current < Holding current (IH)

Prevention Technique:

Surround the transistor with guard rings.
Reduce Rn and Rp. This will cause more current requirement for latch-up to occur.

What are guard rings?

Guard rings are used to collect majority (or) minority carriers flowing in the silicon. Tuning the doping level of the guard ring material helps in increasing or decreasing the resistance in the area of guard ring.

Shallow Trench Isolation (STI)

2020-09-02T11:41:00.002-07:00

Isolation technique to prevent current leakage between adjacent semiconductor device.
Hence, prevents latch-up.
MOSFET's are also called self-isolating devices but as the transistor size decreases the use of reverse bias pn-junction to isolate transistor becomes impractical.
STI allows closer spacing of transistors.
In scenarios as n+ & p+ spacing gets smaller, birds beak shape characteristic is formed which leads to undesirable stress effects in the transistor.
STI has the advantage of minimizing the heat cycle needed for n+ and p+ isolation.
Additionally, it also reduces substrate noise coupling.

Submicron, Deep Submicron, Ultra Deep Submicron

2020-08-30T23:24:00.000-07:00

CMOS Technology Categories:-

Submicron: L >= 350 nm
Deep Submicron: 100 nm <= L <= 350 nm
Ultra Deep Submicron: L <= 100 nm

Source: https://aicdesign.org/

Principle, Concept, Technique, Assumption

2020-08-30T22:21:00.004-07:00

Principles: Fundamental laws (or) facts that never change.

Concepts: Soft-laws, things worth remembering, abstract idea.

Techniques: Method, tool, tricks, assumption to simplify things.

Assumptions: Taking something to be true without formal proof.

**Goal of making assumptions is to eliminate the non-essential information from the essential information.

Analog IC Design Process?

2020-08-30T22:15:00.000-07:00

Broadly analog IC design process can be classified into the following steps:-

1. Electrical Design: It is a process of designing a circuit solution to meet the required specification. Electrical design requires electrical models for creating the design, verifying the design, and to also determine the robustness of the design.

2. Physical Design: It is the process of representing the electrical design in the form of a layout (i.e. putting together various distinct geometrical rectangles at various levels). This layout is then used to create a 3-dimensional integrated circuit (IC) through a process called fabrication.

3. Packaging: Packaging is done to protect the IC, power the IC, and provide electrical & mechanical connections between the IC and the outside world.

4. Testing: Process of measuring the IC performance i.e. to compare the experimental performance with the specifications and the simulation results.

Charge and Current

2020-08-18T06:17:00.006-07:00

Charge: It is the most basic quantity which is responsible for the electric phenomenon.

An atom is a combination of proton, electron, and neutron. The magnitude of an electron is 1.6 x 10e-19 Coulombs and 1 coulomb, therefore, has 6.24 x 10e18 electrons. The conventional direction of the current is opposite to the negative charge (i.e. electron).

i=dq(t)/dt (or) q=∫i(t).dt

Current: It is the time rate of change of electric charge.

Power and Energy

2020-08-18T06:17:00.003-07:00

Power:- Rate of change of energy.

· P=dW/dt (Watt)

· P=dW/dq * dq/dt

· P=V.I ->DC power

· p(t)=v(t).i(t) -> Instantaneous power

Energy:- Capacity to do work is called energy.

· P=dW/dt

· W=∫P.dt

· W=∫V.i(t).dt

· W=V.I.t (Joule)

EMF vs PD

2020-08-18T06:17:00.001-07:00

The work done to move a unit positive charge from infinity to some reference point is known as EMF.

V=dw/dq (volt)

EMF:-

Cause
Source to the circuit
Independent to other elements in the circuit

Potential Difference:-

Effect
Part of the circuit
Dependent

Basic System of Units

2020-08-18T05:25:00.001-07:00

Metric System: International Systems of Unit (SI Unit) -> 1960

Six Fundamental Units:-

Length (meter)
Mass (kilogram)
Time (second)
Electric Current (Ampere)
Temperature (Kelvin)
Luminous Intensity (Candela)

Circuit Theory (Introduction)

2020-08-18T05:18:00.000-07:00

Electromagnetic theory is applicable for all frequency ranges whereas network (aka circuit) theory is applicable for up to a frequency of 1MHz

Circuit:- Interconnection of electrical elements.

Analysis:- For a given circuit, provided with a given input (excitation), the analysis part deals with finding the output (or response) of the circuit e.g. output I or V or Power.

Synthesis:- Designing the circuit provided both input and output is known.

Difference between network and circuit?

Network: May have (or) may not have a closed path.

Circuit: Always have a closed path.

What is FSM and what are its types?

2020-07-23T13:16:00.004-07:00

FSM: Finite State Machine

It is a sequential circuit consisting of a combinational circuit, a storage element, and a feedback path from output to the input. Change in FSM state from one state to another is called transition.

FSM are of two types:

1. Mealy Machine: Output is a function of the current state and the applied input.

2. Moore Machine: Output is a function of the current state only.

State Diagram: It describes the behavior of a finite state machine.

Verilog Module?

2020-07-23T09:10:00.001-07:00

The basic unit of logic description which contains all the information required for modeling the hardware.

It starts with the 'module' keyword and end with the 'endmodule' keyword.

Syntax:

module <module_name> (port declaration);

----------

endmodule

Arrays, Memory and Strings in Verilog?

2020-07-23T08:41:00.007-07:00

Arrays: Collection of objects of the same data type.

e.g.:

reg [7:0] arr; ==> 8-bit vector (or) bus of reg data type

reg arr [7:0]; ==> array of 8 one-bit element

Memory: A memory structure can be created using arrays.

-> Memory structure using a 2-dimensional array: reg [0:7] memo [0:3];

-> Memory structure using a multi-dimensional array: reg [0:7] memo [0:3] [0:3] [0:3];

Strings: Group of characters enclosed in double quotation.

myString = "Welcome to VLSI Digest";

Buses in Verilog?

2020-07-23T08:11:00.000-07:00

A bus is a collection of bits.

Declaration: <type><width or range><identifier>

Bus of wire data type:-

wire [7:0] val;

wire signed [7:0] val;

Bus of reg data type:-

reg [7:0] val;

reg signed [7:0] val;

Bit Select:- Any single bit within a vector (or) an array can be referenced individually.

wire [7:0] val_1;

wire [15:0] val_2;

assign val_1[6] = val_2[12];

Part Select:- Any group of nets in a bus can be referenced as a part select.

The direction of part select must match the original bus declaration.
The bounds of the part select must be within the original bus.

reg [7:0] val = 8'b10101010

Value of part select val[3:0] ==> has value of 10 (1010)

Reg vs Wire (Verilog)?

2020-07-22T03:38:00.008-07:00

Reg Data Type:-

The most commonly used variable data type.
Can hold 0,1, X, Z values. ** Use range declaration for more bits
Doesn't signify what type of value it will hold.
Not to be confused with a register.
Used to model storage elements.

e.g.: D-flip flop output is declared as reg and it will hold the value until the next positive clock edge arrives.

module dff( input d_in, clk, output reg q_out);

always @ (posedge clk)

q_out = d_in;

endmodule

Wire Data Type:-

Most popular net data type.
Default data type.
Assigned using the 'assign' statement.
Continuously updated based on the driver value.

e.g.:

module mux2x1( input a, b, sell, output wire y);

assign y = (a & sel) | (b & ~sel);

endmodule

Reg data type is used whenever a data object is assigned within a Verilog procedural block (like always and initial).

What are Data Objects (Verilog)?

2020-07-22T03:24:00.006-07:00

Data Objects:- These enable the change in state and passing of data from one point to another in logic design.

Two main types of data objects are:

1. Variables

Evaluates when a procedural block executes (always or initial)
It is procedural – stores and holds the value until its next assignment.

e.g.: reg, integer, real, time, realtime

Integer: Represent integer value (e.g. integer a = 7;)
Real: Used to model floating-point values (not synthesizable) (e.g. real val_1 = 3.65;)
Time: Used to represent delay and sequencing (not synthesizable) (e.g. time delay_1 = 2ns;)
Realtime: Store real value of simulation time.

2. Nets

Evaluates when the input changes.
It is structural – i.e. it connects a driver (or multiple drivers) to the receiver.
There are eight data types of nets used for hardware modeling.

e.g.: wire, tri, wand, triand, wor, trior, tri0, tri1, trireg, supply0, supply1

** In general, only wire (i.e. point-to-point connections) is used for FPGA-based synthesis enabling source-code portability.

Inference vs Instantiation (Verilog)?

2020-07-21T12:52:00.001-07:00

Verilog data representation?

2020-07-21T12:29:00.003-07:00

Each bit is treated as data in the Verilog language. Each bit can support any of the following 4 logic values which are: 0, 1, ‘X’ (unknown or uninitialized), ‘Z’ (high impedance).

Syntax for declaring a number: <size><base format><number>

Explicitly-Sized Numbers: Here we have explicitly specified the size for the number;

6’b101101 -> 6-bit binary value

8’sh4a -> 8-bit signed hex value

16’Hfa2z -> 16-bit hex value

** 8’b1010 -> 0000_1010 (automatically zero-extended)

** 4’b10110111 -> 0111 (automatically extra bit's truncated)

Implicitly-Sized Numbers:

** When size parameter is not specified, default value of 32-bit is considered for internal compiler.

‘o12 -> 32-bit octal value

‘shab11 -> 32-bit signed hex value

3674 -> 32-bit signed decimal

Comments (Verilog)?

2020-07-21T12:20:00.001-07:00

Single-line comment:

//This is a single line comment

Multi-line comment:

/*This is a

multi-line comment*/

Keywords vs Identifier (Verilog)?

2020-07-21T12:19:00.001-07:00

Keywords: Reserved identifiers for the Verilog language constructs. Always in lower-case.

e.g.: module, endmodule, input, output, etc.

Identifiers: Name given to an object so that they can be referenced in the design description.

e.g.: a, b, _test, etc.

Levels of Abstraction in Verilog?

2020-07-19T21:31:00.001-07:00

Hardware can be modeled at different levels of abstraction using Verilog.

i.e. Behavioral, RTL (Register-Transfer level), Gate level, Placed cells and route, Switch/Mask