VLSI Interview Questions

Why setup? Why hold?

2009-01-23T10:31:00.003+05:30

savita: hi u know what i was reading that chat session u have

Who says chatting is bad habit! Here is a chat session between two friends about deadly dangerous setup and hold!! Don’t think that the person who is asking these questions doesn’t know about setup and hold. The term “setup” and “hold” is such a word in this VLSI – ASIC design world which only creates questions and questions and questions!

All readers can join hands in this chat! Comment forms are always online!!

BGG: I have a doubt after long time. Why is set up and hold in flip-flop?

KMM: I am honored!

BGG: Can you go beneath transistor and tell me. I know metastability state or charging or discharging of capacitor etc etc?

KMM: Then what you know?

BGG: But flip flop is combination of 2 latches

KMM: Tell whatever you know...may be it has answer!

BGG: And latch is level triggered.

BGG: If so whatever data will be sent two latches will be launched. Why metastability? Why set up time? Why data should be stable before clock edge? WHY SETUP? WHY HOLD?

KMM: So how two level triggered latches form an edge triggered flop??????? If you find answer for this you will get answer for your question!!

KMM: Below link can help u:

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

BGG: Didn’t get.....

See they are telling the same.... we can’t avoid metastability state so we have to make data stable before setup and hold....

BGG: But my question is why metastable state?

KMM: Go inside latch.... how it works???? Say one input is given...then when the output gets stabilized????? ??????Immediately ......or does it take some time....

Remember working of simple SR latch....

KMM: Just think...think and think....that will solve your problem

BGG: Any clue

KMM: You know that any latch output doesn’t stabilize immediately.....

Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1)...

So in this way it takes 2-3 data cycles....right....

This happens for both latches of flop...ok

Now you know that both latches won’t work together ...because you have arranged flop circuit such away that slave follows master

Means....when master latches the data slave sleeps

And then slave follows master....

Means slave releases the data which is latched earlier....

To latch the data, master takes 2-3 cycle

(As I explained earlier) same is the story for slave....

Now extend your imagination...

To a flop which is exclusively designed as edge triggered with basic gates itself

May be NOR or NAND...or may be based on CMOS full custom...

Same story applies here as well.....

All that happens is those 2-3 cycles to stabilize data....

Now imagine one data is under latching process...

May be one cycle is completed...

Data is not at stabilized within this latch...

Now if you allow one more input to enter what will happen to that data which was under process?????????

Naturally latch may start processing new input data or may go to unknown loop state that we call as metastable state...

Same applies for data that was already latched but about to leave out of the latch...

KMM: These two timing delay requirements ultimately constitute setup and hold

KMM: hold for time required for data to come out

While setup for data to get latched....

Hence hold is always related with launch clock

While setup is related with capture clock....

BGG: I am confused now

What hold when you have data already in flip flop? Then why launch edge?

KMM: Always remember that flop has latch structure.....means to say....

When one latch works another doesn't do any work....

BGG: So...

KMM: So if you take register to register connection....

When one is launching data next one is ready to receive data

BGG: yes

KMM: That’s all.....

It continues like that way.....

KMM: When first one is receiving next flop is ready to launch...and so on....

To summarize........it takes one clock cycle to complete the launch or capture....

That’s why we always say....present data ...previous data...and so on...

BGG: So what I understood was right we don’t need a reference for hold since it’s already in flop

KMM: That’s why for hold analysis no clock is considered or..."hold is not dependant on clock"

BGG: Even hold has to be checked for 2nd flop only...right? It’s not for 1st flop

KMM: Let me think ...how I can explain u...

BGG: shall I tell you what I understood if you don’t mind

Please

KMM: wait....

It’s true that hold value is taken from second flop

But remember every capture flop becomes launch flop for new data to be launched...

KMM: So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop

KMM: And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check

Or in other words....

Setup check for present data which is traveling...

Hold for new (future) data

Present data should reach the capture flop input before capture clock reaches there.....

(Setup check)

KMM: new data shouldn't reach too fast to capture flop so that present data doesn't corrupt

BGG: Ok let me analyze... will get back to you... thank you

Some Doubts !

2008-08-22T11:24:00.004+05:30

Recently i had a good chat session with my new friend bgs and i feel it is good idea to share the same..... it may clear or evoke some more doubts you have in your mind. I have given chat session as it is to maintain the originality. Please bear with chatting short cuts and spelling errors !!

so here we go.......

bgs: hi
1st time online?
me: hi...
bgs: i have seen u 1st time online?
me: with u first time
bgs: hm
me: then whts up
bgs: where ru?
me: i was off from bangalore last one month
went to xyz
now ofcourse back in bangalore
bgs: so ur working in PD ri8?
me: ya.....
bgs: which tool
me: astro
bgs: ur working on project now?
me: at present no work....... enjoying free time.....
bgs: oh good
me: trying to learn something new
bgs: so ur online ri8
so what ur learning?
me: thats right !!
how to calculate gate delay?!!!!!!
bgs: shall i ask one doubt in DC
me: and UPF
ya..... come on
shoot me ... let me try
bgs: whats diff bet set_max_capacitance and set_load?
i dont know ans
me: set_max_capacitance applies on pin not on pin and net
but set_load applies capacitance constraint on both net and pin
i.e whole output port gets loaded
bgs: max cap of cell (pin) will be precalculated by lib vender whats the use of setting it again
for higher value
me: pin cap can vary based on fanout...using which u can control fanout
bgs: what?
me: ultimately u r trying to control fanout==>drive strength==>delay
load cap==Cpin+Cnet
either u try to model Cpin or Cnet or both together
as u know gate delay=function of (input transition, Cload)
where Cload=Cpin+Cnet
hence we have set_max_cap and set_load
bgs: 1 sec ....for example if i have and (a,b,y) im seting max cap for y as 2. but default value of y in lib is 1 will it violate
*andgate(a,b,y)
sud i keep set_max _cap on y
me: yes....then tool tries to find a cell that meets your constraint
bgs: oh yes its doing
thanku
one more thing doubt pls
one more doubt pls
me: no need to keep set_max_cap for each and every cell...its impossible...
try to provide a moderate value so that tool take care of high fanout net synthesis
bgs: what is diff between timing engine and timing engine PT
me: DC target is to synthesize the code efficiently.....PT works exclusively on timing analysis
DC-uses less accurate timing algorithm
PT -uses Arnoldi algorithm which is synopsys patented and considered to be very accurate
PT timing correllation with SPICE results are really great
DC-no netlist editing facility
PT can do netlist editing
PT can do crosstalk analysis DC cant
PT can do variation analysis DC cant
bgs: get_allternate_cell is available in DC
me: ya.... u can try to find altrenative cells
thats all
but ofcourse DC can do incremental compilation
bgs: in DC flow if timing is not met will they change constraints or its fixed
me: more important is with PT there are several designs successfully taped out !!!!!
u have two options... improve ur HDL code....if still doesnt work..u have to change constraints itself ..but this is last option
bgs: if constaints r not realistic?
me: what u mean by realistic?
bgs: for example u have clock period is 3 inputdelay is 2
me: input and out delays are always exceptional cases and those can controlled depending on external interfaces...
bgs: ya ur ri8
me: bgs..... let me take a cup of coffeeee
bgs: but timinig is not met
me: i will come back later
bgs: k carry on

18 minutes

me: u can shoot again.....but timinig is not met.....wht is the question

19 minutes

me: gayab???
bgs: ya im back
my question was do i have n option of changing constraints if its not met
as synthesis engineer what all constraints i can change
?
me: welll.... frankly speaking we cant change constraints at logic synthesis stage (physical synthesis onwards we have a little control on constraints !!)
with the available clock if u cant meet timing even after improvement in code, logic and data path optimizations in DC then the left option is to increase clock period itself !
bgs: do u mean to say clk source, n/w latency, uncertainity will given as spec
me: as a part of spec u wont get latency etc....u will get only clock frequency...thats what u have to cahnge finally
bgs: ya then can i play with uncertainity , input n output dely?
max n min delay
me: to certain extent.... provided that if u have back annotated info of similar designs implemented in previous designs....
but at first itself u have modeled everything based on previous design experiences...
then u cant relax those constraints further
bgs: what about drc constraints? can i change them
me: u can provided if u dont have problem with timing and power and reliability !
bgs: k
me: becuase ur timing may be ok but there may be drc violations...in that case power consumption can be more
bgs: so if can i change constraints(not clk period
) n met timing
me: and also imagine a person can carry 50kg... then he can go for 5 kms... now imagine same person is forced to carry 100 kg...can he walk 5kms (reliability issue)?
bgs: hm
me: if u have modeled ur constraints properly then there is no room to change it...
but if u have over constrained the design at first then u got violation...in that case u can relax constraints
bgs: k
so in DC we play with constaints n fix them
me: no..we play with data path optimizations and logic optimizations to achieve timing...
we play with low vt cells and high vt cells to meet timing and power
bgs: hey that we do in
PT
me: but remember...PT is mainly used for analysis
PT wont do any optimization by itself
bgs: k, in dc we make sure violation is clear then y PT?
me: as i said PT timing engine is more robust.... more accurate compared to DC..hence get clearance from PT as well
bgs: ok
one more doubt yar in pt im geting some violation what all option i have other than swap cell to clear violation
me: size the cell
before sizing try to see bottleneck cost
see the depth of data path...if it is large then probably it is better to send the netlist back to synthesis stage
for data path optimizations
bgs: size the cell is increasing drive strength only na
r some thing else?
me: u can increase or decrease...depending on the delay offered by the cell...
also u can add buffers just before a cell which is causing larger delay..
also recalculate path delay with true path analysis...
this u can get with path inspector
bgs: how to add buffer i have not tryed that option
what does recalculate path delay with true path analysis... do?
me: get_recalculated_timing_paths -from xyz -to abc
insert_buffer/remove_buffer
bgs: what does this do buy recalculating timing path?
me: u have to provide buffer name and cell name
bgs: by*
when will we use get_recalculated_timing_paths -from xyz -to abc
me: if u have small violations and less number of violations then use recalcu***
bgs: k
thanku so much
:)
me: what happens in general is while calculating delays worst delay corresponding to different timing arc is considered
hence timing analysis becomes pessimistic....
to make it more accurate tell the tool to calculate timing based on actual true timing arcs
when u do this u may not get any violation...in that case u can tape out !!!!!
hey bgs ....i am leaving now.... see u tomorrow for any more questions.....
hope u r happy now with so many cleared doubts..
bgs: hey thanks yar u gave ur valuable time!!!
ya im :-
)
:-)
me: have a great eve!

Companywise ASIC/VLSI Interview Questions

2008-07-07T10:24:00.010+05:30

Senior Physical design engineer position,

Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be answered in coming blogs.

Common introductory questions every interviewer asks are:

Discuss about the projects worked in the previous company.
What are physical design flows, various activities you are involved?
Design complexity, capacity, frequency, process technologies, block size you handled.

Intel

Why power stripes routed in the top metal layers?

Senior Physical design engineer position,

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Senior Physical design engineer position,

Answer:

This approach allows routability of the design and better usage of routing resources.

What are several factors to improve propagation delay of standard cell?

Senior Physical design engineer position,

Answer:

Improve the input transition to the cell under consideration by up sizing the driver.
Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

How do you compute net delay (interconnect delay) / decode RC values present in tech file?
What are various ways of timing optimization in synthesis tools?

Senior Physical design engineer position,

Answer:

Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.

Less number of logics between Flip Flops speedup the design.

Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.

Better selection of design ware component (select timing optimized design ware components).

Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.

What would you do in order to not use certain cells from the library?

Senior Physical design engineer position,

Answer:

Set don’t use attribute on those library cells.

How delays are characterized using WLM (Wire Load Model)?

Answer:

Senior Physical design engineer position, For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.

Fanout vs net length is tabulated in WLMs.

Values of unit resistance R and unit capacitance C are given in technology file.

Net length varies based on the fanout number.

Once the net length is known delay can be calculated; Sometimes it is again tabulated.

What are various techniques to resolve congestion/noise?

Senior Physical design engineer position,

Answer:

Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.

Noise can be reduced by optimizing the overlap of nets in the design.

Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

Senior Physical design engineer position,

Answer:

No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??

How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?

Senior Physical design engineer position,

Answer:

Better skew targets and insertion delay values provided while building the clocks.

Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.

For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

What are pros/cons of latch/FF (Flip Flop)?

Answer: Pros and cons of latch and flip flop

How you go about fixing timing violations for latch- latch paths?
As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
What are various formal verification issues you faced and how did you resolve?
How do you calculate maximum frequency given setup, hold, clock and clock skew?
What are effects of metastability?

Answer: Metastability

Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
How to solve cross clock timing path?
How to determine the depth of FIFO/ size of the FIFO?

Answer: FIFO Depth

STmicroelectronics

What are the challenges you faced in place and route, FV (Formal Verification), ECO (Engineering Change Order) areas?
How long the design cycle for your designs?
What part are your areas of interest in physical design?
Explain ECO (Engineering Change Order) methodology.
Explain CTS (Clock Tree Synthesis) flow.

Answer: Clock Tree Synthesis

What kind of routing issues you faced?
How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
Define hash/ @array in perl.
Using TCL (Tool Command Language, Tickle) how do you set variables?
What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
What are nanoroute options for search and repair?
What were your design skew/insertion delay targets?
How is IR drop analysis done? What are various statistics available in reports?
Explain pin density/ cell density issues, hotspots?
How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
What is the command for setting multi cycle path?
If hold violation exists in design, is it OK to sign off design? If not, why?

Texas Instruments (TI)

How are timing constraints developed?
Explain timing closure flow/methodology/issues/fixes.
Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
What are synthesis strategies to optimize timing?
Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

Qualcomm

In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
Can a single port have multi-clocked? How do you set delays for such ports?
How is scan DEF (Design Exchange Format) generated?
What is purpose of lockup latch in scan chain?
Explain short circuit current.

Answer: Short Circuit Power

What are pros/cons of using low Vt, high Vt cells?

Answer:
Multi Threshold Voltage Technique
Issues With Multi Height Cell Placement in Multi Vt Flow

How do you set inter clock uncertainty?

Senior Physical design engineer position,

Answer:

set_clock_uncertainty –from clock1 -to clock2

In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer:
Senior Physical design engineer position,

Difference in clock uncertainty values; Clocks are propagated in post CTS.

In post CTS clock latency constraint is modified to model clock jitter.

How is clock gating done?

Answer: Clock Gating

What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Senior Physical design engineer position,

Answer:

Make the clock gating cells as through pins.

What is trade off between dynamic power (current) and leakage power (current)?

Answer:
Leakage Power Trends
Dynamic Power

How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques

Explain top level pin placement flow? What are parameters to decide?
Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
With net length of 1000um how will you compute RC values, using equations/tech file info?
What do noise reports represent?
What does glitch reports contain?
What are CTS (Clock Tree Synthesis) steps in IC compiler?
What do clock constraints file contain?
How to analyze clock tree reports?
What do IR drop Voltagestorm reports represent?
Where /when do you use DCAP (Decoupling Capacitor) cells?
What are various power reduction techniques?

Answer: Low Power Design Techniques

Hughes Networks

What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations?
Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
What are tested in DFT (Design for Testability)?
In equivalence checking, how do you handle scanen signal?
In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the propagation delay?
What are power dissipation components? How do you reduce them?

Answer:
Short Circuit Power
Leakage Power Trends
Dynamic Power
Low Power Design Techniques

How delay affected by PVT (Process-Voltage-Temperature)?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

Why is power signal routed in top metal layers?

Avago Technologies (former HP group)

How do you minimize clock skew/ balance clock tree?
Given 11 minterms and asked to derive the logic function.
Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 switch is open and one end having 5v and other end zero voltage; compute the voltage across C2 when the switch is closed?
Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor) inverter? Show IO (Input-Output) characteristics curve.
Implement a ring oscillator.
How to slow down ring oscillator?

Hynix Semiconductor

How do you optimize power at various stages in the physical design flow?
What timing optimization strategies you employ in pre-layout /post-layout stages?
What are process technology challenges in physical design?
Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.
What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?
Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic. Which path is fastest path to have hold violation and how will you resolve?
What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?
Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse width.

About Contributor

ASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure, process technologies.

Readers are encouraged to discuss answers to these questions. Just click on the 'post a comment' option below and put your comments there. Alternatively you can send your answers/discussions to my mail id: shavakmm@gmail.com

Draw XNOR gate using MUX.

2008-06-18T11:44:00.002+05:30

Draw XOR gate using MUX.

2008-06-18T11:42:00.001+05:30

Draw NOR gate using MUX.

2008-06-18T11:41:00.001+05:30

Draw NAND gate using MUX.

2008-06-18T11:37:00.003+05:30

Draw OR gate using 2:1 MUX.

2008-06-18T11:27:00.005+05:30

Applying similar concept of AND gate using 2:1 MUX, make either of input A or B as select line of MUX, connect other input to 0th input line. 1st input of the MUX is always tied to logic 1.

Related faq

AND gate using MUX
NAND gate using MUX
NOR gate using MUX
XOR gate using MUX
XNOR using MUX

How to get AND gate using 2:1 MUX?

2008-06-17T09:14:00.012+05:30

Look at the truth table of AND gate. When any of the one input is zero output is always zero (or same as that input); when the other input is one, output is dependent on the other input and is same as the other input. Using this property we can draw AND gate in four different ways using 2:1 MUX as shown in the above figure.

Similar concept can be applied to create all basic gates from 2:1 MUX. I will publish all these in coming blog posts along with the elaborated figures.

Related faq

OR gate using MUX
NAND gate using MUX
NOR gate using MUX
XOR gate using MUX
XNOR using MUX

Metastability, Reset

2008-05-22T11:16:00.001+05:30

What is metastability?

When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastability.

What is MTBF? What it signifies?

MTBF-Mean Time Before Failure

Average time to next failure

How chance of metastable state failure can be reduced?

Lowering clock frequency
Lowering data speed
Using faster flip flop

What are the advantages of using synchronous reset ?

No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care).

Simulation of synchronous reset is easy.

What are the disadvantages of using synchronous reset ?

Synchronous reset is slow.

Implementation of synchronous reset requires more number of gates compared to asynchronous reset design.

An active clock is essential for a synchronous reset design. Hence you can expect more power consumption.

What are the advantages of using asynchronous reset ?

Implementation of asynchronous reset requires less number of gates compared to synchronous reset design.

Asynchronous reset is fast.

Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.

What are the disadvantages of using asynchronous reset ?

Metastability problems are main concerns of asynchronous reset scheme (design).

Static timing analysis and DFT becomes difficult due to asynchronous reset.

What are the 3 fundamental operating conditions that determine the delay characteristics of gate?
How operating conditions affect gate delay?

Process
Voltage
Temperature

Click here to read more.

Is verilog/VHDL is a concurrent or sequential language?

Verilog and VHDL both are concurrent languages.

Any hardware descriptive language is concurrent in nature.

In a system with insufficient hold time, will slowing down the clock frequency help?

Making data path slower can help hold time but it may result in setup violation.

In a system with insufficient setup time, will slowing down the clock frequency help?

Yes.

Making data path faster can also help setup time but it may result in hold violation.

Physical Design Objective Type of Questions and Answers

2008-04-08T14:28:00.007+05:30

1) Chip utilization depends on ___.

a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

2) In Soft blockages ____ cells are placed.

a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

3) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

4) Delay between shortest path and longest path in the clock is called ____.

a. Useful skew
b. Local skew
c. Global skew
d. Slack

5) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets

6) Prerouting means routing of _____.

a. Clock nets
b. Signal nets
c. IO nets
d. PG nets

7) Which of the following metal layer has Maximum resistance?

a. Metal1
b. Metal2
c. Metal3
d. Metal4

8) What is the goal of CTS?

a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

9) Usually Hold is fixed ___.

a. Before Placement
b. After Placement
c. Before CTS
d. After CTS

10) To achieve better timing ____ cells are placed in the critical path.

a. HVT
b. LVT
c. RVT
d. SVT

11) Leakage power is inversely proportional to ___.

a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

12) Filler cells are added ___.

a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing

13) Search and Repair is used for ___.

a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

14) Maximum current density of a metal is available in ___.

a. .lib
b. .v
c. .tf
d. .sdc

15) More IR drop is due to ___.

a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

16) The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

17) CRPR stands for ___.

a. Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

18) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths

19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

20) The Solution for Antenna effect is ___.

a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

21) To avoid cross talk, the shielded net is usually connected to ___.

a. VDD
b. VSS
c. Both VDD and VSS
d. Clock

22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup
b. Hold
c. Both
d. None

23) Hold violations are preferred to fix ___.

a. Before placement
b. After placement
c. Before CTS
d. After CTS

24) Which of the following is not present in SDC ___?

a. Max tran
b. Max cap
c. Max fanout
d. Max current density

25) Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delays
b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays

26) Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation
b. Hold violation
c. Skew
d. None

27) Which of the following is best suited for CTS?

a. CLKBUF
b. BUF
c. INV
d. CLKINV

28) Max voltage drop will be there at(with out macros) ___.

a. Left and Right sides
b. Bottom and Top sides
c. Middle
d. None

29) Which of the following is preferred while placing macros ___?

a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O

30) Routing congestion can be avoided by ___.

a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

31) Pitch of the wire is ___.

a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

32) In Physical Design following step is not there ___.

a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS

33) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1ns
b. 3ns
c. 5ns
d. 6ns

36) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

37) Which configuration is more preferred during floorplaning ?

a. Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

38) What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

39) Delay of a cell depends on which factors ?

a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

40) After the final routing the violations in the design ___.

a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

41) Utilisation of the chip after placement optimisation will be ___.

a. Constant
b. Decrease
c. Increase
d. None of the above

42) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

43) What are preroutes in your design?

a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

44) Clock tree doesn't contain following cell ___.

a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above

Answers:

1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c

PVT, Derarting and STA

2008-03-29T12:15:00.001+05:30

What is the derate value that can be used?

For setup check derate data path by 8% to 15%, no derate in the clock path.
For hold check derate clock path by 8% to 15%, no derate in the data path.

What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?

Corners: Worst, Best, Typical.
Same derating value for best and worst.For typical it can be less.

Write Setup and Hold equtions?

Setup equation: Tlaunch clock + Tclk-q_max + Tcombo_max <= Tcapute clock - (Tsetup+skew)
Hold equation: Tlaunch clock + Tclk-q_min + Tcombo_min >= Tcapture clock + (Thold-skew)

Where do you get the WLM's? Do you create WLM's? How do you specify?

Wire Load Models (WLM) are available from the library vendors.
We dont create WLM.
WLMs can be specified depending on the area.

Where do you get the derating value? What are the factors that decide the derating factor?

Based on the guidelines and suggestions from the library vendor and previous design experience derating value is decided.
PVT variation is the factor that decides the derating factor.

What factors decides the setup time of flip-flop?

D- pin transition and clock transition.

Why dont you derate the clock path by -10% for worst corner analysis?

We can do. But it may not be accurate as the data path derate.

Backend (Physical Design) Interview Questions and Answers

2008-03-12T14:10:00.003+05:30

Below are the sequence of questions asked for a physical design engineer.

In which field are you interested?

Answer to this question depends on your interest, expertise and to the requirement for which you have been interviewed.

Well..the candidate gave answer: Low power design

Can you talk about low power techniques?
How low power and latest 90nm/65nm technologies are related?

Refer here and browse for different low power techniques.

Do you know about input vector controlled method of leakage reduction?

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.

How can you reduce dynamic power?

-Reduce switching activity by designing good RTL
-Clock gating
-Architectural improvements
-Reduce supply voltage
-Use multiple voltage domains-Multi vdd

What are the vectors of dynamic power?

Voltage and Current

How will you do power planning?

Refer here for power planning.

If you have both IR drop and congestion how will you fix it?

-Spread macros
-Spread standard cells
-Increase strap width
-Increase number of straps
-Use proper blockage

Is increasing power line width and providing more number of straps are the only solution to IR drop?

-Spread macros
-Spread standard cells
-Use proper blockage

In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?

(buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !)

Near to capture path.

Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack.

How will you decide best floorplan?

Refer here for floor planning.

What is the most challenging task you handled?
What is the most challenging job in P&R flow?

-It may be power planning- because you found more IR drop
-It may be low power target-because you had more dynamic and leakage power
-It may be macro placement-because it had more connection with standard cells or macros
-It may be CTS-because you needed to handle multiple clocks and clock domain crossings
-It may be timing-because sizing cells in ECO flow is not meeting timing
-It may be library preparation-because you found some inconsistancy in libraries.
-It may be DRC-because you faced thousands of voilations

How will you synthesize clock tree?

-Single clock-normal synthesis and optimization
-Multiple clocks-Synthesis each clock seperately
-Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew

How many clocks were there in this project?

-It is specific to your project
-More the clocks more challenging !

How did you handle all those clocks?

-Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree

Are they come from seperate external resources or PLL?

-If it is from seperate clock sources (i.e.asynchronous; from different pads or pins) then balancing skew between these clock sources becomes challenging.

-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy.

Why buffers are used in clock tree?

To balance skew (i.e. flop to flop delay)

What is cross talk?

Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.

How can you avoid cross talk?

-Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength

How shielding avoids crosstalk problem? What exactly happens there?

-High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS.

Coupling capacitance remains constant with VDD or VSS.

How spacing helps in reducing crosstalk noise?

width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk

Why double spacing and multiple vias are used related to clock?

Why clock?-- because it is the one signal which chages it state regularly and more compared to any other signal. If any other signal switches fast then also we can use double space.

Double spacing=>width is more=>capacitance is less=>less cross talk

Multiple vias=>resistance in parellel=>less resistance=>less RC delay

How buffer can be used in victim to avoid crosstalk?

Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor.

Physical Design Questions and Answers

2008-02-16T17:11:00.006+05:30

I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy !

What parameters (or aspects) differentiate Chip Design and Block level design?

Chip design has I/O pads; block design has pins.

Chip design uses all metal layes available; block design may not use all metal layers.

Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.

Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?

First check flylines i.e. check net connections from macro to macro and macro to standard cells.

If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.

If input pin is connected to macro better to place nearer to that pin or pad.

If macro has more connection to standard cells spread the macros inside core.

Avoid criscross placement of macros.

Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?

Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.

Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?

500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?

Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?

Netlist, Technology library, Constraints, SPEF or SDF file.

If the routing congestion exists between two macros, then what will you do?

Provide soft or hard blockage

How will you decide the die size?

By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?

Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!

Metal layers: See your tech file. generally for 90nm it is 7 to 9.

Technology: Again look into tech files.

Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc

Clocks: Look into your design and SDC file !

How many macros in your design?

You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?

Depends on your design.

What are the input needs for your design?

For synthesis: RTL, Technology library, Standard cell library, Constraints

For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?

Clock definitions

Timing exception-multicycle path, false path

Input and Output delays

How did you do power planning?

How to calculate core ring width, macro ring width and strap or trunk width?

How to find number of power pad and IO power pads?

How the width of metal and number of straps calculated for power and ground?

Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.

How to find total chip power?

Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?

Prelayout: Setup, Max transition, max capacitance

Post layout: Hold

How did you resolve the setup and hold problem?

Setup: upsize the cells

Hold: insert buffers

In which layer do you prefer for clock routing and why?

Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?

Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?

Increase power metal layer width.

Go for higher metal layer.

Spread macros or standard cells.

Provide more straps.

Define antenna problem and how did you resolve these problem?

Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.

Decrease the length of the net by providing more vias and layer jumping.

Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.

P increase->dealy increase

P decrease->delay decrease

V increase->delay decrease

V decrease->delay increase

T increase->delay increase

T decrease->delay decrease

Explain the flow of physical design and inputs and outputs for each step in flow.

Click here to see the flow diagram

What is cell delay and net delay?

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

Gate delay =function of(i/p transition time, Cnet+Cpin).

Cell delay is also same as Gate delay.

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?

Linear Delay Model (LDM)

Non Linear Delay Model (NLDM)

What is wire load model?

Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?

Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.

Upsizing

Downsizing

Buffer insertion

Buffer relocation

Dummy buffer placement

What is the significance of negative slack?

negative slack==> there is setup voilation==> deisgn can fail

What is signal integrity? How it affects Timing?

IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.

If Idrop is more==>delay increases.

crosstalk==>there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?

There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.

If IR drop is more==>delay increases.

What is EM and it effects?

Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.

Affects: Either short or open of the signal line or power line.

What are types of routing?

Global Routing

Track Assignment

Detail Routing

What is latency? Give the types?

Source Latency

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

Delay from clock source to beginning of clock tree (i.e. clock definition point).

The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network latency

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?

Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?

If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?

Routing

What are clock trees?

Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?

H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?

Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.

Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

What is the difference between a latch and a flip-flop?

2008-01-14T20:32:00.000+05:30

Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.

They both are hence referred as "sequential" elements.

In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably. [wiki]

In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.[wiki]

A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.

Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.

A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)

A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.

Latches are faster, flip flops are slower.

Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.

Latches take less gates (less power) to implement than flip-flops.

D-FF is built from two latches. They are in master slave configuration.

Latch may be clocked or clock less. But flip flop is always clocked.

For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.

Synthesis perspective: Pros and Cons of Latches and Flip Flops

In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:"if" and "case" statements. This should be avoided sa latches are more prone to glitches.

Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .

Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.

Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable" and "scan_enable" signals as input and feed the output to the enable port of the latch. [ref]

Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.

If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team.

Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch. Read a good article on problems of latch published in eetimes long back !!

Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

What are the different types of delays in ASIC or VLSI design?

2007-12-19T23:58:00.000+05:30

Different Types of Delays in ASIC or VLSI design

Source Delay/Latency

Network Delay/Latency

Insertion Delay

Transition Delay/Slew: Rise time, fall time

Path Delay

Net delay, wire delay, interconnect delay

Propagation Delay

Phase Delay

Cell Delay

Intrinsic Delay

Extrinsic Delay

Input Delay

Output Delay

Exit Delay

Latency (Pre/post CTS)

Uncertainty (Pre/Post CTS)

Unateness: Positive unateness, negative unateness

Jitter: PLL jitter, clock jitter

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

Gate delay =function of(i/p transition time, Cnet+Cpin).

Cell delay is also same as Gate delay.

Source Delay (or Source Latency)

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

Delay from clock source to beginning of clock tree (i.e. clock definition point).

The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network Delay(latency)

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

Insertion delay

The delay from the clock definition point to the clock pin of the register.

Transition delay

It is also known as "Slew". It is defined as the time taken to change the state of the signal. Time taken for the transition from logic 0 to logic 1 and vice versa . or Time taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa.

Transition is the time it takes for the pin to change state.

Slew

Rate of change of logic.See Transition delay.

Slew rate is the speed of transition measured in volt / ns.

Rise Time

Rise time is the difference between the time when the signal crosses a low threshold to the time when the signal crosses the high threshold. It can be absolute or percent.

Low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.

Fall Time

Fall time is the difference between the time when the signal crosses a high threshold to the time when the signal crosses the low threshold.

The low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.

For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric triangular wave, this is reduced to just 50%.

Click here to see waveform.

Click here to see more info.

The rise/fall definition is set on the meter to 10% and 90% based on the linear power in Watts. These points translate into the -10 dB and -0.5 dB points in log mode (10 log 0.1) and (10 log 0.9). The rise/fall time values of 10% and 90% are calculated based on an algorithm, which looks at the mean power above and below the 50% points of the rise/fall times. Click here to see more.

Path delay

Path delay is also known as pin to pin delay. It is the delay from the input pin of the cell to the output pin of the cell.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

Wire delay =fn(Rnet , Cnet+Cpin)

Propagation delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

This is the time required for a signal to propagate through a gate or net. For gates it is the time it takes for a event at the gate input to affect the gate output.

For net it is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

Phase delay

Same as insertion delay

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Extrinsic delay

Same as wire delay, net delay, interconnect delay, flight time.

Extrinsic delay is the delay effect that associated to with interconnect. output pin of the cell to the input pin of the next cell.

Input delay

Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock.

Output delay

Output delay is time required by the external circuit before which the data has to arrive at the output pin of the block with respect to reference clock.

Exit delay

It is defined as the delay in the longest path (critical path) between clock pad input and an output. It determines the maximum operating frequency of the design.

Latency (pre/post cts)

Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered.

Uncertainty (pre/post cts)

Uncertainty is the amount of skew and the variation in the arrival clock edge. Pre CTS uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew + Jitter.

Unateness

A function is said to be unate if the rise transition on the positive unate input variable causes the ouput to rise or no change and vice versa.

Negative unateness means cell output logic is inverted version of input logic. eg. In inverter having input A and output Y, Y is -ve unate w.r.to A. Positive unate means cell output logic is same as that of input.

These +ve ad -ve unateness are constraints defined in library file and are defined for output pin w.r.to some input pin.

A clock signal is positive unate if a rising edge at the clock source can only cause a rising edge at the register clock pin, and a falling edge at the clock source can only cause a falling edge at the register clock pin.

A clock signal is negative unate if a rising edge at the clock source can only cause a falling edge at the register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock pin. In other words, the clock signal is inverted.

A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the clock path. For example, a clock that passes through an XOR gate is not unate because there are nonunate arcs in the gate. The clock sense could be either positive or negative, depending on the state of the other input to the XOR gate.

Jitter

The short-term variations of a signal with respect to its ideal position in time.

Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value.

From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform.

Sources of Jitter

Common sources of jitter include:

Internal circuitry of the phase-locked loop (PLL)

Random thermal noise from a crystal

Other resonating devices

Random mechanical noise from crystal vibration

Signal transmitters

Traces and cables

Connectors

Receivers

Click here to read more about jitter from Altera.

Click here to read what wiki says about jitter.

Skew

The difference in the arrival of clock signal at the clock pin of different flops.

Two types of skews are defined: Local skew and Global skew.

Local skew

The difference in the arrival of clock signal at the clock pin of related flops.

Global skew

The difference in the arrival of clock signal at the clock pin of non related flops.

Skew can be positive or negative.

When data and clock are routed in same direction then it is Positive skew.

When data and clock are routed in opposite then it is negative skew.

Recovery Time

Recovery specifies the minimum time that an asynchronous control input pin must be held stable after being de-asserted and before the next clock (active-edge) transition.

Recovery time specifies the time the inactive edge of the asynchronous signal has to arrive before the closing edge of the clock.

Recovery time is the minimum length of time an asynchronous control signal (eg.preset) must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals.

Equation 1:

Recovery Slack Time = Data Required Time â€“ Data Arrival Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq+ Register to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register =Tsetup

If the asynchronous control is not registered, equations shown in Equation 2 is used to calculate the recovery slack time.

Equation 2:

Recovery Slack Time = Data Required Time â€“ Data Arrival Time

Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay+Tsetup

If the asynchronous reset signal is from a port (device I/O), you must make an Input Maximum Delay assignment to the asynchronous reset pin to perform recovery analysis on that path.

Removal Time

Removal specifies the minimum time that an asynchronous control input pin must be held stable before being de-asserted and after the previous clock (active-edge) transition.

Removal time specifies the length of time the active phase of the asynchronous signal has to be held after the closing edge of clock.

Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. Calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous control is registered, equations shown in Equation 3 is used to calculate the removal slack time.

If the recovery or removal minimum time requirement is violated, the output of the sequential cell becomes uncertain. The uncertainty can be caused by the value set by the resetbar signal or the value clocked into the sequential cell from the data input.

Equation 3

Removal Slack Time = Data Arrival Time â€“ Data Required Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq of Source Register + Register to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register + Thold

If the asynchronous control is not registered, equations shown in Equation 4 is used to calculate the removal slack time.

Equation 4

Removal Slack Time = Data Arrival Time â€“ Data Required Time

Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register +Thold

If the asynchronous reset signal is from a device pin, you must specify the Input Minimum Delay constraint to the asynchronous reset pin to perform a removal analysis on this path.

For more detail about recovery and removal time click here.

What is the difference between soft macro and hard macro?

2007-11-30T18:24:00.000+05:30

What is the difference between hard macro, firm macro and soft macro?

What are IPs?

Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other designs.

Soft macros

Soft macros are in synthesizable RTL.

Soft macros are more flexible than firm or hard macros.

Soft macros are not specific to any manufacturing process.

Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power.

Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data.

From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro Rail user manual !)

Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

Firm macros

Firm macros are in netlist format.

Firm macros are optimized for performance/area/power using a specific fabrication technology.

Firm macros are more flexible and portable than hard macros.

Firm macros are predictive of performance and area than soft macros.

Hard macro

Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).

Hard macos are targeted for specific IC manufacturing technology.

Hard macros are block level designs which are silicon tested and proved.

Hard macros have been optimized for power or area or timing.

In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way.

You have freedom to move, rotate, flip but you can't touch anything inside hard macros.

Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general).. for example it can be a MP4 decoder.

Be aware of features and characteristics of hard macro before you use it in your design... other than power, timing and area you also should know pin properties like sync pin, I/O standards etc

LEF, GDS2 file format allows easy usage of macros in different tools.

From the physical design (backend) perspective:

Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in Magma) as a GDS2 file.

Here is one article published in embedded magazine about IPs. Click here to read.

Synthesis and placement of macros in modern SoC designs are challenging. EDA tools employ different algorithms accomplish this task along with the target of power and area. There are several research papers available on these subjects. Some of them can be downloaded from the given link below.

"Hard Macro Placement in Complex SoC Design" - view and read article from soccentral

"Hard Macro Placement in Complex SoC Design" - download white paper

IEEE/Univerity research papers

"Local Search for Final Placement in VLSI Design" - download

"Consistent Placement of Macro-Blocks Using Floorplanning and standard cell placement" - download

"A Timing-Driven Soft-Macro Placement And Resynthesis Method In Interaction with Chip Floorplanning" - download

What is the difference between FPGA and CPLD?

2007-11-17T17:24:00.000+05:30

FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device-- both are programmable logic devices made by the same companies with different characteristics.

"A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations".

This is what Wiki defines.....!!

Click here to see what else wiki has to say about it !

Architecture

Granularity is the biggest difference between CPLD and FPGA.

FPGA are "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories.FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available.

CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.

CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops and combinational logic. CPLDs based on AND-OR structure.

CPLD's have a register with associated logic (AND/OR matrix). CPLD's are mostly implemented in control applications and FPGA's in datapath applications. Because of this course grained architecture, the timing is very fixed in CPLDs.

FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once.

FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA.

Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.

The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA.

Click here to read one good article.

Features

FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this.

FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500>

Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment).

Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue.

Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families.

Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage.

Use FPGAs for larger and more complex designs.

Click here to read what Xilinx has to say about it.

FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result.

As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future.

There are people who discuss about this. Click here to listen them.

Finally here is one pdf document whcih is downloadable: "Architecture of FPGAs and CPLDs: A Tutorial" Download

Hoping that information and references helps you ....... comments and further references are welcome !

What is the difference between FPGA and ASIC?

2007-11-06T19:33:00.000+05:30

This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.

FPGA vs. ASIC

Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.

FPGA

Field Programable Gate Arrays

FPGA Design Advantages

Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!

No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!

Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.

Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.

Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

FPGA sythesis is much more easier than ASIC.

In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

FPGA Design Disadvantages

Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

You have to use the resources available in the FPGA. Thus FPGA limits the design size.

Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

ASIC

Application Specific Intergrated Circiut

ASIC Design Advantages

Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

ASIC Design Diadvantages

Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)

Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

Structured ASICS

Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.

Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.

Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.

FPGA vs. ASIC Design Flow Comparison

http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm

In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves?

2007-10-29T19:38:00.000+05:30

Answer:

For designs with both positive and negative clocked flops, the scan insertion tool will always route the scan chain so that the negative clocked flops come before the positive edge flops in the chain. This avoids the need of lockup latch.

For the same clock domain the negedge flops will always capture the data just captured into the posedge flops on the posedge of the clock.

For the multiple clock domains, it all depends upon how the clock trees are balanced. If the clock domains are completely asynchronous, ATPG has to mask the receiving flops.

What is difference between normal buffer and clock buffer?

2007-10-29T19:36:00.000+05:30

Answer:

Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle of clock signal from changing when it passes through a chain of clock buffers.

Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum. They too are designed for higher drive strength.

What is difference between HFN synthesis and CTS?

2007-10-29T19:34:00.000+05:30

Answer:

HFNs are synthesized in front end also.... but at that moment no placement information of standard cells are available... hence backend tool collapses synthesized HFNs. It resenthesizes HFNs based on placement information and appropriately inserts buffer. Target of this synthesis is to meet delay requirements i.e. setup and hold.

For clock no synthesis is carried out in front end (why.....????..because no placement information of flip-flops ! So synthesis won't meet true skew targets !!) ... in backend clock tree synthesis tries to meet "skew" targets...It inserts clock buffers (which have equal rise and fall time, unlike normal buffers !)... There is no skew information for any HFNs.

Is it possible to have a zero skew in the design?

2007-10-29T19:33:00.000+05:30

Answer:

Theoretically it is possible....!

Practically it is impossible....!!

Practically we cant reduce any delay to zero.... delay will exist... hence we try to make skew "equal" (or same) rather than "zero"......now with this optimization all flops get the clock edge with same delay relative to each other.... so virtually we can say they are having "zero skew " or skew is "balanced".

What you mean by scan chain reordering?

2007-10-29T19:28:00.000+05:30

Answer1:

Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it.... it maintains the number of flops in a chain.

Answer2:

During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion.

This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains.

Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.

On what basis we decide the clock frequency in any design?

2007-10-29T19:19:00.000+05:30

Answer:

There are several factors. Important of them are:

1) Input and output data rate : For example if you are designing any encryptor or decryptor you need minimum 100 MHz

2) Power: Higher the frequency more the power consumption

3)Accuracy of the results required: If higher accuracy is not needed RC oscillator can be used which saves area... and everything we want in compact size..... but RC cant produce higher frequency !

4) Technology: Lower the node more speed (also more power....again trade off !!).... how much fast we want ?

5) Target platform: Is it FPGA or custom ASIC.... naturally ASIC can give higher clok frequency... but FPGA frequency of operation is limited by several other factors