Jobs in India

Silicon Validation Engineers required for KPIT Cummins, Bangalore

noreply@blogger.com (Sandeep Gor) — Wed, 10 Feb 2010 05:54:00 +0000

Silicon Validation Engineers

Experience: 3 to 5 years

No. of Positions: 6

Education: BE / BTech / ME / MTech

Location: Bangalore

Job description:

Develop validation scripts/drivers for the validation of hardware modules in the SOC
Create validation specifications
Run the SOC validation tests, Capture the observations and generate validation test reports
Identify the bugs in silicon,

Contact: getjobsinindia2007@gmail.com

PDK engineers required for Cadence Design Systems, Bangalore

noreply@blogger.com (Sandeep Gor) — Fri, 05 Feb 2010 10:33:00 +0000

Process Development Kit (PDK) Engineer as Lead/Senior Services AE

Experience: 3 to 8 years

Education: BE / BTech / ME / MTech

Location: Bangalore

Job description:

This engineer’s primary role will be to work in a team oriented environment to create, customize and maintain Process Design Kits (PDKS) for Cadence technology.

He/she will interact and work with other engineers on the worldwide PDK delivery team.

Responsibilities:

Understanding and interpreting integrated circuit process technologies in order to implement specifications for Cadence optimized Process Design Kits (PDKs).
Development and maintenance of PDKs includes creation of techfiles, symbols, PCells, Call Backs, CDFs, netlisting and the creation of Qualification data.
Proficient with the use of PDK automation tools is a plus.
The engineer must have a solid background in circuits, electronics and physics and should either have or be capable of learning new technical and consulting skills.
The candidate should possess the necessary engineering and/or consultancy skills, i.e. that he/she is technically excellent with mature communication skills to be able to consult effectively with clients, e.g. to communicate with Customers.
Contribute to training activities

Requirements:

Execution on VCAD Customer support projects, e.g. Implementation and testing of PDKs, their components, methodology support, operation and maintenance of VCAD design environments.
Design Support in VCAD Customer Design projects, both remotely and onsite.
VCAD Methodology Service Engagements, e.g. Implementation and testing of PDKs, methodology development, operation and maintenance of VCAD design environments.
Ability to undertake design environment implementation tasks alone and architectural tasks with support within the first year.
Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English.
Acquire a basic understanding of the (service) business environment of Cadence within 1 month including pre sales support.

Contact: getjobsinindia2007@gmail.com

C++ Developers required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Wed, 03 Feb 2010 06:47:00 +0000

C++ Developers

Experience: 7+ yrs

Education: BE / BTech / ME / MTech

Location: NOIDA

Skills:

An excellent command in C and C++ programming
Electronics/EDA experience

Contact: getjobsinindia2007@gmail.com

Technical Education Services Engineer required for Cadence Design Systems, NOIDA / Bangalore

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 13:45:00 +0000

Technical Education Services Engineer

Experience: 3-5 yrs

Education: BE / BTech / ME / MTech

Location: NOIDA/Bangalore

Skills:

Practical knowledge of model development in spice, verilog, verilog-a and vhdl
Solid understanding of CMOS analog circuit design techniques and circuit layout considerations
Experience in simulation/validation of mixed signal ASIC’s
Hands on development of analog/mixed signal flows and methodologies
Proficiency in the following front end CAD tools

Contact: getjobsinindia2007@gmail.com

Configuration Management Engineer required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 13:03:00 +0000

Configuration Management Engineer

Experience: 3-7 yrs

Education: BE / BTech / ME / MTech

Location: NOIDA

Skills:

Experience of working on the UNIX platform and usage of a Version Control tool like CVS is a must and Knowledge of PERL and UNIX shell scripting is a plus
Candidate should be familiar with MAKE, and compilation process
CVS experience is a strong match
Work experience in multi-team, multi-sited projects is a plus
Experience in working with computing clusters/ server farms/ grid computing is a definite plus

Contact: getjobsinindia2007@gmail.com

Sr. Technical Writer required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 12:55:00 +0000

Sr. Technical Writer

Experience: 3+ yrs

Education: BE / BTech / ME / MTech

Location: NOIDA

Skills:

Ability to comprehend technical concepts with experience in creating end-user and system-level documentation and help systems for complex software
Thorough knowledge of technical writing concepts
An excellent command over English, with good editing and proof-reading skills
Proficiency in FrameMaker, Webworks, and MS-Office tools
Electronics/EDA experience preferred but not mandatory

Contact: getjobsinindia2007@gmail.com

Project Lead required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 12:49:00 +0000

Project Lead

Experience: 7-10 yrs

Education: BE / BTech

Location: NOIDA

Job Description:

Manages the planning, development, and implementation of procedures for the testing and evaluation of support website
Specifies tests to be performed, compiles data, and makes recommendations for changes required in testing procedures, processes, new testing requirements and/or design of testing environment
Selects, develops, and evaluates personnel to ensure the efficient operation of the function
Receives assignments in the form of objectives with goals and the process by which to meet goals
Management reviews work to measure meeting of objectives
Works on issues where analysis of situation or data requires review of relevant factors
Exercises judgment within defined procedures and policies to determine appropriate action
Erroneous decisions or failure to achieve results will cause delays in schedules
Frequently interacts with functional peer groups.

Technical Experience:

MS Office
MS Project
Website administration

Soft Skills:

Demonstrated ability to lead distributed project teams
Ability to gain cooperation of others
Experience in conducting presentations of technical information concerning specific projects or schedules

Contact: getjobsinindia2007@gmail.com

Project Manager required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 12:41:00 +0000

Project Manager

Experience: 7-10 yrs

Education: BE / BTech

Location: NOIDA

Job Description:

Project manager for project-based timecard system.
Business owner responsible for routine monitoring to ensure the system is operating efficiently, entry and business prioritization of occasional upgrades/improvements to the system per end-user demand, and yearly system upgrades at the beginning of each year.
Must have broad-based proficiency in SAP including but not limited to: creation and deletion of cost centers and work centers, mass upload of labor rates, expenditure reports, cost center reports, ww labor rate reports, removal or changing of employee hours, project creation and update, timecard noncompliance and numerous other profiles. Responsible for generation of time management reports as well as weekly/quarterly Excel-based timecard analysis for worldwide internal customer base.
Requires the ability to work cross functionally and respond to worldwide user base.

Technical Experience:

Substantial expertise with SAP (PF1, PR1, HRP-HCM) focused on Finance/Project Accounting/HR
Experience with electronic timecard systems
Deep expertise in MS Excel (merging multiple databases, writing and debugging VBE macros, usage of pivot tables)
Demonstrated project management experience

Soft Skills:

Demonstrated ability to quickly resolve unusual user issues & demands
Ability to work an extensive work schedule during quarterly and yearly closing periods in a global environment
Strong command of spoken English.

Contact: getjobsinindia2007@gmail.com

Sr. Support AE required for Cadence Design Systems, NOIDA

noreply@blogger.com (Sandeep Gor) — Tue, 30 Jun 2009 12:25:00 +0000

Sr. Support AE

Experience: 3-8 yrs

Education: BE / BTech / ME / MTech

Designation: Mid Level / Lead

Location: NOIDA

Job Description:

The Support Applications Engineer (AE) will provide direct technical customer support for Cadence products and will focus on applying technical expertise in multiple products within a specific technology family.
The person should be able to act as strong team member and contributor, participate in team projects and initiatives.
Expertise in OrCAD Capture, ConceptHDL and Allegro PCB Editor, are added advantage.
The person should possess team-success orientation, mature work attitude, and good judgment under pressure.

Responsibilities:

Provide technical support to customers, internal and external, for Cadence's Allegro PCB Editor, Allegro Design Entry
Provide installation and licensing help
Advocate and negotiate bug/enhancement resolution with R&D
Contribute to and/or lead internal technology rollout projects and training
Develop solutions for inclusion in the Cadence knowledge database

Skills:

Experience on any Allegro Design Entry HDL (Concept HDL), Allegro PCB Editor, spectra and Allegro Package Design or equivalent competitor tools
Knowledge of High speed design, Signal Integrity and packaging will be an added advantage
Possess sound, basic knowledge of EDA industry, R&D Technology Roadmaps, and design flows within own area of technical expertise

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer required for SmartPlay, Bangalore

noreply@blogger.com (Sandeep Gor) — Mon, 22 Jun 2009 08:01:00 +0000

Design Implementation/DFT/Synthesis/STA for SmartPlay (previously TechForce)

Experience: 4-8 yrs

Education: BE / BTech / ME / MTech (electronics )

Designation: Mid Level / Lead

Location: Bangalore

Skills:

Compression insertion with X-tolerance, ATPG TPI insertion for coverage improvement, Test mode timing analysis with PT-SI, Debugging pattern simulation with timing for ATPG & memory BIST
Tester handling & bring-up structural vectors, DFT Verification, DFT implementation, Test Compressor, Full chip SOC, ATPG
Worked on Synthesis ,STA in synopsys flow, FV in synopsys flow, Knowledge of RTL coding, Synthesis of IP’s, Spyglass is an added advantage
Good at STA,Timing analysis forFull chip at 65nm
Should have worked on synopsys tool – DC,primetime
Should have Formal Verification using LEC

Contact: getjobsinindia2007@gmail.com

Embedded Software Engineer required for TechForce, Bangalore

noreply@blogger.com (Sandeep Gor) — Sat, 02 May 2009 13:46:00 +0000

Embedded Software Engineer

Experience: 3 to 5 years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

Experience in Embedded MAC Protocol Stack development (802.16, 802.11, GSM/GPRS)
RTOS based software development (VxWorks, PSOS, Embedded Linux)
Experience in embedded SW development tools
Experience in developing Networking/Protocol Stack Software for Modems, Access Points
Experience in testing communication protocols, Wireless terminals, Base Stations
Experience writing device drivers on PC and embedded platforms (Linux)
Strong RTOS kernel and RTOS driver development experience
Experience in working with wireless, networking, USB stacks

Contact: getjobsinindia2007@gmail.com

SoC Physical Design Engineer required for TechForce, Bangalore

noreply@blogger.com (Sandeep Gor) — Sat, 02 May 2009 13:41:00 +0000

SoC Physical Design Engineer

Experience: 3+ years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)
Work on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout
Clear understanding and command over all aspects of physical design
Experience in ASIC tapeouts, preferably in 90nm or smaller technology technologies
Expertise in Synopsys, Magma or Cadence backend tools
Skill and experience in scripting using Tcl or Perl desirable

Contact: getjobsinindia2007@gmail.com

Custom Layout Lead Engineer is required for TechForce, Bangalore

noreply@blogger.com (Sandeep Gor) — Sat, 02 May 2009 11:45:00 +0000

Custom Layout Lead Engineer

Experience: 8 to 10 years of experience in design and layout of memories and standard cells

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Responsibilities:

Hands-on Lead engineer involved in execution and management of Memory, Standard Cell and other Custom layout projects
Actively interface with the customer and the engineering team and ensure timely delivery of projects
Train, mentor & manage the junior engineers
Job involves execution of work at customer site and at TechForce design center
May have to travel outside India for a brief period of time customer meetings, project kickoff meetings etc.

Job Requirement:

Experience in Spice Simulation, Circuit Design, good understanding of memory architecture
Excellent verbal and written communication skills
Well experienced is using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
Ability to lead the engineering team

Contact: getjobsinindia2007@gmail.com

SoC Design Verification Engineer required for TechForce, Bangalore

noreply@blogger.com (Sandeep Gor) — Sat, 02 May 2009 11:26:00 +0000

SoC Design Verification Engineer

Experience: 3+ years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

Expertise in Verilog, VHDL
Proficiency in one or more HVL's a must (Vera, Specman, System C, System Verilog, C/C++)
Domains – Wireless, Wimax, Graphics, Multimedia, Networking, PCI Express, USB experience a plus
Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
Knowledge of Functional coverage using HVL language features or assertions a plus
Microcode Development
Good Debugging Skills

Contact: getjobsinindia2007@gmail.com

Finance Executive (Consultant) required for Cadence Design Systems, Noida

noreply@blogger.com (Sandeep Gor) — Wed, 17 Dec 2008 06:43:00 +0000

Experience: 1 to 5 years

Locaiton: Noida

No. of Positions: 1

Job Requirement:

Handling Payroll
T & E Accounting
General Accounting
Background in Commerce

Contact: getjobsinindia2007@gmail.com

Senior Services Applicaiton Engineer (DFT) required for Cadence Design Systems, Bangalore

noreply@blogger.com (Sandeep Gor) — Wed, 17 Dec 2008 06:37:00 +0000

Experience: 3 to 5 years

Location: Bangalore

No. of Positions: 1

Job Requirement:

All phases of DFT implementation and analysis (Scan, ATPG, BIST, JTAG)
Post-silicon debugging exposure
Professional experience in Synthesis
Prior knowledge on Conformal/Formal Verification activitie

Contact: getjobsinindia2007@gmail.com

Sr. Technical Writer required for Cadence Design Systems, Noida

noreply@blogger.com (Sandeep Gor) — Wed, 17 Dec 2008 06:32:00 +0000

Experience: 4 to 10 yrs

Location: Noida, India

No. of Positions: 1

Job Requirement:

Experience in writing user manuals, reference manuals a must
Excellent English, with good editing and proof reading skills.
Proficiency in FrameMaker, Webworks, and MS-Office tools

Contact: getjobsinindia2007@gmail.com

Member of Consulting Staff required for Cadence Design Systems, Noida

noreply@blogger.com (Sandeep Gor) — Wed, 17 Dec 2008 05:50:00 +0000

Experience: 4 to 8 years

Location: Noida, India

No. of Positions: 1

Job Requirement:

Should be proficient in synthesis ( worked on block level synthesis using DC and RC) as well as good in LEC, CCD and Low power design area.
Should be good in Tcl, Perl and Shell scripting also

Contact: getjobsinindia2007@gmail.com

Verification Engineer required for Cadence Design Systems, Bangalore or Noida

noreply@blogger.com (Sandeep Gor) — Wed, 15 Oct 2008 07:12:00 +0000

Experience: 4 to 5 years

Location: India, Bangalore or Noida

Job Requirement:

This engineer’s primary role will be to work in a team oriented environment to deliver digital logic design and verification methodologies, customised design environments and design implementation solutions that align with client goals. He/she will interact and work with other engineers on the worldwide D&V VCAD delivery team.
Responsibilities will include creating and customising design environments, design and verification methodologies.
Ideally the canddate should be able to assist with the optimisation of acceleration and emulation technologies using the Cadence Incisive verification flows including the Palladium and Xtreme hardware.
The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain.
The client should have at least a basic understanding of modeling (e.g. Architecture or system), and both block and system level verification experiance, preferably with coverage driven methodologies.
The candidate should possess the necessary engineering and consultancy skills, i.e. that he/she is technically mature with the necessary communication skills to be able to consult effectively with clients, e.g. to talk to, coach and advise Customers.
The engineer must have a solid background in the electronics industry with at least 4 to 5 years experience, and should be willing to learn new technical and consulting skills.

Key Accountabilities:

Execution on VCAD Customer support projects, e.g. Implementation and functional verification of design systems.
Development of customer specific verification environments including components, methodology support, operation and maintenance.
Be prepared to provide design and verification support in VCAD Customer design projects, both remotely and onsite.
Ability to handle all design environment implementation tasks and architectural tasks with the minimum support or through working in a joint team of Cadence and Customer engineers.
Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
Acquire a basic understanding of the (service) business environment of Cadence within 6 months including pre sales support.

Contact: getjobsinindia2007@gmail.com

DFT Engineer required for Cadence Design Systems, Bangalore

noreply@blogger.com (Sandeep Gor) — Wed, 15 Oct 2008 07:10:00 +0000

Experience: 3 to 6 Years

Location: Bangalore, India

Skill Sets: Scan, Jtag, Atpg, Tester interface.

Good to have skills: Exposure to ATPG tools like Encounter Test

Job Description:

This engineer’s primary role will be to work in a team oriented environment to deliver DFT activities for implementation services. He/she will interact and work with other engineers on the worldwide delivery team.
This engineer is expected to provide services using the following technical skills: Scan, JTAG, ATPG, Logic Synthesis, Static Timing Analysis, and to interface with designers / testing team.
In addition to the technical skills they will be expected to operate effectively in project teams delivering the design of leading edge. Additional responsibilities include customer interactions and pre-sales activities.

Key Accountabilities:

Ability to handle all design environment implementation tasks assigned, either personally or through supervising other Cadence and Customer engineers.
Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
Acquire a basic understanding of the (service) business environment of Cadence including pre sales support.

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer required for TechForce, Bangalore

noreply@blogger.com (Sandeep Gor) — Fri, 13 Jun 2008 05:27:00 +0000

Physical Design Engineers, Bangalore

Skills:

Tools - Synopsys, Cadence, Magma tools
Technologies – 45nm, 65nm or 90nm

Location: Hyderabad

Experience: 3 - 15 years experience (from Junior level to Sr Technical Lead Position)

Education: BE / MS / M Tech

Job Requirements:

Minimum 3 year of ASIC physical design experience.
Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
Should have participated in a minimum of 3-4 fullchip tapeouts.
Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
Familiar with Physical Verification will be a plus.

In addition, following is desirable:

Effective written and oral communication skills in English
Understanding Verilog HDL
Understanding Deep Submicron effects such as 90nm and below
Understanding OCV, DFM, DFY
Excellent Block level and Fullchip level Timing closure skills
Displaying motivation, leadership skills and working in teams

Responsibilities:

Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.

Contact: getjobsinindia2007@gmail.com

Senior Verification Engineer required for TechForce Design Services

noreply@blogger.com (Sandeep Gor) — Mon, 14 Apr 2008 09:57:00 +0000

Senior Verification Engineer - Bangalore

Skills/Expertise:

Language: Vera, System Verilog, System C, Verilog, VHDL
Domain: USB, PCI, PCI express, ARM, AMBA, Storage or Any peripherals

Location: Bangalore

Experience: 4 yrs & above

Education: BE / B.Tech / ME / MTech / MS

Qualification:

Expertise in either Vera language or mentioned domain expertise will be preferred
Exposure to gate level simulation (ModelSim)
Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
Knowledge of Functional coverage using HVL language features or assertions a plus
Proficiency in developing testcases and testbench environment.

Contact: getjobsinindia2007@gmail.com

Senior Verification Engineer required for TechForce Design Services

noreply@blogger.com (Sandeep Gor) — Mon, 14 Apr 2008 09:54:00 +0000

Senior Verification Engineer - Hyderabad

Skills/Expertise:

Languages: Vera, System Verilog, Verilog
Domains preferred: MPEG, MP3, Multimedia, Audio, Video

Location: Hyderabad

Experience: 4 yrs & above

Education: BE / B.Tech / ME / MTech / MS

Qualification:

Expertise in either mentioned languages or mentioned domain expertise will be preferred
Exposure to gate level simulation (ModelSim)
Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
Knowledge of Functional coverage using HVL language features or assertions a plus
Proficiency in developing testcases and testbench environment.

Contact: getjobsinindia2007@gmail.com

ASIC Verification Engineer required for TechForce Design Services

noreply@blogger.com (Sandeep Gor) — Mon, 14 Apr 2008 09:50:00 +0000

ASIC Verification Engineer - Noida

Skills/Expertise:

Languages: Verilog / VHDL / Specman / Vera / System Verilog / System C
Location: Noida

Experience: 2 yrs – 8 yrs

Education: BE / B.Tech / ME / MTech / MS

Qualification:

Experience in Verilog / VHDL / Specman / Vera / System Verilog / System C
Exposure to gate level simulation (ModelSim)
Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
Knowledge of Functional coverage using HVL language features or assertions a plus
Proficiency in developing testcases and testbench environment.

Important Note: Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.

Contact: getjobsinindia2007@gmail.com

ASIC Verification Engineer (Specman) required for TechForce Design Services

noreply@blogger.com (Sandeep Gor) — Mon, 14 Apr 2008 09:46:00 +0000

ASIC Verification Engineer – Noida (Specman)

Skills/Expertise:

Languages: Specman “e”
IP verification preferred

Location: Noida

Experience: 2 yrs – 8 yrs

Education: B.E. / B.Tech / ME / MTech / MS

Qualification:

Experience in test bench development in Specman
Experience in IP verification preferred
Experience in writing the test cases with decent debugging skills.

Important Note: Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.

Contact: getjobsinindia2007@gmail.com