Enchanter Space Studio

Finite State Machines (FSM) design in Verilog

2012-01-15T04:48:00.001+08:00

Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. A finite state machine can be divided in to two types: Moore and Mealy state machines. Fig. 1 has the general structure for Moore and Fig. 2 has general structure for Mealy. The current state of the machine is stored in the state memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous” state machine). The state vector (also current state, or just state) is the value currently stored by the state memory. The next state of the machine is a function of the state vector in Moore; function of state vector and the inputs in Mealy.

Fig. 1: Moore State Machine

Fig. 2: Mealy State Machine

Verilog CodingThe logic in a state machine is described using a case statement or the equivalent (e.g., if-else). All possible combinations of current state and inputs are enumerated, and the appropriate values are specified for next state and the outputs. A state machine may be coded as in Code 1 using two separate case statements, or, as in code 2, using only one. A single case statement may be preferred for Mealy machines where the outputs depend on the state transition rather than just the current state.

Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That is, input will be a series of one's and zero's. If two one's or two zero's comes one after another, output should go high. Otherwise output should be low.

Here is a Moore type state transition diagram for the circuit. When reset, state goes to 00; If input is 1, state will be 01 and if input is 0, state goes to 10. State will be 11 if input repeats. After state 11, goes to 10 state or 01 depending on the inp, since overlapping pair should not be considered. That is, if 111 comes, it should consider only one pair.

Following code the Verilog implementation of the state machine. Note that we updated outp and state in separate always blocks, it will be easy to design. inp is serial input, outp is serial output, clk is clock and rst is asynchronous reset. I have used nonblocking statements for assignments because we use previous state to decide the next state, so state should be registered.

module fsm( clk, rst, inp, outp);

   input clk, rst, inp;
   output outp;

   reg [1:0] state;
   reg outp;

   always @( posedge clk, posedge rst )
   begin
   if( rst )
       state <= 2'b00;
   else
   begin
       case( state )
       2'b00:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b10;
       end

       2'b01:
       begin
            if( inp ) state <= 2'b11;
            else state <= 2'b10;
       end

       2'b10:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b11;
       end

       2'b11:
       begin
            if( inp ) state <= 2'b01;
            else state <= 2'b10;
       end
       endcase
   end
end


always @(posedge clk, posedge rst)
begin
    if( rst )
       outp <= 0;
    else if( state == 2'b11 )
       outp <= 1;
    else outp <= 0;

end

endmodule

Here is a testbench that can be used to test all these examples. This testbench generates both directed and random test values. We can specify the sequence in the first part.

module fsm_test;

reg  clk, rst, inp;
wire outp;
reg[15:0] sequence;
integer i;

fsm dut( clk, rst, inp, outp);

initial
begin

   clk = 0;
        rst = 1;
        sequence = 16'b0101_0111_0111_0010;
   #5 rst = 0;

   for( i = 0; i <= 15; i = i + 1)
   begin
      inp = sequence[i];
      #2 clk = 1;
      #2 clk = 0;
      $display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

   end
        test2;
end

task test2;
   for( i = 0; i <= 15; i = i + 1)
   begin
      inp = $random % 2;
      #2 clk = 1;
      #2 clk = 0;
      $display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

   end
endtask


endmodule

Now, let us re-design the above circuit using Mealy style state machine. Output depends on both state and input. State transition diagram is as follows:

When reset, state becomes idle, that is 00. Next, if 1 comes, state becomes 01 and if 0 comes state becomes 10 with output 0. We have showed input 1, output 0 as 1/0. If input bit repeats, output becomes 1 and state goes to 00.

I implemented this state machine as in the code bellow. Only one always block is used because both outp and state are dependent on state and inp.

module mealy( clk, rst, inp, outp);

   input clk, rst, inp;
   output outp;

   reg [1:0] state;
   reg outp;

   always @( posedge clk, posedge rst ) begin
   if( rst ) begin
       state <= 2'b00;
       outp <= 0;
   end
   else  begin
       case( state )
       2'b00: begin
            if( inp ) begin
               state <= 2'b01;
               outp  <= 0;
            end
            else begin
                state <= 2'b10;
                outp <= 0;
            end
       end

       2'b01: begin
            if( inp ) begin
                state <= 2'b00;
                outp  <= 1;
            end
            else  begin
               state <= 2'b10;
               outp <= 0;
            end

       end

       2'b10: begin
            if( inp ) begin
                state <= 2'b01;
                outp  <= 0;
            end
            else begin
               state <= 2'b00;
               outp <= 1;
            end

       end

       default: begin
            state <= 2'b00;
            outp <= 0;
       end
     endcase
   end
end

endmodule

Now, let us discuss difference between Moore and Mealy state machines depending on these codes.

Moore state machine is easier to design than Mealy. First design the states depending on the previous state and input. Then design output only depending on state. Whereas in Mealy, you have to consider both state and input while designing the output.
Mealy state machine uses less states than the Moore. Since inputs influence the output in the immediate clock, memory needed to remember the input is less. So, it uses less flip flops and hence circuit is simpler.
In Mealy, output changes immediately when the input changes. We can observe this point when you simulate the codes above. In Moore example, output becomes high in the clock next to the clock in which state goes 11. So, Mealy is faster than Moore. Mealy gives immediate response to input and Moore gives response in the next clock.

Sequence detector:

Let us design a circuit to detect a sequence of 1011 in serial input. This is an overlapping sequence. So, if 1011011 comes, sequence is repeated twice. Consider these two circuits. First one is Moore and second one is Mealy. In Moore design below, output goes high only if state is 100. Note that we have used 1 less state than Mealy and hence one flip flop less will be enough to design state machine.

This time I will try to implement only Mealy machine. Try to understand the state diagram and compare them first.

When reset, state goes to 00, where there is no previous inputs. State remains same until we get a '1' in the input since there is no possibility of start of sequence. If a 1 comes in the input, it may be start of sequence, so go to state 01. From 01, if again 1 comes, that means sequence is broken. But there is a possibility of start of another new sequence. So, 01 is start of sequence and stay in the same state. If zero comes, go to state 10.

Another 0 when state is 10 breaks the sequence and state goes to 00, no sequence. If 1 comes, continue to next state 11.

If again 1 comes, sequence completes. Make the output high and go to state 01, because there may be a overlapping sequence as I mentioned earlier. If zero comes, sequence breaks and state goes to 10 since it may be second bit of another sequence.

module m1011( clk, rst, inp, outp);

   input clk, rst, inp;
   output outp;

   reg [1:0] state;
   reg outp;

   always @( posedge clk, rst )
   begin
   if( rst )
       state <= 2'b00;
   else
   begin
       case( {state,inp} )
          3'b000: begin
             state <= 2'b00;
             outp  <= 0;
          end
          3'b001: begin
             state <= 2'b01;
             outp  <= 0;
          end
          3'b010: begin
             state <= 2'b10;
             outp  <= 0;
          end
          3'b011: begin
             state <= 2'b01;
             outp  <= 0;
          end
          3'b100: begin
             state <= 2'b00;
             outp  <= 0;
          end
          3'b101: begin
             state <= 2'b11;
             outp  <= 0;
          end
          3'b110: begin
             state <= 2'b10;
             outp  <= 0;
          end
          3'b111: begin
             state <= 2'b01;
             outp  <= 1;
          end

       endcase
   end
end

endmodule

This time I combined state and inp using concatenation operator {} to make code smaller. state and inp is used together to select the case. Using this a I avoided if-begin-end-else-begin-end in every case.

SystemVerilog Resouces

2012-01-12T08:02:00.001+08:00

1. http://www.testbench.in -- SystemVerilog for Functional Verification – free online tutorial with many examples.

2. http://www.project-veripage.com -- Project VeriPage

3. http://www.systemverilog.in/

4. http://www.doulos.com/knowhow/sysverilog The Guide to SystemVerilog

5. http://electrosofts.com/systemverilog/ SystemVerilog Tutorial

6. http://www.systemverilog.org/

7. http://www.asic-world.com/systemverilog/tutorial.html -- ASIC-World – Extensive free online tutorial with many examples

8. http://svug.org/ -- SystemVerilog Users Group

9. http://www.asic.co.in/Index_files/tutorials/system_verilog.pdf -- Design with SystemVerilog

10. http://www.asic.co.in/Index_files/tutorials/SystemVerilog_veriflcation.ppt -- Verification with SystemVerilog

11. http://www.eda.ncsu.edu/wiki/Tutorial:Questa_SystemVerilog_Tutorial – Tutorial : Questa SystemVerilog Tutorial

12. http://www.intelligentdv.com/blog/20/doxygen-filter-for-systemverilog-released/ -- Doxygen Filter for SystemVerilog

How to create tag/branch with git-svn

2011-11-30T10:40:00.001+08:00

The SVN server structure is like this:

http://foo.net/code/design/
                          |-- trunk/
                          |        |-- proj1
                          |        |-- proj2
                          |-- tags/
                          |       |-- forProj1
                          |       |-- forProj2
                          |-- branches/
                          |           |-- forProj1

To create the tag:

Clone SVN:
$ git svn clone http://foo.net/code/design --trunk=trunk/proj1 --tags=tags/forProj1 --branches=branches/forProj1 localProjName
Then the tag can be created with simple command
$ git svn tag -n -m "test tag" test_v1

Do the branch in the same way.

The original question and answer can check http://stackoverflow.com/questions/8306592/git-svn-how-to-create-a-tag-branch-for-a-sub-project-of-svn

How to download Chrome Extension and install it from local

2011-11-10T13:36:00.001+08:00

My computer is set to can't run Google Chrome. I don't know how they did that. But if your run "chrome.exe" it will be automatically killed before it started.

The solution is rename it to any name except "chrome.exe", for example, "ie.exe". Then I can use it.

But that is not perfect. I can't install any extension from Chrome WebStore. I got the error message as below:

Package is invalid. Details: 'Could not create directory for unzipping: C:\XXXXXX".

Check the latest Chrome Dev, it has the "Developer Mode" which can load the local unpacked extension. Then I got the idea to download the extension and load it from local directory.

1. Find the ID of extension

When you press the extension in the Chrome WebStore, you can get the link as below in the URL bar.
https://chrome.google.com/webstore/detail/cfhdojbkjhnklbpkdaibdccddilifddb
The one after webstore/detail/ is the ID (cfhdojbkjhnklbpkdaibdccddilifddb) of it.

2. Open other browser (Not Chrome)

Paste this in the URL bar
https://clients2.google.com/service/update2/crx?response=redirect&x=id%3DRealID%26uc

replace the with the real ID you found in last step.

3. Hit "Enter" then you would ask to save the extension.

4. Unzip it to a directory

5. Press "Load unpacked extension" in the chrome://settings/extensions. It will ask you to locate the directory of extension created in Step 4.

Then, enjoy the extension.

Next time, try to make it automatically.

Any ideas of workaround for using Google Chrome in my situation is welcomed.

Compile UVM DPI for QuestaSim

2011-11-08T08:22:00.000+08:00

Download UVM 1.1 and want to have a try. But when I tried to compile the DPI for QuestaSim:

uvm/examples$ make -f Makefile.questa dpi_lib

I got error message as below:

uvm/src/dpi/uvm_regex.cc:26:22: fatal error: vpi_user.h: No such file or directory

compilation terminated.

make: *** [dpi_lib] Error 1

After check the makefile and here, I found the reason is I don't have MTI_HOME setup in my environment.

Set the MTI_HOME to the install direcotry of QuestaSim. Then make again, everything is fine.

From now on, start my UVM learning progress.

Any good resources for UVM, such as tutorial, forum, articles, blogs, etc, are welcomed.

Free Online Courses from Top Universities

2011-10-26T07:02:00.002+08:00

Economics

American Economic History – iTunes – J. Bradford Delong, UC Berkeley
Austrian Economics: An Introduction – Web Site - Murray N. Rothbard - New York Polytechnic University
Capitalism: Success, Crisis and Reform - iTunes Video - iTunes Audio - YouTube - Web Site – Douglas W. Rae, Yale
Economic Crisis and Globalization – Video – Richard D. Wolff, The New School
Economic Geography of the Industrial World – iTunes – Richard Walker, UC Berkeley.
Financial Markets – YouTube – iTunes Audio – iTunes Video- Download Course – Robert Shiller, Yale
Financial Theory - iTunes Video - iTunes Audio - Web Site – John Geanakoplos, Yale
Game Theory – YouTube – iTunes – Download Course – Ben Polak, Yale
Game Theory in the Social Sciences - iTunes Video – Yves Zenou, UC Berkeley
Intermediate Macroeconomic Theory - YouTube – Professor J. Bradford Delong, UC Berkeley
International Political Economy - iTunes - James Morrison, Middlebury College
International Trade - YouTube - iTunes Video – Steven Wood, UC Berkeley
Introduction to Economics – iTunes – J. Bradford Delong, UC Berkeley
Marxian Class Analysis Theory and Practice Online Course –Video – Richard D. Wolff, The New School
Introduction to Environmental Economics and Policy- YouTube – Professor Gordon Rausser, UC Berkeley
Marxian Class Analysis Theory and Practice - Video - Richard D. Wolff, The New School
Marxian Economics – An Intensive Introduction – Video – Richard D. Wolff, The New School
Marxian Economics: Advanced & Applied Intensive Course –Video - Richard D. Wolff, The New School
Reading Marx’s Capital – Google Video – David Harvey, City University of New York
The Austrian School of Economics: An Introduction – Web Site- Friedrich A. Hayek & colleagues – Recorded at University of Colorado

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China: Traditions and Transformations – Multiple Formats – Peter K. Bol & William Kirby, Harvard
Colonial and Revolutionary America – iTunesU – Jack Rakove, Stanford
Early Modern England: Politics, Religion, and Society under the Tudors and Stuarts - iTunes Video - iTunes Audio - YouTube- Web Site – Keith E. Wrightson, Yale
Epidemics in Western Society Since 1600 - iTunes Video – iTunes Audio - YouTube - Web Site – Frank Snowden, Yale
Europe and the World: Wars, Empires, Nations 1648-1914 –iTunes Audio - David Wetzel, UC Berkeley
European Civilization, 1648-1945 - YouTube – iTunes Audio –iTunes Video - Download Course – John Merriman, Yale
European Civilization from Renaissance to Present – iTunes – Carla Hesse, UC Berkeley
European Civilization from the Renaissance to the Present -YouTube - iTunes Video – Thomas Lacquer, UC Berkeley
European Cultural History, 1500-1815 - MP3s – George Mosse, University of Wisconsin- Madison
European Cultural History, 1660-1870 - MP3s – George Mosse, University of Wisconsin- Madison
European Cultural History, 1880-1920 - MP3s – George Mosse, University of Wisconsin- Madison
France Since 1871 – YouTube – iTunes – Download Course – John Merriman, Yale
Hannibal – iTunes – Patrick Hunt, Stanford.
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History of Information – YouTube – Professors Geoffrey D. Nunberg, Paul Duguid, UC Berkeley
History of Iran to the Safavid Period – iTunes – Richard Bulliet, Columbia University
History of the International System – iTunes – James Sheehan, Stanford University
History of the Modern Middle East – iTunes – Richard Bulliet, Columbia University
History of New York City: A Social History - iTunes – YouTube –Web Site – Daniel Walkowitz, NYU
History of the United States Since 1945 – iTunes – Daniel Sargent, UC Berkeley
History of the World to 1500 CE – YouTube – Richard Bulliet, Columbia University
Intellectual History of the United States since 1865 - iTunes – Richard Candida Smith, UC Berkeley
Introduction to Greek History - YouTube – iTunes – Download Course – Donald Kagan, Yale
Medicine and Public Health in American History – Web Audio - Chris Hamlin, Notre Dame
Modern Civilization: 1750 to Present - YouTube – Lynn Hunt, UCLA
Modern Jewish History – MP3s – George Mosse, University of Wisconsin – Madison
Science, Magic and Religion - iTunes - YouTube – Courtenay Raiai, UCLA
The American Founders and Their World – iTunes – Jack Rakove, Gordon Wood, etc. Stanford
The American Revolution – iTunes Video - iTunes Audio –YouTube - Web Site – Joanne B. Freeman, Yale
The Civil War and Reconstruction Era, 1845-1877 - YouTube –iTunes Audio – iTunes Video - Download Course – David Blight, Yale
The Peculiar Modernity of Britain, 1848-2000 – iTunes – James Vernon, UC Berkeley
The Rise and Fall of the Second Reich – iTunes – Margaret Anderson, UC Berkeley
The United States and the World Since 1945 - iTunes Audio – Daniel Sargent, UC Berkeley
The Western Tradition (Video) – Videos – Course Outline – Eugen Weber, UCLA
War and Peace: International Relations since 1914 – iTunes – David Wetzel, UC Berkeley
World War and Society in the 20th Century: World War II –Multiple Formats – Charles S. Maier, Harvard

Bookmark our collection of free online History courses.

Law

Aims and Limits of the Criminal Law - iTunes Audio – Tamara Lave, UC Berkeley
Climate Change: Law and Policy – YouTube – iTunes Audio –iTunes Video – Cymie Payne, Daniel Farber, UC Berkeley
Environmental Justice and Human Rights in the Aftermath of Katrina – Web Audio – Cynthia Toms Smedley, Notre Dame
Environmental Law and Policy - YouTube – Bob Infelise, UC Berkeley
Environmental Politics and Law - iTunes Video - iTunes Audio- YouTube - Web Site – John P. Wargo, Yale
International Environmental Law – YouTube – iTunes Video –iTunes Audio – Cymie Payne
Introduction to Copyright Law – iTunes – Web Site – Keith Winstein, MIT
Renewable Energy & Alternative Fuels (Law & Policy) –YouTube – UC Berkeley

Political Science, International Relations and Law

African American Studies: Intro to African American Political Thought – YouTube – Mark Sawyer, UCLA
Climate Change: Law and Policy – iTunes – Cymie Payne
Environmental Politics and Law - iTunes Video - iTunes Audio- YouTube - Web Site – John P. Wargo, Yale
Faith and Globalization – YouTube – Tony Blair, Miroslav Volf, Yale
Geography of US Presidential Elections – YouTube – iTunes – Martin Lewis, Stanford
International Politics – Feed – Johns Hopkins
International Political Economy – iTunes - James Morrison, Middlebury College
International Politics – Audio - James Morrison, Middlebury College
Introduction to German Politics – iTunes – Andreas Busch, Oxford University
Introduction to Political Philosophy – YouTube – iTunes –Download Course, Steven B. Smith, Yale
Justice: A Journey in Moral Reasoning (Video) – Video – Michael Sandel, Harvard
Perspectives on China (Video) – Video – Roderick MacFarquhar, Harvard
Politics and Strategy – YouTube – Kathleen Bawn, UCLA
Republicanism – Feed - Johns Hopkins
The Moral Foundations of Politics - iTunes Video - iTunes Audio- YouTube - Web Site – Professor Ian Shapiro, Yale

Bookmark our collection of free online Political Science courses.

Sociology

Foundations of Modern Social Theory – iTunes Video - iTunes Audio - YouTube - Web Site – Iván Szelényi, Yale
Global Sociology - YouTube – Professor Michael Burawoy, UC Berkeley
Introduction to Sociology – Web Site – Harvey Molotch, NYU
The Sociology of Race Relations – iTunes – Gianpaolo Baiocchi, UMASS Amherst

Sciences

Computer Science & Artificial Intelligence

Artificial Intelligence – Introduction to Robotics – YouTube –iTunes – Multiple formats – Oussama Khatib, Stanford
Artificial Intelligence – Natural Language Processing – Multiple formats – Christopher Manning, Stanford
Artificial Intelligence – Machine Learning – YouTube – iTunes –Multiple formats – Andrew Ng, Stanford
Artificial Intelligence – YouTube – P.Dasgupta, IIT
Bits – Multiple Formats – Harry Lewis, Harvard
Building Dynamic Web Sites – iTunes - Video & Audio – David Malan, Harvard Extension
Building Mobile Web Sites – iTunes – Web Site - David Malan, Harvard Extension
Computational Camera and Photography – Download Course – Ramesh Raskar, MIT
Computer Graphics – YouTube – Sukhendu Das, IIT
Computer Language Engineering - YouTube – iTunes Video – Web Site – Martin Rinard, MIT
Computer Networks – YouTube – S.Ghosh, IIT
Computer System Engineering – Web Site – Profs. Robert Morris and Samuel Madden, MIT
Data Structures - iTunes Video – Paul Hilfinger, UC Berkeley
Developing Apps for iOS (iPhone & iPad) – iTunesU – Paul Hegarty, Stanford
Discrete Mathematical Structures YouTube – Kamala Krithivasan, IIT
Intensive Introduction to Computer Science Using C, PHP, and JavaScript – Multiple Formats – David Malan, Harvard
Introduction to Algorithms – iTunes – YouTube - Web Site – Prof. Charles Leiserson & Erik Demaine, MIT
Introduction to Computer Programming for Scientists and Engineers - iTunes Audio – iTunes Video – Roberto Horowitz, UC Berkeley
Introduction to Computer Science and Programming -YouTube – iTunes – MIT Web Site – Eric Grimson, John Guttag, MIT
Introduction to Computer Science: Programming Methodology – YouTube – iTunes – Multiple formats – Mehran Sahami, Stanford
Introduction to Computer Science: Programming Abstractions - YouTube – iTunes - Multiple formats – Julie Zelenski, Stanford
Introduction to Computer Science: Programming Paradigms -YouTube – iTunes - Multiple formats – Jerry Cain, Stanford
Introduction to Computer Graphics – YouTube – Prem Kalra, IIT
Introduction to Embedded Systems - YouTube – Professors Sanjit Seshia, Edward A. Lee, UC Berkeley
Introduction to Problem Solving & Programming – YouTube – Deepak Gupta, IIT
iPhone Application Development (Spring 2009)- iTunes – Stanford
iPhone Application Development (Winter 2010) – iTunes – Stanford
Logic & Proofs – Web Site – Carnegie Mellon
Machine Structures – iTunes Video – David Culler, UC Berkeley
Multimedia Systems - iTunes – Surendar Chandra, Notre Dame
Operating Systems and System Programming – iTunes – Multiple professors, UC Berkeley
Operating Systems Principles – iTunes – Surendar Chandra, Notre Dame
Principles of Digital Communications I - YouTube – iTunes – Profs Gallagher and Zheng, MIT
Principles of Digital Communications II - YouTube – MIT
Programming Languages and Compilers - YouTube – Professor Paul Hilfinger, UC Berkeley
Quantum Computing for the Determined - YouTube – Michael Nielsen, The University of Queensland
Search Engines: Technology, Society and Business – YouTube – Marti Hearst, UC Berkeley
The Beauty and Joy of Computing – iTunes - Brian Harvey, UC Berkeley
The Beauty of Joy of Computing – YouTube – Professor Daniel Garcia, UC Berkeley
The Future of the Internet – iTunes – Ramesh Johari, Stanford
The Structure and Interpretation of Computer Programs –YouTube - iTunes – Brian Harvey, UC Berkeley
Understanding Computers and the Internet – iTunes – Feed – David Malan, Harvard University

Bookmark our collection of free online Computer Science courses. Also find comp sci textbooks in our Free Textbook collection.

Engineering (Mechanical, Civil and Electrical)

Advanced Analog Integrated Circuits – YouTube – Professor Simone Gambini, UC Berkeley
Atomistic Computer Modeling of Materials – YouTube – iTunes Video – Web Site – Gerbrand Ceder & Nicola Marzari, MIT
Convex Optimization I – Multiple Formats – Stephen Boyd, Stanford
Convex Optimization 2 – Multiple Formats – Stephen Boyd, Stanford
Direct Solar/Thermal to Electrical Energy Conversion Technologies – iTunes – Download Course – Gang Chen, MIT
Dynamics of Machines – YouTube – Amitabha Ghosh, IIT
Electrical – Digital Signal Processing YouTube – S.C Dutta Roy, IIT
Electro Magnetic Fields – YouTube – Harishankar Ramachandran, III
Engineering Statistics – Web Site – Carnegie Mellon
Environmental Air Pollution – YouTube -Mukesh Sharma, IIT
Fluid Mechanics – YouTube – T.I.Eldho, IIT
Introduction to Chemical Engineering – YouTube – iTunes – Channing Robertson, Stanford
Introduction to Digital Integrated Circuits - iTunes – Elad Alon, UC Berkeley
Introduction to Digital Integrated Circuits – YouTube – Professor Jan M. Rabaey, UC Berkeley
Introduction to Engineering – iTunes – Tod Laursen, Duke
Introduction to Linear Dynamical Systems - Multiple formats – Stephen Boyd, Stanford
Introduction to Microelectronic Circuits – iTunes – Chang-Hasnain, UC Berkeley
Introduction to Engineering – iTunes Video – Multiple presenters, Duke University
Linear Integrated Circuits – YouTube – Professor Clark Tu-Cuong Nguyen, UC Berkeley
Mechanical Engineering: Introduction to MEMS Design -iTunes Audio – iTunes Video – UC Berkeley
Nano-to-Macro Transport Processes – iTunes Audio – Web Site – Gang Chen, MIT
The Fourier Transform and its Applications – YouTube – iTunes– Multiple formats – Brad Osgood, Stanford

Bookmark our collection of free online Engineering courses.

Mathematics

Abstract Algebra - Multiple Formats – Benedict Gross – Harvard
Calculus – iTunes Audio – F. Michael Christ, UC Berkeley
Calculus Revisited: Single Variable Calculus (1970) – YouTube -iTunes Video – Web Site – Herb Gross, MIT
Computational Science and Engineering I - iTunes – YouTube –Web Site – Gilbert Strang, MIT
Core Science Mathematics – YouTube – SK Ray, IIT
Differential Equations – YouTube – iTunes – MIT – Arthur Mattuck
Engineering Statistics - Web Site – Carnegie Mellon
Geometric Folding Algorithms:Linkages, Origami, Polyhedra -Web Site – Erik Demaine, MIT
Introduction to Probability and Statistics – YouTube – iTunes Video – Deborah Nolan, MIT
Introductory Probability and Statistics for Business - iTunes – Fletcher Ibser, UC Berkeley
Introduction to Statistics - iTunes – Fletcher Ibser, UC Berkeley
Linear Algebra – YouTube – iTunes – Gilbert Strang, MIT
Logic & Proofs - Web Site – Carnegie Mellon
Multivariable Calculus - YouTube - iTunes – Dennis Auroux, MIT
Probability for Math Science – iTunes – YouTube – Herbert Enderton, UCLA
Sets, Counting, and Probability - Multiple Formats – Paul Bamberg, Harvard
Single Variable Calculus - YouTube – iTunesU – David Jerison, MIT
Statistics – Web Site – Carnegie Mellon
The Calculus Lifesaver – Download Videos – Adrian Banner, Princeton

Bookmark our collection of free online Math courses. Also find free math textbooks in our Free Textbook collection.

Physics

Exploring Black Holes: General Relativity & Astrophysics- YouTube - iTunes Video - Web Site – Edmund Bertschinger, MIT
Descriptive Introduction to Physics – iTunes Video - iTunes Audio- Richard Muller, UC Berkeley
Fundamentals of Physics – iTunes - YouTube - Download Course – Ramamurti Shankar, Yale
Fundamentals of Physics II - iTunes Video - iTunes Audio –YouTube - Web Site – Ramamurti Shankar, Yale
Introduction to Astrophysics – iTunes - YouTube – Josh Bloom, UC Berkeley
Introduction to Cosmology and Particle Physics – YouTube – Sean Carroll, Caltech
Introduction to Solar System Astronomy – iTunes – Feed – Richard Pogge, Ohio State
Introductory Physics – iTunes – Michael Deweese, UC Berkeley
Modern Theoretical Physics: Classic Mechanics (Video) – iTunes– YouTube – Leonard Susskind, Stanford
Modern Theoretical Physics: Quantum Mechanics (Video) –iTunes – YouTube – Leonard Susskind, Stanford
Modern Theoretical Physics: Special Relativity (Video) – iTunes– YouTube – Leonard Susskind, Stanford
Modern Theoretical Physics: Einstein (Video) – iTunes –YouTube – Leonard Susskind, Stanford
Modern Theoretical Physics: Cosmology (Video) - iTunes –YouTube – Leonard Susskind, Stanford
Modern Theoretical Physics: Statistical Mechanics (Video) –iTunes – YouTube – Leonard Susskind, Stanford
Quantum Entanglement Part 1: (Video) – iTunes – YouTube - Leonard Susskind, Stanford University
Quantum Entanglement Part 3: (Video) – iTunes – YouTube – Leonard Susskind, Stanford University
Quantum Mechanics – iTunes – JJ Binney, Oxford University
Quantum Mechanics – iTunes – Feed – John Terning, UC Davis
Quantum Physics Made Relatively Simple – Videos - Hans Bethe, Cornell University
Physics I: Classical Mechanics – iTunes – Video Download –YouTube – Walter Lewin, MIT
Physics II: Electricity and Magnetism – iTunes – Video Download– YouTube – Walter Lewin, MIT
Physics III: Vibrations and Waves – iTunes – Video Download –YouTube – Walter Lewin, MIT
Physics for Future Presidents – YouTube – Richard Muller, UC Berkeley
Stars, Galaxies, and the Universe – iTunes – Feed – Richard Pogge, Ohio State
String Theory, Black Holes, and the Laws of Nature (Video) –Videos – Andrew Strominger, Harvard
The Character of Physical Law – Video – Richard Feynman, Cornell

Bookmark our collection of free online Physics courses. Also find free physics textbooks in our Free Textbook collection.

Business

Entrepreneurship and Business Planning – iTunes – Feed – Mark Juliano, Carnegie Mellon
Introductory Probability and Statistics for Business - iTunes – Fletcher Ibser, UC Berkeley
Marketing 321 – iTunes – Elaine Daussy, Texas A&M

The original post comes from Open Culture

Git Resources

2011-10-26T06:40:00.002+08:00

Source code / binaries / GUI

Git for Emacs

MaGit

Setting up Git server

Install Git from source

Diff/merge tools

Git through proxies

Git prompt

Documentation - git related sites

Documentation - books / guides / tutorials

Git Community Book / repository
Pro Git book / website / repository / examples
Git Magic
Git from the bottom up
An Illustrated Guide to Git on Windows
Git for Computer Scientists
Git for the lazy
Understanding Git Conceptually
Git_Guide
Git for beginners: The definitive practical guide
The Git Parable new
Easy Version Control with Git new
Git In Five Minutes new
jeff garzik’ guide to git new
Using Git Efficiently new
Git The Basics Tutorial new
A Git Workflow for Agile Teams new
Version control with Git - Tutorial new
Version Control for Designers new
Git for Subversion users, Part 1: Getting started new
Git for Subversion users, Part 2: Taking control new
A Visual Git Reference new
Git with Eclipse (EGit) - Tutorial new
Diving into Git new
Git Immersion
Git Guys Topics

Documentation - cheat sheets

Documentation - misc

Git Wiki / Git Faq / Blog posts on Git (usage) new
Git website documentation
GIT at DevHeaven
GitCasts
Setting up a new Rails app with Git
Using Git to manage a web site
Using Git to Maintain Your Website
git-notes repo
Why Git is Better than X
A Gaggle Of Git Tips
GIT: Using the stash
Slimming Down a Git Repository new
Creating a git branch without ancestry new
git merge vs git rebase: avoiding rebase hell new
Efficiently Updating Web Sites on Web Clusters new
Windows Git Tutorial: Cygwin, SSH and Projectlocker new
Git Tips new
Fix git “Not currently on any branch” Problem new
Git For Windows Developers - Git Series - Part 1
Some git best practices new
GIT Tips and Tools new
25 Tips for Intermediate Git Users new
Git quickstart new
The Thing About Git new
Git guts: Merging and rebasing new
My Git Workflow new
Bisecting History new
Using Git as a Backup Tool new
How to merge some (not all) files from one Git branch to another new
How to “Merge” Specific Files from Another Branch new
Git Utilities You Can’t Live Without new
The Unsightliness of Merge Commits new
A successful Git branching model new
Deploying A Web Application with Git and FTP new
Git Environment on Windows new
In praise of git’s index new
Some tips on using git with Windows new

Github tutorials

Wireless Mesh Network (WMN)

2011-10-24T19:26:00.000+08:00

In WMNs, nodes are comprised of mesh routers and mesh clients.
A WMN is dynamically self-organized and self-configured.

WMNs consist of two types of nodes:

mesh routers
mesh clients

Architecture of WMNs:

Infrastructure/Backbone WMNs
Client WMNs
Hybrid WMNs

Characteristics of WMNs:

Multi-hop wireless network
Support for ad hoc networking, and capability of self-forming, self-healing, and self-organization
Mobility dependence on the type of mesh modes
Multiple types of network access
Dependence of power-consumption constraints on the type of mesh nodes
Compatibility and inter-operability with existing wireless networks

Advantages of WMNs compared to Ad hoc:

Wireless infrastructure/backbone
Integration
Dedicated routing and configuration
Multiple radios
Mobility

Critical factors influencing network performance:

Radio techniques
Scalability
Mesh connectivity
Broadband and QoS
Compatibility and inter-operability
Security
Ease of use

MAC protocols for WMNs have the following differences compared to classical counterparts for wireless networks:

MAC for WMNs is concerned with more than one hop communication
MAC is distributed and cooperative and works for multipoint-to-multipoint communication
Network self-organization is needed for the MAC.
Mobility affects the performance of MAC.

Open research issues:

Scalability
Self-organization and self-configuration
Security
Network integration

[GIT Submodule] Fatal: Reference is not a tree : xxxx

2011-10-24T14:10:00.000+08:00

These days, try to use submodule to manage a project. But I got



$ git submodule update
fatal: reference is not a tree: ba81b5bf9ffce6b6ec9c50605035ca9dddb50023
Unable to checkout 'ba81b5bf9ffce6b6ec9c50605035ca9dddb50023' in submodule path 'Src/ThermalController'

The cause of this issue is:

I create the orignal project and add the submodule from remote repo.

Then modified the .gitmodule manual to point a local cache of the remote repo.

Then commit the original project.

I cloned the original project from repo as cloned project.

Here is the working flow:

Update from original project and commit, actually, that is committed to the remote repo.

In cloned project, pull and update the submodule, then I got the error message as above.

That because the local repo is not synced with remote yet.

So the solution is:

1. Try to sync the local/remote repo OR

2. Update the orignal project's submodule to point to the local repo as well as cloned project.

Can't make/receive phone calls on DHD

2011-10-23T11:23:00.002+08:00

From last Friday after, I can't make/receive any phone calls on my DHD.

Firstly I think it may caused by I installed some blocking APK. Then I remove everything, it still didn't work.

Secondly, I think maybe something wrong with the RADIO. I reflash different radios and RILs. Changed ROMs and format SDcard. Nothing is helpful.

Finally, I just read some articles said they can't make phone call with WCDMA on DHD. I tried to change it to use GSM only, everything works fine. Call to my carrier provide that they confirm that something wrong with their WCDMA network. ????!!!!

Stupid carrier. No notification in advance, WCDMA signal is full bar when their network has problem ....????

Anyway. they give me chance to practice how to downgrade/return to stock/unlock bootloader on my DHD.

Migrating a Subversion Project to Git on BitBucket (From Neogregious)

2011-10-20T11:58:00.000+08:00

Subversion is still the gold standard for version control (a.k.a. source control) systems, but the new kid on the block - Git - has undeniable advantages for many development models. Even for solo or centralised hierarchical development organisations, Git's agile branching and merging make it a joy to use.

But if you're going to go to the effort of switching version control systems, you probably also want to consider moving your repository to the cloud. This increases your options for off-site developers, and reduces the risks and maintenance costs of internally managed version control servers.

This article describes how to migrate a Subversion repository to Bitbucket, one of several online repositories.
First of all, why Bitbucket? GitHub and Google Code are worthy alternatives, but both have restrictions that make them less desirable for private repositories. Google Code doesn't allow them at all, and GitHub currently charges a small but significant amount per private repository. Bitbucket charges by developer instead, with the first five being free. Another important consideration is that all three are backed by large commercial companies that are unlikely to blink out of existence overnight.

1. Preparation
OK, enough of the justifications, lets get migrating! In the Subversion world, the convention is that you structure your projects as follows:

foobar
   - Trunk
   - Branches
      - Europe
      - US
   - Tags
      - Version 3.11
      - Version 3.12

If you use different conventions (like "trunk" instead of "Trunk"), take extra care to translate these in the code below. Our example Subversion project URL is svn://myserver/myrepo/foobar so you will need to translate this too.

Next, we need to fix a small discontinuity in user handling between Subversion and Git. Subversion users are simple usernames (like gregf), whereas Git requires a user's name and their email address. Create a file calledauthors.txt containing an entry for each of your subversion users (usually listed in svn/myrepo/conf/passwd):

lisas = Lisa Simpson 
barts = Bart Simpson

Finally. make sure you have git and git-svn installed. Google to find out how to do this on your operating system.

2. Convert the Subversion Project to a Local Git Repository
At the command line, enter:

git svn clone svn://myserver/myrepo/foobar --no-metadata -A authors.txt -b Branches -T Trunk -t Tags foobar_local

Make yourself some tea, coffee or martini - this will take a wee while, as it works through the entire history of changes in the Subversion project. Assuming all goes well, you should end up with a directory calledfoobar_local containing both your project, and more importantly a hidden directory called .git. To check, change into the directory and view the log:

cd foobar_local
git log
git branch

That last command doesn't show your branches! Don't panic, this will come right later.

3. Convert Ignore Filemasks
If you have set up filemasks for Subversion to ignore, we can easily convert these into the Git equivalent:

cd foobar_local
git svn show-ignore -i trunk > .gitignore
git add .gitignore
git commit -m 'Convert svn:ignore properties to .gitignore.'

Note that Trunk in Subversion has been lower-cased by Git to trunk.

4. Create a Bare Git Repository
So far you have a local git repository, but you need a bare repository to clone from. As part of this process, we set Git's symbolic HEAD to what was Subversion's (lower-cased) trunk, tell Git about any branches, and renametrunk to master (the convention in Git).

cd ..
git init --bare foobar_bare
cd foobar_bare
git symbolic-ref HEAD refs/heads/trunk
cd ../foobar_local
git remote add bare ../foobar_bare
git config remote.bare.push 'refs/remotes/*:refs/heads/*'
git push bare
cd ../foobar_bare
git branch -m trunk master

After the push, Git will list the new branches. I told you not to panic!

5. Convert Tags
Actually, if you use tags you might still be worried that all your tags seem to be branches. Git handles tags very differently from Subversion - in Git tags are simply aliases to a particular commit, whilst Subversion treats tags as a dead-end branch. Git-svn simply renames these branches, so we still need to convert these branch-tags to real Git tags:

cd foobar_bare
git for-each-ref --format='%(refname)' refs/heads/tags |
cut -d / -f 4 |
while read ref
do
   git tag "$ref" "refs/heads/tags/$ref";
   git branch -D "tags/$ref";
done

6. Push the Bare Repository to Bitbucket
Don't worry, we're nearly there now. The last step is to push all the branches up to Bitbucket. Log in to Bitbucket, and create a new repository calledfoobar. It will then show you the command required to clone this repository, which will include the HTTPS URL. The command will be something like this:

$ git clone https://myname@bitbucket.org/myname/foobar.git

The URL is the yellow section above. Now on your local machine, set the orgin and push the master (old trunk) and each branch to Bitbucket:

git remote add origin https://myname@bitbucket.org/myname/foobar.git
git push origin master
git push origin europe
git push origin us

Your project is now on Bitbucket.

7. Tidy Up
The only thing left now is to tidy up the local and bare repositories left on your machine.

cd ..
rm -rf foobar_local
rm -rf foobar_bare

And... you're done. Time for another tea, coffee, or martini to celebrate your success!

Original Post: http://neogregious.blogspot.com/2011/10/migrating-subversion-project-to-git-on.html

Using Git with Subversion

2011-09-29T09:33:00.000+08:00

Using Git with Subversion

Install Git

sudo apt-get install git-core

Tips

svn:mime-type property

If you're adding new files through git svn, you should set the svn:mime-type property on those files. You can have SVN do this automatically and git will respect those settings. Put the following in your~/.subversion/config file:

[miscellany]
enable-auto-props = yes

# Add an additional line for each type of binary file you wish to commit.
# You can add as much as you like.
[auto-props]
INSTALL = svn:eol-style=native
KEYS = svn:eol-style=native
Makefile = svn:eol-style=native
README = svn:eol-style=native
*.aart = svn:eol-style=native
*.ac = svn:eol-style=native
*.am = svn:eol-style=native
*.bat = svn:mime-type=text/plain;svn:eol-style=native
*.bit = svn:mime-type=application/octet-stream
*.c = svn:mime-type=text/plain;svn:eol-style=native
*.cat = svn:eol-style=native
*.cgi = svn:eol-style=native
*.cgp = svn:mime-type=text/plain;svn:eol-style=native
*.classpath = svn:eol-style=native
*.cmd = svn:eol-style=native
*.coe = svn:mime-type=text/plain;svn:eol-style=native
*.cpp = svn:mime-type=text/plain;svn:eol-style=native
*.css = svn:mime-type=text/plain;svn:eol-style=native
*.cwiki = svn:eol-style=native
*.data = svn:eol-style=native
*.dcl = svn:eol-style=native
*.do = svn:mime-type=text/plain;svn:eol-style=native
*.doc = svn:mime-type=application/msword
*.dsp = svn:eol-style=CRLF
*.dsw = svn:eol-style=CRLF
*.dtd = svn:eol-style=native
*.egrm = svn:eol-style=native
*.ent = svn:eol-style=native
*.grm = svn:eol-style=native
*.g = svn:eol-style=native
*.h = svn:mime-type=text/plain;svn:eol-style=native
.htaccess = svn:mime-type=text/plain;svn:eol-style=native
*.html = svn:mime-type=text/plain;svn:eol-style=native
*.ihtml = svn:mime-type=text/plain;svn:eol-style=native
*.in = svn:eol-style=native
*.ini = svn:mime-type=text/plain;svn:eol-style=native
*.java = svn:eol-style=native
*.jed = svn:mime-type=text/plain;svn:eol-style=native
*.jpg = svn:mime-type=image/jpeg
*.jsp = svn:eol-style=native
*.js = svn:eol-style=native
*.junit = svn:eol-style=native
*.m4 = svn:mime-type=text/plain;svn:eol-style=native
*.mif = svn:mime-type=text/plain;svn:eol-style=native
*.mod = svn:eol-style=native
*.ngc = svn:mime-type=application/octet-stream
*.pdf = svn:mime-type=application/pdf
*.pen = svn:eol-style=native
*.pl = svn:eol-style=native
*.png = svn:mime-type=image/png
*.ppr = svn:mime-type=text/plain;svn:eol-style=native
*.project = svn:eol-style=native
*.properties = svn:eol-style=native
*.py = svn:mime-type=text/plain;svn:eol-style=native
*.rb = svn:eol-style=native
*.rdf = svn:eol-style=native
*.rnc = svn:eol-style=native
*.rng = svn:eol-style=native
*.rnx = svn:eol-style=native
*.rtf = svn:mime-type=application/msword
*.sh = svn:mime-type=text/plain;svn:eol-style=native
*.svg = svn:mime-type=text/plain;svn:eol-style=native
*.tim = svn:mime-type=text/plain;svn:eol-style=native
*.tld = svn:eol-style=native
*.txt = svn:mime-type=text/plain;svn:eol-style=native
*.types = svn:eol-style=native
*.ucf = svn:mime-type=text/plain;svn:eol-style=native
*.v = svn:mime-type=text/plain;svn:eol-style=native
*.vh = svn:mime-type=text/plain;svn:eol-style=native
*.vhd = svn:mime-type=text/plain;svn:eol-style=native
*.vhdl = svn:mime-type=text/plain;svn:eol-style=native
*.vho = svn:mime-type=text/plain;svn:eol-style=native
*.xco = svn:mime-type=text/plain;svn:eol-style=native
*.xcat = svn:eol-style=native
*.xconf = svn:eol-style=native
*.xegrm = svn:eol-style=native
*.xgrm = svn:eol-style=native
*.xise = svn:mime-type=text/plain;svn:eol-style=native
*.xlex = svn:eol-style=native
*.xls = svn:mime-type=application/msexcel
*.xmap = svn:eol-style=native
*.xml = svn:mime-type=text/plain;svn:eol-style=native
*.xsd = svn:mime-type=text/plain;svn:eol-style=native
*.xsl = svn:mime-type=text/plain;svn:eol-style=native
*.xslt = svn:mime-type=text/plain;svn:eol-style=native
*.xsp = svn:mime-type=text/plain;svn:eol-style=native
*.xul = svn:mime-type=text/plain;svn:eol-style=native
*.mhs = svn:mime-type=text/plain;svn:eol-style=native
*.mss = svn:mime-type=text/plain;svn:eol-style=native
*.pao = svn:mime-type=text/plain;svn:eol-style=native
*.mpd = svn:mime-type=text/plain;svn:eol-style=native
*.bbd = svn:mime-type=text/plain;svn:eol-style=native
*.ldd = svn:mime-type=text/plain;svn:eol-style=native
*.pdd = svn:mime-type=text/plain;svn:eol-style=native
*.xje = svn:mime-type=text/plain;svn:eol-style=native

Fastboot on ubuntu can't find devices

2011-05-18T18:14:00.001+08:00

1. Open a terminal window.
2. Log in as root.

sudo -i

3. Create a UDEV rule file.

cat > /etc/udev/rules.d/51-android.rules

This should give you a blinking cursor at the very beginning of a blank line, it’s waiting for you to tell it what the file needs to contain.

4. Enter this AFTER YOU REPLACE “XXXX” WITH YOUR VENDORID:

SUBSYSTEM=="usb", SYSFS{idVendor}=="XXXX", MODE="0666"

(You can find your vendor ID on this page.
For example, for my Dell Streak, I would use:

SUBSYSTEM=="usb", SYSFS{idVendor}=="413c", MODE="0666")

5. Press CTRL + D to save, it should return you to the terminal prompt

6. chmod the new file

chmod a+r /etc/udev/rules.d/51-android.rules

7. Reboot system

8. Try fastboot. It should work now.

fastboot devices

Ubuntu -wine中文乱码的解决方法

2011-04-25T21:20:00.000+08:00

新装的wine中文全是乱码，需要修改一下几个配置文件，找到一篇比较详细的配置说明，分享一下：

步骤：
1. 初始设置
运行 winecfg，把模拟的 Windows 系统设置为 Windows XP 或者 Windows 2000。
2. 准备字体
为了让 Windows 应用程序看上去更美观，所以需要 Windows 下面的字体。
由于我已经将 simsun.ttc 复制到 /usr/share/fonts/windows/ 目录中了。所以我只需要在 ~/.wine/drive_c/windows/fonts/ 目录中为 simsun.ttc 创建一个符号连接：

cd ~/.wine/drive_c/windows/fonts
ln -s /usr/share/fonts/windows/simsun.ttc simsun.ttc
ln -s /usr/share/fonts/windows/simsun.ttc simfang.ttc

创建一个 simfang.ttc 是许多 Windows 应用默认使用 simfang.ttc 字体。
3. 修改 ~/.wine/system.reg
装好字体后，还要修改一下 Wine 的注册表设置，指定与字体相关的设置：
gedit ~/.wine/system.reg
（一定要使用 gedit 或其他支持 gb2312/utf8 编码的编辑器修改这些文件，否则文件中的中文可能变乱码）
搜索： LogPixels
找到的行应该是：[System\\CurrentControlSet\\Hardware Profiles\\Current\\Software\\Fonts]
将其中的：
"LogPixels"=dword:00000060
改为：
"LogPixels"=dword:00000070
搜索： FontSubstitutes
找到的行应该是：[Software\\Microsoft\\Windows NT\\CurrentVersion\\FontSubstitutes]
将其中的：
"MS Shell Dlg"="Tahoma"
"MS Shell Dlg 2″="Tahoma"
改为：
"MS Shell Dlg"="SimSun"
"MS Shell Dlg 2″="SimSun"
4. 修改 ~/.wine/drive_c/windows/win.ini
gedit ~/.wine/drive_c/windows/win.ini
在文件末尾加入：

[Desktop]
menufontsize=13
messagefontsize=13
statusfontsize=13
IconTitleSize=13

5. 最关键的一步，网上很多文章中没有提到的一步──把下面的代码保存为zh.reg，然后终端执行
regedit zh.reg

REGEDIT4
[HKEY_LOCAL_MACHINE\Software\Microsoft\Windows NT\CurrentVersion\FontSubstitutes]
"Arial"="simsun"
"Arial CE,238"="simsun"
"Arial CYR,204"="simsun"
"Arial Greek,161"="simsun"
"Arial TUR,162"="simsun"
"Courier New"="simsun"
"Courier New CE,238"="simsun"
"Courier New CYR,204"="simsun"
"Courier New Greek,161"="simsun"
"Courier New TUR,162"="simsun"
"FixedSys"="simsun"
"Helv"="simsun"
"Helvetica"="simsun"
"MS Sans Serif"="simsun"
"MS Shell Dlg"="simsun"
"MS Shell Dlg 2"="simsun"
"System"="simsun"
"Tahoma"="simsun"
"Times"="simsun"
"Times New Roman CE,238"="simsun"
"Times New Roman CYR,204"="simsun"
"Times New Roman Greek,161"="simsun"
"Times New Roman TUR,162"="simsun"
"Tms Rmn"="simsun"

再winecfg，就可以看到中文能正常显示了。

Why use Active-Low reset signal?

2011-03-29T06:48:00.002+08:00

Just list some reasons that I think they are correct. Comments are welcome.

1. Board design methods. Usually capacitor circuit is used for Power-On-Reset, such that the voltage at reset pin gradually goes to HIGH value. And by this time all reset activity is done.
2. In CMOS technology, the falling edge of a signal is sharper than a rising one.
3. Library implies.
4. After reset, the reset signal change to high, so the reset signal will not infer by noise.
5. Personal habits

VCS and coverage

2011-03-22T06:50:00.000+08:00

As usual I am putting mixed unstructured infromation on yet another tool, this time it is VCS.
I believe that it will provide a lot of practical information for users than the user guides or any other tutorial
provides. Any questions, please write to me at avimit at yahoo dat com.

VCS is 3 step process
1. Analyze (vhdlan vlogan) This command complies the given code and checks for syntax errors.
2. Elaborate ( vcs or or or )
3. Simulate ( simv )

While using VHDL design files, a simulaiton file 'synopsys_sim.setup' is usually defined, which defines
the compiled vhdl library.
Example 'synopsys_sim.setup' file:
------------
WORK > DEFAULT
DEFAULT : ./work
memlib : ./mem_lib
xm_bus_lib : ./xm_bus_lib
---------------------------------
The first line maps the WORK library to a name 'DEFAULT', and the second line maps the 'DEFAULT' library
to a physcial directory called './work'.
The second line defines a library memlib which is mapped to a physcial directory called 'mem_lib'.

In the absence of any 'synopsys_sim.setup' file in your working directory, vcs will look for the same file in your home directory,
and if there is no 'synopsys_sim.setup' in your home directory, it will look for the same file in the tool installation directory.
The default 'synopsys_sim.setup' is in the tool installation directory, which maps the default work directory to '.'.
You will see complied VHDL files in '.' in case you dont have a 'synopsys_sim.setup' file.

Example vhdlan commands:

vhdlan -w memlib../../pid_filter/rtl/fun_pkg.vhdl
vhdlan -w work ../vhdl/state_machine.vhd
vhdlan ./state_machine_tb.vhd

Example elaboration commands:
vcs -cm line+cond+fsm+tgl+path pid_filter_tb
This steps generates an executable file which is named simv by default. This name can be changed.

Example simulaiton commands:
simv -ucli -do file.cmds
Contents of a simple file.cmds
---------------
run 1 ms
exit
------------------------------------
simv -gui
simv -cm line+cond+fsm+tgl+path -gui
simv -g generics_file

contents of 'generic_file'
----------------
assign 1 /TOP/LEN
assign "OK.dat" /TOP/G1/vhdl1/FILE_NAME
assign (4 ns) /TOP/G1/VHDL1/delay
assign 16 /TOP/width
assign 4 /TOP/add_width
------------------------------------------

VCS can be a 2 step process if only verilog is being used
vcs [compile options]

Generating Makefile:
vcs -lca -makedepends=makefile state_machine_tb
It seems that the same above command is used to generate makefile, and to do an incrimental compliation.
Incremental compliation is enabled by default:

VCS commands
removing like ncrm
updating like ncupdate
hierarchy browsing using commands
dump values in a txt file like ncsim
how to define the hierarchy
forcing nets in simulation, syntax.

LEDA:
Latches, linting, cross clock domain checking. Can write the rule in leda.

setenv VCS_HOME <>
set path = ($VCS_HOME/bin $path)
syschk.sh -v : will tell about environment
vcs -doc
command_name -help

The simulation flow:
synopsys_sim.setup : to map logical and physcial libraries
vlogan
vhdlan
vcs
vsim

setenv SYNOPSYS_SIM_SETUP / : global preference
1 tools setup
2 home
3 current dir
4 $SYNOPSYS_SIM_SETUP

include: not sure.

WORK> logical_name
Example:
WORK > gate_lib
gate_lib : /libs/glib

LIBRARY_SCAN = TRUE | FALSE
ASSERT_IGNORE = NOTE
ASSERT_IGNORE_NOTE
ASSERT_IGNORE_WARNING
ASSERT_IGNORE_ERROR
ASSERT_IGNORE_FAILURE

TIME_RESOLUTION = 10 ps

ASSERT_STOP = NOTE | WARNING | ERROR | FAILURE | NOSTOP

RUNREAD =
run this file automatically when it starts.

show_setup

show_setup -lib

-v means file containing many modules
-y means directories where tech libs are

makedepends

-xlrm
uum : unified use model. $VCS_HOME/doc/uum.pdf

-ucli - Enable Tcl command-line interface
-debug : allows to dump waveforms
-debug_all : line debug
-cm : enable coverage options

vcs -makedepends =
gamke makefile

vcs -cflags "vcs -hsopt improve gate-level and debug simulation speed

vcs -debug_pp (post processing)
for tcl and gui
use
vcs -debug

checkpointing:

$vcdpluson
$dumpvars

vcs -debug +memcbk to dump say vhdl record types, which are not dumped by default
initial $sdf_annotate(...);
vcs -sdf=[min|typ|max]:instance_name:

-P $VCS_ROOT/include/hdl_xmr.tab for
hdl_xmr instead of init_signal_spy in modelsim

library synopsys;
use synopsys.hdl_xmr_pkg.all

above to use the signal_spy kinda thing

ncmirror I guess is an eq in cadence.

add_wave /E/UUT/T_BLOCK/HRS_OUT
scope /E/UUT/A_BLOCK
add_wave RESET : will add a wave from A_BLOCK as the scope has been set

-gv -Override run time VHDL generics
-do instead of -i : because gives more than -i
-i

-gv can also be used with vcs -gv, which will help in changing all generics instead of limited as in vsim -gv

Recommendation: Always analyze verilog first

vcs -cm line : enable line coverage

IF it crashes, to clean up do the following:
rm -rf physcial_lib_dirs/*, simv*, csrc*
OPTIMISE = FALSE -- In synopsys_sim.setup

vcs -gui -debug : only show if compilation is successfull
vcs -debug_pp
vcs -debug_all
vcs -debug=1|2|3|4(level of debug)

simv -gui : preferred way of doing it. I.E first create a executable.

vcs -assert dve -Enable assertion debug
dve -vpd

run -posedge my_sig

restart

help -ucli
help -gui

alias

dump -file -type VPD
dump -add /tb
dump -add -depth
dump
dump -fid -VPD0 -add * -depth 0

fid is a file identifier returned by command dump -file -type VPD
add '-aggregates' in the dump command for dumping multi dim arrays

vpd2vcd +morevhdl
+morevhdl will dump 'records' type as well.

//VCS coverage off
//VCS coverage on

vcs -cm
simv -cm

urg : unified report generator
urg -dir ./simv.cm -grade -report ./reports

-------------------------------------
VCS libraries for VHDL compilation
-------------------------------------

VHDL files are compiled into a library.
Usually the default library is 'work' which is mapped to your current working directory i.e "."

Usually you will see that this 'work' library path is changed by defining the work library in synopsys_sim.setup file

WORK > DEFAULT
DEFAULT : ./work_lib

Then other libs may be defined in the same file i.e synopsys_sim.setup file:

memlib : ./memlib
pkg_lib : ./allcompiledpkgs
xm_bus_lib : ./xm_bus_lib

Further observation about vhdl library and vhdl compliation:

vhdlan -work work fun_pkg.vhdl
OR
vhdlan fun_pkg.vhdl

which means that 'fun_pkg.vhdl' is complied into work_lib
when you see the contents of work_lib you will see files FUN_PKG.sim FUN_PKG__.sim

Now I have another file called
xmbus_master.vhd which intends to use 'fun_pkg' package from the work lib
i.e the xmbus_master.vhd has the following lines

use work.fun_pkg.all

now if I compile the xmbus_master.vhd like this

vhdlan -w xm_bus_lib xmbus_master.vhd

I would expect that the complier picks up fun_pkg from work_lib. But it DOESNOT!

Which emplies that 'work' in the statemetn use work.fun_pkg.all refers to the library xm_bus_lib, to which xmbus_master.vhd is being complied into.

On the other hand if I do the following

vhdlan -w memlib fun_pkg.vhdl

Then I use the following lines in xmbus_master.vhd

library memlib;
use memlib.fun_pkg.all;

then I compile xmbus_master.vhd like

vhdlan -w xm_bus_lib xmbus_master.vhd

Then things are FINE, this time the complier picks up complied 'fun_pkg' from the memlib.

So the conclusion is:

when using 'use work.abcd.all', 'work' refers to the current compliation lib given with -w option while compliling the file
containing 'use work.abcd.all' , and NOT to the 'work_lib' which is the default compliation lib

IMP CMDS:

show_setup -lib
show_setup

llib

llib -l pidf
It will show the source file, dependency files

vhdlan options:

-q : quite
-nc : supress the copyright message
-l : log file

VCS OPTIONS:

vcs -debug_all : to enable force/line debug etc.

vcs -o gives named output executable

VCS/Synopsys Code Coverage:

3 Step Process: (after vhdlan or vlogan)
Step 1: Include -cm option during vcs: This step makes sure that the selected code is complied for selected type of coverage
Example:
vcs -cm line+cond+fsm+tgl+path pid_filter_tb
OR
vcs -cm_tgl mda -lca -cm line+cond+fsm+tgl+path -debug_all pidf_tb
OR
vcs -lca -cm line+cond+fsm+tgl+path -debug pidf_tb -cm_tgl mda -cm_hier cm_hier.file

Step 2: Include -cm option during simulation: This Step makes sures that simulator doesnot forget to collect coverage data during simulaiton
Example:
simv -cm line+cond+fsm+tgl+path -gui

Step 3: cmView : for gui based analysis : This Step will let you see coverage results in a GUI
Example:
cmView

Step 3: vcs -cm_pp : for batch mode post processing. This step outputs report files
Example:
vcs -cm_pp -cm_report summary
This will generate human viewable reports in the simv.cm/reports directory.
it also writes a summary file in the same directory, named 'cmView.summary'

Example command
vcs -cm line+cond pid_filter_tb

vcs -cm line+cond+fsm+tgl+path pid_filter_tb

adding -path gives an Error to avoid it use -lca

vcs -lca -cm path pid_filter_tb

And dont forget the -debug, in case you want to see anything : ).

vcs -lca -debug_all -cm line+cond+fsm+tgl+path pid_filter_tb

Still I have to face problems, so the final command line looked like:

vcs -cm_tgl mda -lca -cm line+cond+fsm+tgl+path -debug_all pidf_tb

Now simulaiton may be launched, again all the coverage options given at the 'vcs' compilation
MUST be given to the simv as well or there will be NO coverage recorded.
But then you cant use '-cm_tgl mda'. You see dont apply your common sense, or nothing will work.
After all vcs is developed by Synopsys not Google.

simv -cm line+cond+fsm+tgl+path -gui

NOTES:

-cm option creates simv.cm directory

During Simulation following files are produced:
test.line and test.fsm etc.. depending upon the coverage option.

To over ride the default 'test' name you can use
vcs source.v -cm line -cm_name test1
vcs source.v -cm line -cm_name test2 ...etc
OR
simv -cm line -cm_name test2
simv -cm line -cm_name test3 etc...

Also, during simulation, VCS and VCS MX write the cm.decl_info file
in either the simv.cm/db/verilog directory (for Verilog) or the simv.cm/
db/vhdl directory (for VHDL). cmView needs this file to show
coverage information.

If you invoke your binary executable from a different location, then
use -cm_dir option at runtime to specify the the path for the
coverage database directory

By default VCS does not compile the following for coverage:
• The source code in Verilog library directories
• Verilog library files
• Any module defined under the celldefine compiler directive

yv
For compiling for coverage source code from Verilog libraries.
celldefine
For compiling for coverage modules defined under the

vcs source.v -v mylib.v -y /net/libs/teamlib -cm fsm -cm_libs yv+celldefine

To prevent this lowering of coverage percentages, use the
-cm_noconst compile-time option
Constant filtering for toggle coverage is available only for
Verilog-only designs

simv -cm fsm -cm_log run1.log

Hierarcy in the design, and inclusion/exclusion of modules/files/instances.
-tree instance_name [level_number]
A level number of 0 (or no level number) specifies the entire
subhierarchy, 1 specifies only this instance, 2 specifies this
instance and those instances directly under this instance, and so
on

vcs -lca -cm line+cond+fsm+tgl+path -debug pidf_tb -cm_tgl mda -cm_hier cm_hier.file

cm_hire.file contents
begin
line+cond+fsm+tgl+path -file ../../pid_filter/rtl/fun_pkg.vhdl
end
begin
line+cond+fsm+tgl+path -tree STATE_MACHINE_TB 1
end

Interesting observation
If I miss (all) coverage options on the command line, with this file its an error
If I miss (all) coverage options in the cm_hier.file, its an error.

Various hit and trials:
Works
vcs -lca -cm line+cond+fsm+tgl+path -debug pidf_tb -cm_tgl mda -cm_hier cm_hier.file
simv -cm line+cond+fsm+tgl+path -gui
cm_hier file is:
begin
line+cond+fsm+tgl+path -module pidf
//The above line means exclude line, cond, fsm, tgl, path coverage from module pidf
end

Another example which worked
begin
cond+tgl+path -module pidf
end

I intended to exclude cond+tgl+path, and include the fsm coverage.
The above does write the fsm coverage, since fsm is not excluded from the list inside the cm_hier.file
NOTE: line coverage is always opened for modules or instances that have cond/path/fsm/branch coverage ON.

After several unsuccessfull runs to use '-tree' options, I concluded that it is 'case sensitive', even though i have a VHDL design,
and in my vhdl design pidf_tb, and pidf_u1 are lower case.
For some reason I am required to put the instance name in upper case
Following works
begin
fsm+line -tree PIDF_TB.PIDF_U1
end
BUT the following DoestNOT work.
begin
fsm+line -tree pidf_tb.pidf_u1
end

Now my objective is only to remove the top level testbench from coverage collection. For this I will have to use [level number]
begin
line+cond+fsm+tgl+path -tree PIDF_TB 1
//using level number 1 will make sure only the testbench level is excluded from the coverage collection
end

If I dont use the [level number] in front of PIDF_TB, then by default all scopes under PIDF_TB will be excluded from coverage
This is the same as using level number 0.

PROBLEM: while trying to use the -file option
------------------------
Warning-[VCM-HFUFR] Hier Config: regions not found
In the hier config file ( given by -cm_hier option ), pattern "-file or
specified by -filelist ---
/projects/leota/amittal/block_design_flow_dev/pid_filter/rtl/pidf.vhd" did
not match any pattern.
Please check the hier config file "cm_hier.file".

Warning-[VCM-HFNM] Hier Config: No pattern match
None of the patterns in the hier config file ( given by -cm_hier option )
matched any pattern.
Please check the hier config file "cm_hier.file".
----------------------------------------------------------------------

I have been trying to use -file option and above is the warning message. The corresponding cm_hier.file is
Note that I have used full path for the file I wanted to exclude. This doesNOT work.
---------------
begin
line+cond+fsm+tgl+path -file /projects/leota/amittal/block_design_flow_dev/pid_filter/rtl/pidf.vhd
end
--------------------------------

Now if I use relative path, then vcs does not complain about the file and things go on fine: The corresponding cm_hier.file is
This Does Work.
-------------
begin
line+cond+fsm+tgl+path -file ../rtl/pidf.vhd
end
----------------------------

The HDL Compiler and Behavioral Compiler user can use the
//synopsys translate_off directive in place of the //VCS
coverage off pragma and the
//synopsys translate_on directive in place of the //VCS
coverage on pragma.
The //VCS coverage on pragma enables line coverage after a
//synopsys translate_off directive and a
//synopsys translate_off directive disables line coverage
after a //VCS coverage on pragma.
Similarly the //VCS coverage off pragma disables line coverage
after a //synopsys translate_on directive and a
//synopsys translate_on directive enables line coverage after
a //VCS coverage off pragma.

Pragmas do not exclude module instances. For example:
module test;
reg clk, a;
// Synopsys translate_off
mod1 inst1(a,clk);
// Synopsys translate_on
.
.
.
endmodule
This example does not exclude test.inst1 from coverage

--synopsys coverage_off or --VCS Cover off
--synopsys coverage_on or --VCS Cover on
--vhdlcoveroff
--vhdlcoveron

Glitch supression.
To prevent this, there is the -cm_glitch compile-time option. Its
syntax is as follows:
vcs -cm line+cond+tgl -cm_glitch period

The -cm_glitch option is also a runtime option, but it only works
for toggle coverage

Collecting an Execution Count
-cm_count compile-time option

Post Processing:
vcs -cm_pp -cm_report summary
The above command is used to post process the results of Code Coverage generated during simulaion.
This command produces results in simv.cm/reports directory.

Some more imp commands:
vcs -cm_pp -cm line+cond -cm_report testlists

NOTE:
The graphical user interface (GUI) for cmView does not display
path coverage information. You must have cmView write path
coverage reports

VCS and VCS MX do not monitor the if statement in the for loop
statement and the if statement in the user-defined task

Branch coverage is implemented for Verilog simulation only :(

NOTE:
By default VCS and VCS MX do not monitor for branch coverage if
and case statements and uses of the ternary operator (?:) if they
are in user-defined tasks or functions or in code that executes as a
result of a for loop. You can, however, enable branch coverage in
this code. See “For Loops and User-Defined Tasks and Functions”
on page 4

Assignment Coverage
-cm_line assigntgl compile-time option and keyword argument.
Note:
This is a Verilog-only feature. There is no similar report for VHDL

Glitch suppression does not work for VHDL code

Call Google Voice Number with SIP

2011-03-09T06:37:00.000+08:00

Say you are wanting to contact your friend, whose Google Voice Number is (555)123-4567. You could now sign up for a free SIP to SIP service, register your account via an SIP app (such as csipsimple or sipdroid), and contact +15551234567@sip.voice.google.com. Doing this would call your friend’s Google Voice number at no cost. The sip.voice.google.com suffix was not previously known to work in any capacity.

Free Timing Diagram Drawing tools

2011-02-24T19:37:00.002+08:00

Many a times we need to generate/draw timing diagrams for multitude purposes. While browsing web for the same I came across these free/easy-to-use timing diagram drawing utilities.

Timing Diagram Font -- Timing diagram can be generated in MS Word using this
Timing Analyzer -- A tool for doing the same
Timing Diagram from verilog - using the above tool and small snippet of verilog code, one can generate timing waveform from the design itself. One problem I see with it is that the code snippet doesn't use verilog macro for achieving the same. Handy Timer - A simple and handy timing diagram editor
Timing Editor - Another free waveform editor
Draw Timing - Command line based waveform drawing SW which take a script as its input

Emacs: Start window default size

2011-02-24T04:12:00.000+08:00

dit or create ~/.Xdefaults

Put something like this in it:

Code:

Emacs.geometry: 80x30+0+30

Save the file. This should make emacs open a window which is 80 characters wide, 30 lines tall, and shifted 0 pixels to the right and 30 pixels down from the upper left corner.

Then in a terminal run:

Code:

xrdb -merge ~/.Xdefaults

Launch emacs.

fastboot says "< waiting for device >" forever

2011-02-09T04:17:00.002+08:00

To be able to use fastboot, you need to be running either an ADP1 or the Engineering Bootloader on your HTC phone.

If you are developing on a linux host, you may need to tweak UDEV to recognize the phone in fastboot mode. You may already have done this to get the phone recognized in Eclipse, but you need to do it again for fastboot, since fastboot uses a different device ID: 0bb4:xxxx. The warning sign is that fastboot says "<>" forever, even when you have the "FASTBOOT" message on the phone; if this happens, try adding the device ID 0bb4:xxxx to your UDEV configuration for Android.

The following config file, in /etc/udev/rules.d/11-android.rules, seems to work:

SUBSYSTEMS=="usb", ATTRS{idVendor}=="0bb4", ATTRS{idProduct}=="xxxx", MODE="0666", OWNER="your login name"
SUBSYSTEMS=="usb", ATTRS{idVendor}=="0bb4", ATTRS{idProduct}=="xxxx", MODE="0666", OWNER="your login name"

NOTE: change "your login name" to your Linux login ID. Also note that the product ID bit is optional (probably easier to leave it out), and you need to change "0bb4" to the vendor ID for your phone if it isn't made by HTC (whose vendor ID is 0bb4). You can find the vendor id using 'lsusb'. An alternative to this is just to run fastboot as root, using sudo.

Display Colorful Messages

2011-01-12T07:35:00.000+08:00

How many among you know that you can actually display color messages using Verilog and SystemVerilog?

You can implement a logic in your testbench to have nicely colored display messages at the end of your simulation which will give you a PASS/FAIL messages. I have written a piece of code given below and you can refer the same. I have captured a snapshot of output which you can see below.

program clr_display();
class color ;
task display ();
$display("%c[1;34m",27);
$display("***************************************");
$display("*********** TEST CASE PASS ************");
$display("***************************************");
$write("%c[0m",27);

$display("%c[1;31m",27);
$display("***************************************");
$display("*********** TEST CASE FAIL ************");
$display("***************************************");
$display("%c[0m",27);
endtask
endclass

initial
begin
color clr;
clr = new ();
clr.display ();
end
endprogram

OUTPUT:

The message to be printed is ("%c[TYPE;COLOURm",27);.

TYPE specifies how the message should be?

1 set bold
2 set half-bright (simulated with color on a color display)
4 set underscore (simulated with color on a color display)
5 set blink
7 set reverse video

COLOR specifies the message color.

30 set black foreground
31 set red foreground
32 set green foreground
33 set brown foreground
34 set blue foreground
35 set magenta foreground
36 set cyan foreground
37 set white foreground

With an above example you can have a display messages with colors. So this way you can have nicely and colored messages on your terminal.

在SDK 2.2模擬器中安裝Market

2010-12-20T10:49:00.001+08:00

1. 建立AVD，名稱為DAVID_2.2

2. 執行「開始—執行—cmd」，預設會在這個資料夾：
C:\Documents and Settings\%HOME%>

3. 切換目錄至「.android/avd/DAVID_2.2」，指令參考如下：

C:\Documents and Settings\David.Lanz>cd .android
C:\Documents and Settings\David.Lanz\.android>cd avd
C:\Documents and Settings\David.Lanz\.android\avd>cd DAVID_2.2.avd

畫面結果：

C:\Documents and Settings\David.Lanz\.android\avd\DAVID_2.2.avd>

4.複製SDK裡的system.img至此，指令如下：

copy d:\sdk\android\platforms\android-8\images\system.ing

5.在DOS視窗中切換目錄至SDK的tools資料夾，手動啟動模擬器，指令：

cd d:\sdk\android\tools\
emulator -avd DAVID_2.2 -partition-size 96

順利執行模擬器畫面

6.在DOS視窗裡執行指令，取出build.prop檔案。

adb pull /system/build.prop

7.利用文字編輯器開啟編輯build.prop這個檔案，將 ro.config.nocheckin=yes 移除（再最前面加上 mark 符號 #）

8.將剛才取出修改好的檔案存檔，然後執行以下指令將檔案放回去。

adb remount
adb push build.prop /system

9.至此下載Froyo用的Market程式，將之解壓縮後，存放至SDK資料夾(舉例如下)：

D:\SDK\android\tools\GoogleServicesFramework.apk
D:\SDK\android\tools\Vending.apk

10.將步驟9的兩個apk檔案丟入模擬器/system/app資料夾，並刪除SdkSetup.apk，指令如下：

adb push GoogleServicesFramework.apk /system/app
adb push Vending.apk /system/app
adb shell rm /system/app/SdkSetup.apk

11.關閉 Emulator（直接關閉模擬器的視窗即可）。

12.切換目錄至avd的資料夾下：
C:\Documents and Settings\%HOME%\.android\avd\DAVID_2.2.avd>

執行以下指令，刪除由系統產生的「userdata-qemu.img」與「userdata.img」、「cache.img 」這三個檔案刪除，讓Emulator完成初始化。

del userdata*.img cache.img

13.執行「Android SDK and AVD Manager」來啟動模擬器。

大功告成，Market順利在模擬器裡執行。第一次執行Market必須要以google帳號登入，登入後即可下載程式囉。

I can install the market, but I can't install App from it. Maybe someone can help me.

Change your Network Card MAC Address on Ubuntu

2010-12-07T07:01:00.000+08:00

There are a lot of reasons you might want to manually set your MAC address for your network card. I won’t ask you what your reason is.

To change this setting, we’ll need to edit the /etc/network/interfaces file. You can choose to use a different editor if you’d like.

sudo gedit /etc/network/interfaces

You should see the line for your network interface, which is usually eth0. If you have dhcp enabled, it will look like this:

auto eth0
iface eth0 inet dhcp

Just add another line below it to make it look something like this:

auto eth0
iface eth0 inet dhcp
hwaddress ether 01:02:03:04:05:06

Obviously you would want to choose something else for the MAC address, but it needs to be in the same format.

sudo /etc/init.d/networking restart

You will need to restart networking or reboot to take effect.

Enchanter Space Studio

Finite State Machines (FSM) design in Verilog

SystemVerilog Resouces

How to create tag/branch with git-svn

How to download Chrome Extension and install it from local

Compile UVM DPI for QuestaSim

Free Online Courses from Top Universities

Git Resources

Source code / binaries / GUI

Setting up Git server

Install Git from source

Diff/merge tools

Git submodules

Git-svn

Remote repositories

Git through proxies

Git prompt

Documentation - git related sites

Documentation - books / guides / tutorials

Documentation - cheat sheets

Documentation - misc

Github tutorials

Wireless Mesh Network (WMN)

[GIT Submodule] Fatal: Reference is not a tree : xxxx

Can't make/receive phone calls on DHD

Migrating a Subversion Project to Git on BitBucket (From Neogregious)

Using Git with Subversion

Fastboot on ubuntu can't find devices

Ubuntu -wine中文乱码的解决方法

Why use Active-Low reset signal?

VCS and coverage

Call Google Voice Number with SIP

Free Timing Diagram Drawing tools

Emacs: Start window default size

fastboot says "< waiting for device >" forever

Display Colorful Messages

在SDK 2.2模擬器中安裝Market

Change your Network Card MAC Address on Ubuntu