Team VLSI

VLSI EDA Companies in India | Top EDA Companies

2022-02-20T15:19:00.008+05:30

In any modern electronic chip, there are multimillion logic gates inside it. To handle the design part of any such chips engineers need to take the help of CAD tools. The CAD tools used for ASIC development is called Electronic Design and Automation (EDA) tools.

In the ecosystem of the semiconductor industry, EDA companies play a vital role. All the service/product companies take support from these EDA companies to develop any chip. The EDA companies are very specialized to solve new challenges especially related to a new technology node. Some EDA companies also work on the IP development side also along with tools development and support.

In this article, we have listed the top 10 EDA companies along with their basic details like their offices and India and offshore, their LinkedIn page and their website. Hope this article will help you to explore the EDA sector.

S.N	Company name	Inception	Offices in India	Offices Outside India	LinkedIn	Website
1	Cadence Design Systems	1988	Noida, Bengaluru Pune, Ahmedabad	USA, Europe, China,Japan, Malaysia, Singapore, Korea, Taiwan	LinkedIn	Website
2	Synopsys Inc	1986	Bengaluru, Noida Hyderabad, Pune Mumbai	USA, Canada Europe, China Singapore, Korea Taiwan, Japan	LinkedIn	Website
3	Mentor Graphics Acuired by Siemens EDA In 2017	1981	Noida Bengaluru Hyderabad	USA, Canada Europe, Taiwan Japan Rusia	LinkedIn	Website
4	Xilinx	1984	Hyderabad, Bengaluru	USA, Europe, China, Japan Singapore, Korea	LinkedIn	Website
5	Ansys	1970	Mulshi (Maharastra) Bengaluru, Pune Hyderabad, Noida	Canada, USA Europe, China Singapore, Japan Korea Taiwan	LinkedIn	Website
6	Keysight Technologies	2014	Bengaluru, Kolkata Gurugram	USA, Europe, China, Malaysia Taiwan, Singapore, Korea, Japan	LinkedIn	Website
7	Silvaco Inc	1984	Bengaluru	USA, Brazil Japan, Taiwan Korea, China Singapore, Europe	LinkedIn	Website
8	Dorado Design Automation Acquired by Synopsys	2003	Bengaluru	USA, China	LinkedIn	Website
9	Agnisys Inc.	2007	Noida	USA, Europe, China, Taiwan Korea, Japan	LinkedIn	Website
10	Aldec	1984	Bengaluru	USA, Europe, Japan	LinkedIn	Website

Your suggestions are most welcome in the comment section.

Thank you!

VLSI Product Companies in India | Top 30 Semiconductor Product Companies

2022-02-07T01:30:00.013+05:30

The electronics devices which we use on daily basis either come directly from a Semiconductor product company or the final chip developed by the product company is sold to some other company and they use the chip and make the final product and market it. Example: A Samsung mobile phone or a laptop of HP which is powered by an AMD processor. That's the reason why common people also know the name of a semiconductor product company whereas the name of a service company is not known to common people. Whereas the role of service companies is limited to supporting product/IP companies, they are the best solution provider in the industry and have expertise in a particular type of work.

So most of the semiconductor professionals want to join a product company, its not true for all but it's true for most. These product companies could be either a fabless company that takes support from a pure-play foundry to build their chip or they have their own foundries like Intel and Samsung.

In this article, we have listed out the product companies especially those working in India along with some basic details like offices in India and offices outside India, their LinkedIn page, their website and provided the hyperlink in the list. We believe this will be very helpful to you to know the industry in a better way and also will help you to select a good company if you are looking for a job change or wanted to enter into the industry first time.

S.N	Company name	Inception	Offices in India	Offices Outside India	LinkedIn	Website
1	Intel Corporation	1968	Bengaluru, Hyderabad	USA, Europe, China, Israel, Japan, Malaysia, Singapore, S. Korea, Taiwan	LinkedIn	Website
2	Samsung Electronics	1938	Bengaluru	S. Korea, USA, Singapore, Bangkok,	LinkedIn	Website
3	Nvidia	1993	Bengaluru, Pune, Hyderabad, New Delhi	USA, Brazil, Europe, Israel, China, Japan, Korea, Taiwan, Singapore	LinkedIn	Website
4	AMD	1969	Bengaluru, Hyderabad, Mumbai, Gurugram	USA, Europe, China, Korea, Singapore, Taiwan, Japan	LinkedIn	Website
5	Google	1998	Bengaluru, Mumbai, Hyderabad, Gurugram	USA, Europe, China, Australia, Korea, Singapore	LinkedIn	Website
6	MediaTek	1997	Bengaluru, Mumbai, Noida	USA, Europe, China, Dubai, Taiwan, Singapore, Korea, Japan	LinkedIn	Website
7	Qualcomm	1985	Bengaluru, Chennai, Hyderabad, Mumbai, Noida, Gurugram	USA, Europe, Canada, Israel, Russia, Korea, Singapore	LinkedIn	Website
8	Apple	1976	Bengaluru, Hyderabad, Chennai, Gurugram, Mumbai	USA, Canada, Europe, Australia, China, Singapore, Japan, Russia, Korea	LinkedIn	Website
9	NXP	2006	Bengaluru, Hyderabad, Noida, Pune	USA, Canada, Europe, China, Japan, Korea, Singapore,	LinkedIn	Website
10	Texas Instruments	1951	Bengaluru	USA, Europe, China, Japan, Korea, Malaysia, Taiwan	LinkedIn	Website

S.N	Company name	Inception	Offices in India	Offices Outside India	LinkedIn	Website
11	Cisco	1984	Bengaluru, Pune, Hyderabad	USA, Europe, China, Singapore, Australia	LinkedIn	Website
12	Broadcom Inc. Acquired by Avago Technology in 2016	1991	Bengaluru, Hyderabad, Pune	USA, Canada, Europe, China, Australia, Japan, Korea, Singapore	LinkedIn	Website
13	Micron Technology	1978	Bengaluru, Hyderabad	USA, Europe, Singapore, China, Taiwan	LinkedIn	Website
14	Arm Acquesition in progress by Nvidia	1990	Bengaluru, Noida	USA, Europe, China, Korea	LinkedIn	Website
15	Analog Devices	1965	Bengaluru, Hyderabad	USA, Canada, Europe, Australia, China , Israel, Japan, Taiwan, Turkey	LinkedIn	Website
16	STMicroelectronics	1987	Noida, Bengaluru	Europe, USA, China, Australia, Korea, Japan, Singapore	LinkedIn	Website
17	Juniper Networks	1996	Bengaluru	USA, Europe, China, Israel	LinkedIn	Website
18	Xilinx	1984	Hyderabad	USA, Europe, China, Singapore, Japan	LinkedIn	Website
19	ON Semiconductor Now Onsemi	1999	Bengaluru	USA, Europe, China, Taiwan, Japan, S.Korea	LinkedIn	Website
20	Applied materials	1967	Bengaluru, Chennai, Mumbai, Noida, Coimbatore	USA, Canada, Europe, Israel, China, Japan, Korea, Taiwan	LinkedIn	Website

S.N	Company name	Inception	Offices in India	Offices Outside India	LinkedIn	Website
21	Nordic Semiconductor	1983	Hyderabad	USA, Europe, China, Taiwan, Korea	LinkedIn	Website
22	Microchip	1989	Bengaluru, Chennai, Pune, New Delhi	USA, Europe, China, Singapore, Australia, Taiwan, Korea, Japan	LinkedIn	Website
23	Redpine Lab	2001	Hyderabad	USA	LinkedIn	Website
24	Marvel Technology	1995	Pune, Bengaluru	USA, Europe, China, Singapore, Taiwan, Korea, Japan	LinkedIn	Website
25	Silicon Labs	1996	Hyderabad	USA, Canada, Europe, Singapore, China, Japan, Korea, Taiwan	LinkedIn	Website
26	Ceremorphic	2020	Hyderabad	USA	LinkedIn	Website
27	Rambus	1990	Bengaluru	USA, Holand	LinkedIn	Website
28	Fungible Inc.	2015	Bengaluru	USA	LinkedIn	Website
29	Seagate Technology	1979	Pune	USA, Europe Singapore	LinkedIn	Website
30	Western Digital Acquired: SanDisk in 2016	1970	Bengaluru	USA	LinkedIn	Website

We tried to list out all the known product companies here, but if we missed some, please help us to add them here by your comment in the comment box below this article.

Thank You.

VLSI Service Companies in India | Top 40 VLSI Service companies

2022-02-04T01:35:00.531+05:30

If you are looking for a job change or you are a fresher and wanted to enter the VLSI Industry, then this article will help you a lot. It is difficult to find the company details or even a list of VLSI companies working in India. In this article, we have tried to prepare a list of all the well-known service companies working in India. We have also included the basic details of all the companies like the year of inception of the company, the City where the company has offices, the LinkedIn page link, and the website of companies.

Let me explain how this article could be useful to find the companies where should you apply. First I would like to recommend you make a decent LinkedIn profile and let's connect to people of your domain. You will find the official LinkedIn page of each company, you can go to the company's official LinkedIn page by just clicking the hyperlink provided in the list. You are suggested to follow the company so that you will get the feed when those companies post any opening on LinkedIn. By following the company on LinkedIn you will get updates on the job posts by the company.

You can also follow/connect to the recruiters of those companies where you want to join. You can make connections to the people of those companies. Further, you can also ask for a reference if you know someone on LinkedIn and working where you want to apply. Believe me, reference has a very good impact and If you have matching experience or skills set, you can easily get the interview call.

S.No	company name	Inception	office in India	Offices outside India	LinkedIn	Website
1	eInfochips Acquired by Arrow Electronics in 2018	1994	Ahmedabad, Bangalore, Pune, Hyderabad, Noida, Kolkata, Bhubneshwar	USA, Japan	LinkedIn	Website
2	Eximius Design Acquired by Wipro in 2020	2013	Bangalore, Ahmedabad,	USA, Malaysia	LinkedIn	Website
3	OpenFive (Formerly Open-Silicon) Acquired by SiFive in 2020	2003	Bangalore, Pune	USA, Israel France, China Korea, Taiwan Japan	LinkedIn	Website
4	Sankalp Semiconductor Acquired by HCL Technologies in 2019	2005	Bangalore, Kolkata	USA	LinkedIn	Website
5	Synapse Design Inc. Acquired by QuEST Global in 2021	2003	Bangalore, Ahmedabad	USA, China Europe, Japan Malaysia, Vietnam	LinkedIn	Website
6	Cerium Systems Acquired by Tech Mahindra in 2020	2013	Bangalore, Cochin, Vizag	USA, Malaysia	LinkedIn	Website
7	SeviTech Systems Acquired by UST Global in 2018	2013	Bangalore, Hyderabad		LinkedIn	Website
8	Altran Technology Acquired by Capgemini Engineering in 2019	1982	Bangalore	France, China,	LinkedIn	Website
9	Cypress Semiconductor Crop Acquired by Infinion Technology in 2020	1982	Bangalore, Chennai, Noida, Mumbai	USA, Japan, China, Europe	LinkedIn	Website
10	Graphene Semiconductor Acquired by L&T Technology Service in 2018	2013	Bangalore	USA, Europe, Israel, China Singapore, Taiwan	LinkedIn	Website
11	wafer Space Acquired by ALTEN Calsoft Labs, in 2019	2011	Bangalore	USA	LinkedIn	Website
12	Mirafra Technologies	2004	Bangalore, Hyderabad	USA, Singapore	LinkedIn	Website
13	Insemi Technology	2013	Bangalore	NA	LinkedIn	Website
14	Moschip	1999	Hyderabad, Bangalore	USA	LinkedIn	Website
15	Digicomm Semiconductor	2012	Bangalore, Pune, Hyderabad, Noida	USA	LinkedIn	Website

S.No	company name	Inception	office in India	Offices outside India	LinkedIn	Website
16	SignOff Semiconductors	2015	Bangalore	USA	LinkedIn	Website
17	PerfactVIP	2010	Bangalore, Bhubaneswar Ahmedabad, Noida	USA	LinkedIn	Website
18	TrueChip	2008	Noida, Bangalore	USA	LinkedIn	Website
19	Infineon Technologie	1999	Bangalore, Chennai, Noida, Mumbai	USA, Japan, China, Europe	LinkedIn	Website
20	Smart SOC	2016	Bangalore	USA, Europe, Singapore, Malaysia, South Koria	LinkedIn	Website
21	Ensilica	2001	Bangalore	USA, Europe	LinkedIn	Website
22	ASM Technologies	1968	Bangalore	USA, Singapore, UK, Canada, Mexico, Japan	LinkedIn	Website
23	SPEL	1988	Chennai	USA, Europe, Singapore	LinkedIn	Website
24	Spicaworks	2018	Bangalore, Noida, Hyderabad	USA	LinkedIn	Website
25	DXCorr Design Inc	2005	Bangalore	USA, Japan	LinkedIn	Website
26	SkandySys	2017	Bangalore	NA	LinkedIn	Website
27	Igniterium	2012	Bangalore, Kochi	USA	LinkedIn	Website
28	Adept Chip Services	2011	Bangalore	USA	LinkedIn	Website
29	Chip logic	2018	Bangalore	UK	LinkedIn	Website
30	Incise Infotech	2010	Noida, Bangalore		LinkedIn	Website

S.No	company name	Inception	office in India	Offices outside India	LinkedIn	Website
31	ChipOn Time Technologies	2019	Bangalore	NA	LinkedIn	Website
32	Marquee Semiconductor	2019	Bhubaneswar	USA, Singapore, Philippines	LinkedIn	Website
33	Pozibility Technologies	2016	Bangalore	USA	LinkedIn	Website
34	BitSilica	2019	Hyderabad		LinkedIn	Website
35	Laksh Semiconductors	2016	Bangalore, Hyderabad		LinkedIn	Website
36	NikSperri Technologies	2020	Bangalore		LinkedIn	Website
37	Soctronics		Hyderabad, Bangalore	USA	LinkedIn	Website
38	Alpha-Numero		Bangalore, Ahmedabad, Hyderabad	USA	LinkedIn	Website
39	Masamb	2007	Noida, Bangalore		LinkedIn	Website
40	Blueberry Semiconductors	2017	Bangalore		LinkedIn	Website
41	BloomConn	2021	Ahmedabad		LinkedIn	Website
42	Excel VLSI Technology	2017	Bangalore		LinkedIn	Website
43	Siliconus Technologies	2016	Bangalore		LinkedIn	Website
44	Sivaltech	2016	Bangalore	USA	LinkedIn	Website
45	Cientra		Bangalore	USA, Europe	LinkedIn	Website
46	Pronesis Technologies	2014	Ahmedabad	Singapore	LinkedIn	Website
47	Sibridge Technologies	2007	Ahmedabad	USA	LinkedIn	Website

There are many more companies and I might miss their name in this list. I am requesting my readers if you find any name is missing, you may add their name in comment section, I will add them to the list.

Thank you.

Input Files Required for PnR and Signoff Stages

2021-11-05T17:15:00.005+05:30

In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of inputs into two parts, one is mandatory and the other is an optional set of inputs.

A. Place and Route stages:

I. Pre Placement Stage

Gate level netlist
Logical Library
Physical Library
SDC file

Optional inputs

Block partition def
Pin def
Power plan script
Welltap placement rule
Macro placement guidelines
MMMC Setup file
EndCap, Decap cell list
Spare Cell module definition and rule

Note: (i) Logical Library, Physical Library and SDC file will be required in each stage.

(ii) Netlist will get modified in each stage and an updated netlist will be used in the next stage.

II. Placement

Preplace database

Optional Inputs

Placement blockage script
Path groups script
Placement setting script
Timing and Congestion Optimization scripts
Clock tree constraints (In case of Early Clock Flow)

III. CTS

Placement database
Clock tree constraints

IV. Route

CTS database

V. Chip Finish

Route database
Filler cell list

B. Metal Fill

OASIS/GDS of Chip finish stage

C. RC Extraction

ICT File / Quantus Techfile (qrcTechFile)
MMMC setup file
LEF
DEF
Merged OASIS/GDS file

D. IR Analysis

Technology/Library Data

LEF file (.lef)
LIB file (.lib)
Technology file (.tech)
GDS file of standard cells (.gds)
GDS Layer map file
Device model file*
SPICE Netlist of Standard cells*

Design Data

DEF file
Netlist file
SPEF file
STA File* (Timing Window, slew, instance frequency, clock domain info)
VCD file*
PLOC file*

* Files required only for dynamic analysis

Types of Analysis:

I. Static IR Analysis

II. Dynamic IR Analysis
III. EM Analysis

E. Static Timing Analysis

Design Netlist
SDC
LIB
SPEF
MMMC view definition file

Optional inputs:

Instance-based IR drop file
SI library
Base/Incr Delay annotation file

F. Physical Verification

I. DRC

Merged GDS file
DRC RuleDeck file

II. Antenna

Merged GDS file
Antenna RuleDeck file

III. Layout Vs Schematic Check (LVS)

PD Netlist
Merged GDS file

IV. Logic Equivelence Check (LEC)

Golden Netlist
PD Netlist
LEC Constraints (if any)

In case you find anything missing or need a correction, please let me know in the comment section.

Thank You!

TSMC 7nm, 16nm and 28nm Technology node comparisons

2021-09-25T01:39:00.008+05:30

Before starting this article, I would like to say this topic is highly sensitive and we are not supposed to reveal any foundry data. So Instead of making comments on any data which you know and I have not given here, you may mail me along with the reference link. The purpose of writing this article is only to make aware to new people who are preparing to enter into VLSI industry in an easy way.

Kindly note that none of the data is being added from our side in this article which is not available in the public domain. You will notice that many fields I have left blank intentionally, which you may know but the foundry has not reviled those data in the public domain.

So this article is just a collection of various data available on different websites instead of any data from my side. I will provide all the references at the end of this article, from where I have collected this information. I took all the care to maintain confidentiality but if anything you found is not appropriate to publish, please let us know through email.

Below image may help you to understand various parameters of FinFET. This image is taken from https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/

Figure: FinFET structure and dimensions


S.N	Parameters	7nm	16nm	28nm
A.	Transistor wise
1	Transistors	4th Gen FinFET	FinFET	Planner MOSFET
2	Gate Length (Lg)	16 nm	34 nm	24 nm
3	Fin Width (Wfin)	6 nm		NA
4	Fin Heigth (Hfin)	52 nm	37 nm	NA
5	Fin Pitch (Pfin)	30 nm	48 nm	NA
6	Contacted Poly Pitch (CPP)	57 nm (HD) 64 nm (HP)	90 nm	117 nm
7	W effective	3.66
8	Minimum Metal Pitch (MMP)	40 nm	64 nm	90 nm
9	Standard Cell Height	240 nm (6T)
10	Transistor Density	91.2 M/mm2	28.9 M/mm2
11	6T SRAM bit cell size	0.027 um2	0.074 um2	0.127 um2 (HD)
12	Contact Trench Fill	Cobalt	Tungsten
13	Opertating Voltage		750 mV	800mv and 1V
B	Metal wise
14	Total Metal Layers	17		10
15	Double Patern Layers	7 (Fin, Poly, M0, M1, M2, M3, M4)
16	Patterning	Fins (SAQP) Poly to M4 (SADP) Rest Single		DP
17	DUV/EUV	193nm DUV + 13.5nm EUV	193nm DUV	193nm DUV
18	Via Pillers	Yes	No
19	PG Routing	Dual M1 PG Structure
C	General
20	Mass Production Year	Q2 2018	2015	Q4 2011
21	Speed Improvement	30%, comapre 16nm with same power
21	Speed Improvement		40% , compare to 28nm with same power
22	Power Reduction	-55% compare to 16nm with same speed
22	Power Reduction		-55% compare to 28nm with same speed
23	Density	3.3X compare to 16nm
23	Density
24	Cut metal	Area reduction through Cut metal layers. Routers are cut metal aware

Reference

https://en.wikichip.org/wiki/7_nm_lithography_process
https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/
https://en.wikichip.org/wiki/16_nm_lithography_process
https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_28nm
https://en.wikichip.org/wiki/28_nm_lithography_process
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/tsmc2

Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers

2021-09-24T00:39:00.004+05:30

One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely be TCL (Tool Command Language). TCL is widely used everywhere in the VLSI industry because many tools are based on the tcl. We can directly interact with the tool using tcl CLI (Command Line Interpreter).

It has been observed that many beginners initially hesitate to start the TCL scripting. Most of the cases user know the basic tcl commands but how to connect all them and create a script is the only problem. I would say even you know some basic tcl commands you can start writing your own script for your day to day requirements. Most important this is BEGIN the process of writing the script. Here I am presenting 20 common tcl syntax which I use frequently in my tcl scripting and hope it will help you to break the ice. Improvement and prefection will come as you practice but start is the most important. These 20 syntax will definitely help you lot to start and improve your tcl scripting a lot.

1. foreach loop

Use:
Where we have to iterate on each element on a list of elements and have to perform some operation on each element.
Syntax:
foreach var $Var_list {
//operations for each $var
}
Example:
Supposed we want to print all the macros instance name, reference name and total count of macro in a block.
set macros [dbGet [dbGet top.insts.cell.baseClass block -p2].name]
set i 0
foreach macro $macros {
set refName [dbGet top.insts.name $macro -p].cell.name
puts "$macro - $refName "
incr i
}
puts total macro count = $i

2. Nested foreach loop

Use:

If we have to iterate on each element of a list and then further we need to iterate on each parameters associated with the element.
Syntax:
foreach i $list1 {
//list2 is derived based on $i
   foreach j $list2 {
      //operations on $j
   }
}
Example:
Suppose we have to find the list of feedthrough pins and the total numbers of feedthrough pins in each edge of a rectilinear block. A script can be written like this for that.

set edges [dbget top.terms.edge -u]
set i 0
foreach edge $edges {
   set j 0
   foreach pin [dbget [dbget top.terms.edge $edge -p].name ft* ] {
       puts "$edge $pin"

       incr j
   }
   puts "$edge : total ft pin count = $j"
   incr i

}
puts "Toal edge of block = $i"

3. for loop

Use:

Where we want to repeat a loop in between a certain start and endpoint with a certain increment

Syntax:

for {initialization}{condition}{increment} {

statements

}

Example:

Suppose we want to know the metal layer's width and pitch of all metal from M5 to M10 in innovus tool.

for {set i 5}{$i <= 10}{incr i}{

set width [dbGet [dbGet top.head.layers.name M{$i} -p].minWidth]

set pitch [dbGet [dbGet top.head.layers.name M{$i} -p].pitchX]

puts "M{$i} $width $pitch"

}

4. Nested for loop

Same as above example only syntax change and one loop in running inside another loop.
Syntax:
for {initialization}{condition}{increment} {
   for {initialization}{condition}{increment} {
       statements
   }
}

5. while loop

Use:

When we need to repeat a loop until a particular condition is true.
Syntax:
while {condition} {
//statements
}
Example:
Suppose we need to read all the lines of a file one by one and store is a variable dynamically.

set fp [open my_report.tcl r]
while {[gets $fp data] >= 0} {
   if {[regexp "VIOLATED" $data]} {
      //desired statement for operation
   }
}

6. if-else conditions

Use:
When we want to do something if certain condition is true. We can either put else statement or skip it.
Syntax:
if {bolean_condition} {
//statements
} else {
//Statements
}

Example:
Suppose we need to convert SVT cell to ULVT cell.

if {[regexp SVT $cell_ref]} {
set eco_ref [regsub {SVT} $cell_ref "ULVT"]
}

7. if-elseif... else condition

Use:

When we want to check another if condition if one prior if condition is not true.

Syntax:
if {bolean_condition} {
//statements
} elseif {bolean_condition} {
//Statements
} else {
//statement

}

Example:

Suppose we need to read a report file inside a script and generate an eco file in which if there is Weak Driver then need to upsize the driver from D1--> D3, D2-->D4 and D3-->D5. We can write script as follow.

set fp [open existing.rpt r ]
set fp1 [open new_ecofile w+]
while {[gets $fp data] >= 0 } {
   if {[regexp "Weak Driver" $data]} {
       set inst [lindex $data 7]
       set cell [lindex $data 8]
       if {[regexp D1BWP $cell]} {
           regsub "D1BWP" $cell "D3BWP" newCell
       } elseif {[regexp D2BWP $cell]} {
           regsub "D2BWP" $cell "D4BWP" newCell
       } elseif {[regexp D3BWP $cell]} {
           regsub "D3BWP" $cell "D5BWP" newCell

       }
       if { [ info exists newCell ]} {
       puts $fp1 "ecoChangeCell -inst {$inst} -cell $newCell"
   }
}
close $fp
close $fp1

8. Arithmetic operations

Use:
When we need to add/subract/multiply/devide some numbers

Syntax:
set s [expr $a + $b + $c]
set d [expr $a - $b ]
set m [expr $a * $b]
set d1 [expr $a / $b ]

Example:

If we need to know, how much space will take a 4X, a 8X and a 16X decap cell together.

set cell4X [dbget [dbget head.libCells.name $decap4 -p].size_x -u]
set cell8X [dbget [dbget head.libCells.name $decap8 -p].size_x -u]
set cell16X [dbget [dbget head.libCells.name $decap16 -p].size_x -u]
set distX [expr $cell16X + $cell16X + $cell4X]
puts $distX

Note: Be careful like in the following cases

like:
>expr 3/2
>1

>expr 3/2.0
>1.5

9. regexp

Use:
To match the regular expression. Regular expression has a wide list, we will see only few which we use mostly.
Syntax :
regexp {pattern} $string
Example:

Suppose we want to change the D1, SVT cell to D2, LVT we can check the cell with regexp and then we can perform regsub for substitution and generate an eco file.

if {[regexp {D1BWP240H11.*PDSVT} $clock_cell_ref]} {
   regsub {D1BWP240H11} $clock_cell_ref {D2BWP240H8} new_clock_cell_ref
   regsub {PDSVT} $new_clock_cell_ref {PDLVT} new_clock_cell_ref
   puts $fp_w "ecoChangeCell -inst $clock_cell -cell $new_clock_cell_ref"
}

10. regsub

Use:
To substitute the regular expression
Syntax:
regsub {old_pattern} $string {new_pattern} new_string_name
Example:
As explained in the regexp section

11. Reading a file

Use:
Many times we have to read a report file inside the tcl scripting to make some fixes based on the violation reported. We read the file line by line and store the data in a file pointer variable dynamically.
Syntax:
set fp [open existing_file_name r]

Example:

we can read a file line by line in a variable like this.

set fp1 [open $old r]
while {[gets $fp1 data] >= 0 } {

// $data variable will get string line by line of old file

}
close $fp1

12. Writing a file

Example:
We can write a file and close that as follow.

set fp2 [open $new w+]
puts $fp2 "Whatever we want to write in file will go line by line"
close $fp2

13. proc

Use:

If we need to use a few lines of code, again and again, we can make a proc using those codes and can call easily by the proc name. No need to write code every time.
Syntax:
proc proc_name {} {
// lines of code
}
proc_name

Example:

If we need to find the basic details of a block, we can write a proc something like this.

proc blockInfo {} {
   puts "Block name: [dbget top.name]"
   puts "All Layers: [dbget head.layers.name]"
   puts "Block Area: [dbget top.fPlan.area]"
   puts "Box size: [dbget top.fPlan.box_size]"
   puts "Boxes: [dbget top.fPlan.boxes]"
   puts "Toatl pins: [dbget top.numTerms], Inputs - [dbget top.numInputs], Outputs -              [llength [dbget top.terms.isOutput 1 -p]]"
   puts "Macro Count: [llength [dbget top.insts.cell.baseClass block -p2]]"
   // Many more parameters can be added
}

We just need to source above file and call the proc blockInfo proc, it will display all the above info of block.

14. proc with arguments

Use:

Sometimes we need to pass some arguments in proc and we want the result of proc based on user argument.
Syntax:
proc proc_name { arg1 arg2 arg3 ...} {
// lines of code
}
proc_name arg1 arg2 arg3

Example:
Suppose we want to write a general proc in which if we pass the net_name, it should return the net_length of that particular net. We can write that as follow.

proc netLength {net_name} {
   set net_length 0
   set net_wires_length [dbget [dbget top.nets.name $net_name -p].wires.length]
   foreach i $net_wires_length {
       set net_length [expr $net_length + $i]
   }
   puts $net_length
}

Note:

We can also set a default value of the proc argument. So in case the user does not pass the argument value, proc will take the default value.
Syntax:
proc proc_name {{arg1 10} {arg2 20}} {
set a $arg1
set b $arg2
// More statements
}
So if we call the proc like
proc_name

it will take the default value of arg1 and arg2 and will set a 10 and set b 20.

But if we call this proc like
proc_name 50

It will set a 50 and b 20

we can also call like
proc_name 50 45

In the above way proc will set a 50 and b 45

15. exec

Use:

To use bash command inside tcl script
Syntax:
exec date

Example:
set timestamp_prefix [exec date +%m%d_%H_%M]

16. dbGet/dbSet/dbQuery

Use:
These are the innovus tool-specific commands, and widely used in innovus tool related scripting.
Syntax and Examples will be discussed in a separate article.

The link will made available here [Not now].

17. list operations

Use:

There are various list operations, all are important in various way and frequently used.
Syntax:
llenght, lappend, lindex, lreplace, lset, lsort etc.

Example:

Kindly do the man command for more details

18. alias

Use:

To shorten a long command or a command with its switches to a short command.

Syntax:

alias short_commad "original_commad"

Example:

alias si "selectInst"

alias sn "selectNet"

19. grep

Use:

To find the particular pattern
Syntax:
exec grep "pattern" $file_name

egrep and zgrep are also used in place of grep.

Example:

Will discuss in details in a separate article

Link [Not now]

20. sed

Use:

sed is called stream editor, it can do lots of tasks. we use generally sed to replace or delete a particular pattern in a file or string.
Syntax:
exec sed

Example-1:

If we want to replace a line having particular unique pattern completely by another line . We can do that like folow.

exec sed -i "s|Pattern .*|$new_line|" $file_name

Example 2:

If we want to write some lines of code which are stored in a file just after a line having some uniqe pattern. we can do that as follow

set num [exec sed -n "/^Source Script.*/=" $file_name ]

incr num

exec sed -i "$num r $script_file" $file_name

Example 3:

If we want to delete all lines having a unique pattern

exec sed -i "/DEL*/d" $file_name

Note: grep, sed and awk is a very handy command for various operations, these commands has explained in more details in the following article.

Link [Not available now]

Thank You.

Interview questions for experienced Physical Design Engineer, Question set - 9

2021-09-08T23:04:00.007+05:30

Code: CDN4Y072021PD

Experience level: 4 Year

Profile: Physical Design Engineer

1. Introduction and physical design experience

2. What major differences have you observed in the 7nm and 14nm process nodes?

3. What is the functionality of this circuit? (He drawn schematic in paint)

4. Do you think, is there any issue with the above circuit? If so what would you suggest for improvement?

5. When clock gatting circuit has added in the design RTL/Synthesis/PnR?

6. What are the checks you perform before starting the floorplan?

7. What is a library check?

8. What are the information available inside the .lib file?

9. How is the timing of a cell defined in .lib file?

10. What if the .lib file is missing but .lef file is available for a cell? and similarly, if .lef file is missing but .lib file is present for a cell?

11. How do we define the core area for any block?

12. How do we decide the height and width of a block?

13. What are the guidelines we need to follow in macro placement?

14. Is there any rule for abutting the macros?

15. What steps exactly tool does in the placement stage?

16. Why do we use boundary cells?

17. Why can't we use placement blockage at the end of each row in place on the boundary cell?

18. What was the target latency in your block and what has been achieved?

19. Can you explain the ccopt method?

20. Which flavour of Vt cell you used in the clock tree?

21. Which type of derating you have been used in your different projects?

22. Why do we start using POCV when we had AOCV derate?

23. What is the shielding of a net? How it works?

24. Have you used shielding in your block?

25. What is NDR?

26. What is the difference between shielding and NDR? Can we use only one of these two?

27. Where did you placed the clock gating cell, near the sink or source?

28. Can you tell me the advantage and disadvantages of placing ICG near the sink and near the source?

29. What is CPPR?

30. (A diagram has been drawn in paint as shown below) In this diagram can you tell me between which edges the setup and hold timing will be checked?

31. If we change the scenario like below, Now between which edge setup and hold will be checked?

32. What is internal power and switching power?

33. What is the impact of the threshold voltage of a cell on the internal power and switching power?

34. What is the impact of IR drop in cell delay?

35. How do you fix the static IR drop?

36. What was the limit of dynamic IR drop in your recent project?

Flip-flop and Latch : Internal structures and Functions

2021-08-28T20:30:00.001+05:30

The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D indicates delay, which means the output is a delayed version of input D. Whereas a latch is the simplest and a basic sequential element. In general, there are two latches used to make a flip flop. the flip-flop is sensitive to clock edge and the latch is sensitive to clock level. The following section will explain the internal structure and operation of flip flops and latch. In this article, we will limit our discussion to only d type flip flops and d type latch which are most common in ASIC design.

Schematic of the latch and flip-flop

The simplest design latch and flip-flop both are having 3 pins, One input data pin (D), one input clock/enable pin (CP/E) and, one output pin (Q). There could be a set and reset pins also but here for simplicity we are not including those in our discussion. The symbolic representation of a latch and a flip flop has been shown in figure-1.

Figure-1: Symbolic representation of Latch and flip-flop

In figure-1, the symbol of a posotive level sensitive d-latch and a positive edge triggered d flip-flop has shown. In negative latch and flip-flop only a dot appears before the E/CP pin. At a high level, we can think that latch and flip flop in terms of 2:1 multiplexer. A latch can be realized using a 2:1 multiplexer whereas to realize a flip flop, two multiplexers are required. Figure-2 showing the architecture of positive level sensitive d-latch and a positive edge triggered flip flop in terms of multiplexers.

Figure-2 : A positive d-latch and flip-flop using multiplexer

In a positive level sensitive latch the output is fed to I0 input of multiplexer as shown in figure-2. In same way in a negative level sensitive d-latch the output Q is fed back to input I1. A positive edge triggered d-flip flop is made of two negative level sensitive d-latch connected back to back. In case of negative d flip flop two positive level sensitive d-latch would be required. If we dive deep inside the multiplexer and go to the transistor level, we will find the transistor level schematic of a positive level sensitive d-latch and positive edge triggered d flip-flops as shown in figure -3.

Figure-3.a : A positive level sensitive d-latch using transmission gates

Figure-3.b: A positive edge triggered d flip-flop using transmission gates

A 2:1 multiplexer is made of two transmission gates and a transmission gate is made using a pMOS and an nMOS transistor as shown in the above figure. A latch is having two transmission gates in which the input of one transmission gate is connected to the output. A flip flop is made of two latches (that is four transmission gates) connected back to back as shown in figure-3. From the above figure, it is clear that a flip flop is having more transistors (double) as compare to a latch and hence a flip flop is having double the area as compared to the latch. The understanding of the working of latch and flip-flop is the most important part which will be discussed in the next section.

Working of a d- latch

The working of a positive level sensitive d-latch only is discussed here with the help of input and output waveform. The working of flip-flop will be discussed in the next section.

Figure-4: Input-Output waveform of latch

There are two transmission gates are used in a d-latch. In case of a positive level sensitive d-latch the output is feedback to the input of TGO transmission gate. Transmission gates are made of a nMOS and a pMOS as shown in above figure and it is being controlled by the enable signal E which is actually the clock signal. When the enable signal is high, the nMOS and pMOSof TG1 is in on state and at the same time, both transistors of TG0 are in off state and vice-versa happens when the enable signal is low. There is a direct path established from pin D to pin Q when the Enabe signal is high and it is called latch is in transperent state. But when enable signal goes low, TG1 gate is in off state and a feedback loop is established between Q to input of TG0 which insures that there is no change in output Q irrespective of changes in input pin D, which is termed as latch state. Figure-5 shows when the latch is transperent and when it is latched through the waveform.

Figure-5: Working of a positive level sensitive d latch.

The working of a positive level sensitive d-latch is straight forward, it keep passing the input D to Q when its enable signal E is high and and it keep the output Q unchanged when enable signal is low. Same can be seen in figure-5, only output changes when input changes and enable signal is high.

Working of a d flip-flop

In a positive edge triggered d flip flop, there are two negative level sensitive d latch connected back to back and the second latch is having inverted enable signal as compare to first latch. This inverted enable signal to second latch makes sure that both the latch never goes transperent or latched state simultaneously. A typical input output waveform has shown in figure-6 for better understanding.

Figure-6: Input output waveform of a positive d flip-flop

Lets consider the the case when the clock signal is low, the first latch is transperent and input D is transmitted up to QM point. But at the same time second latch will be in latched state because it gets inverted clock signal so the output Q is latched with QM. There is no chance the outupt Q will get changed in this duration.

The next moment when clock signal transits from low to high, the first latch will go from transperent mode to latched mode and second latch will go from latched mode to transperent mode. So during the clock transition from low to high, whatever signal is sampled at QM previously gets transferred to the output Q.

The next moment when clock signal goes to high, there is not transfer of input signal D anymore and Wahtever signal previously samples at QM will be available at output Q.

The next moment when the clock signal transits from high to low, first latch will trasit from latched to transparent mode and second latch will transit from transparent to latche mode. So at this edge of clock transition there will be no change in output.

The operation of positive d flip flop can be summarized as, the output changes only at the rising clock edge and at this moment input D is trasfered to output Q and all other moment output is remain unchanged. So it is better in terms of avoid glitch as comapare to latch but more in area and more prone to process variation. For detailed operation and comparison please watch this playlist.

Thank you.

Tie Cells in Physical Design

2021-08-23T16:23:00.007+05:30

The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any logic gate. The high/low signal can not be applied directly to the gate of any transistors because of some limitations of transistors, especially in the lower node. The limitation will also be discussed along with the schematic and operation of tie cells in this article. We will discuss the following sub-topics in this article.

Need of tie cells
Schematic of tie cells
The function of tie cells
Placement of tie cells

Need of tie cells:

In the lower technology node, the gate oxide under the poly gate is a very thin and the most sensitive part of the transistor. We need to take special care of this thin gate oxide while fabrication (associated issue is antenna effect) as well as in operation too. It has been observed that if the polysilicon gate connects directly to VDD or VSS for a constant high/low input signal, and in case any surge/glitch arises in the supply voltage it results in damage of sensitive gate oxide. To avoid the damages mentioned above, we avoid the direct connection from VDD or VSS to the input of any logic gates. A tie cell is used to connect the input of any logic to the VDD or VSS.

Figure-1: Need of tie cell

There are two types of tie cells.

Tie-high cell
Tie- low cell

As the name suggests, the tie-high cell's output is always high and the tie-low cell's output is always low.

Schematic of tie cells:

The tie cell has no input pin and only one output pin. The output of the tie-high cell is always high and the output of the tie-low cell is always low and it is the glitch-free output that connects to the input of any logic gates. The schematic of tie high cell and tie-low cell is shown in the figure-2.

Figure-2: Tie-high and tie-low cells

In the tie-high cell, the drain and gate of nMOS are shorted together and connected to the gate of pMOS, and output is taken from the drain of pMOS. Whereas in the tie-low cell the drain and gate of pMOS are shorted together and connected to the gate of nMOS and output is taken from the drain of nMOS. The function of these schematics is explained in the next section.

Function of tie cells:

Both tie-high and tie-low cells have similar working. Here working of the tie-high cell is explained. A similar logic can think for tie-low cell. From figure-2 tie-high cell, the drain and gate of nMOS are shorted.

So Vg = Vd
==> Vgs = Vds
Therefore, Vds > Vgs -Vt

This shows that the nMOS will always be in the saturation region. The configuration of MOS where drain and gate are shorted is popularly known as a diode-connected transistor. And when nMOS is behaving like a diode here, the gate of pMOS is always low and so pMOS is always in on state. When pMOS is in on state its drain which is output will always be high.

Similarly, for the tie-low cell, the pMOS is always in saturation region so the gate of nMOS is always high and hence the drain of nMOS will always be at the low logic.

One more important thing is here that the sudden spike in VDD or VSS will be not propagated to the output of the tie cell.

Placement of tie cells:

Tie cells are not present in the synthesized netlist and not placed in the initial placement of the standard cells. Tie cells are inserted in the placement stage and more specifically at the final stage of placement. Where ever netlist is having any pin connected to 0 logic or 1 logic (like .A(1'b0) or .IN(1'b1), a tie cell gets inserted there. Click here to read more about the placement stage and the order where the tie cell get inserted in the placement stage.

Thank you.

Integrated Clock Gating (ICG) Cell in VLSI

2021-08-21T22:56:00.004+05:30

Low power ASIC design is the need of the hour, especially for hand-held electronics gadgets. In all hand-held products, the customer demands more battery life. This could be possible only if our SoC (System on Chip) inside the gadget consumes lesser power. There are various low-power design techniques that are being implemented the reduce the power consumption of application-specific integrated circuits (ASIC). The clock gating technique is one of the widely used techniques for low power design. Integrated Clock Gating (ICG) Cell is a specially designed cell that is used for clock gating techniques. In this article, we will go through the architecture, function, and placement of ICG cells.

Why ICG Cell?

ICG cell basically stops the clock propagation through it when we apply a low clock enable signal on it. This phenomenon is termed clock gating. We use the ICG cell to stop the clock signal propagation to a big group of logic cells when the group is not required to operate. This is done through a clock enable signal generated internally in the block and applied to the EN pin of the ICG cell. We know that the total power consumption of an SoC is the sum of dynamic power and static power. The clock tree is a major contributor to dynamic power as the clock signal has maximum switching activities. The ICG cell allows to stop the clock signal propagation beyond it and it helps to reduce dynamic power consumption in the design.

The architecture of ICG Cell:

There are various ways to implement the clock gating techniques and there are many architectures of ICG cells also. Here the most common architecture is Latch-AND based ICG cell.

Figure-1: Latch-and based ICG Cell

Prevention of glitches is one of the qualities of ICG cells. The latch-and gate based ICG cell is good on that front and that's why this architecture of clock gating circuit is used widely. There are various architectures of ICG cells but we are limiting our discussion to only this architecture in this article.

The function of ICG Cell:

Figure-2: Waveform of ICG Cell

As shown in the above figure it provides a glitch-free clock gated output. and passed the clock single only when the enable signal is high and stop the clock propagation when enable signal is low.

Why not only AND gate as a clock gating?

The issue with the AND gate as clock gating is, it can not provide a glitch-free output whereas a glitch-free clock wave is highly desired.

Figure-3: AND gate as a clock gater

If there is a transition in clock enable signal when the clock signal is low, there is no effect on the gated clock. But if there is a transition in clock enable signal when the clock signal is high, there will be a glitch in the gated clock. To suppress such glitches, latch-and gate based ICG cell is preferred.
The placement of ICG cells will be discussed in the next article.

Thank you

Important questions from Readers:

1. Why do we use Latch in ICG why not flip flop? (by Ramcharan)

Ans:

1. As we not that flip flop will capture the data only at the edge of the clock signal so any data change between one active edge to next active edge will not be captured.

2. If we use -ve edge FF the setup timing requirement for FF to ICG will be half cycle which is again difficult to meet in case of ICG placed near the sink.

Here is a waveform showing the differences in operation.

Physical Design Interview Questions for 3 years experience , Question set - 8

2021-08-04T11:16:00.007+05:30

Code: EXIM4Y062021PD

Experience level : 3 years

Brief Introduction and major projects?
Tell me the most challenging part of your recent project
How does the lockup latch help to fix hold violations?
If we add a lockup latch, it might violate the setup? How will we fix it further?
How did you fix SigEM? What are patch wires?
What CTS constraints have you used?
How did you fix the setup violation?
Apart from setup and hold, what other checks do we perform in timing signoff?
What are the PV checks?
What are the sanity checks we do before starting PnR?

What are the reports of synthesis we check before PnR?
What are the physical cells we have used in PD and what are the uses of all those?
What is the latch-up issue and how well tap cells prevent latchup?
What is the endCap cell and what is the purpose of using that?
What is Dcap Cell and why do we use it?
What is the antenna effect?
What are the ways to fix the antenna effect?
How do antenna diodes help to fix the antenna violations?
If we have timing criticality and we can't use antenna diodes or floating gates, How can we fix the antenna?
If antenna violation is already the highest metal layer and we can use higher metal for metal hopping, how will fix the antenna?
How will you fix the antenna violations on via?
What is a metal cut layer?
What is the crosstalk delay?
What is the crosstalk noise?

Physical Design Interview Questions : Question set -7

2021-08-04T11:00:00.004+05:30

Code: CDN5Y062021PD

Experience level: 5 Years
For Application Engineer

What are the major differences between 7nm and 12/14nm technology nodes?
What are the new DRC rules in the 7nm technology node?
What is the via-piller?
What is double patterning?
How many layers have double patterning in the 7nm node?
How tool performs placement steps?
Why do we perform scan chain reordering?
What is scan mode, why do we need that?
What is ECF (Early Clock Flow) flow?
What are the benefits of ECF flow?

Can you explain the CTS flow?
What are the low power techniques used in data and clock paths?
Where does the clock-gater use?
Have you built a custom clock tree?
What are the constraints you have given to the clock tree?
How did you solve max_trans violations in the clock path?
How to provide different clock tap points in H-Tree?
How many clocks were there in your block?
How were they related?
How did you analyze the clock domain crossing paths?
What is a lock-up latch and how does it helps in hold fixing?
What was the target skew in your block?
What value of skew you achieved?

Placement Steps in Physical Design

2021-07-08T16:29:00.009+05:30

Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps in a sequence to complete the placement stage. In this article, we will try to understand what are the important steps and the order in which the EDA tools perform to complete the placement stage.

Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing. Every PnR tool provides various commands/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray to place and optimize it for better QoR. Placement does not place only the standard cells present in the synthesized netlist but also places many physical only cells and adds buffers/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps which the tool performs during the placement and optimization stage.

placement steps:

Pre Placement
Initial Placement / Course Placement / Global Placement
Legalization
HFNS (Hign Fanout Net Synthesis)
Iteration for Congestion, Timing, DRV, and Power Optimization
Multibit flop conversion
Timing optimization iterations
Scan-Chain Reorder
Tie Cell insertion
Save Design

1. Pre Placement:

Figure-1: Pre-placement step

Before starting the actual placement of the standard cells present in the synthesized netlist, we need to place various physical only cells like end-cap cells, well-tap cells, IO buffers, antenna diodes, and spare cells. A typical view after preplacement has shown in figure-1. Why these cells are required to place and how do we place them has been discussed separately in this article. Here we will focus mainly on the placement steps of standard cells present in the synthesized netlist.

2. Initial Placement / Global Placement / Course Placement

Figure-2: Global placement before legalization

Once the pre Placement stage has been completed, We can start the placement of standard cells but before that, we have to provide all the correct placement and optimization settings that we want to be applied while the tool does the placement and optimization. These settings could be like partial placement blockage or density screen setting, bound or region creation, cell/instance padding, path_groups and effort, enabling the early clock flow (ECF) in case of innovus, enabling the extreme flow, enabling the useful skew, global congestion effort, global timing effort, power effort, Multibit flop conversion and many more.

After providing all these placement settings we can call the placement command (place_opt_design in case of innovus). The tool first does the global placement in which the tool determines the approximate location of each cell according to the timing, congestion, and multi-voltage constraints (in the case of innovus Gigaplace engine is called in this step). Any pre-placed macros will work as a placement blockage. In this stage, the tool will not check any overlap of instances. A typical figure of global placement has shown in figure-2 where you can see that the standard cells are placed in an approximate location but without legalization.

3. Legalization

In the global placement stage, the instances are left with overlap. In this step, the tool will move the instances in nearby places to overcome the overlap. To match the proper power pins like the vdd pin of a standard cell should be on the vdd rail and vss on vss rail and for that if the fliping of instance is required tool also do the flipping. This process is called legalization. After this step, every instance should be placed in a legal location and there should be no overlaps. This step is also called refine placement.

4. HFNS (Hign Fanout Net Synthesis)

Initially, there are some nets which have very high numbers of fanout. We have a constraint of maximum fanout, so we need to distribute the sinks on nets to different drivers. The process of adding buffers and splitting the fanout is called high fanout net synthesis (HFNS). So In this step, all high fanout nets get synthesized.

5. Iteration for Congestion, Timing, DRV, and Power Optimization

In this step tool first, do an early global route and estimate the routing overflow/congestions in the design. The tool tries to initially minimize the congestion in this stage. Next, the tool starts the RC extraction to calculate the delay for setup analysis. The tool tries to minimize the setup WNS and TNS in this step. Similarly, the tool also tries to minimize the DRV and Power in this stage.

6. Multibit flop conversion

If the user enables the multi-bit flip flop conversion in the flow then the tool will first check the available multibit flops in the library. (You can read more about multi-bit cell here) The tool considers the criticality of timing associated with a single bit of flop and the user constraint set for multi-bit conversion and based on the constraints the tool converts the single-bit flop into multibit flops.

7. Timing optimization iterations

This is a long step in which the tool tries to minimize the WNS and TNS of each path group in various iterations. There are several iterations required to get a minimum WNS and TNS depending upon the effort set and initial WNS number. In case the result is not good after this stage, we can further run incremental optimization for timing. Similarly, for congetion, we can run congestion repair followed by incremental optimization to get a better result. But these additional steps will increse the run time.

8. Scan-Chain Reorder

Figure-3: Scan Chain before placement

Scan chain stitching has been done arbitrarily in synthesis. After placement and optimization, we have a location for each scan flops so it needs to be reordered for better routability. The tool performs a reordering of the scan chain in this step which is good for both timing and congestions.

Figure-4: Scan chain after placement

Figure-5: Scan Chain after Scan chain reodrder

9. Tie Cell insertion

There are some unused inputs of logic gates in the netlist which is tied to either vdd or vss. We can not leave any inputs of the standard cell as floating, it must be tied either vdd or vss. Connecting an input of logic cell that is the gate of a transistor directly to vdd or vss is not recommended and for that, we have tie high and tie low cells in the library. (You may watch this video on tie cells for more details). So In this step tool places tie high and tie low cells which is basically a single output logic cell, and it connects the input of the logic gate which needs to connect vdd or vss respectively.

10. Save Design

Finally, we save the database and we will use this database in the next stage, that is in the clock tree synthesis.

Clock Tree Constraints in VLSI | ccopt file in Physical Design | CTS Constraints

2021-06-28T18:12:00.010+05:30

Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every sequential element gets the clock within a target global skew limit. To build the clock tree we have to provide certain constraints as input to the APR tool, which commonly known as clock constraints, and in the case of the Innovus tool, this constraint file is popularly known as ccopt file.

In this article, we will learn some important clock tree constraints which are commonly used in every design and their actual meaning that why those constraints provided. Now a day it's very common that if you are going to appear in an interview in physical design and your experience is in the bracket of 0-5Y, you have to face the question related to clock tree constraints in your interview.

clocks tree constraints:

Clock tree cell list
Preferred clock tree routing layers and Non-Default Rules (NDR)
Target Skew
Target Maximum Transition
Target Maximum Capacitance
Maximum Fanout
Cell Density
Cell Halo

1. Clock tree cell list

We use clock inverters and clock buffers in the clock tree building. Sometimes we use only clock inverters and not clock buffers. We also use clock gating cells in the clock tree. so we have to provide the list of cells that we want to use in the clock tree.

set_ccopt_property inverter_cells {}

set_ccopt_property buffer_cells {}

set_ccopt_property clock_gating_cells {}

set_ccopt_property logic_cells {}

2. Preferred clock tree routing layers and Non-Default Rules (NDR)

We need to provide the top and bottom preferred routing layer for clock tree nets. We generally define here trunk and leaf net. the net which connects the clock to the sequential element's clock pin is called the leaf net and the net which delivers the clock to the leaf net is called trunk net.

set_ccopt_property -name trunckRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 2w2s

set_ccopt_property -name leafRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 1w2s

3. Target skew

Skew balancing is one of the challenges in clock tree optimization. We provide a target skew as a clock tree constraint. PnR tool will try to balance the skew within the given limit of skew.

set_ccopt_property -target_skew <>

4. Target Maximum Transition
We provide a max_trans limit for clock nets in the clock tree constraint. The tool will try to meet the max_trans limit.

set_ccopt_property -target_max_trans <>

5. Target Maximum Capacitance
We provide a max_cap limit for clock nets in the clock tree constraint. The tool will try to distribute the load capacitance and try to meet the max_cap limit.

set_ccopt_property -target_max_capacitance <>

6. Maximum fanout
We limit the maximum fanout of any instance in the clock tree through this constraint. Tool will try to build the clock tree by following this limit.

set_ccopt_property -max_fanout <>

7. Cell Density
A maximum cell density limit is mandatory for the clock tree instances.

set_ccopt_property -cell_density <>

8. Cell Halo
We need to provide a halo around the clock tree instance to avoid a denser placement which may cause IR / Crosstalk issue. So we provide halo constraints in the x and y direction over the cells.

set_ccopt_property -cell_halo_x <>
set_ccopt_property -cell_halo_y <>

These are the main constraint which we provide before the clock tree building. There are some more constraints but the main constraints are explained in the above sections. The following image summarizes the clock tree constraints.

CTS Constraints

Thank you! Any suggestions are welcomed in the comment section.

Installation of Synopsys EDA tools

2021-06-05T17:29:00.006+05:30

Most of the EDA tools used in the VLSI Industry are designed for use in UNIX operating system. These tools must require licenses to work which can be purchased from EDA Companies or a company that is authorized for sales and supports. Synopsys tools can be purchased either from www.synopsys.com or from authorized sales and support partner www.eigen.in (in India).

Once you buy the tools, they provide login credentials on their website. Using the login credential the licenses and tools can be downloaded to your local machine/server. We can also update the licenses whenever it gets expired and we can also download the latest release of any tools from the website using the login credential. For Synopsys tools, we need to login into their official website https://solvnet.synopsys.com to download the tools and licenses.

Generally, EDA companies provide support to install the tools and help in case of any issue, but it's better to know the installation process of tools and basic debugging to manage the tools in our own hands. The following section is going to describe how to download and install the Synopsys tools in your local machine/server.

Step-1: Download the synopsys installer, SCL and tools setup files

Go to https://solvnet.synopsys.com and login with your login credentials.

Solvenet Login

After login, you need to download:

Synopsys Installer (An application which provinde nice gui interface to install the tools)
SCL (Synopsys Common Licensing)
All the EDA tools which you have license and want to install.
Synopsys license (Incase it is not set already)

Step-2: Launch the synopsys installer GUI

Step-2.1: Open the terminal with root prevelage and go to the directory where synopsys installer is downloaded.

Step-2.2: Provide the execute permission to the synopsysInstaller.

chmod 755 synopsysInstaller_V3.2.run

Step-2.3: Run the following commands to unpack the installer ( -d switch is for creating a directory)

./synopsysInstaller_V3.2.run -d installer

Step-2.4: Go to installer directory created in above step and if you see the contents, it will look like.

cd installer

ls installer

Step-2.5: Now we have to launch the installer in GUI mode by following command.

./installer -gui

Step-3: Provide the source location (installation setup directory) and destination location (directory where you want to install the tool)

Step-3.1: After above step a GUI will be opened up. Now when we click to start, it will ask to site ID which is provided by synopsys when you purchase the tool.

Step-3.2: Next we need to provide the source location where the tools is kept which we want to install.

Step-3.3: Next we need to provide the destination location where we want to install the tool.

Step-3.4: Next we need to accept and proceed, after that installation will be started.

In the same way, we can install all the tools.Once we done with installation we need to configure the license and set a path of all the tools in form of a bashrc/cshrc file. That will be explained in seprate article.

Thanks

Temperature Inversion in VLSI

2021-05-29T17:57:00.006+05:30

If a simple question comes before you that "What will impact on the delay of a standard cell if temperature varies? " Are you going to answer straightforward the delay of the cell will increase with temperature OR The delay of the cell will decrease with temperature? If you are going with either of the above answers, Then you need to spare some moment in this article and understand the concept of Temperature Inversion.

Figure-1: Trend of cell delay with temperature

What is temperature inversion?

In general, as temperature increases, the delay of standard cells increases because of mobility degradation at higher temperatures. But in lower technology nodes the impact of temperature on the delay of the cell is inverse. In lower nodes, the delay of the cell decreases with an increase in temperature. So in the lower technology node, the effect of temperature on the delay of the cell is inverted and this effect is called the temperature inversion. The main reason behind this inversion is in the lower technology node, the effect of the threshold voltage is dominating over the mobility.

So an appropriate answer to the above question could be we should answer this question with respect to the technology node. One can say that at the lower technology nodes as temperature increases the delay of cell decreases. Here lower technology node means the technology node below 65nm. Why part of this question is important, but we should wait if it is asked further. In the next part, we will learn why temperature inversion occurs.

Figure-2: Temperature inversion

The following section will explain in detail of factors affecting the delay of cells and their variation.

Reason for temperature inversion

The delay of a cell is simply the time required to charge/discharge the load capacitance. The charging and discharging time of the load capacitor depends on the drain current. If the drain current is high, it will take a lesser time to charge/discharge the load capacitor and so delay will be lesser and vice-versa. Now let's see the dependency of drain current Id.

The saturation current of MOSFET is,

The drain current Id is directly proportional to the mobility of charge carriers. So as the temperature increases, the lattice scattering increases, and ultimately the mobility of the charge carrier decreases which leads to the decrease in drain current Id and so it increases in the delay of the cell.

Now let's come to the second important factor, the term (Vgs - Vt) in the above equation is called overdrive voltage. There is a variation in threshold voltage with temperature as per the following equation,

As temperature increases, the threshold voltage decrease, and overdrive voltage increases. This overdrive voltage is more dominating in the lower technology node because in the lower technology node the Vgs and Vt are more closers and so a slight change in Vt will have more impact on overdrive voltage. But in a higher technology node since Vgs is much larger than Vt so a slight change in Vt not causes much change in overdrive voltage. Again the Id is proportional to the squire of overdrive voltage. So changes in overdrive voltage are further amplified and it is dominating over the mobility in lower technology node.

In a nutshell, In a lower technology node, as temperature increases the threshold voltage decreases so overdrive voltage and drain current increase which leads decrease in cell delay. Here overdrive voltage is dominating over the mobility factor. But in higher technology nodes, overdrive voltage is not much dominating, and delay of the cell varies as per variation in carrier mobility and we have discussed as temperature increases mobility decreases and so drain current decreases which lead increase in cell delay.

So There are two major factors that drive the variation in cell delay, mobility and overdrive voltage. In lower technology nodes overdrive voltage is more dominating which causes the temperature inversion effect.

Thank you.

Interview questions asked for DFT Engineer (Fresher) - Question Set - 07

2021-04-28T08:50:00.012+05:30

Code: INTL0Y032021DFT

This interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic which will help the freshers in other domains too.

Round-1:

1) Differences between MOSFET and FINFET ?
2) Puzzle: A blind man walking in a desert has 2 red pills and 2 blue pills with him. He has to take one red pill and one blue pill each per day. How can he do that correctly?
3) Limitations of MOSFET
4) Puzzle: If a man climbs 15 m well. He climbs 4 m every day and slips 3 m . How many days it takes for him to get outside of the well?
5) What is set up time and hold time?
6) What is set up time and hold time violations?

7) What is metastability and do you know its physical significance?
8) What is a critical path?
9) How can you improve the timing?
10) How can you fix the setup time violations?
11) Implement a 2:1 mux for AND gate?
12) Draw the timing diagram of half adder?
13) What is blocking and non-blocking assignments?

14) What is synchronous and Asynchronous reset?

15) Why do we need DFT and what do you mean by that ?
16) Explain briefly the methods of DFT?
17) Why do you need to make flip flops initialized in an ad hoc technique?
18) What are controllability and observability?
19) If you fabricate a full adder and do the functional test and verify outputs are correct, then do you still require DFT also?
20) What is BIST?
21) What is JTAG?
22) Difference between verification and DFT?
23) What is yield?
24) Explain your course works and the projects.
25) Difference between RAM, ROM.
26) What is DMA?

Round-2:

1) Short channel effects in MOSFET.
2) Brief about JTAG.
3) Any insight into BSDL.
4) What are the different faults that occur while fabrication?
5) What is bridging fault?
6) What is fault collapsing?
7) Draw a D-flipflop along with a timing diagram.
8) What is Stuck at faults?

9) What do you mean by clock skew?
10) Is Hold time dependent on clock frequency?
11) Is clock skew an advantage or not?
12) Current technology node used in industry?
13) Is set up time-dependent on clock frequency?
14) Why do you need a reset in flip flop?
15) What is the multicycle path?
16) Any tools for DFT?

17) Why DFT is in the front end?
18) VLSI design flow.
19) OR gate using 2:1 mux
20) How to do if statement synthesis?
21) How do a case statement in Verilog synthesis?
22) What is Inferred latch?
23) List out a few Power optimization methods in STA.

My sincere thanks to the teamVLSI member who shared this genuine question set with us. If you feel such questions help you in your interview preparation, You are encouraged to share your interview questions with us at teamvlsi2014@gmail.com and help the community as you are getting help.

Multi Bit Flip Flop Vs Single Bit Flip Flops

2021-04-25T17:07:00.002+05:30

In modern ASIC design use of multi-bit flip flops (MBFF) has increased due to its various promising advantages of MBFF over single-bit flip flop (SBFF). Traditionally we study only a single-bit flip flop in our academics. So it becomes important to understand the design of multi-bit flip-flops, how it works, and what are the advantages/disadvantages of multi-bit flip-flops over single-bit flip-flops.

Why Multi-bit Flip Flops?

Multi-bit flip flop has many advantages due to its architecture over the single-bit flip flop. There are many recent research publications also which show these facts with proper statics. We also witness these advantages while place and route (PnR) implementation. Here I would like to explain the basic facts of MBFF in a simple way without any detailed statics. The exact statics can be referred from any recent research publications. The main advantages of multi-bit flip flop are as follows and that's why MBFF is used widely now a day.

Area reduction
Power reduction (promising for low power designs)
Better clock skew control
Timing improvement

So we can say that it improves the area, power, and timing. The reason for these advantages will be explained in the next section.

Multi-bit Flip Flop Architecture:

All the advantages of multi-bit flip-flops are due to their architecture. A single-bit FF and a 2-bit MBFF schematic have shown in the figure-1. A similar architecture can imagine for higher bit MBFF also.

Figure -1: Multi-Bit Flip Flop

One can notice that the inverter count reduces when we use the multi-bit flip flop as compare to the single-bit flip flop. The effect of this reduction is more visible when we use bigger MBFF. A comparison of inverter count in SBFF and MBFF has shown in figure-2.

Figure-2: Number of Inverters used in SBFF and MBFF

Instead of 16 inverters inside 8 single-bit flip flops, there are only 2 inverters used inside a 16-bit flip flop. A schematic of 8-bit MBFF has shown in figure-3.

Figure-3: 8-bit MBFF

As the number of inverters reduced in the case of MBFF, it saves the clock power and area. There is no change in the operation of flops after MBFF conversion. Now let's discuss the mechanism of how PnR tools convert the SBFFs into MBFFs.

MBFF conversion:

Figure-4: Placement of flops before MBFF conversion

Figure-5: Placement of MBFF after conversion

Figures 4 and 5, show how the conversion of SBFF into MBFF. Figure-4 is showing the scenario before MBFF conversion is done and figure-5 shows the scenario after MBFF conversion. In figure-5, we can see that instead of 8 different SBFF only one 8-bit MBFF is used. So MBFF is generally bigger in size and having multi-row height standard cell.

PnR tools have algorithms to convert SBFF into MBFF. The tool picks the equivalent MBFF available in the standard cell library and performs the conversion with respect to the user input provided for conversion. This conversion happens in the placement stage.

If we talk about the Cadence Innovus tool, we have a command

setOptMode -multiBitFlopOpt true

Which enables PnR tools for multibit flop conversion. By default, this conversion is disabled in the tool. There are many such commands in the tool which can be explored further.

Thanks.

EDA tools in ASIC Industry

2021-04-10T10:05:00.072+05:30

We have noticed that when a person enters into the ASIC industry, He/She comes across various EDA tools of different EDA companies. It's natural for experienced professionals that the name of tools/company easily gets remembered, but for the freshers, they often forget the name because it's new for them. It has also been noticed that in interviews sometimes interviewers ask the tool's name on which candidate has worked just to get the idea that which areas they have explored. Although remembering the tool's name does not define the level of intelligence of the candidate but of course, if you are not able to tell the name of the tools on which you have worked, will not give a good impression before the interviewer. It is always good to keep some information beyond your initial experience. For example, one might have worked only one STA tool say primeTime, but it's good to know what are other tools being used in Industry.

This article will let you know the major EDA tools which are being widely used in the ASIC industry for different purposes. Each tool has some specialty over others but that is not a part of this article. We are not going to compare them. Here we will learn the popular tools used in ASIC Industries for various purposes and their company name.

Kidly note that there are only a handful of EDA companies exists in the industry because If we look over the history of EDA company, we will find that there are lots of mergers and acquisitions had happened in this sector in past. Many new companies have come with their new innovative tool in past but somehow those have been acquired by the big players of this sector, and finally, the number of major EDA companies in the industry is very handful namely Cadence Design System, Synopsys, Mentor Graphics (now Siemens) and few more.

Here we will categorize the major tools and their vendor as per their utility. I request to my readers there are lots of updates going on, many new tools beings launched every year, Therefore if I missed something important keep adding those in the comments, I will keep updating the list.


Purposes	Tool	company
RTL Simulations	VCS	Synopsys
	Xcelium	Cadence Design System
	NC-Sim	Cadence Design System
	QuestaSim	Mentor Graphics (Now Siemens)
	ModelSim	Mentor Graphics (Now Siemens)
	ISE Simulator	Xilinx
	Incisive	Cadence Design System
RTL Signoff	SpyGlass	Synopsys
RTL Signoff	JasperGold	Cadence Design System
Logic Synthesis	Fusion Compiler (RTL-to-GDSII solution)	Synopsys
	Design Compiler	Synopsy
	Genus Synthesis Solution	Cadence Design System
	RTL Compiler (upgraded to Genus)	Cadence Design System
LEC	Conformal	Cadence Design System
LEC	Formality	Synopsys
Place and Route	Innovus	Cadence Design System
	IC Compiler (ICC)	Synopsys
	Encounter (upgraded to Innovus)	Cadence Design System
RC Extraction	Quantus RC Extraction	Cadence Design System
RC Extraction	StarRC	Synopsys
STA	primeTime	Synopsys
	Tempus	Cadence Design System
	Tweaker	Dorado (Now a part of Synopsys)
	Encounter Timing System (ETS)	Cadence Design System
IR Analysis	Voltus	Cadence Design System
IR Analysis	RedHawk	Ansys
Pyhsical Verification (Fill, DRC, LVS, Antenna, PERC)	Calibre	Mentor Graphics (Now Siemens)
	IC Validator	Synopsys
	Pegasus	Cadence Design System
	PVS (Physical Verification System)	Cadence Design System
Power simulation	Jules	Cadence Design System

There are some other useful tools here.


Tools	Used for	Company Name
OrCAD	PCB Design, Digital Design	Cadence Design System
Spectre	SPICE Simulation	Cadence Design System
HSPICE	SPICE Simulation	Synopsys
Virtuoso	Schematic and Layout Editor	Cadence Design System
Custom Designer	Schematic and Layout Editor	Synopsys
Abstract	Abstract generation (.lef)	Cadence Design System
Custom Waveview	Waveform viewer of simulated result	Synopsys
Sentaurus SDevice	Device Simulator	Synopsys
Sentaurus SProcess	Processes editor	Synopsys
Sentaurus Sedit	GUI of device editor	Synopsys
Svisual	visual tool for device and waveform	Synopsys
3D TCAD	3D Device simulation	Synopsys
Silvaco TCAD	TCAD Tool	Silvaco
ICCAP	Device characterization/Testing	KeySight
Liberate	Library characterization (.lib)	Cadence Design System
LT Spice	A free SPICE simulator	Linear Technology

Thank You!

If you feel, Something important is missing from this list, feel free to comment.

ECO Flow in Physical Design

2021-02-28T10:00:00.004+05:30

The tapeout is the final stage of the physical design process which definitely gives a big mental relax to the entire team involved in the project. The process of sending a clean layout file in form of gds/oasis to the foundry for fabrication after passing all the checks set by the foundry is termed as tapeout. But before the tapeout there might be many sleepless nights which physical design engineers / Signoff engineers spend and close the design. There are many signoffs like physical signoff, timing signoff and IR signoff which we need to get a closer state after which our layout is ready to send the foundry. And all these final achievements are done in the ECO (Engineering Change Order) phase. In this article, we will discuss the various aspects of the ECO cycle and how it works

ECO Phase:

ECO phase is the phase of design where we close all the signoff checks which remain open in the PnR stage. Generally in PnR we make timing, DRC and IR closable but the final closing is done in ECO phase. In ECO phase, we close the PnR implementation activities and solve all the open issue through the ECO only. But before entering the ECO stage we need to achieve good timing and DRC numbers and we must have confidence that all the open issues are closable in the ECO phase. In ECO phase we focus on closing each open issue, we generate ECO file and implement them on PnR tool incrementally.

What is ECO cycle and how it works?

In the ECO cycle, we perform various analysis one by one for every check which we need to close but not closed till PnR stage. There are specialized signoff tools that help us to analyze the issue and also suggest the changes we need to do in order to close the issue. The suggested change is captured in an eco file.

Once we generate the ECO file for the fixes, we implement that on the PnR database on which we have performed the analysis. After the implementation of ECO file, we save the updated database which we carry forward for the next ECO generation and implementation. We repeat this ECO cycle for every open issue and close one by one all issues. There are chances that we might need multiple ECO cycle to close a single issue.

ECO Cycles

So basically there are the following steps in each ECO cycle.

Analysis of an issue on the latest database
ECO generation for fixing the issue
ECO Implementation on the analyzed database
Save the database after ECO implementation for the next ECO cycle

Signoff Tools

Signoff tools are very specialized tools to perform the analysis for a particular issue thoroughly and also have the capability to generate the ECO file for the fixes. We have various types of signoff tools as per the issue like timing signoff tool, Physical Signoff tool and IR signoff tools. Some of the popular signoff tools are as bellow.

Timing Signoff:

PrimeTime or PT (of Synopsys)
Tempus (of Cadence Design Systems)
Tweaker (of Dorado, now a part of Synopsys)

Physical verification signoff tools:

Calibre (of Mentorgaphics now a part of Siemens)
IC Verification or ICV (of Synopsys)

IR Signoff Tools:

Redhawk (of Ansys)
Voltus (of Cadence Design Systems)

ECO file

ECO file contains a series of changes required in the form of PnR tool command for fixing the issue. Based on the analysis, sometimes we generate the eco file from the signoff tool itself or sometimes we create our own eco file.

For example, to fix the setup timing, we need to upsize the combinational cells or need to convert them to lower vt cells. In the case of a few hundred violating paths, these conversions of cells might be in thousands or more. So signoff tool will generate commands for each cell that need to be changed and write in a file that we call eco file. Later we source these file in PnR tool followed by refine placement and eco route.

ECO Implementation

Once we have the solution of any issue in the form of ECO file, we need to load the database which was used to generate the ECO file and source the eco file. ECO implementation is generally done in the batch mode of the tool. We need to delete the fillers before sourcing the eco file. Once the eco file is sourced, all the required changes is done. Now there might be a change in the size of cells or addition/deletion of some cells so we need to do refine placement to followed by the eco route. These two steps will take care of any overlap of cells and routing of cells. The updated database need to be saved for next stage of ECO or the final database in case of all issues are fixed.

Thanks.

Floorplan Strategies for Macro Dominating Blocks

2021-02-14T00:46:00.005+05:30

A physical design engineer's main focus is to achieve a decent Quality of Result (QoR) and optimized Power Performance and Area (PPA). The start of this journey begins with the Floorplan steps. What will you achieve at the end of PnR is depends on how good your floorplan is. In case of a macro dominating block, the importance of quality floorplan is quite more. To achieve a good floorplan in a macro dominating block, it might take several iterations and also requires good experience. A detailed analysis of data flow, hierarchy, macro to input-output pins connection, logical depth and many more factors which need to understand and analyzed thoroughly to produce a good floorplan. In this article, we will discuss some of the basic rules on which are helpful to produce a good floorplan and so good QoR.

There are some basic rules of macro placement which help to produce a good floorplan. There are many things which can be analyzed only after the first cut of floorplan result and macro placement can be improved in a few iterations in macro dominating blocks. There are some standard rules which help to achieve a good floorplan.

Grouping of macros as per hierarchy
Analysis of macro to input/output pins connection
Logical depth analysis among macros and macros to Input/Output pin
Maximizing the core area
Avoid notch formation
Channel spacing
Macro abbutment
IO pins to macro spacing
Halo over macros
Routing blockage over macros
Partial placement blockage in the macro channels and macro to io pins region

Above rules are the standard floorplan rules which generally people use as a thumb rule for better and timing and congestion results. Here it is important to understand that a where a well-planed floorplan can result in god timing and congestion result at the same time if the floorplan is not well planned could result in high congestion and high WNS/TNS/FEPs (Worst Negative Slack / Total Negative Slack / Failing End Points). So It is very important to follow the standard practice of macro placement to avoid high congestion and bad timings.

Grouping of macros as per hierarchy

In a hierarchical design, macros must be placed as per their group in the hierarchy. We can highlight the macros with different clours as per their group for better visibility of macro groups. PnR tools provide the option to see the macros and standard cells as per their hierarchy. For Innovus GUI this can be explored as Design Browser --> Modules

We can further visualize the group size and roughly estimate the required area for any particular group and place them in a better way after one-time placement is done. In a macro dominating block the macro count could be several hundred and the group could also be large. A sample picture has shown bellow.

Macro Grouping

Design Browser in Innovus

Analysis of macro to Input/Output pin connections

Generally, we place the macros near to their io pins and if the logic level is only one than we can not put macro away from the pins to avoid in2reg or reg2out timing violation. So we need to check fanin and fanout of macro and try to place them near the connected pins.

Logical depth analysis among macros and macros to Input/Output pins

Inside the groups of macro, the macro order must be as per their logical connection. Macro directly talking to each other should be placed together. Similarly, if two groups of macros have a logical connection with one register (only one level) we can not place them far away. But yes if two groups of a macro taking each other with logic level 3 or 4 or more, we can place them relatively apart from each other.

Maximize the core area

We always try to maximize the core area so that standard cells get more room for placement. If there are more rooms for placement there will be less chance of congestion and ultimately shorts. Generally, we try to place all the macro near the core boundary and try to maximize the centre area for the standard cells.

Avoid notch formation

Notch area is not utilised effectively, so it will increase the placement density of the core and will rise the congestion. We always keep in mind while macro placement that notch should not be formed while macro placement especially in the case where the macro count is high and the placement density is also high.

Notch formation is not good because it affects uniform placement density. So we try to maximize the core width and height at the centre of the core area. So we should try to macro placement in such a way that the core area width/height should be maximum in the centre.

A notch formation is shown in the figure below by the red circled area. This can be avoided in the macro placement style used in first figure.

Notch formation in macro placement

Macro channel spacing

The area between two close macros is termed macro channel spacing. In the macro channel, there will be standard cell placement and need a power connection. But if the macro spacing is too less, there is a chance that the power rails in not connected to power straps which is problematic.

Macro channel spacing

If there is area crunch we can abut two macros as shown on the right side of the image. But if we are not abutting the macro than between two macros the spacing should be minimum in which at least one VDD and VSS stripe should cross. If the channel width is too low so that no power strip crosses in this area then the rails of this region will not get power. The channel on the left side of the above figure is problematic as the standard cells seating in this region may lose PG connection.

Macro abutment

If required we can abut two macros as shown on the right side of the above figure. Only thing two remember while abutment is this pins should not be on the abutment edge. Pins should be on non-abbutment edge.

IO pins to macro spacing

If there are no pins on the core boundary we can place the macro close to the boundary but on the boundary, there are io pins, we should place macro a with some spacing to avoid congestion near the pins.

Halo over the macro

Halo is nothing but a placement blockage which are associated with macro, so if we move macro, the halo will move accordingly. To avoid the congestion on the edge of macro and also base DRC we avoid placing standard cells on the edge of the macro. A halo is put on the macro to block around the macro.

Routing blockage over the macro

Macro designing needs some more metal layers as compared to standard cells. So the metal layers already used inside the macro can not be used for routing over macro and need to block over the macro. So we need routing blockage over the macro.

Partial placement blockage in macro channel and macro to io pins area

To avoid congestion in the macro channels, We apply partial placement blockage in the macro channel so that we can control the placement density. We can also apply the partial placement blockage in the region between io pins and macro as shown in the figure below. All yellow region is showing the partial placement blockage region, we can set the placement density in these regions.

Partial placement blockage

Macro placement is the most important part of PnR as the QoR strongly depends on the macro placement. The above-mentioned rules are standard rules which generally followed in macro dominating blocks.

Thank You.

Pre-placement Activities in Physical Design

2021-02-07T00:06:00.012+05:30

In a broader sense, PnR (Place and Route) stage in physical design is basically Placement and Routing of all the instances present in the netlist in a defined core area in such a way that it should meet design rules and timing requirements. But before starting the actual automatic placement of instances by the PnR tool, there are certain activities which must be done prior to placement and those are called pre-placement activities. In this article, we will discuss some important pre-placement activities.

Pre-placement activities in PnR

Major pre-placement activities:

Pin placement
Macro placement
Halo and routing blockage
Power plan
Boundary cell/End cap cell placement
Well tap cell placement
Partial placement blockage /Density screen creation

Here we will discuss these activities in details in order as they needed to be performed.

Pin placement:

In block-level PnR, input-output pins location are generally decided by the full-chip owner and the pin def is given to block owners. But some times pin location are not fixed at the top level and meanwhile block owner need to place them as per their convenience.

PnR tools provide a pin editing utility in their tools through which large numbers of pins can be placed easily. For innovus we can open the pin editor as Edit --> Pin Editor

Basically, we need to provide the following inputs to pin editor and corresponding image is shown a typical pin placement.

Pin list

Metal layer

Pin width
Pin depth
Side/edge
Spread / Distance between two pins

Pin placement in PnR

Pins location could be either on edge of core or inside the core also. In case of pin def is available, we just need to defIn the pin.def file. In Innovus we can defIn the pin def file as bellow.

defIn <pin.def>

Once all pins are placed, we can check that. In innovus we have a command.

checkPinAssignment

The above command will give the total number of pins, the number of legal/illegal pins, the number of placed/unplaced pins.

Sometimes some i/o pins might have short with the PG structure, We can verify those shorts using following innovus command.

verify_PG_short -no_routing_blkg -no_cell_blkg

In case there are some shorts, we can fix those using following innovus command.

editPin -pin <pin name> -fixOverlap

Once all the pins are placed, we can defOut pins in a file for future use.

selectPin * ; Or selectPin [dbGet top.terms]

defOut -selected <file_name>

Macro Placement:

Macro placement is a major step of the floorplan and the QoR (quality of result) of PnR is strongly dependent on the macro placement. A good macro placement requires thorough analysis of data flow in the block.
A bad floorplan could result in congestion and bad internal timings. There are some steps which must be followed especially in a macro dominating block. A detail discussion on macro placement strategy is explained in this article (will be linked soon).

Halo and Routing blockage:

Macros having high pins count near the edges generally and if the standard cell placement is high there, it could lead congestion. To avaoid this congestion we neet to put halo around the macro. (Halo is explained here - will be linked soon). The macro design needs more metal layers than normal standard cell and its pins are available in higher metal layers than the standard cells. So we need to put routing blockage for the layers which are used inside the macro. The power rails are blocked over the macros and power is delivered to the macros directly from power stripes.

Power Plan:

A power plan is a very robust power grid structure to deliver power to all macros and standard cells available in the design without much IR drop in the power grid. power grid takes power from bumps on the top metal layer and it delivers power to the lowest maetal layer in which standard cells follow pin available.

From bumps, power goes to power stripe and power stripe delivers power to the VDD and VSS rails. Macros get power directly from power stripe as in place of macro there are no power rails drawn.

Boundary cell placement:

Each placement row must be terminated with a boundary cell at both ends. Why we need boundary cells and what are the function of boundary cells, has been discussed in this article.

Well tap cell placement:

To get tap the psub to VSS and the nwell to VDD in order to avoid the latch-up issue in the design we need to place well tap cells at regular intervals in the core area. A detail discussion on well tap cells and its placement has been discussed in this article.

Partial placement blockage:

To avoid the congestion, we need to place partial placement blockage especially in the region where the pin density is more. We generally place partial placement blockage in the channel regions and the regions where io pins are placed. If the cell placement density will become high in this region, it may cause congestion as these areas already has lots of pin connections.

Apart from these major activities, there are many other things which we need to on block specific like antenna cell placement, TCD Cells, PCLAMP cell placement. In the lower node, we need to check base DRC also after the macro placement steps.

Thanks!

Follow the blog for more updates.

Written Test Question for Physical Design Engineer: Question Set - 6

2020-12-13T01:14:00.011+05:30

Code: ALTRN0Y112020PD

Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions.

We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section.

1. Hold slack equation

2. Setup slack equation

3. When did hold analysis depends on the frequency of the clock

a) half cycle path
b) single cycle path
C) multicycle path
d) it never depends

4. While doing OCV which things are considered for setup analysis

a) max launch path delay and min capture path delay
b) min launch path delay and max capture path delay
c) max launch and capture path delay
d) min launch and capture path delay

5. How to fix EM effect

a) decreasing the space between metal layers
b) decreasing straps
c) increasing drive strength of the driver
d) increasing space between metal layers

6. Why do we add tap cells

a) to maintain well continuity
b) to prevent latch up
c) to prevent DRC's
d) all of the above

7. Why do we add metal fillers

a) to ensure etching properly
b) to ensure density issues
c) to increase the area of the chip
d)to ensure well continuity

8. If the schematic has 11 and layout is 10 nets then, what might be reason

a) opens
b) shorts
c) ERC
d) all of the above

9. Numerical problem related to finding clock frequency

10. Numerical problem related to finding slack

11. High positive skew leads to

a) setup violation
b) hold violation
c) DRcs
d) all of the above

12. In VLSI Design, CMP stands for?

13. Numerical problem to find setup slack

14. Nand and Nor gate logic diagram SOP forms

15. Setup uncertainty increases from placement to CTs

a) true
b) false
c) based on SDC
d) based on clock frequency

16. Only clearing LVS leads to the proper functioning of the chip

a) true
b) false

17. Numerical problem related to reg to reg data path delay calculation

18. A CMOS circuit consumes only a significant amount of power during

a) static state
b) when cooling
c) when warming
d) all of the above

19. Routing congestion depends on which factors

a) ratio of required layers and available layers
b) ratio of available and required
c) depending on availability of metalayers
d) none of the above

20. Question related to ground bounce, power bounce and glitch

21. Value of threshold voltage depends on

a) doping concentration
b)distance between source and drain
c) temperature
d) all of the above

22. Why we reorder scan chains during placement stage?

23. For multi-voltage blocks which power cells are used

a) isolation cells
b) retention cells
c) level shifters
d) all

24. Which configuration is more preferable for floorplan

a) double BACK + channel width spacing
b) without double back + channel width spacing
c) double back + row alignment
d) none of the above

25. Concept of fixing time violations by adjusting clock arrival times at the registers in the preCTS stage is called

a) time borrowing
b) managing skew
c) maintaining timing
d) none of the above

26. While calculating standard cell utilization what are all will be considered

a) macro + blockage + standard cell (area)
b) macro + blockage (area)
c) macro + physical cells + standard cells (area)
d) all of the above

27. RV checks Are needed for

28. Inputs for LVS

a) spice + netlist + rule deck
b) spice + rule deck + lib files
c) OASIS + netlist + lib
d) none of the above

29. Via3 will connect which of the following metal layers

a) 1 and 3
b) 2 and 3
c) 3 and 4
d) none

30. A 4-bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to

31. A pulse has a period of 15 ms. Its frequency is

32. A 8-bit successive approximation ADC has a full-scale reading of 2.55 volts and its conversion time for an analog input of 1 volt is 20 µs. The conversion time for a 2 volts input will be?

33 . How many binary numbers are required to represent a decimal number 748?

34. DRC is used to

a)to ensure chip fabrication
b)to ensure chip doesn't get heated
c)to verify parasitics on chip
d) all of these

35. Antenna diodes are used for

a) to protect the gate
b) protect VDD and VSS
c) to protect the substrate
d) all of the above

36. Buffers are added to

a) to fix timing violations
b) to fix DRC
c) to fix parasitic values
d) all

37. Metal pitch and metal spacing are the same

True
False

38. What is the effect of high drive strength buffer when added in the long net

a) delay of net decreases
b) delay of net increases
c) delay doesn't effect
d) none of the above

39. Cross talk glitch leads to

a)timing failure
b) functional failure
c) substrate failure
d)all of these

40. Programmable special cells used during ECO

a) gate array filler cells
b) filler cells

c) metal fills
d)decap cells

41. What is a physical cell?

a) cell which doesn't have any functionality
b) cell is not synthesized
c) cell which is inserted only in layout
d) all of the above

42. Power gating technique in low power is used to reduce

a)static power
b)leakage power
c)internal power
d) all of the above

43. Which of the following is not present in SDC

a) max cap
b) max trans
c) max current density
d) max fanout

44. The phenomenon associated with transistor switching when the gate voltage may appear less than the local ground potential

a) ground bounce
b) supply bounce
c) glitch
D) none

45. Leakage recovery can be achieved through

a)Hvt to Svt
b) Lvt to Hvt
C)Rvt to Lvt.
d) svt to lvt

46. Which of the following must be fixed during physical design

a) floating inputs
b) floating outputs
C) floating metals
d) both b and c

47. Which slew value will be propagated to slew _out of slew _A is 100 ps and slew_B is 80ps for hold analysis

a) 80 ps
b) 100 ps
c) 20 pls
d) 180 ps

48. A 16-bit modulo 16 ripple counter uses JK flops if propagation delay is 25 ns, the max frequency of the clock is

a) 25
b) 10
c) 2
d) 16

49. Digital signals transmitted on a single conductor must be transmitted in

a) serial
b) digital
C) slow speed
d) none

50. In a certain digital waveform, the period is four times the pulse width, the duty cycle of the waveform will be?

51. Follow pin connections to the standard s are done in encounter through

a)z- route
b)s-route
c)trail route
d) nano- route

52.set Y[ ];

set Z[a,b,c];

lappend $Y,$Z;

What is the output

a) empty list
b) [a b]
c) [a b c]
d) none

[ Note: If you find any question has typo error or wrong, comment for the correction.]

Thank you.

Synthesis and Physical Design Interview Questions: Question Set -5

2020-12-13T00:25:00.009+05:30

Code: CYPR2Y102020PD

Introduction and Experiences

Self Introduction
Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
Explain about Synthesis Inputs.
Differentiate between Logical and Physical Synthesis. (QoR impact between them)
Wire load model(WLM), Mode, Types of trees
Delay Calculation in WLM method. (Fanout based delay calculation)

Place and Route

What are Inputs for PnR and Initial Checks need to be done?
How to check for uniqueness of Netlist?
Explain stages in PnR.
Explain about useful skew and how it impacts the design.
How do we achieve a better insertion delay?
Explain about the CTS issues that you solved.
Explain Physical Cells at the transistor level.
Explain UPF, power domains, supply sets, isolation cells, retention registers.
Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
Write RTL code for the traffic light system.

SignOff

Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
How do we fix Setup and Hold time violations?
Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
Scripting related to finding empty modules, Unix commands.

Post Credit:

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!

50 Most Useful Linux Commands for VLSI Engineers

2020-11-21T13:33:00.004+05:30

Linux is an open-source operating system which is the first choice of every technocrat. For VLSI Design Engineers also most of the EDA tools are only compatible with Linux. In Linux, we interact with OS majorly with Command-Line Interface (CLI). In beginning, it might look a bit tedious as you have to remember lots of commands and we are addicted to GUI interface but later you will definitely love it.

In this article, we will learn some of basic Linux commands with examples. I would request to my reader don't just read this article but, practice these commands parallelly for best understanding and clarity. If you wish you can also make a small cheat sheet for your use. In this article, we will learn 4 categories of 50 most useful basic commands. For advance level commands we are going to publish another article later.

Category-1: File System Management

1. ls

: list files and directories

Use:

ls -l ; indicates file/directory type, permissions, owner, size, last modified

- normal, d- directory, s-socket file, l-link file

ls -a ; shows hidden files/directories

ls -t ; lists the files/directory on basis of modification time

ls -lart ; lists all the files and directories in order of last modified.

2. clear

: clear the terminal (but keep the history of commands intact)

3. man / --help

: Show a manual of command and switches written in details.

4. pwd

: Print Working Directory, The directory where you are currently.

5. cd

: Change Directory, to move to another directory.

Use:

cd .. ; back to parent directory

cd - ; back to previous directory

cd ~ ; go to home directory

cd ../../../ ; back to n steps

cd ‘abc xyz’ ; go to a directory whose name contain white space

6. mkdir

: create a directory

Use:

mkdir directory_name ; To create a new directory with the given name.

mkdir dir1 dir2 dir3 ; To create multiple directories in a single step.

7. touch

: create a file

Use:

touch file_name ; create a new file

touch file1 file2 file3 ; To create multiple files

touch –a file_name ; to change file access time

touch –m file_name ; to change the file modification time

8. gedit file_name &

: create and edit a file in GUI mode

Use:

gedit /path/to/file_name ; create and edit a file in specified location

; word count, line no. , language

9. vi file_name

: create and edit a file using command-line interface

Use:

i ; Switch to edit mode

ESc ; Exit from edit mode and Switch to command mode

/string ; find the string

Esc + :q ;exit without saving

Esc + :s ; Save only not exit

Esc + :wq ; save and exit

10. cp source destination

: copy command

Use:

cp source_file destination_dir ; To copy a file

cp source_file . ; To copy a file to current directory ("." means current dir)

cp -f source_file destination_dir ; To copy forcefully a regular file

cp -R source_file destination_dir ; To coppy recursive a directory

11. mv source destination

: move command, like cut+paste

Use:

mv f1 f2 ; rename f1 by f2

mv -rf ; recursive and force moving of a directory

12. rm

: remove file/directory, like delete

Use:

rm -rf ; remove recursive and force

! One of dangerous command as root, use carefully!!!

rm *.txt ; Will remove all the file having extension .txt in PWD

13. cat

: stands for concatenate

Use:

cat file_name ; Display a contain of a file in CLI

cat text1 > text2 ; redirection of text, overwrite

cat text1 >> text2 ; appending the text

14. which

: Path of the command

Use:

which virtuoso ; Display the path of the executable file for virtuoso

which vi ; Will show the vi command path

which python ; Will show the installation path of the python program

15. find

: searching a file/directory

Use:

find / -name "dir_name" ; to find a file/dir

find /home/user_name -name "file_name" ; to find a file/dir only in user's home area

man find ; to get more details on find command

16. history

: Get the list of executed commands

Use:

history ; the history of all command

history n ;list of last n command executed

!n ; repeat any command in the history list

export HISTTIMEFORMAT=‘%F %T ’ ; setting history command with timestamp format

unset export HISTTIMEFORMAT ; unsetting the time format

history -c ; clear all the history

~/.bash_history ; location of stored command history

17. chmod

: Change mode, change the permission of file/directory

Use:

ls -l file_name ; To see the current permissions of the file/dir

Let's understand the permissions through this ecample.

r w x 7 7 7 7 5 4

4 2 1 rwx rwx rwx rwx r-x r- -

Numeric and Symbolic permissions

chmod 777 file_name ; set all the permission for all users

chmod 754 file_name ; set rwx for owner, r-x for the group and r– for others

chmod –R 777 dir_name ; Set all permission recursively inside the dir

Category-2: Text processing commands

18. touch

: create a new file

Use:

touch file1 ; create an empty file

touch file1 file2 file3 ; create multiple files in one command

touch –am file2 ; change access and modification time

19. gedit

: A GUI based Linux text editor

Use:

gedit & ; open gedit text editor and release the CLI

gedit file1 ; create/open a file in geditor

20. head

: To read the first 10 lines of a file in CLI

Use:

head file_name ; To read the first 10 lines of a file

head –n 8 file_name ; To read first 8 lines of a file OR head -8 file

head -4 *.log ; Read first 4 lines of all log files in PWD

21. tail

: To read the last 10 lines in the command line

Use:

tail file_name ; To read last 10 lines of a file

tail –n 12 file_name ; To read last 12 lines of a file OR tail -2 file

22. sort

: To sort the list

Use:

sort file_name ; sort the content of file

sort –n file_name ; sorting a file which has numbers

sort –r file_name ; sorting the file in reverse order

sort –o outputfile inputfile ; redirection of sorted output

sort –n -k2 file_name ; sorting the file on basis of the nth column

23. unique

: An utility for filtering the repeated lines in a file

Use:

unique file_name ; will display only unique lines

unique –c file_name ; will tell no. of times a line has repeated

24. more

: Display text one screen at a time

Use:

more file_name ; display the text in command line

<space> next screen,

<b> back to previous screen,

<enter> next line

more -10 file_name ; will display 10 lines at a time

dmesg | more ; more with pipe.

25. less

: to read the text file in the command line

Use:

less file_name ; To view the content of a file

similar to more command with some advance features

less -N file_name ; Will show the content with line number

<Enter> or Down Arrow: To move next line

Up Arrow: to move up a line

<space>: To move down one page

<b>: To move up one page

26. grep

: global regular expression print

Use:

grep –i words file_name ; display the line contains searched word

dmesg | grep sda ; filtered the output and show only line having sda

dmesg | grep sda –A 5 ; Display 5 lines after the matching word sda

27. diff or vimdiff

: find the difference between two files/dir

Use:

diff file1 file2 ; To check the difference between two files

diff dir1 dir2 ; To check the difference between contains of two dir

A similar GUI tool is “meld”

vimdiff f1 f2 , gvimdiff f1 f2

28. wc

: word count of a file

Use:

wc file_name ; Newline, word and byte count in the file

wc –l file_name ; To count total new lines in the file

wc –w file_name ; T count total words only

wc –c file_name ; T count total characters only

Category-3: Process management commands

29. top or htop

: It will show the status of various resources and tasks

Use:

top ; you can see the utilization statics for resources and get PID of all running process

htop ; Similar to the top command but an improved version.

30. ps

: Known as Process Status

Use:

ps ; process for the current shell

ps -e ; Display all active process

ps -ef ; Display all active process in full format

ps –ef | grep virtuoso ; If the list is too big we can grep it to a specific command

31. kill

: To terminate a process

Use:

kill PID ; Killing a process by PID, PID is a numeric value.

kill PID1 PID2 PID3 ; Kill multiple processes together. You can specify the signal name in between Kill and PID. If no signal has been specified, by default TERM signal will be sent.

32. who

: Display the users who are currently logged in your Linux machine

Use:

who ; Without any argument who command will display user's login name, terminal, login time and host

who –q ;Display the name of all users and total no. of users logged in

33. w

: information about current logged user and what they are doing

34. users

: Display the all current users name in a single line

35. last

: it display the list of user who logged the system

Use:

last ; If no options provided the last command displays a list of all users logged in (and out) since /var/log/wtmp file was created

last user_name ;Will display the activities of a particular user only

36. free

: Used to check available physical memory and swap memory

Use:

free ; Command used to check used and free memory space in KB

free –m/g ;Space will be shown in MB or GB

free -s 5 ; Will update the status in every 5 seconds.

37. lshw

: Used to check hardware information

Use:

lshw ; Generates detail reports about various hardware of system

lshw –class memory ;Details memory in the system

lshw –class processor ; Details of processor in the system

lshw –short –class disk ; Details about the hard drives (network)

38. lscpu

: Display information about CPU architecture

Use:

lscpu ; Give the detailed information about the CPU

39. cat /proc/cpuinfo

: Similar information like lscpu

40. dmidecode

: Is a tool for dumping System Management BIOS (SMBIOS) table content in a human-readable format

Use:

dmidecode ; Gives all the hardware details

dmidecode –t system ; Gives the manufacturer, model no. etc details

dmidecode –t bios ; Gives the bios information of system (/memory)

41. uptime

: Gives the time how long system is running

Use:

uptime -p ; Gives the duration of the system running

42. reboot

: Will shutdown and restart the machine instantly

43. shutdown

: Can be used to shut down or restart the machine

Use:

shutdown –h now ; System will be shut down instantly

shutdown –h +5 “message” ; System will be shut down after 5 minute

shutdown –r +5 ; System will be restart after 5 minutes

Category-4: Bash Environment Related Commands

44. date

: Will show the current date, time and of time zone

Use:

date ; Will show day, date, current time and timezone

date –d “1990-12-31” ; Details of any specific date

timedatectl ; Will show details of local and universal time and timezone

timedatectl set-time ‘2018-12-27 07:30:10’ ; to set specific date and time

timedatectl set-time ‘Asia/Kolkata’ ; Setting time by time zone

45. cal

: Will display the calendar of current month in terminal

Use:

cal ; Will show calendar of current month in terminal

cal 08 1947 ; To display a calendar of particular month and year

cal –y 2019 ; Will show calendar of all month of a particular year

46. env

: Used to print all the current environment variables and it’s value

47. whoami

: prints the username of the current user

48. uname

: It provides kernel versions and other details

Use:

uname ; Without any option, will print kernel name only

uname -a ; Get all the information like, kernel name, version, architecture, host name, current date and time.

49. hostname

: To know the hostname

hostname ;It will display the hostname

cat /etc/hostname ;Inside the hostname file hostname is stored and we can read and edit.

vi /etc/hostname ;to change a new hostname edit the name here and reboot the machine

50. echo $BASH_VERSION

: To know the BASH version. For more variables value run env command

Your suggestions are most welcome in the comment section. If you wish to get this article and upcoming articles of this blog in your email, follow this blog.

Thank you!

Team VLSI

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Input Files Required for PnR and Signoff Stages

A. Place and Route stages:

I. Pre Placement Stage

II. Placement

III. CTS

IV. Route

V. Chip Finish

B. Metal Fill

C. RC Extraction

D. IR Analysis

Technology/Library Data

Design Data

Types of Analysis:

I. Static IR Analysis

II. Dynamic IR Analysis

III. EM Analysis

E. Static Timing Analysis

F. Physical Verification

I. DRC

II. Antenna

III. Layout Vs Schematic Check (LVS)

IV. Logic Equivelence Check (LEC)

TSMC 7nm, 16nm and 28nm Technology node comparisons

Reference

Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers

1. foreach loop

2. Nested foreach loop

3. for loop

4. Nested for loop

5. while loop

6. if-else conditions

7. if-elseif... else condition

8. Arithmetic operations

9. regexp

10. regsub

11. Reading a file

12. Writing a file

13. proc

14. proc with arguments

15. exec

16. dbGet/dbSet/dbQuery

17. list operations

18. alias

19. grep

20. sed

Thank You.

Interview questions for experienced Physical Design Engineer, Question set - 9

Flip-flop and Latch : Internal structures and Functions

Schematic of the latch and flip-flop

Working of a d- latch

Working of a d flip-flop

Tie Cells in Physical Design

Need of tie cells:

Schematic of tie cells:

Function of tie cells:

Placement of tie cells:

Integrated Clock Gating (ICG) Cell in VLSI

Why ICG Cell?

The architecture of ICG Cell:

The function of ICG Cell:

Why not only AND gate as a clock gating?

Important questions from Readers:

Physical Design Interview Questions for 3 years experience , Question set - 8

Code: EXIM4Y062021PD

Physical Design Interview Questions : Question set -7

Code: CDN5Y062021PD

Experience level: 5 YearsFor Application Engineer

Placement Steps in Physical Design

placement steps:

1. Pre Placement:

2. Initial Placement / Global Placement / Course Placement

3. Legalization

4. HFNS (Hign Fanout Net Synthesis)

5. Iteration for Congestion, Timing, DRV, and Power Optimization

6. Multibit flop conversion

7. Timing optimization iterations

Experience level: 5 Years
For Application Engineer

1) Short channel effects in MOSFET.
2) Brief about JTAG.
3) Any insight into BSDL.
4) What are the different faults that occur while fabrication?
5) What is bridging fault?
6) What is fault collapsing?
7) Draw a D-flipflop along with a timing diagram.
8) What is Stuck at faults?

17) Why DFT is in the front end?
18) VLSI design flow.
19) OR gate using 2:1 mux
20) How to do if statement synthesis?
21) How do a case statement in Verilog synthesis?
22) What is Inferred latch?
23) List out a few Power optimization methods in STA.