VLSI Made Easy

Low-Power Digital VLSI Design

2011-11-03T00:23:00.001+05:30

Low-Power Digital VLSI Design

http://www.mediafire.com/?ygb1oeqsdfymjqo

Ground Bounce

2011-11-02T23:44:00.001+05:30

Ground Bounce Definition

Ground bounce is usually seen on high density VLSI where insufficient precautions have been taken to supply a logic gate with a sufficiently low resistance connection (or sufficiently high capacitance) to ground. In this phenomenon, when the gate is turned on, enough current flows through the emitter-collector circuit that the silicon in the immediate vicinity of the emitter is pulled high, sometimes by several volts, thus raising the local ground, as perceived by the transistor, to a value significantly above true ground. Relative to this local ground, the BASE voltage can go negative, thus shutting off the transistor. As the excess local charge dissipates, the transistor turns back on, possibly causing a repeat of the phenomenon, sometimes up to a half-dozen bounces.

Ground bounce is one of the leading causes of "hung" or metastable gates in modern digital circuit design. This happens because the ground bounce puts the input of a flip flop effectively at voltage level that is neither a one or a zero at clock time, or causes untoward effects in the clock itself. A similar phenomenon may be seen on the collector side, called VCC sag, where VCC is pulled unnaturally low.

Ground Bounce defines a condition when a device's output {really a number of outputs} switches from High to Low and causes a voltage change on other pins.

"Ground Bounce is a voltage oscillation between the ground pin on a component package and the ground reference level on the component die. Essentially it is caused by a current

surge passing through the lead inductance of the package." , IDT.

The problem is cause by the large current flow through the ground pin which develops a voltage drop over the lead inductance. This voltage drop on the ground line creates two main problems; first it rises the chip off ground [0 volts] potential

which increases the devices input threshold level, and increases the voltage level on an output pin which is not switching. Because a quiet output is effected by the other switching outputs, this is also called Simultaneous Switching Noise. Ground Bounce is really an issue with loss of noise margin, and is sometimes also called Ground Bounce Noise. The faster the slew rate of the logic family, the worse the problem becomes.

Normally when the information is provided in the data sheet ground bounce is given as Volp [Voltage Output Low Pulse], or output ground bounce. Ground Bounce will be given as some maximum voltage pulse, or a peak voltage below some maximum value.

Ground Bounce Elimination

With Glue Logic, the ground pins may have been moved around to reduce the inductance. Older families of Glue Logic used the far side pins as power and ground. For example a 14-pin IC would use pin 14 for power and pin 7 as ground. Newer ICs moved the power and ground pins to the center pins of the IC [pins 3 and 12 in this example]

Using a Surface Mount Device [SMD] instead of a Through Hole device will reduce the lead inductance. Normally SMD components are smaller, their leads are closer together and have a lower lead inductance. Refer here for a list of SMD ICs.

For FPGA's with hundreds of possible output pins the situation may change, and it's more up to the designer to deal with the issue. In most cases only a small portion of an FPGAs pins are connected to a separate set or power and ground connections. Every dozen Input/Output [I/O] pins switch off their own power and ground pins. So any one group of switching pins does not effect any other group of pins.

Start a noise budget to determine if the ground bounce, rise in ground potential, effects the design [Noise Margin Calculation ]. The voltage developed over the ground lead is proportional to the rate of change in current, so the faster the logic family the worse the problem becomes: V = L * [d_i/d_t]. The more outputs switching at the same time, the larger the current value, and greater voltage bounce. Ground Bounce also occurs when the outputs switch from a 0 to a 1 but to a much smaller degree.

Series Termination

Series termination of the line is one method of reducing ground bounce [Trace Termination Methods ]. Series termination resistors slow the rate of change of the output, and so reduce the instantaneous current on the ground line. How ever placing series resistors on all the possible output lines may not be practical. Also Resistor Pull-Ups on the line cause the ground bounce voltage to increase. The pull-up resistor allows the load capacitor to charge to it's full value, so as the line switches maximum current is delivered back to the driver. When practical eliminate pull-up resistors on devices with an issue, use pull-down resistors or series resistors if possible. Reducing the loading on the driver also reduces ground bounce. Ground Bounce may also be called Ground Lift.

Design Pitfalls

Ground Bounce is easy to understand, but you have to know the condition could exist. Without realizing the condition may exist could lead to a circuit failure. A one bit error [bit bounce] could occur at any time, weeks after system testing, when enough bits change in the same direction and at the same time. Any possible random data pattern could cause a ground bounce and an uncontrolled bit change in any near-by data pin. The only real way to test for this is to send every possible bit pattern down the bus while watching all the other unused pins for a change.

There are a number of other Logic Hazards when designing digital circuits.

Simultaneous Switching Outputs

Switching Outputs vs. Propagation Delay

In addition to causing ground bounce Simultaneous Switching outputs will also cause the propagation delay of the output to increase. The greater the number of outputs switching simultaneously the larger the increase in propagation delay. Note that the graph shows Number of Outputs Switching vs delta Change in propagation delay for the outputs. Five different IC packages are shown, including SSOP, TSSOP, TVSOP, and LFBGA. The green trace representing the LFBGA shows a larger increase in delta prop delay because the LFBGA contains 96-pin instead of the 48 pins of the other packages. Of course because the increase in prop delay is unintended it could also be considered noise. Graphic credit; TI.

Design Guidelines [from Altera]

1. Add decoupling capacitors for as many VCC/GND pairs as possible.

2. Place the decoupling capacitors as close as possible to the power and ground pins of the device.

3. Limit load capacitance by buffering loads with an external device, or by reducing the number of devices that drive the bus.

4. Eliminate sockets whenever possible.

5. Reduce the number of outputs that can switch simultaneously and/or distribute them evenly throughout the device.

6. Use multi-layer PCBs that provide separate VCC and ground planes.

7. Add appropriate resistors in series to each of the switching outputs to limit the current flow into each of the outputs.

8. Use surface mount capacitors to minimize the lead inductance.

9. Use low effective series resistance (ESR) capacitors.

10. Each GND pin/via should be connected to the ground plane individually.

11. Eliminate pull-up resistors or use pull-down resistors.

... "Some bus applications use pull-up resistors to create a default high value for the bus. These resistors cause the load capacitances to charge up to the maximum voltage. Consequently, the driving device produces a higher level of ground bounce..."

editor note; there were additional design guidelines listed from this source, but they only related to programmable devices and are not listed here.

Of course implementing some of these guidelines may not be possible, but they are guidelines and not design rules. For example it my not be possible to reduce the number of outputs switching at the same time, as an 8-pin bus driver IC may have all its outputs switching half of the time. Also, using the same bus driver example which would already be the buffer, there would be no way to reduce its load capacitance.

Acronyms Defined

LFBGA; Low-profile Fine-pitch Ball Grid Array

SSOP; Shrink Small-Outline Package

TSSOP; Thin Shrink Small-Outline Package

TVSOP; Thin Very Small-Outline Package

Volp; Voltage Output Low Peak

Additional IC Package Styles.

References:
http://en.wikipedia.org/wiki/Ground_bounce

http://knol.google.com/k/ic-ground-bounce#

Floor Planning

2011-10-23T19:35:00.000+05:30

Floor Planning

The first step in the Physical Design flow is Floor Planning. Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floor Planning takes into account the macro's used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floor planning also decides the IO structure, aspect ratio of the design. A bad floor-plan will lead to waste-age of die area and routing congestion.

In many design methodologies, Area and Speed are considered to be things that should be traded off against each other. The reason this is so is probably because there are limited routing resources, and the more routing resources that are used, the slower the design will operate. Optimizing for minimum area allows the design to use fewer resources, but also allows the sections of the design to be closer together. This leads to shorter interconnect distances, less routing resources to be used, faster end-to-end signal paths, and even faster and more consistent place and route times. Done correctly , there are no negatives to Floor-planning.

As a general rule, data-path sections benefit most from Floorplanning, and random logic, state machines, and other non-structured logic can safely be left to the placer section of the place and route software.

Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and Muxes.

Latch-Up

2011-10-21T23:38:00.004+05:30

What is latch up in CMOS design and ways to prevent it?

A Problem which is inherent in the p-well and n-well processses is due to relatively large number of junctions which are formed in these structures, the consequent presence of parasitic diodes and transistors.

Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results

Latch-up may be induced by glitches on the supply rails or by incident radiation.

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS).

Preventions for Latch-Up

by adding tap wells, for example in an Inverter for NMOS add N+ tap in n-well and conncet it to Vdd, and for PMOS add P+ tap in p-substrate and connect it to Vss.
an increase in substrate doping levels with a consequent drop in the value of Rs.
reducing Rp by control of fabrication parameters and by ensuring a low contact resistance to Vss.
and the other is by introducing of guard rings.....

Latchup in Bulk CMOS

A byproduct of the Bulk CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to the base of the other transistor in a positive feedback structure. A phenomenon called latchup can occur when (1) both BJT's conduct, creating a low resistance path between Vdd and GND and (2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one. The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction of the device.

Cross section of parasitic transistors in Bulk CMOS

Equivalent Circuit

Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is formed. If the gains are such that b1 x b2 > 1, latchup may occur. Once latchup has begun, the only way to stop it is to reduce the current below a critical level, usually by removing power from the circuit.

The most likely place for latchup to occur is in pad drivers, where large voltage transients and large currents are present.

Preventing latchup

Fab/Design Approaches

Reduce the gain product b1 x b1

move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces gain beta2 > also reduces circuit density
buried n+ layer in well reduces gain of Q1

2. Reduce the well and substrate resistances, producing lower voltage drops

· higher substrate doping level reduces Rsub

· reduce Rwell by making low resistance contact to GND

· guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic resistances.

CMOS transistors with guard rings

Systems Approaches

Make sure power supplies are off before plugging a board. A "hot plug in" of an unpowered circuit board or module may cause signal pins to see surge voltages greater than 0.7 V higher than Vdd, which rises more slowly to is peak value. When the chip comes up to full power, sections of it could be latched.
Carefully protect electrostatic protection devices associated with I/O pads with guard rings. Electrostatic discharge can trigger latchup. ESD enters the circuit through an I/O pad, where it is clamped to one of the rails by the ESD protection circuit. Devices in the protection circuit can inject minority carriers in the substrate or well, potentially triggering latchup.
Radiation, including x-rays, cosmic, or alpha rays, can generate electron-hole pairs as they penetrate the chip. These carriers can contribute to well or substrate currents.
Sudden transients on the power or ground bus, which may occur if large numbers of transistors switch simultaneously, can drive the circuit into latchup. Whether this is possible should be checked through simulation.

Referrences:
http://www.ece.drexel.edu/courses/ECE-E431/latch-up/latch-up.html

Delays in ASIC Design

2011-10-04T23:30:00.002+05:30

Delays in ASIC Design

We encounter several types of delays in ASIC design. They are as follows:

· Gate delay or Intrinsic delay

· Net delay or Interconnect delay or Wire delay or Extrinsic delay or Flight time

· Transition or Slew

· Propagation delay

· Contamination delay

Wire delays or extrinsic delays are calculated using output drive strength, input capacitance and wire load models. Other delays are intrinsic properties of each and every gate.

Delays are interdependent on different electrical properties. [Nekoogar]:

Input capacitance of the logic gate is a function of output state, output loads and input slew rate.
Internal timing arcs and output slew rate is a function of switching input(s).
Capacitance of the wire is dependent on frequency.
Internal timing arcs are a function of input slew rates.
Output slew rate is a function of input slew rate on each input.
Wires exhibit RLC characteristics instead of lumped RC.

Gate Delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output. [Magma]

Gate delay =function of (input transition (slew) time, Cnet+Cpin).

Gate delay =function of (input transition (slew) time, Cload).

where Cload=Cnet+Cpin

Cnet-->Net capacitance

Cpin-->pin capacitance of the driven cell

Cell delay is also same as Gate delay.

How gate delay is calculated?

Cell or gate delay is calculated using Non-Linear Delay Models (NLDM). NLDM is highly accurate as it is derived from SPICE characterizations. The delay is a function of the input transition time (i.e. slew) of the cell, the wire capacitance and the pin capacitance of the driven cells. A slow input transition time will slow the rate at which the cell’s transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), as well as a large output load Cload (Cnet + Cpin), thereby increasing the delay of the logic gate.

There is another NLDM table in the library to calculate output transition. Output transition of a cell becomes the input transition of the next cell down the chain.

· Table models are usually two-dimensional to allow lookups based on the input slew and the output load (Cload). A sample table is given below.

timing() {

related_pin : "CKN";

timing_type : falling_edge;

timing_sense : non_unate;

cell_rise(delay_template_7x7) {

index_1 ("0.012, 0.032, 0.074, 0.154, 0.318, 0.644, 1.3");

index_2 ("0.001278, 0.0046008, 0.0112464, 0.0245376, 0.05112, 0.10454,0.212148");

values ( \

"0.225894, 0.249015, 0.285537, 0.352680, 0.484244, 0.748180, 1.279570", \

"0.231295, 0.254415, 0.290938, 0.358081, 0.489646, 0.753585, 1.284980", \

"0.243754, 0.266878, 0.303398, 0.370542, 0.502105, 0.766044, 1.297440", \

"0.267240, 0.290389, 0.326908, 0.394052, 0.525615, 0.789561, 1.320950", \

"0.307080, 0.330200, 0.366721, 0.433861, 0.565425, 0.829373, 1.360760", \

"0.380552, 0.403875, 0.440426, 0.507569, 0.639136, 0.903084, 1.434500", \

"0.497588, 0.521769, 0.558548, 0.625744, 0.757301, 1.021260, 1.552680");

}

rise_transition(delay_template_7x7) {

index_1 ("0.012, 0.032, 0.074, 0.154, 0.318, 0.644, 1.3");

index_2 ("0.001278, 0.0046008, 0.0112464, 0.0245376, 0.05112, 0.10454, 0.212148");

values ( \

"0.040574, 0.068619, 0.125391, 0.246672, 0.497688, 1.005982, 2.030120", \

"0.040570, 0.068618, 0.125390, 0.246672, 0.497688, 1.005940, 2.030240", \

"0.040565, 0.068616, 0.125389, 0.246650, 0.497770, 1.006180, 2.030120", \

"0.040532, 0.068612, 0.125387, 0.246670, 0.497710, 1.006164, 2.030100", \

"0.040578, 0.068621, 0.125392, 0.246636, 0.497688, 1.006182, 2.030040", \

"0.041763, 0.069211, 0.125662, 0.246758, 0.497726, 1.005930, 2.030000", \

"0.045813, 0.071321, 0.126671, 0.247154, 0.497846, 1.005962, 2.030180");

}

index_1 --> input transition values

index_2--> output load capacitance values

values--> delay values

Situation 1:

Input transition and output load values match with table index values

If both input transition and output load values match with table index values then corresponding delay value is directly picked up from the delay “values” table as highlighted by yellow shaded data.

Situation 2:

Output load values doesn't match with table index values

· When the actual load capacitance values does not fall directly on or at one of the load-axis index points, the delay is determined by interpolation from the closest points. Note that to carry out interpolation input transition point should match with the any one of the table index values.

· Determine the equation for the line segment connecting the two nearest points in the table.

To do this first we need to find the slope value.

Slope m = (y2-y1)/(x2-x1) where (y2-y1) is delay segment (generally in ns) on y axis and (x2-x1) is load segment (generally in pf) on x-axis.

· Solve for the delay at the load point of interest.

The linear equation is:

y = mx+c

where

y-->delay (ns)

m-->slope

x-->load capacitance (pf)

i.e. delay=slope*load point of interest (constant value is zero)

Load point of interest means load capacitance value for which delay has to be calculated.

Situation 3:

Both input transition and output load values doesn't match with table index values

· If both input transition and load capacitance values do not match exactly with the look up table index values then bilinear interpolation is used.

· Multiple linear interpolations (~3) are performed on multiple closest table data points (~4) as shown in highlighted violet color in the look up table.

Situation 4:

Output load values doesn't match with table index values and is outside the table boundary

· When the load point is outside of the boundary of the index, the delay is extrapolated to the closest known points.

· Lookup value too far out of range of the given table value could lead to inaccuracy. [Cadence]

Intrinsic delay

· Intrinsic delay is the delay internal to the gate. This is from input pin of the cell to output pin of the cell.

· It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition. It is caused by the internal capacitance associated with its transistor.

· This delay is largely dependent on the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

References

[Nekoogar] Farzad Nekoogar, “Timing Verification of Application Specific Integrated Circuits”, Prentice Hall

[Magma] Magma Blast Fusion User Guides

[Cadence] Cadence SOC Encounter User Guides

What is Static Timing Analysis (STA)

2011-10-04T23:22:00.001+05:30

What is Static Timing Analysis (STA)?

In Static Timing Analysis (STA) static delays such as gate delay and net delays are considered in each path and these delays are compared against their required maximum and minimum values. Circuit to be analyzed is broken into different timing paths constituting of gates, flip flops and their interconnections. Each timing path has to process the data within a clock period which is determined by the maximum frequency of operation. Cell delays are available in the corresponding technology libraries. Cell delay values are tabulated based on input transition and fanout load which are characterized by SPICE simulation. Net delays are calculated based on the Wire Load Models(WLM) or extracted resistance R and capacitance C. Wire Load Models(WLM) are available in the Technology File. These values are Table Look Up(TLU) values calculated based on the net fanout length.

The static timing analyzer will report the following delays (or it can do following analysis):

Setup times of all external synchronous inputs

Clock to Output delays

Pin to Pin combinational delays

Different Analysis Modes-Best, Worst, Typical, On Chip Variation (OCV)

Data to Data Checks

Case Analysis

Multiple Clocks per Register

Minimum Pulse Width Checks

Derived Clocks

Clock Gating Checks

Netlist Editing

Report_clock_timing

Clock Reconvergence Pessimism

Worst-Arrival Slew Propagation

Path-Based Analysis

Debugging Delay Calculation

and many more......!!

The wide spread use of STA can be attributed to several factors [David]:

The basic STA algorithm is linear in runtime with circuit size, allowing analysis of designs in excess of 10 million instances.

The basic STA analysis is conservative in the sense that it will over-estimate the delay of long paths in the circuit and under-estimate the delay of short paths in the circuit. This makes the analysis ”safe”, guaranteeing that the design will function at least as fast as predicted and will not suffer from hold-time violations.

The STA algorithms have become fairly mature, addressing critical timing issues such as interconnect analysis, accurate delay modeling, false or multi-cycle paths, etc.

Delay characterization for cell libraries is clearly defined, forms an effective interface between the foundry and the design team, and is readily available. In addition to this, the Static Timing Analysis (STA) does not require input vectors and has a runtime that is linear with the size of the circuit [Agarwal].

Advantages of STA:

All timing paths are considered for the timing analysis. This is not the case in simulation.

Analysis times are relatively short when compared with event and circuit simulation.

Timing can be analyzed for worst case, best case simultaneously. This type of analysis is not possible in dynamic timing analysis.

Static Timing Analysis (STA) works with timing models. STA has more pessimism and thus gives maximum delay of the design. DTA performs full timing simulation. The problem associated with DTA is the computational complexity involved in finding the input patterns (vectors) that produce maximum delay at the output and hence it is slow.

Disadvantages of STA:

All paths in the design may not run always in worst case delay. Hence the analysis is pessimistic.

Clock related all information has to be fed to the design in the form of constraints.

Inconsistency or incorrectness or under constraining of these constraints may lead to disastrous timing analysis.

STA does not check for logical correctness of the design.

STA is not suitable for asynchronous circuits.

References

[David] David Blaauw, Kaviraj Chopra, Ashish Srivastava and Lou Scheffer, “Statistical Timing Analysis: From basic principles to state-of-the-art.”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), IEEE.

[Agarwal] Agarwal, A. Blaauw, D. Zolotov, V. Sundareswaran, S. Min Zhao Gala, K. and Panda, R., “Statistically Delay computation considering spatial correlations,” Proceedings of the ASP-DAC 2003, pp.271-276, Jan 2003.

Dynamic vs Static Timing Analysis

2011-10-04T23:21:00.000+05:30

Dynamic vs Static Timing Analysis

Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing! Timing analysis can be static ordynamic. Dynamic timing analysis verifies functionality of the design by applying input vectors and checking for correct output vectors whereas Static Timing Analysis checks static delay requirements of the circuit without any input or output vectors.

Dynamic timing analysis has to be accomplished and functionality of the design must be cleared before the design is subjected to Static Timing Analysis (STA). Dynamic Timing Analysis (DTA) and Static Timing Analysis (STA) are not alternatives to each other. Quality of the Dynamic Timing Analysis (DTA) increases with the increase of input test vectors. Increased test vectors increase simulation time. Dynamic timing analysis can be used for synchronous as well as asynchronous designs. Static Timing Analysis (STA) can’t run on asynchronous deigns and hence Dynamic Timing Analysis (DTA) is the best way to analyze asynchronous designs. Dynamic Timing Analysis (DTA) is also best suitable for designs having clocks crossing multiple domains.

Example of Dynamic Timing Analysis(DTA) tool is Modelsim (from mentor Graphics), VCS (from Synopsys). DTA is also carried out on post layout netlist to verify that functionality of the design has not changed. Test vectors remain same for both.

Setup Time and Hold Time-Story of Poor Flip-Flop

2011-10-04T23:20:00.000+05:30

Setup Time and Hold Time-Story of Poor Flip-Flop !

It is always interesting to talk about setup and hold!! Don’t think that if anybody asks questions related to setup time and hold time, he or she doesn’t know about setup and hold. He or she may know everything about setup time and hold time, time being it confuses. The term “setup” and “hold” is such a word in this VLSI – ASIC design world which only creates continuous questions, hard to explain in words, at least i myself is concerned! I remember, during my MTech days my professor used to say always "whole VLSI world is depending on two pillars, setup time and hold time". It would be more realistic if i say that he used to scold us !!

The doubt why is set up and hold in flip-flop always lingers in my mind. Being a digital design engineer, i should be able to go beneath transistor and convince myself the existence of setup delay and hold delay. I know metastability state of the flip flop or charging or discharging of capacitor on a CMOS, upon which all the gates, flip flops are built. When i say "i know metastability" i may know about its standard definition as per data book. If i advent into getting answer to "why metastability", i believe i must be able to understand setup time and hold time.

Let me try to dig myself. What i know? Flip flop is combination of 2 latches, and latch is level triggered. One is positive level triggered and another in negative level triggered. If so whatever data sent to two latches will be launched or captured on different edges. Then why metastability? Why set up time? Why hold time?

So how two level triggered latches form an edge triggered flop? Let me get in to the latch. After all how it works? Say one input is given...then when can i expect the output data? Is it immediately ? or does it take some time ?

If i remember working of simple SR latch from several theory classes and text books i know that any latch output doesn’t stabilize immediately. Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1). It used to take 2 or 3 looping of data between NOR (or NAND ) gates.
So in this way it takes 2-3 data cycles....right....This must happen for both latches of flop. Hence this must take some time, may be in nano second or pico second, but it consumes some time !

Now, from the working principle of Master slave flip flop, i know that both latches won’t work together. Because i have arranged flop circuit such away that slave follows master. It means to say that when master latches the data slave sleeps, then slave follows master. Or in other words, slave releases the data which is latched earlier by the master. As i understood earlier, to latch the data, master takes 2-3 cycle. Same should be the story for slave.

Now let me extend my imagination to the next horizon.

To a flop which is exclusively designed as edge triggered with basic gates itself, may be NOR or NAND based, or may be based on CMOS full custom circuit, same of 2-3 cycle delay applies here as well. All that happens is those 2-3 cycles to stabilize data which is coming in and going out !

I should analyze practical conditions of latching the data.

Considering one internal data cycle is completed in logic gate,data is not yet stabilized within this latch. If i allow one more input to enter at the same time what will happen to that data which was under process? Naturally latch may start processing new input data or may go to unknown loop state that i think i call as metastable state ! Poor latch, it must have completely confused, whether to drop the catching of present data or should i try to catch new one? I am the boss and hence i, as a designer of latch, has instructed latch to to both, to process present data (so that it can catch it and memorize it), then look for new one. As a duty bound soldier latch will try to do both.

Same applies for data that was already latched but about to leave out of the latch. These two timing delay requirements ultimately constitute setup and hold; hold time is for time required for data to come out while setup for data to get latched. Hence, i believe, hold is always related with launch clock whereas setup is related with capture clock.

So, what I can i understand is i don’t need a reference for hold since it’s already in flop. That’s why for hold analysis, clock period is always considered as 0ns, which virtually turns out to be no clock. ( or..."hold is not dependent on clock"). This is not always true. There are exceptional cases where data is not launched at 0ns with respect to capture clock. These kind of situations should be dealt separately.

Always i must remember that flop has latch structure, this means to say, when one latch works another doesn't do any work. So if i consider register to register path, when one is launching data next one is ready to receive data. That’s all ! It continues like that way throughout the digital circuit. When first one is receiving next flop is ready to launch...and so on. To summarize, it takes one clock cycle to complete the launch or capture. That’s why we always use terms such as present data, previous data when dealing with data flow through flip flop so that i can understand the delay introduced by the flop (due to its latch architecture) which i technically termed it as setup time and hold time.

As per the definition, data should be stable at input before clock pulse ticks at the clock pin of the flip flop. I understand from the definition that data at the input should have completed the process of 2-3 cycle interchanging values at the receiving gates section of the latch to settle down to a known value. By any means, if clock is faster (or data is slower in its arrival at input), then it can tick at at the time when data might have completed its 1 or 2 cycle interchanging state. Then i am sure any one of these intermediate value can get latched, which may not the actual intended original input data.

For hold, definition is time for which data should be stable after clock edge. Once the clock edge ticks data present within latch tries to go out. I know this takes another 2-3 cycle intermediate values within latch and settle to known value at the output pin of the flip flop. Imagining that output pin is connected to input of another flip flop and there is no combinational circuit in between them, lets assume that delay is zero or very less. In this case intermediate value can immediately reflect at the input of receiving flip flop, which is functionally fatal error. Introduce a delay element which is more than 2-3 cycle delay time (i.e. hold time), then delay element provides sufficient time for the data to settle to known value.

Looking into these aspects minimum period for the clock can't be less than the addition of setup time and hold time. if clock period becomes lesser than this, i am sure flip flop will fail.

But i should be cautious in understanding that every capture flop becomes launch flop for new data to be launched. So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop. And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check. Or in other words, setup check for present data which is traveling, hold for new (future) data. Present data should reach the capture flop input before capture clock reaches there.(Setup check). New data shouldn't reach too fast to capture flop so that present data doesn't corrupt.

Well...after all these literature exercise i must agree that i don't want all jargons to implement a practical design. What i need is basic understanding of setup time, hold time and how this affects or controls the timing of a timing path. It would be nice if i can fix setup and hold violations by adjusting rest of the parameters such as skew, latency and jitter.

VLSI Design Related Private Companies in India

2011-10-04T23:10:00.002+05:30

VLSI Design Related Companies

Adaptec India Pvt. Ltd.

1st Floor, Salarpuria Infinity,
No. 5, Ward no. 63,
Banneraghatta Road,
BANGALORE -- 560 029.

Phone : 080-51339000.
  FAX : 080-51xxxxxx.
Email : ...@adaptec.com

6-3-1086, 4th Floor, Vista Grand Towers,
Raj Bhavan Road,
Somajiguda,
HYDERABAD -- 500 082.

Phone : 040-55661555.
  FAX : 040-55661560.
Email : ...@adaptec.com

Area : Disk Controllers, Peripheral Controllers.
Skill : Physical Design, VLSI Design, ASIC Design, Architectures, Circuit Design, C/Perl.

AMD India Engineering Centre Pvt. Ltd.
```
#10, "Chambers@Mantri",
Richmond Road,
BANGALORE -- 560 025.

Phone : 080-41372400.
  FAX : 080-xxxxxxxx.
Email : ...@amd.com
```
Area : Microprocessors, Flash Memory.
Skill : Physical Design, VLSI Design, Architectures, Formal Verification, Circuit Design, DFT, C/Perl, VHDL/SystemVerilog.

Agere Systems India Pvt. Ltd.

2nd Floor, Explorer Block,
International Technology Park Ltd.,
Whitefield Road,
BANGALORE -- 560 066.

Phone : 080-8411831, 8411832, 8411833, 8411834
  FAX : 080-8411839.
Email : ...@agere.com

Area : Communications (ATM, SONET, DSL), Networking, VPN, VoIP, Broadband, Optoelectronics.
Skill : VLSI Design, ASIC Design, Timing Simulation, SoC.

Alliance Semiconductor (India) Pvt. Ltd.

Consulate 1,
No.1, Richmond Road,
Bangalore -- 560 025.

Phone: 080-56604800, 56630066, 22129841/42.
  FAX: 080-22129840
Email : ...@alsc.com

Alliance Hyderabad India Office,
403-404, Aditya Trade Center,
Aditya Enclave Road,
Ameerpet,
HYDERABAD -- 500 038.

Phone: 040-23753710/11/12/13/14.
  FAX: 040-23753715.
Email : ...@alsc.com

Area : Design Services, Memory Design and Testing, PCI Controller, DSP.
Skill : VHDL/SystemVerilog, Physical Design, ASIC Design, Analog CMOS Design, Mixed Signal, Device Physics, Testing.

Ample Communications Pvt. Ltd.
```
6B, 80 Feet Road,
7th Block, Kormangala,
BANGALORE -- 560 095.

Email : ...@amplecomm.com
```
Area : Communications, Networking, Optical Routers/Switches, SONET, ATM/IP.
Skill : VHDL/SystemVerilog, ASIC Design, ATPG.

Analog Devices India Pvt. Ltd.

Bangalore Design Center,
26, Palmgrove Road,
Off Victoria Road,
BANGALORE -- 560 047.

Phone : 080-5305467.
  FAX : 080-5305198.
Email : ...@analog.com

Hyderabad Design Center,
2nd Floor, Akashganga,
Plot No. 144, Srinagar Colony,
HYDERABAD -- 500 073.

Phone : 040-23750250.
  FAX : 040-23750249.
Email : ...@analog.com

Area : DSP Processors, Wireless, Broadband, Embedded Systems.
Skill : VHDL/SystemVerilog, VLSI Design, RF Design, FPGA Design, Microprocessor/DSP Architecture.

Aplion Networks (India) Pvt. Ltd.
```
B-21, Sector 58,
NOIDA -- 201 303.

Phone : 0120-xxx.
  FAX : 0120-2585039.
Email : ...@aplion.stpn.soft.net
```
Area : Telecommunication, Networking.
Skill : VHDL/SystemVerilog, ASIC/FPGA Design, Architectures, DFT/BIST, SoC/Embedded Systems.
Arcus Technology Pvt. Ltd. Taken over by Cypress in June, 1999
```
201, Embassy Chambers,
5, Vittal Mallya Road,
BANGALORE -- 560 001.

Phone : 080-2217307.
  FAX : 080-2210336.
Email : ...@arcustech.com
```
Area : Mixed-Signal Embedded Systems, Communication, Networking, RISC/DSP, IP Blocks.
Skill : VHDL/SystemVerilog, VLSI Design, Analog Design.
Armedia Labs Pvt. Ltd. Taken over by Broadcom in June, 1999
```
Sarfarazi,
87/27, Richmond Road,
BANGALORE -- 560 025.

Phone : 080-2275615, 2994072.
  FAX : 080-2294029.
Email : ...@armediainc.com
      : ...@armedialabs.com
```
Area : Multimedia, Broadcasting, DSP, Digital TV.
Skill : VHDL/SystemVerilog, Synthesis, Architectures, Physical Design.

Artech Information Systems Pvt. Ltd.

Artech India Ltd. (Softek Ltd.)
A-2, Okhla Industrial Area, Phase-I
NEW DELHI -- 110 020.

Phone : 011-26837384, 26415312.
  FAX : 011-26837388, 26482680.
Email : ...@artechinfo.com

Area : Design Services, Communications.
Skill : VHDL/SystemVerilog, ASIC Design, Physical Design, Analog Design, PLL.

Artisan Components Pvt. Ltd. Merged with ARM ?
```
BANGALORE -- 560 0xx.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@artisan.com
```
Area : IP Blocks, Cell Libraries, I/O Pad Cells, Memory Generators.
Skill : VLSI Design, Physical Design, Circuit Simulation, Logic Design.

ATI Technologies India Pvt. Ltd.

Plot no. 90,
Road no. 2,
Banjara Hills,
HYDERABAD -- 500 034.

Phone : 040-23542674.
  FAX : 040-2xxxxxxx.
Email : ...@ati.com

Area : Graphics/Video/Multimedia Chips.
Skill : ASIC Design, VLSI Design, Physical Design.

Atrenta India Pvt. Ltd.

61, 3rd Floor,
Sector 9,
NOIDA -- 201 301.

Phone : 0120-2536182, 2536183.
  FAX : 0120-xxx.
Email : ...@atrenta.com

Area : Design Services.
Skill : VHDL/SystemVerilog, Physical Design.

AustriaMicroSystems India Pvt. Ltd.

#01-07, Cyber Pearl, Block 2,
Hitec City,
Madhapur,
HYDERABAD -- 500 081.

Phone : 040-2xxxxxxx.
  FAX : 040-2xxxxxxx.
Email : ...@ati.com

Area : Graphics/Video/Multimedia Chips.
Skill : ASIC Design, VLSI Design, Physical Design.

Barco Electronic Systems Pvt. Ltd.
```
A-38, B&C, Sector 64,
NOIDA -- 201 301.

Phone : 0120-4020000.
  FAX : 0120-4020100.
Email : ...@barco.com
```
Area : Visual/Display Solutions, Inspection Systems.
Skill : VHDL/SystemVerilog, FPGA Design, Image Processing Architectures, PCB Design, High-speed Circuits Design.
Bisquare Technologies Pvt. Ltd.
```
J-11, Lajpat Nagar III,
NEW DELHI -- 110 024.

Phone : 011-26910083, 26910084, 26910085.
  FAX : 011-26840912.
Email : ...@bisquare.com
```
Area : Design Services, Embedded Systems, Appliances, Security.
Skill : VHDL/SystemVerilog, ASIC Design, Architectures, DFT, SoC Design.
Bit Mapper Integration Technologies Pvt. Ltd.
```
A-1, Success Chambers,
CTS No. 1232,
Apte Road
PUNE -- 411 044.

Phone : 020-25539942, 25539943.
  FAX : 020-25464046.
Email : bitmapper@vsnl.com
```
Area : Design Services, PCI Interface Cards, Other Interface Cards, Training.
Skill : VHDL/SystemVerilog, ASIC Design.

Broadcom India Pvt. Ltd.

Campus 3A, 5th Floor,
RMZ Eco Space,
Bellandur Village,
Varthur Hobli,
BANGALORE -- 560 037.

Phone : 080-51484444.
  FAX : 080-51539999.
Email : ...@broadcom.com

Area : Communications, VoIP, Multimedia, Consumer.
Skill : VLSI Design, Architectures, VHDL/SystemVerilog, Analog Design, DFT, Physical Design.

Celox Networks (India) Pvt. Ltd.
```
BANGALORE -- 500 0xx.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@celoxcom.com
```
Area : Networking, Broadband Internet.
Skill : SystemVerilog/VHDL, ASIC Design, Codesign, Testing.

Centillium India Pvt. Ltd. Also see vEngines

C-60, Shivalik,
Malaviya Nagar,
NEW DELHI -- 110 017.

Phone : 011-26682084.
  FAX : 011-26682085.
Email : ...@centillium.com

Ground Floor, Haleema Centre,
5th A Block, 60 Feet Road,
Kormangala,
BANGALORE -- 560 095.

Phone : 080-5523575, 5523576, 5523577.
  FAX : 080-5523514.
Email : ...@centillium.com

Area : Voice-Data Networks (VoIP, ATM, xDSL, Cable, ...), Home Networks, Embedded Systems.
Skill : SystemVerilog, ASIC Design, RT Synthesis, Architecture, DFT, SoC, DSP Algorithms.

CG-CoreEl Programmable Solutions Pvt. Ltd.

21, 7th Main, I Block,
Kormangala,
BANGALORE -- 560 034.

Phone : 080-5528940, 5529841, 5529842.
  FAX : 080-5528955.
Email : ...@cg-coreel.com

Area : Network Protocols, ATM, Switching, DSP.
Skill : FPGA Design, VHDL/SystemVerilog.

Cherrysoft Bharat Pvt. Ltd.

SPIC Annexe,
97, Mount Road, Guindy,
CHENNAI -- 600 032.

Phone : 044-22353172.
  FAX : 044-22351917.
Email : cherry@giasmd01.vsnl.net.in

Area : A/D Converters, Mixed Digital Design.
Skill : Analog CMOS Design, VLSI Design.

Chip Engines (India) Pvt. Ltd.

1-8-271 to 273, 301 Asoka Bhoopal Chambers,
S. P. Road,
SECUNDERABAD -- 500 003.

Phone : 040-27721642, 27720885.
  FAX : 040-27720884.
Email : ...@chipengines.com

Area : Design Services, WAN, ATM, SONET/SDH, Gigabit Ethernet.
Skill : VHDL/SystemVerilog, ASIC Design, Physical Design, RTL Synthesis.

Chip Logic (India) Pvt. Ltd. Taken over by Analog Devices
```
Plot 144, II Floor,
Akashganga Chambers,
Srinagar Colony,
HYDERABAD -- 500 073.

Phone : 040-23308432.
  FAX : 040-xxxxxxx.
Email : ...@chiplogic.com
```
Area : Embedded Systems, EDA Tools Flow.
Skill : VHDL/SystemVerilog, VLSI Design, Mixed-Signal Design.
Chipsculpt
```
India Design Centre,
MUMBAI -- 400 0xx.

Phone : 022-xxxxxxx.
  FAX : 022-xxxxxxx.
Email : ...@chipsculpt.com
```
Area : Design Services, IP Blocks.
Skill : SystemVerilog/VHDL, ASIC/FPGA Design, Physical Design, VLSI Design, Formal Verification.
Ciena India Pvt. Ltd.
```
India Research Centre,
Plot Number 14, Sector 32,
GURGAON -- 122 002.

Phone : 0124-xxxxxxx.
  FAX : 0124-xxxxxxx.
Email : ...@ciena.com
```
Area : Telecommunications, Networking, Switching/Data Networks, Optical Switching.
Skill : SystemVerilog/VHDL, ASIC Design, FPGA Design, RF Design.
Cirrus Logic Software (India) Pvt. Ltd.
```
106-A, Muttha Chambers,
Senapati Bapat Road,
PUNE -- 411 016.

Phone : 020-25671092.
  FAX : 020-25671090.
Email : ...@cirrus.com.
```
Area : Mass Storage, Consumer Audio, Multi-media, Data Conversion.
Skill : VHDL/SystemVerilog, Analog/Mixed Signal, Architectures, Physical Design.

Cisco Systems (India) Pvt. Ltd.

Bangalore R-D Centre,
5th Floor, Sona Towers,
71, Miller's Road,
BANGALORE -- 500 052.

Phone : 080-xxxxxxx.
  FAX : 080-2289955, 2289360.
Email : ...@cisco.com

Area : Networking, Telephony.
Skill : SystemVerilog/VHDL, ASIC Design, DFT/BIST, Verification, Physical Design.

CMOS Chips India Pvt. Ltd.
```
Electronics City,
Hosur Road,
BANGALORE -- 561 229.

Phone : 080-5536991.
  FAX : 080-5536992.
Email : ...@cmoschips.com
        ...@cmosindia.co.in
        ...@cmossystems.com
```
Area : Design Services, Embedded Systems, SoC, Networking Products, Wireless, Telecommunications.
Skill : VHDL/SystemVerilog, ASIC Design, Logic Design, Physical Design, Processor Architectures, Analog Blocks, RF Design, Mixed Signal.

Concept-to-Chip Solutions Pvt. Ltd. (C2C) Defunct ?

1174, 1st Cross, 12th B Main,
HAL II Stage,
Indira Nagar,
BANGALORE -- 560 008.

Phone : 080-5202652, 5202661.
  FAX : 080-xxxxxxx.
Email : c2csol@vsnl.in

Area : Design Services, IP Cores.
Skill : ASIC/FPGA Design, VHDL/SystemVerilog, VLSI Design, Analog Design.

Conexant Systems India Pvt. Ltd.

D-3, Mariner Block,
Vanenburg IT Park,
Madhapur,
HYDERABAD -- 500 081.

Phone : 040-55723000.
  FAX : 040-55723099.

Conexant Systems (PB) Pvt. Ltd. (aka Paxonet)
3rd Floor, B-Block,
Maruthi Infotech Centre,
S. No. 11/1 to 12/1, Amar Jyoti Layout,
Koramangala-Indira Nagar Inner Ring Road,
BANGALORE -- 560 071.

Phone : 080-51858400; 25216932; 25216933.
  FAX : 080-25272669.

Conexant Systems Noida Pvt. Ltd.
FC 2-4, Sector 16A,
NOIDA -- 201 301.

Phone : 0120-2512833; 2512836.
  FAX : 0120-2516047.

Conexant Systems (PB) Pvt. Ltd. (aka Paxonet)
Devi House, 4th Floor,
1576 Shivaji Nagar,
PUNE -- 411 005.

Phone : 020-25510474.
  FAX : 020-25510500.

Email : ...@conexant.com

Area : Networking, SONET/SDH, IP Cores, Wireless, Set-top Box.
Skill : VHDL/SystemVerilog, FPGA/ASIC Design, Analog Design. VLSI Design.

ControlNet (India) Pvt. Ltd.
```
Unit 1, Plot L-44,
Software Technology Park,
Verna Industrial Estate,
Verna, Salcette,
GOA -- 403 722.

Phone : 0832-2783615.
  FAX : 0832-2783614.
Email : ...@controlnet.co.in
```
Area : Design Services, Network Protocols, Ethernet, Switching, Chip Cores.
Skill : ASIC/FPGA Design, VHDL/SystemVerilog, VLSI Design, Mixed-signal, Testing.

Cosmic Circuits Pvt. Ltd.

#303, A-Block, AECS Layout,
60 Ft. Road,
Kundalahalli,
BANGALORE -- 560 037.

Phone : 080-40526200.
  FAX : 080-40526255.
Email : ...@cosmiccircuits.com

Area : IP Blocks, Design Services.
Skill : Analog Design, Mixed-signal, RF design, VLSI Design.

Cypress Semiconductor Technology India Pvt. Ltd.
```
Sharada Towers, 1st Floor,
56, Nandidurg Road,
Benson Town,
BANGALORE -- 560 046.

Phone : 080-3530132, 3530134.
  FAX : 080-3438679.
Email : ...@cypress.com

Also at
HYDERABAD -- 

Phone : 040-xxxxxxx.
  FAX : 040-xxxxxxx.
Email : ...@cypress.com
```
Area : Graphics, Video, Communications, Networking, Consumer Products, Memory, Microcontrollers, SONET, In-house CAD Tools.
Skill : VHDL/SystemVerilog, VLSI Design, Analog Design, Physical Design, Mixed-Signal Design, SPICE, Tools for Layout and Verification.
D'GIPRO Systems Pvt. Ltd.
```
510, 7th Cross, 10th Main,
HAL 3rd Stage,
BANGALORE -- 560 075.

Phone : 080-5282107.
  FAX : 080-5299228.
Email : dgipro01@giasbg01.vsnl.net.in
```
Area : Design Services, Space and Aviation Control, Technology Libraries.
Skill : VHDL/SystemVerilog, VLSI Design, Physical Design.

DCM Technologies Ltd. Moved to Embedded Systems ?

ASIC Design Group,
8th Floor, Vikrant Tower,
4, Rajendra Place,
NEW DELHI -- 110 008.

Phone : 011-25769248, 25719967.
  FAX : 011-25755731.
Email : ...@dcmtech.com
      : ...@dcmtech.co.in

Area : Design Services, Wireless Protocols, Automotive Electronics, PCI Interface.
Skill : VHDL/SystemVerilog, ASIC Design, Embedded Design.

DSipher Design Solutions

206, Kristal Olivine,
Outer Ring Road,
Bellandur
BANGALORE -- 560 103.

Phone : 080-41643253.
  FAX : 080-4xxxxxxx.
Email : ...@dsipherdesign.com

Area : Design Services.
Skill : VHDL/SystemVerilog, ASIC Design, VLSI Design, Embedded Design.

Duet Technologies Pvt. Ltd. Now Part of Freescale/Motorola

SDF # B2, NEPZ,
NOIDA -- 201 305.

Phone : 0120-2567001, 2567002, 2567003, 2567004.
  FAX : 0120-2562970.
Email : ...@duettech.com

Area : Cell Library, CAD Tools.
Skill : VHDL/SystemVerilog, VLSI Design.

Dusk Valley Technologies Ltd.

227, Okhla Industrial Estate Phase III,
NEW DELHI -- 110 020.

Phone : 011-26319980, 26319981, 26319982, 26319983.
  FAX : 011-26822774.
Email : ...@duskvalley.com
      : duskvalley@vsnl.net

Area : Design Services, ATM, Networking, Peripheral Buses.
Skill : VHDL/SystemVerilog, ASIC Design, VLSI Design.

ESB India Pvt. Ltd.

G-17A, III Floor,
Kalkaji,
NEW DELHI -- 110 019.

Phone : 011-26425638.
  FAX : 011-26425638.
Email : esbindia@vsnl.net
      : tech@esbindia.com

Area : Design Services, Medical Electronics, Defence Projects.
Skill : VHDL/SystemVerilog, ASIC Design, FPGA Design.

Embedded Wireless Labs Ltd.
```
No. 1, First Floor,
Cunnigham Road
BANGALORE -- 500 052.

Phone : 080-2281001, 2380269.
  FAX : 080-2282600.
Email : asic@embeddedwireless.com
      : digital@embeddedwireless.com
```
Area : Telecommunications, Digital Communications, Wireless Communications, Internet.
Skill : Microcontrollers, Architecture, DSP, RF Design, VHDL/SystemVerilog, ASIC/FPGA Design, PLL Design, Mixed Signal.

Emerging Memory Technologies (India) Pvt. Ltd.

1118/19, B-Wing,
Mittal Towers,
M. G. Road
BANGALORE -- 500 001.

Phone : 080-30570639.
  FAX : 080-30521232.
Email : ...@emergingmemory.com

Area : Memory.
Skill : Memory Design, Analog Design, Mixed Signal.

Freescale India Pvt. Ltd.
```
Freescale India Design Centre
Motorola Excellence Centre (VLSI Design),
415/2, Sector 14,
Mehrauli-Gurgaon Road,
GURGAON -- 122 001.

Phone : 0124-2303212, 2307212.
  FAX : 0124-2306688.
Email : ...@india.freescale.com
      : ...@freescale.com
```
Area : Microcontrollers, Wireless Communication, Networking, Imaging, Technology Library, Automotive Electronics, Space Electronics, DSP.
Skill : VHDL/SystemVerilog, Architectures, Memory/IO Design, Physical Design, Library Design, Perl/C, DFT, Codesign, RF.
Freescale India Pvt. Ltd.
```
Freescale India Design Centre
Noida Development Centre,
E-21/22, SDF, NEPZ,
NOIDA -- 201 305.

Phone : 0120-2568670, 2568671, 2568672, 2568673.
  FAX : 0120-2568320.
Email : ...@india.freescale.com
      : ...@freescale.com
```
Area : Wireless Communication, Imaging, DSP, Networking, Automotive Electronics, Space Electronics, Embedded Products.
Skill : VHDL/SystemVerilog, Architectures, ASIC Design, Codesign, Analog Design, Physical Design, DFT, Perl/C, RF.

Future Techno Designs Pvt. Ltd.

121/4, 20th C Main,
Opp. Indoor Stadium,
8th Cross, 8th Block,
Koramangala,
BANGALORE -- 560 095.

Phone : 080-5711582.
  FAX : 080-xxxxxxx.
Email : ...@ftdpl.com.sg

Area : Design Services, Cell Library, Design Porting.
Skill : VLSI Design, Physical Design.

GE India Design Centre

Lake Shore Towers,
Raj Bhavan Road,
Somajiguda,
HYDERABAD -- 500 082.

Phone : 040-xxxxxxx.
  FAX : 040-23300501.
Email : ...@geind.ge.com

c/o Satyam GE Services Ltd.,
Edison Towers,
Near HUDA Office,
SP Road, Begumpet,
HYDERABAD -- 500 003.

Phone : 040-27881780.
  FAX : 040-27905004.
Email : ...@geind.ge.com

Area : Controllers, Consumer Electronics, Transport.
Skill : VHDL, ASIC Design, VLSI Design, Physical Design, Mixed Analog-Digital Design, Analog, Architectures.

GDA Technologies Ltd. Fully-owned Subsidiary of L&T Infotech Ltd.

L&T Infotech Park,
Mount Poonamalle Road,
Manapakkam,
CHENNAI -â€“ 600 089.

Phone : 044-22537900
  FAX : 044-2xxxxxxx.
Email : ...@gdatech.co.in

Plot No 25-30,
EPIP 1st Phase,
KIADB Industrial Area,
Whitefield, 
BANGALORE -- 560 066

Email : ...@gdatech.co.in

Door No 104, 1st Floor,
North Wing,
Tejomaya, L&T Techpark Ltd
Infopark, Kusumagiri PO,
Kakkanad,
KOCHI -- 682 030.

Phone : 0484-2415041.
  FAX : 0484-2xxxxxx.
Email : ...@gdatech.co.in

Area : Design Services, IP Development, Coomunications, Video, Appliances.
Skill : VHDL/SystemVerilogVLSI Design, Physical Design, ASIC Design, DFT.

Genesis Microchip India Pvt. Ltd. Now acquired by STMicroelectronics -- This was earlier Sage India's New Avatar
```
Sage Design Systems (India) Pvt. Ltd.
(A subsidiary of Genesis Microchip Inc.)
George Thangiah Complex (E), 2nd Floor,
80 Feet Road, Jeevan Bhima Nagar,
BANGALORE -- 560 075.

Phone : 080-25263878.
  FAX : 080-25296245.
Email : ...@gnss.com
```
Area : TV/Monitor/Display Technology, IP Development.
Skill : VLSI Design, Physical Design, ASIC Design, Image Processing, Graphics, Analog Design.

GPS Usha Pvt. Ltd. Defunct ? GEC-Plessey got acquired by Mitel and then Zarlink

27, Lavelle Road,
BANGALORE -- 560 001.

416, 4th Main, 8th Cross,
2nd Block, RT Nagar,
BANGALORE -- 560 032.

Phone : 080-2271397.
  FAX : 080-2210125, 3436619.
Email : ...@gpsemi.com

Area : Cell Library, Design Porting.
Skill : VLSI Design, Physical Design.

HCL Technologies Ltd.

Advance Technologies Centre,
244, Udyog Vihar,
Phase I,
GURGAON -- 122 016.

Phone : 0124-xxxxxx.
  FAX : 0124-xxxxxx.
Email : ...@hcltech.com
      : ...@ggn.hcltech.com
  Web : www.hcltechnologies.com

Embedded Systems Group,
A-11, Sector 16,
NOIDA -- 201 301.

Phone : 0120-2510794, 2510736.
  FAX : 0120-2510713, 2510226.
Email : ...@hcltech.com
      : ...@noida.hcltech.com

Global Resourcing Group,
1785, I Block, 26th Street,
Thiruvalluvar, Kudiyiruppu,
Anna Nagar West,
CHENNAI -- 600 040.

Phone : 044-xxxxxxx.
  FAX : 044-xxxxxxx.
Email : ...@hcltech.com

Area : Design Services, Soft Cores, Embedded Systems, Telecommunications, Networking, Wireless, DSP, Multimedia.
Skill : VLSI Design, FPGA/ASIC Design, VHDL/SystemVerilog, Physical Design, Architectures, Formal Verification, Analog Design, Mixed-Signal Design, RTL Synthesis.

HelloSoft India Pvt. Ltd.

India Development Center
8-2-703, Road No.12,
Banjara Hills,
HYDERABAD -- 500 034.

Phone : 040-23327062, 23327063.
  FAX : 040-23314221.
Email : ...@hellosoft.com

Area : VoIP, Wireless and Mobile Communications.
Skill : SystemVerilog/VHDL, VLSI Design, ASIC Design, FPGA Design, DSP Architectures.

Himachal Futuristic Communications Ltd.

R&D Centre,
8, Commercial Complex,
Masjid Moth,
Greater Kailash - II,
NEW DELHI -- 110 048.

Phone : 011-xxxxxxx.
  FAX : 011-xxxxxxx.
Email : ...@hfcl.com

Area : Telecom, Wireless, Optical, Wideband, Switching.
Skill : VHDL, FPGA Design, DSP, uP/uC, RF Design.

Honeywell Technology Solutions Lab.
```
151/1, Doraisanipalya,
Bannerghatta Road,
BANGALORE -- 560 076.

Phone : 080-6588360.
  FAX : 080-6584750.
Email : ...@honeywell.com
```
Area : Sensors, Control, Instrumentation.
Skill : VLSI Design, Mixed-Signal Design, MEMS, Circuit Design.

IBM Global Services India Pvt. Ltd.

Hardware Design Center -- VLSI,
6th Floor, Golden Enclave,
Airport Road,
BANGALORE -- 560 017.

Phone : 080-5094637, 5262355, 5267117, 5269299.
  FAX : 080-5277053, 5268553, 5274517.
Email : ...@in.ibm.com

Area : SoC, Networking, Processors, Peripheral Controllers, Graphics Controller.
Skill : VHDL/SystemVerilog, ASIC Design, VLSI Design, Physical Design.

Ikanos Communication India Pvt. Ltd.

3rd Floor, Corporate Miller,
332/1, Thimmiah Road,
Vasanthnagar,
BANGALORE -- 560 052.

Phone : 080-41096300.
  FAX : 080-41327589.
Email : ...@ikanos.com

Also at
HYDERABAD -- 5xx xxx.

Phone : 040-xxxxxxxx.
  FAX : 040-xxxxxxxx.
Email : ...@ikanos.com

Area : Networking, Controller.
Skill : VHDL/SystemVerilog, ASIC Design, VLSI Design, Physical Design.

IKOS India Pvt. Ltd.
```
A-4, Sector 10,
NOIDA -- 201 301.

Phone : 0120-2538988, 2522576.
  FAX : 0120-2538204, 2538259.
Email : ...@ikos.com
```
Area : Design Verification, HW/SW Simulation Accelerators.
Skill : VHDL/SystemVerilog, VLSI Design, FPGA Design, Codesign.
Infineon Technologies India Pvt. Ltd. Earlier Siemens Semiconductors Group; Some parts sold to Intel in August, 2010
```
Bangalore R&D Center,
10th Floor, Discoverer Building,
International Tech Park,
Whitefield Road,
BANGALORE -- 560 066.

Phone : 080-8410017, 8410018.
  FAX : 080-8410012.
Email : ...@infineon.com
```
Area : Wired/Wireless Communications, Networking, Automotive, Industrial, Speech and Signal Processing, Memory, Security Systems, I/O Library Cells, Embedded Systems, Mobile, Smart Cards.
Skill : VHDL/SystemVerilog, VLSI Design, Analog Design, Mixed Signal, DSP Architectures, RF Design, Testing, Physical Design, Formal Verification, ASIC Design, Memory Design, DFT/BIST, IO Design.
Infinera India Pvt. Ltd.
```
Level 4, Prestige Solitaire,
Brunton Road,
BANGALORE -- 560 025.

Phone : 080-66731300.
  FAX : 080-66731401.
Email : ...@infinera.com
```
Area : Optical Networking, Communications, SONET, GigaEthernet.
Skill : SystemVerilog, Scripting, ASIC Design, FPGA Design, Micro-architectures, Synthesis, DFT, PLL Design.
Infosys Technologies Ltd.
```
Electronics City,
Hosur Road,
BANGALORE -- 561 299.

Phone : 080-8520902.
  FAX : 080-8520851.
Email : ...@infy.com
```
Area : Embedded Systems, Automotive Electronics, Industrial Automation, Internet Appliances.
Skill : uP/uC/DSP Architectures, ASIC Design, VLSI Design, SoC.
inSilica Semiconductors India Pvt. Ltd.
```
India Design Centre,
Frontline Grandeur,
14, Walton Road,
BANGALORE -- 560 001.

Phone : 080-41186600.
  FAX : 080-xxxxxxxx.
Email : ...@insilica.com
```
Area : Design Services, Graphics, IP Development, Consumer.
Skill : VLSI Design, SoC, Analog Design, RF Design, Memory Design, Mixed-signal Design.
Intel Technologies India Pvt. Ltd.
```
136, Airport Road,
BANGALORE -- 560 017.

Intel India Development Centre,
Salarpuria Chambers,
28, Cubbon Road,
BANGALORE -- 560 001.

Phone : 080-22869330.
  FAX : 080-22867431.
Email : ...@intel.com
```
Area : Microprocessors, Network Processors, DSP Processors, Switching, Embedded Processors.
Skill : VHDL/SystemVerilog, VLSI Design, ASIC Design, Architecture, Testing/DFT/BIST.
Interra Software (India) Pvt. Ltd.
```
SDF E-14, NEPZ,
NOIDA -- 201 305.

Phone : 0120-2568037.
  FAX : 0120-2568110.
Email : ...@interra.com
```
Area : Design Services, Digital Video, EDA Blocks.
Skill : VHDL/SystemVerilog, VLSI Design.
Invensys India Pvt. Ltd.
```
E-3/7, Vasant Vihar,
NEW DELHI -- 110 057.

Phone : 011-xxxxxxx.
  FAX : 011-xxxxxxx.
Email : ...@invensys.com
```
Area : Design Services, Intelligent Automation, Embedded Systems.
Skill : VHDL/SystemVerilog, ASIC Design, SoC, EDA Tools, High-Speed Digital Design.

Ishoni Networks Ltd.

5th Floor, Stock Exchange Towers,
51, J. C. Road,
BANGALORE -- 560 007.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@ishoni.com

Area : Design Services, DSP, VoIP, ATM.
Skill : VHDL/SystemVerilog, VLSI Design, Testing.

Juniper Networks India Pvt. Ltd.

Plot# 66/1/3, 3rd Floor,
Bagmane Tech Park,
CV Raman Nagar, 
BANGALORE -- 560 093.

Phone : 080-3053 8700.
  FAX : 080-3053 8824.
Email : ...@juniper.net

Ankeena Networks Private Limited
Shree Park, 2nd and 3rd Floor,
578, Anna Salai,
CHENNAI -- 600 006.

Phone: 044-2432 9190.

Area : Routers, Networking.
Skill : VHDL/SystemVerilog, VLSI Architecture, ASIC Design, VLSI Design, Physical Design.

Lara Networks India Pvt. Ltd.

104, DBS Centre,
26, Cunnigham Road,
BANGALORE -- 560 052.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@laranetworks.com

Area : Network Processors, Switching and Routing Equipment.
Skill : SystemVerilog, ASIC Design, Perl.

Lattice Semiconductor (India)
```
703-704, Prestige Meridien-II,
No. 30, M. G. Road,
BANGALORE -- 560 001.

Phone : 080-40952233.
  Fax : 080-41631889.
Email : ...@latticesemi.com
```
Area : FPGAs/CPLDs, Applications.
Skill : SystemVerilog/VHDL, ASIC Design, VLSI Design, Mixed Signal Design, Micro-controllers, Architecture.
Masamb Electronics Systems Pvt. Ltd.
```
A-8, Sector-41,
NOIDA -- 201 303.

Phone : 0120-4340020.
  FAX : 0120-4255827.
Email : ...@masamb.com
```
Area : DSP, Reconfigurable IP Cores, Verification.
Skill : VLSI Design, DSP Processor Design, FPGA Design, Architectures, Physical Design, Library Design, Functional Verification.
Maxim India Integrated Circuit Design Pvt. Ltd.
```
Royal Arcade, 2nd Floor,
6, Koramangla Industrial Area,
BANGALORE -- 560 095.

Phone : 080-51104584, 51104585.
  FAX : 080-51104657.
Email : indian_cntr@design.mxim.com
```
Area : Microcontrollers, Data Converters, Telecommunications.
Skill : VLSI Design, Analog Design, Physical Design, Architectures, Mixed-Signal Design, RF Design.

Microchip Technology Designs (India) Pvt. Ltd.

1st Floor, Wing A (A3/A4),
Divyasree Chambers,
No. 11, O'Shaugnessey Road,
BANGALORE -- 560 025.

Phone : 080-22290061.
  FAX : 080-22290062.
Email : ...@microchip.com

Area : Embedded Systems, Microcontrollers, Microperipherals.
Skill : VLSI Design, ASIC Design.

Mirafra Technology Pvt. Ltd.

#23, Industrial Layout,
5th Block,
Koramangala,
BANGALORE -- 560 095.

Phone : 080-41216687.
  FAX : 080-41216541.
Email : ...@mirafra.com

Area : Design Services,
Skill : SystemVerilog, ASIC Design, FPGA Design, VLSI Design.

MosChip Semiconductor Technology Ltd.

#43, Whisper Valley,
H. S. Darga,
HYDERABAD -- 500 008.

Phone : 040-xxxxxxx.
  FAX : 040-xxxxxxx.
Email : ...@moschip.com

SDF # G-9B, 2nd Floor, NEPZ,
NOIDA -- 201 305.

Phone : 0120-xxxxxxx.
  FAX : 0120-xxxxxxx.
Email : ...@moschip.com

Area : Design Services, ATM, SONET/SDH, Gigabit Ethernet.
Skill : VHDL/SystemVerilog, ASIC Design, Physical Design.

Motorola India Electronics Ltd.

The Senate,
33A, Ulsoor Road,
BANGALORE -- 560 042.

Phone : 080-5598615, 5298511.
  FAX : 080-5594687, 5298514, 5065066.
Email : ...@bangalore.mot.com
      : ...@miel.mot.com

Area : VLSI CAD, Library Automation, Communication/Networking Software.
Skill : Physical Design, Backend Tools, CAD Tools, C/C++.

NatSem India Design Centre
```
7/6, Brunton Road,
Off M. G. Road,
BANGALORE -- 560 025.

Phone : 080-5587918, 5587919, 5587920.
  FAX : 080-5587921.
Email : ...@malkauns.nsc.com
```
Area : Information Appliances, PDAs, Embedded Systems, Wireless, Networking, Standard Products, Technology Library.
Skill : Architectures, Analog VLSI, Physical Design, RF Design, VHDL/SystemVerilog.

Ncore Technology Pvt. Ltd.

4F Leo Complex,
44-45, Residency (Cross) Road,
BANGALORE -- 560 025.

Phone : 080-5580405, 5588257.
  FAX : 080-5587690.
Email : ...@ncoretech.com

Area : Design Services, DSP Products (Modem, Speech Encoding, Telephony).
Skill : Physical Design, VHDL Synthesis, Software.

NEC India Pvt. Ltd.

405, Paharpur Business Centre,
Nehru Place,
NEW DELHI -- 110 019.

Phone : 011-26207478.
  FAX : 011-xxxxxxxx.
Email : ...@nec.com

Area : Semiconductors.
Skill : Physical Design, VHDL Synthesis.

NeoMagic Semiconductor India Pvt. Ltd.
```
First Floor, Polyplex Building,
B-37, Sector-1,
NOIDA -- 201 301.

Email : ...@neomagic.com

7th Floor, UPSIDC Complex,
Lakhanpur,
KANPUR -- 208 024.

  FAX : 0512-2583381.
Email : ...@neomagic.com
```
Area : Audio/Speech Processing, Image Processing, 3D Graphics, Multimedia, PDA, Library Development, IP Cores.
Skill : VHDL/SystemVerilog, ASIC Design, Architectures, DSP, VLSI Design, Analog Design, Memory Design, Embedded Systems.

nSys India Pvt. Ltd.

707, B-09, ITL Twin Tower,
Netaji Subhash Place,
Pitam Pura,
NEW DELHI -- 110 034.

31, Ashoka Park Extension,
East Punjabi Bagh,
NEW DELHI -- 110 026.

Phone : 011-47572300.
  FAX : 011-xxxxxxxx.
Email : ...@nsysinc.com

Area : Design and Verification Services, Communications IP.
Skill : SystemVerilog, ASIC Design, FPGA Design, Processor Architectures.

Nuelight Semiconductors India Pvt. Ltd.

8-2-334, Plot no. 25,
Road no. 3,
Banjara Hills,
HYDERABAD -- 500 034.

Phone : 040-23548892, 23548893.
  FAX : 040-23548868.
Email : ...@nuelight.com

Area : OLED, TFT-LCD, Displays.
Skill : Analog Design, Mixed Signal Design, VLSI Design.

Nulife Semiconductor India Pvt. Ltd.
```
Ground Floor, JVL Plaza,
501, Anna Salai Mount Road,
CHENNAI -- 600 018.

Email : ...@nulifetech.com

Also at NOIDA.
```
Area : Mixed Signal IP, Signal Processing, Design Services.
Skill : Analog Design, Mixed Signal Design, VLSI Design, RF IC Design.

Nvidia Graphics Pvt. Ltd.

Brigade South Parade,
10, MG Road,
BANGALORE -- 560 001.

Phone : 080-56948400.
  FAX : 080-56610980.
Email : ...@nvidia.com
      : ...@nvidia.in

Level 1-4, Muttha Chambers,
Senapati Bapat Road,
PUNE -- 411 016.

Phone : 020-56413000.
  FAX : 020-56022744.
Email : ...@nvidia.com
      : ...@nvidia.in

Area : Graphics, Media Processors.
Skill : VHDL/SystemVerilog, ASIC Design, VLSI Design, Architectures, Computer Arithmetic.

Open-Silicon Research Pvt. Ltd.

No. 11/1 and 12/1,
Maruthi Infotech Centre,
Indiranagar-Kormangala Intermediate Ring Road,
BANGALORE -- 560 071.

Phone : 080-51123843, 51123844.
  FAX : 080-xxxxxxxx.
Email : ...@open-silicon.com

Area : IP Development, Design Services.
Skill : VLSI Design, Architectures, VHDL/SystemVerilog, ESD/IO Design, DFT.

Patni Computer Systems Pvt. Ltd.
```
55, SDF II, SEEPZ,
Andheri (E),
MUMBAI -- 400 096.

Phone : 022-28291454.
  FAX : 022-28292764.
Email : ...@patni.com
```
Area : Design Services, Embedded Systems.
Skill : VHDL/SystemVerilog, VLSI Design, Architectures (uP/uC/DSP), Mixed-Signal Design, Analog Design, RF Design.
Philips Semiconductors Centre
```
Philips Innovation Campus,
No. 1, Murphy Road,
Ulsoor,
BANGALORE -- 560 008.

Phone : 080-25579000.
  FAX : 080-25560580, 25561280, 25560584.
Email : ...@philips.com
```
Area : Consumer, Digital Audio/Video, Wireless, Medical Imaging.
Skill : ASIC/FPGA Design, VHDL/SystemVerilog, VLSI Design, Architectures, DFT, Codesign, C/Tcl/C++, SystemC, Embedded Systems.
Philips Bangalore Software Centre
```
Philips House,
150/1 Infantry Road,
BANGALORE -- 560 001.

Phone : 080-2282094.
  FAX : 080-2285424.
Email : ...@blr.sc.philips.com
```
Area : Audio/Video, Telecommunications, Technology Library, IP Cores.
Skill : Physical Design, VHDL, ASIC/FPGA Synthesis.

PMC-Sierra India Pvt. Ltd.

First floor, Cyber Park,
Electronics City, Phase-1,
BANGALORE -- 560 100.
 
Phone : 080-41827002.
  FAX : 080-41827033.
Email : ...@pmc-sierra.com

Area : Telecommunications, Networking, IO Products.
Skill : Mixed-Signal Design, Analog Design, Physical Design, VLSI Design.

Posedge Technologies

Unit 2, 5th Floor, Building 9,
Mindspace, Hitech City,
Madhapur,
HYDERABAD -- 500 081.
 
Phone : 044-44182246, 44182299.
  FAX : 044-4xxxxxxx.
Email : ...@posedge.com

Area : Design Services, Wireless, Networking, Security, SoC.
Skill : Physical Design, Mixed-Signal Design, Analog Design, RF Design, VLSI Design.

PulseCore India Pvt. Ltd. Bought by ON Semiconductors in November, 2009
```
Consulate-1,
No. 1, Richmond Road,
BANGALORE -- 560 025.

Phone : 080-66604800
  FAX : 080-22129840
Email : ...@pulsecoresemi.com
```
Area : Design Services, Clock Generators, Buffers, FCC Compliance.
Skill : Mixed Signal Design, Analog Design, Electromagnetic Interference (EMI), Signal Integrity, Low Power Design, Interconnects.

QuantumThink Technologies Pvt. Ltd.

Bangalore Design Center
178/5, First Floor,
Lakshmi Chambers
8th F Main Road,
Jayanagar
BANGALORE -â€“ 560 011.
 
Phone : 080-2xxxxxxx.
  FAX : 080-2xxxxxxx.
Email : ...@qthink.com

Area : Design Services, Telecommunications, Networking, Multimedia.
Skill : VHDL/SystemVerilog, VLSI Design, DFT/BIST, Physical Design.

Qualcomm India Pvt. Ltd.

Design Centre,
HYDERABAD -- 500 0xx.

Phone : 040-2xxxxxx.
  FAX : 040-2xxxxxx.
Email : ...@qualcomm.com

Hardware Design Centre,
Export Promotion Industrial Park,
Sonnenahali Village, Hobli,
Whitefield,
BANGALORE -- 560 0xx.

Phone : 080-39841800.
Email : ...@qualcomm.com

Area : CDMA Wireless Communications, 3G Chip Sets, Library Development.
Skill : VLSI Design, ASIC Design, DSP Architectures, Physical Design, DFT, Verification, VHDL/SystemVerilog.

QLogic India Pvt. Ltd.

B-301-306, MCCIA Trade Towers,
Senapati Bapat Road,
PUNE -- 411 016.

Phone : 020-30255900.
  FAX : 020-30220070.
Email : ...@qlogic.com

Area : Networking, Communications, Storage Systems.

Skill : SystemVerilog/VHDL, ASIC Design.






QualCore Logic India Pvt. Ltd.
Design Centre,
HYDERABAD -- 500 0xx.

Phone : 040-2xxxxxx.
  FAX : 040-2xxxxxx.
Email : ...@qualcorelogic.com

Area : Mixed Signal IP, Analog IP.

Skill : VLSI Design, Physical Design, Analog Design, Mixed-signal Design.






Rambus Chip Technologies Ltd. 
India Design Centre,
#30, Pratibha Complex,
4th B Cross, 5th Block,
Industrial Layout,
Kormangala,
BANGALORE -- 560 095.

Phone : 080-xxxxxxxx.
  FAX : 080-xxxxxxxx.
Email : ...@rambus.com

Area : IP Development, IO Buses, Interfaces, Memory Technology.



Skill : VLSI Design, Physical Design, Communications Protocols,
Mixed-signal, Analog Design, Memory Design, DFT, ASIC/FPGA Design,
VHDL/SystemVerilog, Architectures, Formal Verification.





RealChip Pvt. Ltd. same as SiCore ?
161, Greams Road,
CHENNAI -- 600 006.

Phone : 044-8291013, 8291014, 8294017.
  FAX : 044-8294019.
Email : ...@realchip.com

Area : Design Services, SoC, Embedded Systems, VoIP, Communications.



Skill : SystemVerilog, Processor Architecture, ASIC Design,
Physical Design, DFT/BIST, Testing, Codesign.





Realtime Systems Ltd.
A-235, Okhla Phase I,
NEW DELHI -- 110 020.

Phone : 011-xxx.
  FAX : 011-xxx.
Email : ...@rtsindia.com

Area : Set-top Box, Voice Access Products, Communications.



Skill : VHDL/SystemVerilog, Processor Architecture, FPGA
Design, Memory Design, Analog Design, Circuit Design.





Sage Design Systems (India) Pvt. Ltd. Acquired by Genesis Microchip and then by STMicroelectronics
#1096, 12th A Main,
HAL II Stage,
Indira Nagar,
BANGALORE -- 560 008.

Phone : 080-5263878.
  FAX : 080-5296245.
Email : ...@sageindia.co.in

Area : Design Services, Graphics/Video Controllers.



Skill : SystemVerilog, Mixed Signal Design, ASIC Design, Synthesis, Physical Design, Analog Design.





Sankalp Semiconductors Pvt. Ltd.
HUBLI -- xxx xxx.

Phone : 080-5263878.
  FAX : 080-5296245.
Email : ...@sankalpsemi.co.in

Area : Design Services.



Skill : Mixed Signal Design, Analog Design, RF IC Design, Physical Design.





Sanyo LSI Technology India Ltd. In hibernation ?
Unit # 3, Level # 8, Discoverer Block,
International Technology Park,
Whitefield Road,
BANGALORE -- 560 066.

Phone : 080-8410600, 8410601, 8410602, 8410603.
  FAX : 080-8410604, 8410606.
Email : ...@sanyo.co.in

Area : Multimedia (Audio/Video), Graphics, Consumer Electronics,
Wireless, Embedded Systems, Memories.



Skill : VHDL/SystemVerilog, Architectures, DFT, Physical
Design, Analog Design, RF Design.





Sarnoff Innovative Technologies Pvt. Ltd.
Asha Arch,
Magrath Road,
BANGALORE -- 560 025.

Phone : 080-51999555.
  FAX : 080-xxxxxxxx.
Email : ...@sitpl.com

Area : Security, Medical, Automotive, Consumer, IP Development,
Consumer, Vision Technologies.



Skill : VLSI Design, Architectures, Analog, CCD Technology,
ESD/IO Design, DFT.





Sasken Communications Technologies Ltd. Formerly SAS
#139/25, Domlur Layout,
Ring Road,
Domlur P.O.,
BANGALORE -- 560 071.

Phone : 080-5355501, 5281229.
  FAX : 080-5351133, 5284397.
Email : ...@sasken.com

5th Floor, Plot No. 3,
Knowledge Park-III,
Surajpur-Kasna Main Road,
GREATER NOIDA -- 201 308.

QuickLogic/FPGA Group,
3008, 12th B Main, 8th Cross,
HAL IInd Stage, Indiranagar,
BANGALORE -- 560 008.

Phone : 080-25281461, 25281229.
  FAX : 080-25284396, 25284397.

Area : Design Services, Telecommunications, Embedded Systems.



Skill : VHDL/SystemVerilog, ASIC Design, Physical Design, DFT,
Logic Synthesis, VLSI Design.





Satyam Computers Services Ltd. (SLTI)
No. 14, Langford Avenue,
Langford Gardens,
Lalbagh Road,
BANGALORE -- 560 025.

Phone : 080-xxxxxxx.
  FAX : 080-2271882.
Email : ...@satyam.com

Area : Set-top Boxes, Embedded Systems, Automotive Electronics,
Medical Electronics, Robotics.



Skill : VHDL/SystemVerilog, ASIC Design, Neural Networks,
Physical Design, Codesign.





Scicom Infotech Pvt. Ltd.
A-67, Sector 57,
NOIDA -- 201 301.

Phone : 0120-xxxxxxx.
  FAX : 0120-xxxxxxx.
Email : ...@scicmp.com

Area : Imaging, Medical, Mobile.



Skill : VLSI Design, SoC Design, Simulation.





SiCore Systems Pvt. Ltd. same as RealChip ?
161, Greams Road,
CHENNAI -- 600 006.

Phone : 044-8224689, 8228607.
  FAX : 044-xxxxxxx.
Email : ...@sicore.com
      : ...@rrsycore.co.in

Area : Design Services, PCI-related Products, Audio/Video Technology.



Skill : Physical Design, VHDL Synthesis.





Siemens Semiconductors Group
Siemens Public Communications Networks Ltd.,
10th Floor, Raheja Towers,
M. G. Road,
BANGALORE -- 560 001.

Phone : 080-5594067.
  FAX : 080-5594369.
Email : ...@blr.siemens.de

Area : Microcontrollers, Standard Products, Technology Library.



Skill : Physical Design, CAD Tools.





Silicon Interfaces Pvt. Ltd.
606, Nirman Kendra,
Dr. E. Moses Road,
Mahalaxmi,
MUMBAI -- 400 011.

Phone : 022-xxxxxxx.
  FAX : 022-24981379.
Email : ...@siliconinterfaces.com

Area : Design Services, Networking, Communications.



Skill : SystemVerilog/VHDL, VLSI Design, ASIC/FPGA Design.





Siliconweb India Pvt. Ltd.
205, Block A, SNS Arcade,
Airport Road,
BANGALORE -- 560 017.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@siliconwebinc.com

Area : Design Services.



Skill : SystemVerilog/VHDL, VLSI Design, Physical Design.





SiRF Technology (India) Pvt. Ltd.
SiRF Technology (India) Pvt.Ltd.
A1-A, Sector 16
NOIDA -- 201 301.

Phone : 0120-3052424, 2510256.
  FAX : 0120-2510584.
Email : ...@sirf.com

Area : IP Cores, GPS, Wireless Communication.



Skill : SystemVerilog/VHDL, VLSI Design, RF Design,
Physical Design.





Software Pundits
DBS Centre,
Cunnigham Road,
BANGALORE -- 560 052.

Phone : 080-2202240.
  FAX : 080-2202240.

211 Appejay,
12, Haddows Road,
CHENNAI -- 600 006.

Phone : 044-8224949.
  FAX : 044-8224949.

Email : asic@pundits.com

Area : Design Services, Telecommunications, Networking, Multimedia, Avionics, Embedded Systems.



Skill : VHDL/SystemVerilog, ASIC/FPGA Design, C/C++.





Software-Silicon Systems (India) Pvt. Ltd. NOW part of Intel
5th Floor, Prestige Meridian,
29, M. G. Road,
BANGALORE -- 560 001.

Phone : 080-5550888.
  FAX : 080-5550718.
Email : ...@siliconsystems.co.in

Area : Telecommunications, Networking.



Skill : VHDL/SystemVerilog, ASIC Design, Architecture.





Spectross Digital Systems Pvt. Ltd.
4, Siri Fort Road,
NEW DELHI -- 110049

Phone : 011-26264077.
  FAX : 011-29830210.
Email : ...@spectross.com

Area : Embedded Systems, Networking, Wireless, Consumer Electronics.



Skill : SystemVerilog/VHDL, VLSI Design, FPGA Design.





Spike Technologies (India) Pvt. Ltd. Taken over by Qualcomm in October, 2004
951, Vijayalaxmi Complex, II Floor,
24th Main, JP Nagar, II Phase,
BANGALORE -- 560 078.

Phone : 080-xxxxxxx.
  FAX : 080-6540312.
Email : design@spikeindia.soft.net
      : ...@spiketech.com

Area : Design Services, Networking, ASIC Library Development.



Skill : VHDL/SystemVerilog, ASIC/FPGA Design, Physical Design, DFT, Memory Design.





STMicroelectronics Ltd.  aka SGS-Thomson (Old Name)
India Design Centre,
Plot no. 1, Knowledge Park III,
GREATER NOIDA -- 201 308.

Phone : 0120-2352999.
  FAX : 0120-2569497.
Email : ...@st.com

Area : Consumer, Memory, Standard Products, Technology Library, Peripherals,
Industrial Control, Imaging, Multimedia.



Skill : Analog, Mixed-signal, Physical Design, VHDL/SystemVerilog, Architectures,
DFT, Formal Verification, Scripting.





Sun Microsystems India Pvt. Ltd. Defunct ?? Now part of Oracle
6th Floor, Divyasree Chambers,
Off Langford Road,
BANGALORE -- 560 027.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@india.sun.com

Area : Embedded UltraSPARC, Megacells/Blocks, Memory.



Skill : MOS Physics, Physical Design, VLSI Design, Circuit Design, Clock Analysis, Power Analysis, Verification/Validation.





Sydaap Technologies Pvt. Ltd.
Second Floor, Prestige Omega,
No. 104 EPIP Zone,
Whitefield,
BANGALORE -- 560066

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...@sydaap.com

Area : Design Services, IP Cores, Wireless Communications, RFID, Encryption.



Skill : Physical Design, VLSI Design, Verification/Validation, Analog Design.





Tality India Services Pvt. Ltd.
57 A+B, NEPZ,
NOIDA -- 201 301.

Phone : 0120-2562842.
  FAX : 0120-xxxxxxx.
Email : ...@tality.com

Area : Design Services, Multimedia, Networking, Wireless,
Appliances.



Skill : VHDL/SystemVerilog, ASIC Design, Physical Design,
VLSI Design, Architectures, RF Design.





Tallika India Pvt. Ltd.
CHENNAI -- 6xx xxx.

Email : ...@tallika.com

Area : Design Services, IP Blocks, PCI Express, Memory Controllers.



Skill : RTL Design, Mixed Signal Design, VLSI Design.





Tata Elxsi Ltd.
VLSI Design Group,
123, Richmond Road
BANGALORE -- 560 025.

Phone : 080-5563945, 5364835, 5363956.
  FAX : 080-5583168.
Email : ...@tataelxsi.com

ASIC Design Group,
Whitefield Road,
Hoody,
BANGALORE -- 560 048.

Phone : 080-8410148, 8410149.
  FAX : 080-841xxxx.
Email : ...@teil.soft.net

Area : Design Services, Embedded Systems, Communications, Networking.



Skill : VHDL/SystemVerilog Synthesis, ASIC/FPGA Design, VLSI Design, High-speed Digital Design.





Tata Infotech Ltd.
BANGALORE -- 560 00x.

Phone : 080-266xxxx.
  FAX : 080-2672xxx.
Email : ...@tatainfotech.com

Area :



Skill : VHDL Synthesis, CAD Tools.





Tejas Networks India Pvt. Ltd.
Zone 2, 1st Floor, Khanija Bhavan,
49, Race Course Road,
BANGALORE -- 560 001.

Phone : 080-2267495, 2384712, 2384713, 2384714, 2384715.
  FAX : 080-2267494.
Email : ...@tejasnetworks.com

Area : Optical Networking, SONET/SDH, DWDM.



Skill : SystemVerilog/VHDL, FPGA Design.





Telecruz Technology Ltd.
3rd Floor, HCL Towers,
44, Dwarkadas Colony,
Chikoti Gardens,
Begumpet,
HYDERABAD -- 500 016.

  FAX : 040-27762964.
Email : ...@telecruz.com

Area : TV/Consumer Electronics, Set-top Boxes.



Skill : SystemVerilog/VHDL, ASIC Design, VLSI Design.





Texas Instruments (India) Pvt. Ltd.
Bagmane Tech Park,
C. V. Raman Nagar,  
Bangalore 560 093.

Phone : 080-25345454, 25345455.
  FAX : 080-25048213.
Email : ...@india.ti.com
      : ...@ti.com

[OLD ADDRESS]

Wind Tunnel Road,
Murgeshpalya,
BANGALORE -- 560 017.

Phone : 080-25269451, 25269452, 25099849, 25099851.
  FAX : 080-25298373, 25298519, 25269456.


Area : DSP Processors, Memory, PCI, 3G Wireless.



Skill : VHDL/SystemVerilog, VLSI Design, CAD Tools,
RF Design.




ThinkIT (India) Pvt. Ltd.
BANGALORE -- 560 0xx.

Phone : 080-xxxxxxx.
  FAX : 080-xxxxxxx.
Email : ...

Area : Design Services, Multimedia, Graphics.



Skill : VHDL/SystemVerilog, VLSI Design.





TranSwitch (India) Pvt. Ltd.
India Design Center,
A-27, Mohan Coop. Industrial Estate,
Mathura Road,
NEW DELHI -- 110 044.

Phone : 011-40530000, 40530001, 400530010.
  FAX : 011-41678889.
Email : ...@txc.stpn.soft.net
      : ...@transwitch.com

Area : Design Services, Networking, Voice/Data Communications, IP Blocks.



Skill : VHDL/SystemVerilog, FPGA Design, Mixed-signal,
Verification, DFT, VLSI Design, Architectures.





V3 Logic Pvt. Ltd.
813, Pradeep Chambers,
Bhandarkar Institute Road,
PUNE -- 411 004.

Phone : 020-5662832, 5662833.

330/1, 2nd 'A' Main Road,
Domlur,
BANGALORE -- 560 071

Phone : 080-5351561, 5351562.

Email : ...@v3logic.com

Area : Design Services, Training



Skill : VHDL/SystemVerilog, ASIC/FPGA Design, VLSI Design.





Vedatech India (Software) Pvt. Ltd.
BANGALORE -- 560 025.

Phone : 080-xxxxxxx.
  FAX : 080-2291291.
Email : ...@vedatech.net

Area : Design Services, Telecommunications, Consumer, Microprocessor.



Skill : VLSI Design, VHDL/SystemVerilog.





Velankani Information Systems Ltd.
43, Electronics City, Phase II,
BANGALORE -- 561 229.

Phone : 080-8522507.
  FAX : 080-8522508.
Email : ...@velakani.com
      : ...@visindia.com

Area : Design Services, Telecommunications, Networking.



Skill : VHDL/SystemVerilog, ASIC/FPGA Design, Physical Design, SPICE, DSP, RF Design.





vEngines India Pvt. Ltd. Taken over by Centillium in Jan, 2001
Ground Floor, Haleema Centre,
5th A Block, 60 Feet Road,
Kormangala,
BANGALORE -- 560 095.

Phone : 080-5523575, 5523576, 5523577.
  FAX : 080-5523514.
Email : ...@vengines.com

Area : Voice-Data Networks (ATM, xDSL, Cable, ...), Telecommunications, Embedded Systems.



Skill : SystemVerilog, ASIC Design, RT Synthesis, Architecture, DFT, SoC, DSP Algorithms.





Virage Logic International Acquired by Synopsys in June, 2010
India Design Center,
A-75, Sector 57,
NOIDA -- 201 307.

Phone : 0120-2588881, 2588882.
  FAX : 0120-2587880.
Email : ...@viragelogic.com

Area : IP Blocks/Cores, Cell Library, SoC, Embedded Systems.



Skill : VLSI Design, VHDL/SystemVerilog, Physical Design,
DFT/BIST, Low-Power, VLSI Architectures.





Vitesse Semiconductor India Pvt. Ltd.
HYDERABAD -- 500 0xx.

Phone : 040-2588881, 2588882.
  FAX : 040-2587880.
Email : ...@vitesse.com

Area : Networking, Ethernet, Data Interconnect, Storage
Solutions.



Skill : VLSI Design, VHDL/SystemVerilog, Physical Design,
DFT/BIST, Low-Power, VLSI Architectures.





Wipro Technologies Ltd.
Global R&D Solutions,
30, Mission Road, I Main,
S. R. Nagar,
BANGALORE -- 560 027.

Phone : 080-xxxxxxx.
  FAX : 080-2241769.
Email : ...@wipinfo.soft.net
      : ...@wipro.co.in

Also at HYDERABAD, CHENNAI and PUNE.

Area : Design Services, Telecom, Datacom, Wireless, Networking,
Automotive Electronics, Multimedia.



Skill : VLSI Design, VHDL/SystemVerilog, Mixed-signal,
RF Design, Physical Design, ASIC/FPGA Design, Cell Library.

Digital Design

2011-09-30T13:19:00.001+05:30

Foundation of Switching Theory and Logic Design.pdf
http://www.mediafire.com/?mmb9j86yr398j46

STA

2011-09-30T13:11:00.002+05:30

Static-Timing-Analysis-for-Nanometer-Designs
http://www.mediafire.com/?neckl9d2fw0y97i

Physical Design

2011-09-30T12:59:00.003+05:30

CMOS IC Layout
http://www.mediafire.com/?dc6fbfv9s9bj8aj

Digital Design

2011-09-30T12:53:00.006+05:30

Digital Integrated Circuits (2nd Edition) by Rabaey
http://www.mediafire.com/?8iam12af9rkhmcw

Analog Design

2009-10-02T18:43:00.003+05:30

Analog Integrated Circuit Design