Utopia

Learning SDL Part II

2024-07-14T18:39:00.010-04:00

In Learning SDL Part I I talked about the 2DLight example from https://glusoft.com/sdl2-tutorials. It might be a bit too advanced for beginner. The examples have external dependencies, and might not easy to be understood without basic concept of SDL. Code might have not been maintained after years. And may due to build tools update or package update, code cannot be built out-of-box. So I decide to start from simple one: https://lazyfoo.net/tutorials/SDL.

The first example is "01_hello_SDL". Since it is a simple one, I'm going to try to build it with NMake. A simple Makefile for x64 would be like this:

# Compiler
CC=cl
# Include directory for SDL headers
SDL_INCLUDE=C:\path\to\SDL\include\SDL2
# Library directory for SDL library files
SDL_LIB=C:\path\to\SDL\lib\x64
# Compiler flags, appending /Zi if want to debug
CFLAGS=/I$(SDL_INCLUDE) /Dmain=SDL_main
# Linker flags
LFLAGS=/link /LIBPATH:$(SDL_LIB) SDL2.lib SDL2main.lib SDL2_image.lib Shell32.lib /SUBSYSTEM:CONSOLE

# Target executable name
TARGET=01_hello_SDL.exe
# Source files
SOURCES=01_hello_SDL.cpp

# Rule to make the target
$(TARGET): $(SOURCES)
    $(CC) $(CFLAGS) /Fe:$(TARGET) $(SOURCES) $(LFLAGS)

# Clean target
clean:
    del $(TARGET) *.obj

Note: 1) have to specify /SUBSYSTEM:CONSOLE, otherwise may get entry point not defined error as Win32 app will look for WinMain as entry point.

2) Have to link to SDL2main.lib and Shell32.lib. SDL2main.lib provides SDL entry function. The Shell32.lib is needed, otherwise, will get error 'LNK2019: unresolved external symbol __imp_CommandLineToArgvW referenced in function main_getcmdline'

3) For some projects need more image format support such as png, would need link to more lib, such as 06_extension_libraries_and_loading_other_image_formats, would need libpng16-16.dll and zlib1.dll which is a dependency of the png dll. If this zlib1 is missing, will only see error complaining "Failed loading libpng16-16.dll" which might be misleading.

4) For projects which needs font, would need link to SDL2_ttf.lib, and needs libfreetype-6.dll at runtime

5) For projects which needs audio, would need link to SDL2_mixer.lib,

Run this to setup x64 env: "C:\Program Files (x86)\Microsoft Visual Studio\2022\BuildTools\VC\Auxiliary\Build\vcvars64.bat", then run 'NMake' to build. Can copy the x64 SDL dll to C:\Windows\System32 folder, then won't need to copy them to working folder every time.

6) For projects using OpenGL, OpenGL very likely is already installed on the system. May check whether opengl.dll and glu.dll under \windows\system32. To link the lib, add these two libs:

opengl32.lib glu32.lib

7) For OpenGL Extension Wrangler library, can be downloaded from https://glew.sourceforge.net/

Learning SDL Part I

2024-07-14T14:21:00.010-04:00

While trying to add more feature to the Tanks game, I realized that I need dive deeper into SDL programming. For this reason, I went to https://glusoft.com/sdl2-tutorials/ and downloaded project files. As I didn't have the Visual Studio installed, but only the build tools, so need some tweak to build the examples. The downloaded package comes with solution (.sln) and project (.vcxproj) files. So the project can be built with command like: msbuild 2DLight.sln /p:Configuration=Release /p:Platform="x86"

Also need to update the vcxproj file with v141=>v143, set WindowsTargetPlatformVersion to 10.0.22621.0 which matches my environment, and set AdditionalIncludeDirectories and AdditionalLibraryDirectories to have my SDL2 header file and lib paths, and need to make sure the setting is in 'x64' session if using x64 as platform in above command line. And for the first 2DLight example, would need download https://github.com/trylock/visibility and SDL2_gfx as well. Note SDL_gfx is not from libsdl.org as other SDL lib. And note, there is SDL2_gfx-1.0.4.tar.gz (.zip) and SDL_gfx-2.0.27.tar.gz, though the 2.0.27 is a newer release (Ver 1.0.4 – 11 Feb 2018 vs Ver 2.0.27 – Sun Dec 10 2023), the later is not compatible with SDL2, and though it comes with a SDL2 patch (also needs some tweak such as needs to link with SDL2.lib instead of SDL.lib, rename the project file as SDL2_gfx.vcxproj), the resulted lib may not work with the example code from sdl2-tutorials.

Need to make similar update for SDL2_gfx.vcxproj. And it does not have x86, but Win32, so build command is:
msbuild SDL2_gfx.sln /p:Configuration=Release /p:Platform="Win32"

May see this error: SDL2_gfx-1.0.4\SDL2_gfxPrimitives_font.h(1559,1): warning C4819: The file contains a character that cannot be represented in the current code page (936). Save the file in Unicode format to prevent data loss

Just remove these characters (all are inline comment) should be OK.

For error SDL2_gfx-1.0.4\SDL2_gfxPrimitives.c(1771,2): error C2169: 'lrint': intrinsic function, cannot be defined, refer to https://www.ferzkopp.net/wordpress/2016/01/02/sdl_gfx-sdl2_gfx. Just comment out the define/implementation as this is already defined as intrinsic function.

There would be a bunch error for building test if those vcxproj files have not been updated, and can be ignored for now. If all test project files got updated, 3 of the 4 tests should work out-of-box, but for TestImageFilter, would not see any thing displayed or printed to terminal. By checking the code, this Image filter test is using 'printf' to log information, and the test has no graphics display. The 'printf' won't spite out anything either, probably due to SDL hijacked the console I/O. The C code also includes 'windows.h' when 'WIN32' is defined. And in fact, w/ or w/o this header file makes no difference. The way to get some print out is replacing 'printf' in the code with 'SDL_Log' call. With SDL_Log, I got 23 of 27 passed OK.

Now, back to the 2DLight example, all build are OK, but will get runtime error as "The application was unable to start correctly. 0xc00007b". Turns out this is due to mixed using x64 build tools to build x86 dll and executable. And the behavior is very weird. So, just avoid doing that.

Now with x86 build environment, build SDL2_gfx as Win32 target, and use other x86 SDL2 lib/dll, also make sure the image/PNG files are copied to the run folder, no more 0xc00007b, however, seeing an assert for vector subscript out of range. Per Copilot:

The vx.reserve(result.size()) call in the code snippet reserves memory for result.size() elements in the vector vx. However, it does not change the size of the vector. The reserve() function is used to allocate memory in advance to prevent frequent reallocations when adding elements to the vector.

To actually change the size of the vector to match the reserved capacity, you can use the resize() function instead of reserve(). The resize() function not only reserves memory but also sets the size of the vector to the specified value.

After I replaced the two reserve() with resize(), the code mostly works as expected, may still see 'Expression: vector subscript out of range' sometimes, likely usually happened when moving the mouse cursor out of the frame, probably due to missing boundary checking. Updated source code was pushed to forked https://github.com/quyq/2DLight-SDL.

If you are using VSCode as editor like me, you may create task.json like this to allow building the project with MSBuild using shortcut 'ctrl+shift+b' (the top half set build env for x86, the bottom half run MSBuild with the solution file):

{
    "version": "2.0.0",
    "windows": {
      "options": {
        "shell": {
          "executable": "cmd.exe",
          "args": [
            "/C",
            // The path of batch file and platform parameter for setting the build env
            "\"C:/Program Files (x86)/Microsoft Visual Studio/2022/BuildTools/VC/Auxiliary/Build/vcvarsall.bat\"",
            "x86",
            "&&"
          ]
        }
      }
    },
    "tasks": [
      {
        "type": "shell",
        "label": "MSBuild.exe build active file",
        "command": "MSBuild.exe",
        "args": [
            "2DLight.sln",
            "-p:Configuration=Release"
        ],
        "problemMatcher": ["$msCompile"],
        "group": {
          "kind": "build",
          "isDefault": true
        }
      }
    ]
}

If want to use VSCode built-in debugger, may create launch.json as:

{
    "version": "0.2.0",
    "configurations": [
        {
            "name": "2DLight",
            "type": "cppvsdbg",
            "request": "launch",
            "program": "2DLight.exe",
            "args": [],
            "stopAtEntry": false,
            "cwd": "${workspaceFolder}/Release",
            "environment": [],
            "console": "externalTerminal"
        }
    ]
}

Update Tanks (坦克大战) with network support

2024-07-10T02:18:00.004-04:00

With Revisit 坦克大战编程, can easily build Tanks on Windows or under WSL. However, with one player the game would be a bit boring and a bit frustrate; and with two player2 on same PC, it would be a bit crowd for four hands on one keyboard. If would be more attractive if two players can play together remotely, or even play against each other, would be much fun. So, we need to bring in network support. Would need to choose a suitable networking library, (e.g., SDL_net, which complements SDL, or another networking library like Boost.Asio for C++). Need to initialize the networking in the application, setting up one instance as the server and the other as the client.

I haven't been using either network library. So will pick SDL_net since we already have used other library from SDL. SDL_net was moved to github as: https://github.com/libsdl-org/SDL_net. Similar as other SDL libraries, I downloaded SDL2_net-devel-2.2.0-VC.zip.

Now it's time to deep dive to the code to understand the design. The main loop is App::run with state of m_app_state check/switch, eventProces, m_app_state->update, m_app_state->draw, and FPS control. m_app_state initially is pointing to an instance of Menu, then it is pointing to an instance of Game, Scores and Menu sequentially after invoke of nextState, which updates the state machine. Menu is the state to allow user to select player and quit, Scores is the state to show the score. So we most are interested of the Game state.

It would be complex to maintain two state machine on two hosts, even one is a mirror of the other. Need to clone all object on fly, with dynamic create and destroy, and need to merge input from both side, and one side needs to be the master for random number generation, state control by user. Also consider network latency, might be a bit messy to maintain the sync between server and client. The easier approach would be let the master to maintain the state machine, for client side, just relay the input to server, and mirror the render result from server.

(to be continue)

Program D-Link DCS-5010L - Part 3

2024-06-30T19:11:00.004-04:00

As mentioned in Program D-Link DCS-5010L - Part 2, I wasn't able to successfully open DCS-5010L stream with OpenCV+GStreamer, so I'm going to explore OpenCV+ffmpeg. Ffmpeg is famous OpenSource Multimedia framework which contains a set of utility with almost all codec supported. Here is a Ffmpeg vs. GStreamer comparison.

To going this approach, there is FfmpegCV, which might be served as OpenCV replacement with ffmpeg support, has compatible API as OpenCV. Here I'm going to give it a try. Similar as using GStreamer, would need to install ffmpeg executable separately. Then do: pip install ffmpegcv

This will install the stable version, without cuda acceleration as I don't have nVidia GPU. After trying around, I realized that I need to use this API to open the stream:

cap = ffmpegcv.VideoCaptureStream(stream_url)

However, I don't see how it can help to play the audio.

Then I turned to PyAV. With that, I figured out that the 'video.cgi' would only provide video stream. Need to open 'audio.cgi' for the audio stream which is in wave format.

I added my code to forked dlink-dcs-python-lib github repository, with arrow key support for tile/pan the camera. There is no need to put the OpenCV video into a Tcl/tk gadget, but may create a TK GUI for setting configuration/options such as video file saving path, resolution, motion detecting and so on.

Program D-Link DCS-5010L - Part 2

2024-06-22T17:18:00.002-04:00

OpenCV is mainly focusing on video. It does not support audio directly. To playback audio, would rely on ffmpeg or GStreamer. ffmpeg is mostly a standalone offline multimedia converting tools. OpenCV has GStreamer built-in support, but it is optional. I used pip installed opencv-python on Windows for Python 3.12, and GStreamer isn't enabled. May refer to github opencv-python and https://discuss.bluerobotics.com/t/opencv-python-with-gstreamer-backend/8842. Even install the full package with pip install opencv-contrib-python won't get GStream enabled CV2. Might need to build with source. Either way, would need to install GStreamer first, which is available here: https://gstreamer.freedesktop.org/download. To build GStreamer enabled opencv-python:

git clone --recursive https://github.com/opencv/opencv-python.git
cd .\opencv-python
set CMAKE_ARGS="-DWITH_GSTREAMER=ON" or $env:CMAKE_ARGS="-DWITH_GSTREAMER=ON" for PowerShell
pip wheel . --verbose

The build gets setuptools 59.2.0, I'm using miniConda and I'm seeing "conda 24.1.2 requires setuptools>=60.0.0, but you have setuptools 59.2.0 which is incompatible". This is not my environment setuptools out-of-date issue, have tried: pip install setuptools --upgrade, python -m pip install pip --upgrade, conda update -n base setuptools, nothing works. And after this, seeing:

Running command Getting requirements to build wheel
Traceback (most recent call last):
File "C:\ProgramData\miniconda3\Lib\site-packages\pip\_vendor\pyproject_hooks\_in_process\_in_process.py", line 353, in <module>
main()
...

    File "C:\Users\squ\AppData\Local\Temp\pip-build-env-lekizdpu\overlay\Lib\site-packages\pkg_resources\__init__.py", line 2172, in <module>
      register_finder(pkgutil.ImpImporter, find_on_path)
                      ^^^^^^^^^^^^^^^^^^^
AttributeError: module 'pkgutil' has no attribute 'ImpImporter'. Did you mean: 'zipimporter'?
error: subprocess-exited-with-error

Sounds same as opencv-python issues 988, one comment there mentioned:

I encountered the same problem while running pip wheel . --verbose |& tee install_opencv.log. It worked after removing the ==59.2.0" from the "setuptools==59.2.0" https://github.com/opencv/opencv-python/blob/4.x/pyproject.toml#L16.

The pyproject.toml file is under the root, with the setuptools line removed, the original problem is resolved. Build under Windows would need Visual Studio Build Tools (refer to Revisit 坦克大战编程)., need to do the build under the Native build environment. The build will try Ninja, Visual Studio and NMake generator, and will try from v144 to v141. I have v143, and have "Developer Command Prompt for VS 2022" environment launched, all Ninja and NMake will fail as no support of platform, VS v143 progress a bit far, but still get error as:

-- Trying 'Visual Studio 17 2022 x64 v143' generator

-- The C compiler identification is unknown
CMake Error at CMakeLists.txt:3 (ENABLE_LANGUAGE):
No CMAKE_C_COMPILER could be found.

After some research, turns out Windows SDK is needed (I deselected it when installing Visual Studio Build Tools to save some space). It takes a while to build, depends on your computer. But it works. The opencv_python-*.whl file will be generated in the root folder. Just run pip to install it.

At beginning of the build, it will show the configuration, make sure Gstreamer is ON. It will stay OFF if GStreamer develop isn't installed. And with Gstreamer is enabled, I'm getting runtime error as:

ImportError: DLL load failed while importing cv2: The specified module could not be found

which is similar as opencv-python issues 856. Installed Microsoft Visual C++ Redistributable for Visual Studio 2022, but that didn't help. My Windows is not the 'N' one, so not a problem of Windows Media Feature Pack. I have tried the build whl before Gstreamer option enabled and not seeing problem, so I believe the problem is with GStreamer dll, but adding "C:\gstreamer\1.0\msvc_x86_64\lib\gstreamer-1.0" to path didn't help. Have to hook up Sysinternals' Process Monitor, and it shows the run is looking for a bunch of gstreamer's runtime dll which were not in site-packages\cv2 folder. Added "C:\gstreamer\1.0\msvc_x86_64\bin" to environment variable 'PATH' didn't help. Copy dlls over works, but not a clean way. Per https://stackoverflow.com/questions/214852/python-module-dlls, since version python 3.8 they added a mechanism to do this more securely. Read documentation on os.add_dll_directory https://docs.python.org/3/library/os.html#os.add_dll_directory. So doing this in code would work:

import os
gst_root = os.getenv('GSTREAMER_1_0_ROOT_MSVC_X86_64', 'C:/gstreamer/1.0/msvc_x86_64/')
os.add_dll_directory(gst_root+'bin')
import cv2

With Gstreamer enabled, I'm still not able to open the stream with log as:

[ WARN:0@2.620] global cap_gstreamer.cpp:2840 cv::handleMessage OpenCV | GStreamer warning: Embedded video playback halted; module souphttpsrc0 reported: Could not establish connection to server.
[ WARN:0@2.623] global cap_gstreamer.cpp:1698 cv::GStreamerCapture::open OpenCV | GStreamer warning: unable to start pipeline
[ WARN:0@2.623] global cap_gstreamer.cpp:1173 cv::GStreamerCapture::isPipelinePlaying OpenCV | GStreamer warning: GStreamer: pipeline have not been created
[ WARN:0@2.623] global cap.cpp:206 cv::VideoCapture::open VIDEOIO(GSTREAMER): backend is generally available but can't be used to capture by name

A bit frustrate on this. The http url is all right as I can open it without using GStreamer. Most example I can find are using rtsp protocol but not http. Will leave this aside until I can figure out how to use GStreamer alone to open the stream. I'm going to try OpenCV+ffmpeg next

Program for D-Link DCS-5010L

2024-06-21T23:50:00.002-04:00

D-Link DCS-5010L is a pretty old generation Pan & Tilt WIFI network camera. It is so old, only can be accessed with old IE web browser as it needs ActiveX. For Edge, may work by using IE mode. And almost impossible to use Firefox or Chrome browser. And for some feature and function, would need java installed. And it might not work due to old firmware and interface.

D-Link's Android app even cannot connect to the camera. Give up on that as so frustrate. The TinyCam app can view and control the movement of the camera, but cannot change video resolution, codec type, and motion detection setting.

So come to the idea to use Python script to control and view the camera, more flexibility. Later, may think to make my own Android app for the camera. There is github dlink-dcs-python-lib can be used as lib or reference. This lib has unit test code, but does not have stream video viewer code. Github copilot suggests to use opencv-python for video processing and use requests for handling HTTP requests. Code like below, worked quite well:

import cv2
import requests
import numpy as np
import os

CAM_HOST = os.environ.get('CAM_HOST') or ''
CAM_PORT = os.environ.get('CAM_PORT', 80)
CAM_USER = os.getenv('CAM_USER', 'admin')
CAM_PASS = os.getenv('CAM_PASS', '')

# URL of the video stream
stream_url = f'http://{CAM_HOST}:{CAM_PORT}/video.cgi'

# Start a session
session = requests.Session()
response = session.get(stream_url, stream=True, auth=(CAM_USER, CAM_PASS))

# Check if the connection to the stream is successful
if response.status_code == 200:
    bytes_data = bytes()
    for chunk in response.iter_content(chunk_size=1024):
        bytes_data += chunk
        a = bytes_data.find(b'\xff\xd8')  # JPEG start
        b = bytes_data.find(b'\xff\xd9')  # JPEG end
        if a != -1 and b != -1:
            jpg = bytes_data[a:b+2]  # Extract the JPEG image
            bytes_data = bytes_data[b+2:]  # Remove the processed bytes
            frame = cv2.imdecode(np.frombuffer(jpg, dtype=np.uint8), cv2.IMREAD_COLOR)
            if frame is not None:
                cv2.imshow('Video Stream', frame)
                if cv2.waitKey(1) & 0xFF == ord('q'):  # Exit loop if 'q' is pressed
                    break
    cv2.destroyAllWindows()
else:
    print("Failed to connect to the stream.")

Above code is for viewing Motion Jpeg. To view h.264 stream, can use below code:

import cv2
import os

# URL of the H.264 video stream
CAM_HOST = os.environ.get('CAM_HOST') or ''
CAM_PORT = os.environ.get('CAM_PORT', 80)
CAM_USER = os.getenv('CAM_USER', 'admin')
CAM_PASS = os.getenv('CAM_PASS', '')

# URL of the video stream
stream_url = f'http://{CAM_USER}:{CAM_PASS}@{CAM_HOST}:{CAM_PORT}/video.cgi'

# Create a VideoCapture object
cap = cv2.VideoCapture(stream_url)

# Check if camera opened successfully
if not cap.isOpened():
    print("Error: Could not open video stream.")
else:
    # Read until video is completed
    while cap.isOpened():
        # Capture frame-by-frame
        ret, frame = cap.read()
        if ret:
            # Display the resulting frame
            cv2.imshow('Video Stream', frame)

            # Press Q on keyboard to exit
            if cv2.waitKey(1) & 0xFF == ord('q'):
                break
        else:
            break

# When everything done, release the video capture object
cap.release()

# Closes all the frames
cv2.destroyAllWindows()

Revisit 坦克大战编程

2024-06-19T00:49:00.002-04:00

In 2021 I posted two blog regarding building Tank natively with Visual Studio Build tools:

When I trying to redo the build from scratch, I noticed some is missing in my post, for example, there is no 'Build' folder by default. No need of Cygwin. Also, I'm planning to add network support, so player can play the game over internet. So I decide to make another blog to explore this. So here is a complete step by step for creating the build:

Download Visual Studio Build Tools. Go to https://visualstudio.microsoft.com/downloads/?q=build+tools, scroll down and looking for something like Build Tools for Visual Studio 2022. When install, only need select "Desktop Develoment with C++", and for optional modules, the build environment such as MSVC v143 and C++ CMake tools for Windows are needed. All other can be deselected to save some space.
Run "git clone https://github.com/quyq/Tanks.git" in working directory to pull the source code
Install SDL2 header file and lib. SDL2 binary can be download from:

https://www.libsdl.org/release/, such as SDL2-devel-2.30.4-VC.zip
https://www.libsdl.org/projects/SDL_ttf/release, such as SDL2_ttf-devel-2.22.0-VC.zip
https://github.com/libsdl-org/SDL_mixer/releases, such as SDL2_mixer-devel-2.8.0-VC.zip
https://www.libsdl.org/projects/SDL_image/release, such as SDL2_image-devel-2.8.2-VC.zip
May create a SDL folder in project root, and extract include and lib from above zip files (may delete those license files and optional files). Then change directory to 'include' folder, create 'SDL2' subfolder there, and move all header file to this 'SDL2' folder as that is the path used in source code.

Start a Visual Studio Build Tools environment, and do:

create 'build' folder (such as 'mkdir build') under project root
change working directory to 'build' (i.e. run 'cd build'), then run:

cmake -G "NMake Makefiles" ..
Note: the two dots is a must which set the source folder as one level up, and this will create Makefile, out folder and several other files/folder under 'build'

Run 'NMake' which should create 'tank.exe' under 'build/out' folder. Resource files would be copied to there too.

For using "NMake Makefiles" generator, update settings.json as:

{
    "terminal.integrated.defaultProfile.windows": "Command Prompt",
    "cmake.generator": "NMake Makefiles",
}

The first line will change default terminal from "Power Shell" to "Command Prompt". The next line select the generator. By default, it will use Visual Studio 16 2019 generator.

Build under WSL might be much easier, just install make/g++ and SDL2 develop package, then run make. If using Win11+WSL2, then no other extra work needed. If running WSL2 on Win10, may need update to latest WSL which has systemd support for GUI. And for audio, may follow instruction from https://x410.dev/cookbook/wsl/enabling-sound-in-wsl-ubuntu-let-it-sing/ which has clear step by step instruction and does not open unnecessary permission for utilizing PulseAudio.

Developing Android App with chart supported by MPAndroidChart

2024-05-11T16:15:00.002-04:00

MPAndroidChart (https://github.com/PhilJay/MPAndroidChart) is a powerful Android chart view / graph view library, supporting line- bar- pie- radar- bubble- and candlestick charts as well as scaling, panning and animations. As Open Source Project, the source code is free available from GitHub. There is general introduction, javadocs, and example code. But I cannot find a user guide document for how to use this lib from an Android project. This project was actively development several years ago. So it is using Java and Gradle Groovy. Unfortunately, latest Android Studio only support Gradle Kotlin, and no longer provides option to select java as language. I was having a lot of problem to run the example code. Also tried following other online example/tutorial using MPAndroidChart, but no luck either. That makes me decide to make this post to write down notes I have.

First, as mentioned here and several other posts, you would need to add 'jitpack.io' to your Project level Gradle file like this:

repositories {
maven { url 'https://jitpack.io' }
}

However, with recent Android Studio created project, if you add above to your root build.gradle file, you will get error like "Build was configured to prefer settings repositories over project repositories but repository 'maven' was added by build file 'build.gradle'". The correct way is adding it to the settings.gradle file like this:

dependencyResolutionManagement {
    repositoriesMode.set(RepositoriesMode.FAIL_ON_PROJECT_REPOS)
    repositories {
        google()
        mavenCentral()
        maven { url 'https://jitpack.io' }
    }
}

Second, if the project is using Gradle Kotlin, then would need to update settings.gradle.kts like this:

dependencyResolutionManagement {
    repositoriesMode.set(RepositoriesMode.FAIL_ON_PROJECT_REPOS)
    repositories {
        google()
        mavenCentral()
        maven { setUrl("https://jitpack.io") }
    }
}

Note, the syntax is different for the two types gradle file.

RISC-v on ZC706 Evaluation Board - Part VI: Building fesvr-zynq with Petalinux

2024-02-07T14:52:00.009-05:00

As of RISC-v on ZC706 Evaluation Board - Part V: Running Petalinux, I'm back to square one, need to figure out how to build fesvr-zynq with Petalinux. First, set all environment as I can:

source <path-to-installed-PetaLinux>/settings.sh
source <path-to-installed-PetaLinux>/components/yocto/buildtools/environment-setup-x86_64-petalinux-linux
source <path-to-installed-Xilinx>/Vitis/2022.1/settings64.sh
export PATH=$PATH:<path-to-installed-Xilinx>/Vitis/2022.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/x86_64-petalinux-linux/usr/bin/arm-xilinx-linux-gnueabi
cd <path-to-fpga-zynq>/zc706 && make fesvr-zynq

Now, it complain:
arm-xilinx-linux-gnueabi-g++ -O2 -std=c++11 -Wall -L fpga-zynq/common/build -lfesvr -Wl,-rpath,/usr/local/lib -I fpga-zynq/common/csrc -I fpga-zynq/testchipip/csrc -I fpga-zynq/rocket-chip/riscv-tools/riscv-fesvr/ -Wl,-rpath,/usr/local/lib -o fpga-zynq/common/build/fesvr-zynq /mnt/ext4/fpga-zynq/common/csrc/fesvr_zynq.cc fpga-zynq/common/csrc/zynq_driver.cc fpga-zynq/testchipip/csrc/blkdev.cc

Vitis/2022.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/x86_64-petalinux-linux/usr/lib/arm-xilinx-linux-gnueabi/gcc/arm-xilinx-linux-gnueabi/11.2.0/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory

9 | # include_next <stdint.h>
| ^~~~~~~~~~

Still sounds like some configuration is missing for the build. With export CFLAGS/CPPFLAGS/CXXFLAGS or set them in make cmdline to "-I<path-to-Xilinx>/Vitis/2022.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/x86_64-petalinux-linux/usr/include" doesn't help either.

Search shows me a link from lowRISC as Building the front-end server:

# set up the RISCV environment variables
# set up the Xilinx environment variables
cd $TOP/riscv-tools/riscv-fesvr
mkdir build_fpga
cd build_fpga
../configure --host=arm-xilinx-linux-gnueabi
make -j$(nproc)

Once compilation has completed, you should find the following files:

ls -l fesvr-zedboard
ls -l libfesvr.so

To copy your new front-end server to the FPGA image:

cd $TOP/fpga-zynq/zedboard
make ramdisk-open
sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/fesvr-zedboard \
  ramdisk/home/root/fesvr-zynq
sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/libfesvr.so \
  ramdisk/usr/local/lib/libfesvr.so
make ramdisk-close
sudo rm -fr ramdisk

The proxy kernel (pk) used by the FPGA is the same one used in simulation. While not normally necessary, the proxy kernel can be recompiled using the following commands:

cd $TOP/fpga-zynq/zedboard
make ramdisk-open
sudo cp $TOP/riscv-tools/riscv-pk/build/pk ramdisk/home/root/pk
make ramdisk-close
sudo rm -fr ramdisk

lowRISC also has its risc-fesvr build instruction at fpga-zynq/README.md, slightly different from https://github.com/ucb-bar/fpga-zynq. And actually the two would behave same, if I use Xilinx 2016, which create a 'SDK' folder, and after run 'source SDK/2016.2/settings64.sh', 'make fesvr-zynq':

mkdir -p fpga-zynq/common/build
cd fpga-zynq/common/build && \
fpga-zynq/rocket-chip/riscv-tools/riscv-fesvr/configure \
--host=arm-xilinx-linux-gnueabi && \
make libfesvr.so
checking build system type... x86_64-unknown-linux-gnu
checking host system type... arm-xilinx-linux-gnueabi
checking for arm-xilinx-linux-gnueabi-gcc... arm-xilinx-linux-gnueabi-gcc
checking whether the C compiler works... no
configure: error: in `fpga-zynq/common/build':
configure: error: C compiler cannot create executables
See `config.log' for more details

same error as following the lowRISC instructions. Now need to figure out the problem from the config.log file. The log file indicates several warnings for same thing:

fpga-zynq/rocket-chip/riscv-tools/riscv-fesvr/configure: line 2365: ~/SDK/2016.2/gnu/arm/lin/bin/arm-xilinx-linux-gnueabi-gcc: No such file or directory

The gcc compiler does exist, but file ./arm-xilinx-linux-gnueabi-gcc shows:
./arm-xilinx-linux-gnueabi-gcc: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), dynamically linked, interpreter /lib/ld-linux.so.2, for GNU/Linux 2.6.16, stripped

which means I need to enable 32bit support in WSL as I mentioned in Run Linux on Windows - WSL, by doing:

sudo dpkg --add-architecture i386
sudo apt-get update

sudo apt install gcc:i386 gcc-multilib g++-multilib libc6:i386

With that, finally I'm able to do make fesvr-zynq, fesvr-zynq and libfesvr.so would be generated under fpga-zynq/common/build folder. When copying fesvr-zynq, also need to copy common/build/libfesvr.so to /usr/local/lib on the board. As mentioned in above lowRISC instructions and fpga-zynq, it is possible to recreate the ram disk, however, I'm getting this when trying the commands under WSL: cpio: dev/console: Cannot mknod: Operation not supported. Not sure whether this is WSL limitation or something I have missed. Give up on this for now. So I tried to copy the new executable. For that, might need to get IP from dhcp server if the board is connected to a network. Modifying /etc/network/interfaces with line 'iface eth0 inet dhcp', then do 'ifdown eth0' and 'ifup eth0' will temporarily work as the change of the interfaces file won't survive of a reboot. After successfully get IP from dhcp server, ssh may still not work with error: Unable to negotiate with a.b.c.d port 22: no matching key exchange method found. Their offer: diffie-hellman-group1-sha1,diffie-hellman-group14-sha1. Can try tftp as:

cd ~

tftp -g -r fesvr-zynq tftp_server

cd /usr/local/lib

tftp -g -r libfesvr.so tftp_server

Now, run fesvr-zynq without argument would get usage print out (with the original fesvr-zynq executable, used to get "ERROR: No cores found" error, same error as running 'fesvr-zynq pk hello'), but still not able to load the bbl or run the hello code.

PS: README.md in fpga-zynq/rocket-chip/riscv-tools/fpga-fesvr shows:

This repository is deprecated; it has been absorbed into the Spike repository (https://github.com/riscv/riscv-isa-sim).

Use Blink Mini camera without Amazon subscription

2024-02-04T14:23:00.000-05:00

Blink Mini is a cheap camera. Auto detection is a bit awkward to me as it always detected change out of the region I set for motion detecting. And after one year, recording video stop working without subscription.

Luckily, there are Open Source solution, using Python, likely are all based off the documentation at: https://github.com/MattTW/BlinkMonitorProtocol:

1) https://pypi.org/project/blink-cameras/ I didn't try it as likely the development was paused since May 2019

2) https://pypi.org/project/blinkpy, github: https://github.com/fronzbot/blinkpy. This library was built with the intention of allowing easy communication with Blink camera systems, specifically to support the Blink component in homeassistant.

Following is note for using blinkpy.

The blinkpy github site has a brief introduction for how to use it. Information at the pypi.org page likely is out-of date, as module 'blinkpy' has no attribute 'Blink'.

When I try the example code from the Readme, I got this:

Unclosed client session
client_session: <aiohttp.client.ClientSession object at 0x00000201A7EE2310>
Unclosed connector
connections: ['[(<aiohttp.client_proto.ResponseHandler object at 0x00000201A7EE6040>, 57822.015)]', '[(<aiohttp.client_proto.ResponseHandler object at 0x00000201A7F22460>, 57822.593)]']
connector: <aiohttp.connector.TCPConnector object at 0x00000201A7EE2370>
Fatal error on SSL transport
protocol: <asyncio.sslproto.SSLProtocol object at 0x00000201A7EE2970>
transport: <_ProactorSocketTransport fd=844 read=<_OverlappedFuture cancelled>>
Traceback (most recent call last):
File "C:\miniconda3\lib\asyncio\sslproto.py", line 684, in _process_write_backlog
    self._transport.write(chunk)
File "C:\miniconda3\lib\asyncio\proactor_events.py", line 359, in write
    self._loop_writing(data=bytes(data))
File "C:\miniconda3\lib\asyncio\proactor_events.py", line 395, in _loop_writing
    self._write_fut = self._loop._proactor.send(self._sock, data)
AttributeError: 'NoneType' object has no attribute 'send'

Sounds like the connection isn't successfully established? Actually it isn't. I added more code to read the camera name and attribute, and all these information can be read back correctly before above error showing up. Likely, above error raised at the closing or exiting. As a comment for aiohttp issues 5941, loop._proactor is None means loop.close() was called before session.close() call.
This is incorrect; and not aiohttp problem.

RISC-v on ZC706 Evaluation Board - Part V: Running Petalinux

2024-01-29T13:29:00.009-05:00

Follow up on RISC-v on ZC706 Evaluation Board - Part IV: petalinux. As mentioned in the previous post, I didn't have tftp setup on my host PC. With 'BOOT.BIN' copied to SD card, when booting up the board, U-Boot will look for tftp server, and trying to download Linux image from there. I guess it is possible to copy the Linux image to the SD card and boot from there. But let's setup the tftp server, then it be more convenience to update the Linux image without the need to transfer image to the SD card, why not? It's also possible to run SCP on the ZC706 EV board to copy image to SD card.

It's very easy to setup tftp (Trivial File Transfer Protocol). Searching Internet may recommend tftp-hpa, which is an enhanced version of the BSD TFTP client and server. It possesses a number of bugfixes and enhancements over the original. May follow this to setup tftp backed by xinetd. If cannot update /etc/xinetd.d/tftp file, and 'sudo kill -HUP pid_of_inetd' doesn't help, then try 'sudo kill -9 pid_of_inetd'. Then restart xinetd with: sudo /etc/init.d/xinetd restart

There might be multiple tftp servers on the same subnet, so may need to specify the server on the ZC706 board. This can be done with cmd:

setenv serverip 192.168.1.117

Somehow, it still try to download from the other tftp server. So I tried to boot the image with QEMU:

source petalinux/settings.sh
petalinux-boot --qemu --prebuilt 2

It can boot to Linux, and will ask for login credential, and 'root/root' doesn't work. Per https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide/Login-Changes, the root account is disabled, The default user is petalinux and the password should be set on first boot. For me, using both 2 and 3 for prebuilt option will boot to Linux, but with 2, it will show more information for uboot boot.

Refer to QEMU User Documentation for how to use QEMU, such as:

To quit the emulation, press CTRL+A followed by X. To switch
between the serial port and the monitor, use CTRL+A followed by C.

Now, back to the UBoot with tftp, do a power cycle and press 'space' key within 3 seconds to pause UBoot. printenv shows:

arch=arm
baudrate=115200
board=zynq
board_name=zynq
boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
boot_efi_binary=load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootarm.efi; if fdt addr ${fdt_addr_r}; i
boot_efi_bootmgr=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr;fi
boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf}
boot_net_usb_start=usb start
boot_prefixes=/ /boot/
boot_script_dhcp=boot.scr.uimg
boot_scripts=boot.scr.uimg boot.scr
boot_syslinux_conf=extlinux/extlinux.conf
boot_targets=mmc0 jtag mmc0 mmc1 qspi nand nor usb0 usb1 pxe dhcp
bootcmd=run distro_bootcmd
bootcmd_dhcp=devtype=dhcp; run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;set;
bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;
bootcmd_mmc0=devnum=0; run mmc_boot
bootcmd_mmc1=devnum=1; run mmc_boot
bootcmd_nand=nand info && nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && echo NAND: Trying to boot script at ${;
bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && echo NOR: Trying to boot script at ${scriptaddr} && sou;
bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
bootcmd_qspi=sf probe 0 0 0 && sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && echo QSPI: Trying to boot script at;
bootcmd_usb0=devnum=0; run usb_boot
bootcmd_usb1=devnum=1; run usb_boot
bootcmd_usb_dfu0=setenv dfu_alt_info boot.scr ram $scriptaddr $script_size_f && dfu 0 ram 0 60 && echo DFU0: Trying to boot scr;
bootcmd_usb_dfu1=setenv dfu_alt_info boot.scr ram $scriptaddr $script_size_f && dfu 1 ram 1 60 && echo DFU1: Trying to boot scr;
bootcmd_usb_thor0=setenv dfu_alt_info boot.scr ram $scriptaddr $script_size_f && thordown 0 ram 0 && echo THOR0: Trying to boot;
bootcmd_usb_thor1=setenv dfu_alt_info boot.scr ram $scriptaddr $script_size_f && thordown 1 ram 1 && echo THOR1: Trying to boot;
bootdelay=2
bootfile=pxelinux.0
bootfstype=fat
bootm_low=0
bootm_size=30000000
cpu=armv7
dfu_alt_info=mmc 0:1=boot.bin fat 0 1;u-boot.img fat 0 1
distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
efi_dtb_prefixes=/ /dtb/ /dtb/current/
ethact=ethernet@e000b000
ethaddr=??:??:??:??:??:??
fdt_addr_r=0x1f00000
fdtcontroladdr=3eadf220
ipaddr=x.x.x.x
kernel_addr_r=0x2000000
load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
loadaddr=0x0
mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
modeboot=sdboot
pxefile_addr_r=0x2000000
ramdisk_addr_r=0x3100000
scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for;
scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_t
scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}e
scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefi
scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; te
script_offset_f=9c0000
script_offset_nor=0xE2FC0000
script_size_f=0x40000
scriptaddr=3000000
serverip=y.y.y.y
soc=zynq
stderr=serial@e0001000
stdin=serial@e0001000
stdout=serial@e0001000
ubifs_boot=env exists bootubipart || env set bootubipart UBI; env exists bootubivol || env set bootubivol boot; if ubi part ${bi
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
vendor=xilinx

ethaddr, ipaddr and serverip are all set valid value, somehow it will keep trying a different tftp server. With uboot paused, manually issue 'bootcmd' will make it able to load from the desired tftp server. May get lot of network error, but after multiple retries, it should be able to load pxelinux.0, rootfs.cpio.gz.u-boot, zImage, system.dtb, then start the kernel successfully. uname -a =>

Linux xilinx-zc706-2022_2 5.15.36-xilinx-v2022.2 #1 SMP PREEMPT Mon Oct 3 07:50:07 UTC 2022 armv7l GNU/Linux

So it is still running on the ARM core. Still need to figure out how to fix fesvr-zynq issue. Probably need to rebuild fesvr-zynq with petaliux SDK? Need to explore more.

RISC-v on ZC706 Evaluation Board - Part IV: petalinux

2023-12-20T14:34:00.011-05:00

One year ago (Dec 2022) I made two posts to try modelling RISC-v on ZC706:

Then later in this April I post RISC-v on ZC706 Evaluation Board - Part III to dive into generating FPGA bit stream with Vivado 2016.2. It is a bit success, but eventually still running into issue: "./fesvr-zynq pk hello" still get "ERROR: No cores found". As mentioned in the old post, likely that I need to setup PetaLinux. After several busy months, now I get some spare time to tackle this.

fesvr-zynq probably was built from rocket-chip/riscv-tools/riscv-fesvr, but per https://github.com/ucb-bar/fpga-zynq/issues/87, the issue likely is not coming from this binary:

zhemao commented Jul 9, 2018

Sorry, I forgot to update all the binaries in the uramdisk.image.gz.

Could you please try the files in the master branch of fpga-images-zedboard? I've tested them on my board and they seem to work. https://github.com/ucb-bar/fpga-images-zedboard.

But likely https://github.com/ucb-bar/fpga-images-zc706 not updated. So likely what I need is using PetaLinux tools to build this uramdisk.image.gz for fpga-images-zc706.

Since I haven't been touching the zc706 board for a while, also it is now connected to a new Linux host, let me refresh the whole thing for reproducing the problem. With zc706 UART connected to Linux, once power up the board, kernel log shows:

usb 2-10: new high-speed USB device number 7 using xhci_hcd
usb 2-10: New USB device found, idVendor=0403, idProduct=6014, bcdDevice= 9.00
usb 2-10: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 2-10: Product: Digilent USB Device
usb 2-10: Manufacturer: Digilent
usb 2-10: SerialNumber: 210251842966
ftdi_sio 2-10:1.0: FTDI USB Serial Device converter detected
usb 2-10: Detected FT232H
usb 2-10: FTDI USB Serial Device converter now attached to ttyUSB0

This ttyUSB0 likely is the Jtag. Per host kernel log ([ 5.208150] usb 4-4: cp210x converter now attached to ttyUSB1), the Uart over USB device ttyUSB1 is there no matter the zc706 board is powered on or off. To connect to the Uart, would need terminal like putty(needs XServer) or minicom(runs in shell). I take minicom as I'm connecting the host with ssh. Run: sudo minicom -s to setup serial port.

Once connected, it would prompt zynq login, use root/root which is default credential. If Ethernet cable is connected, then can use ssh to login the board, the default IP is 192.168.1.5 (refer to the fpga-zynq project page).

With the h/w environment ready, now let's start the PetaLinux adventure.

I have downloaded PetaLinux Tools Installer and ZC706 BSP from Xilinx site several months back. The site also provides common images for Embedded Vitis Platforms. And per note:The ‘common image’ packages contain a prebuilt Linux kernel and root file system that can be used with any Zynq™, Zynq™ MP or Versal board for embedded Vitis platform developers. These files need to be copied to an SD flash card along with the platform specific boot image (boot.bin) available from the Vitis™ Embedded Platform page. Also included is the ‘sysroot’ required for embedded Vitis platform application development. The sdk.sh script must to be used to setup the compressed Yocto Project SDK on a Linux development host properly...PetaLinux Tools installation is not necessary to use the common images. Licenses and sources used to create the common image content is provided. This is a bit confusing. Which do we really need? Regarding Vivado v.s. Vitis, Digilent has a page of explanation: Fundamentally, the differences are down to the perspective of the developer using the tool. Vivado offers a hardware-centric approach to designing hardware, while Vitis offers a software-centric approach to developing *both* hardware and software. Sounds like we don't need Vitis stuff?

To start the journey, I'm following UG1144 - PetaLinux Tools Documentation Reference Guide.

To setup working environment, run:

source <path-to-installed-PetaLinux>/settings.sh

To use PetaLinux SDK, run:

source <path-to-installed-PetaLinux>/components/yocto/buildtools/environment-setup-x86_64-petalinux-linux

The first is creating PetaLinux project with zc706 BSP:

petalinux-create -t project -s <path-to-bsp>

As the user guide said, using -p to specify the platform architecture, such as '-p arm' for Zynq and '-p aarch64' for Zynq UltraScale+ MPSoC, may save a little disk space. Also tftp server is preferred, Without a TFTP service, you cannot download Linux system images to the target system using the U-Boot network/TFTP capabilities. This can be ignored for other boot modes.

The user guide mentioned exporting hardware platform to PetaLinux project, which can be done from Vivado menu File=>Export=>Export Hardware=>choice of 'Pre-synthesis' and 'Include bitstream', no idea, so I selected the 2nd options to include more. This step generates rocketchip_wrapper.xsa file.

The user guide also mentioned creating project with template, I guess that is for complexity, since I already created project from BSP, I don't see a need of that.

Run 'petalinux-config --get-hw-description ../fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/rocketchip_wrapper.xsa' to launch system config. There is lot of setting, and likely can keep the default setting per the User Guide.

Run 'petalinux-build' to build images and it will take a while (will perform a lot of download as well), with 4232 tasks in my case.

The project folder will hold pre-built image once created, even before performing the build. Description of images can be found from the README under the root of the project. The build will generate new images to images/linux folder, such as: zynq_fsbl.elf, image.ub, zImage, uImage, u-boot.elf, system.dtb, and rootfs.tar.gz, which might be the replacement of uramdisk.image.gz? The fpga-zynq project zc706/fpga-images-zc706 contains files as:
boot.bif
boot.bin
devicetree.dtb
uImage
uramdisk.image.gz
boot_image
|-FSBL.elf
|-rocketchip_wrapper.bit
|-u-boot.elf

So the boot_image folder contains FSBL, FPGA bitstream and U-Boot.

The uramdisk.image.gz seems is not a normal gzip archive as I cannot open it with 7-zip, therefore cannot confirm whether it is rootfs.tar.gz from the build. Following https://xilinx.github.io/Embedded-Design-Tutorials/docs/2022.1/build/html/docs/Introduction/Zynq7000-EDT/4-linux-for-zynq.html, I packed the boot.bin with following:

cd images/linux

petalinux-package --boot --fsbl zynq_fsbl.elf --fpga system.bit --u-boot u-boot.elf

Then copy the generated "BOOT.BIN" to SD card, yes, the name is all in capital.

Some Acronym for PetaLinux:

FSBL: First Stage BootLoader

PMU: Platform Management Unit, manage and perform the multi-staged booting process

TF-A: Trust Firmware-A, a transparent bare-metal application layer executed in Exception Level 3 (EL3) on the APU.

BIF: Bootgen Image Format

APU: Application Processing Unit

RPU: Realtime Processing Unit

MCS: might stand for Intel Micro Computer Set, which is file ext name for Intel Hex (refer to wikipedia)

Developing code with WSL: 2 - Install docker

2023-09-02T13:41:00.008-04:00

(continue of Developing code with WSL: 1 - Common problem)

The easy way to try docker with WSL would be installing Docker Desktop on host Windows. Some detail can be found from Microsoft tutorial site: Get started with Docker containers on WSL | Microsoft Learn. But if you prefer to decouple Docker with the host OS, just want to install everything under WSL, you can following Docker Linux installation instruction to just install Docker engine, such as instruction here: https://docs.docker.com/engine/install/ubuntu/#install-using-the-repository.

When run ~$ docker run hello-world, might get this:

docker: Cannot connect to the Docker daemon at unix:///var/run/docker.sock. Is the docker daemon running?.

See 'docker run --help'.

If google this, may see this got asked on Stack Overflow: ubuntu - docker：Cannot connect to the Docker daemon at unix:///var/run/docker.sock. Is the docker daemon running?

The suggestion there is run: systemctl start docker && systemctl enable docker. Then may get another error message:

System has not been booted with systemd as init system (PID 1). Can't operate. Failed to connect to bus: Host is down

This is due to limitation of older version of WSL which does not support systemd, or systemd flag has not been set in WSL setting. In that case, try: sudo service docker start. Systemd is supported with WSL version 0.67.6 or newer(reference from Microsoft: Systemd support is now available in WSL! - Windows Command Line). As the link mentioned, if checking WSL version with 'wsl --version' failed, it means you are running the in-Windows version of WSL and need to upgrade to the Store version.

To enable systemd:You will need to edit the wsl.conf file to ensure systemd starts up on boot.Add these lines to the /etc/wsl.conf with sudo:

[boot]
systemd=true

With that, run ~$ docker run hello-world would get this:

~$ sudo docker run hello-world
Unable to find image 'hello-world:latest' locally
latest: Pulling from library/hello-world
719385e32844: Pull complete
Digest: sha256:dcba6daec718f547568c562956fa47e1b03673dd010fe6ee58ca806767031d1c
Status: Downloaded newer image for hello-world:latest

Hello from Docker!
This message shows that your installation appears to be working correctly.

If you prefer not to use 'sudo' for docker operation, may refer to this 'Ask Ubuntu' post. It works for docker 0.5.3 and up. Basically you would need to add the desired user to 'docker' group, like this:

sudo gpasswd -a $USER docker

Then re-login this user if it is the current user. For WSL, you can run 'logout' and you will automatically get re-login. After login, should be able to run docker command without 'sudo'.

Developing code with WSL: 1 - Common problem

2023-09-02T13:38:00.007-04:00

<WIP>

The two things Microsoft did recent years I would give a thumb up are WSL and VisualStudio Code. Both are gaining a lot of attraction along all software developers, I believe. Now, I'd like to make some note with WSL first. I had talked about WSL before, as:
Feb 2019: Running Linux on Windows

Jun 2020: Windows10 运行Ubuntu - WSL2

I'm going to create multiple post for what I learned while using WSL. This first one would be some common tips.

Accessing files cross host Windows and WSL filesystem

share folder: /mnt/c

running windows application

share git: cache issue

If user frequently or occasionally would switch between Windows and WSL, and run git command, may see that git will refresh index. As explained from this stackoverflow post:

The thing you're using here, which Git variously calls the index, the staging area, or the cache, does in fact contain cache data.
The cache data that it contains is the result of system calls.
The system call data returned by a Linux system is different from the system call data returned by a Windows system.

Especially if have VS-Code installed on Windows, and w/o using WSL extension to access the repo, VS-Code will run the windows native git.exe with the GitLens extension.

Another thing user may need to consider is: under WSL, the host Windows' git.exe is faster than the WSL linux git. So a simple and efficient solution would be set an alias by adding one line in ~/.bashrc file with:

alias git=git.exe

With this, under WSL it will always invoke the Windows git.exe for fetching the index. It's faster, no refresh when switch between Windows and WSL Linux. A side note is this won't work for tcl/expect which is used by the autobld script. This probably is due to the way how WSL is handling running navtive Windows app under WSL. For that, we can take the other approach mentioned in the same stackoverflow post: set environment variable of GIT_INDEX_FILE

Makefile : Clock skew detected

Makefile : Clock skew detected - Stack Overflow, this is not the case for WSL build. In fact: WSL2 Clock is out of sync with Windows - Stack Overflow. Another easy way to get around this is: close all WSL session, then from a console, issue: wsl --shutdown. Then open a new WSL session, it will automatically sync the time with Windows host.

GUI: Windows 11, or MobaXterm and 32 bit/64bit executable

Refer to Run Linux on Windows - WSL

RISC-v on ZC706 EVB - Part III: build w/ Win11/WSL2/Vivado 2016.2

2023-04-06T17:50:00.010-04:00

Continue my journey with of RISC-v on ZC706 Evaluation Board - Part II. Finally get some spare time can back on this. Since it may need some effort to get PetaLinux setup and debug the executable issue, I changed my focus to setup Vivado 2016.2 on another Windows 11 + WSL2 PC. Luckily Xilinx_Vivado_SDK_2016.2_0605_1.tar.gz is just around 11.1GB, even much smaller than 2016.4 package. And I chose WSL2 as on Windows 11 it support GUI, and would be less hassle do the build under Linux. However, I do run into several problem with fresh installed WSL2:

Got 'libawt_xawt.so: libXrender.so.1: cannot open shared object file: No such file or directory' when running Vivado xsetup to install Vivado. Search from internet shows I need to do "sudo apt-get install libxrender1" , and that did work. Then hit next issue as below:
Got 'libawt_xawt.so: libXtst.so.6: cannot open shared object file: No such file or directory', turns out that I need do 'sudo apt install libxtst6'. Then next issue:
Got 'libawt_xawt.so: libXi.so.6: cannot open shared object file: No such file or directory', need to do "sudo apt install libxi6"

With that, xsetup is up and running. For installing option, I selected Vivado HL Design Edition as the WebPACK one might not have all features I need, and I don't need DSP support (for choices, may refer to Xilinx 2016.4 WebPACK Vivado and SDK Install on Windows 7 SP1 (css-techhelp.com) for more detail). Then the installation stuck with the flash screen for quite long time, which made me doubt whether it hanged or crashed. Luckily, it is not. After a while, the install option diag shows up, and I can select and continue the installation. At beginning I checked the option for creating Desktop shortcut, but not sure where it will go as I don't have Ubuntu Desktop installed. The installation not proceeding after a while, with log file name showed in console. By checking the log, likely there is issue with the shortcut. So re-run the installer, this time, not select the shortcut and create group box, however, installer still hangs, and log file shows it probably is running tcl script for generating the device list:

Executing script Generating installed device list: /home/Suser/Vivado/2016.2/bin/vivado [-nolog, -nojournal, -mode, batch, -source, /home/$user/.xinstall/Vivado_2016.2/scripts/xlpartinfo.tcl, -tclargs, /home/$user/Vivado/2016.2/data/parts/installed_devices.txt]
Tried 'sudo apt install tcl' but doesn't help. If manually run about line, will get:
application-specific initialization failed: couldn't load file "librdi_commontasks.so": libncurses.so.5: cannot open shared object file: No such file or directory

Per this link, need to do: sudo apt install libncurses5

With that, I successfully installed Vivado 2016.2 under WSL. Then I start to pull fpga-zynq.git and build with it as described in fpga-zynq: 2) Pushing your rocket modifications to the FPGA, steps as:

Start WSL Ubuntu terminal
git clone https://github.com/ucb-bar/fpga-zynq.git to /mnt/c/workspace which can be easily accessed from Windows
Run sudo apt install openjdk-8-jdk-headless; sudo update-alternatives --install "/usr/bin/java" "java" "/usr/lib/jvm/java-8-openjdk-amd64/bin/java" 1
There is a strange thing happened. To install JDK8 under WSL, sometime would need to do sudo apt update, but somehow WSL give me an error as: "Release file for http://archive.ubuntu.com/ubuntu/dists/jammy-updates/InRelease is not valid yet (invalid for another 1d 3h 20min 52s). Updates for this repository will not be applied.". https://itsfoss.com/fix-repository-not-valid-yet-error-ubuntu/ gives me a clue on this: my WSL clock is skewed for some reason and it is lagged more than 1 day. So have to issue 'wsl --shutdown' then restart WSL to fix the problem
For fresh WSL, would need do: sudo apt install make
cd to git repo zc706 subfolder, run:
```
make init-submodules
```
Run below command, may get a lot of warn and error related to sbt, probably just ignore them:
```
make rocket
```
If see Cannot run program "dtc", do: sudo apt install device-tree-compiler
Once 'make rocket' successfully completed, run Vivado setting script in the installation path such as: source ~/Vivado/2016.2/settings64.sh
run make project, and soon will see something like 'Wrote : </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>' at the end. 'system.bd' is folder contains system folder.
Now run
```
make fpga-images-zc706/boot.bin
```
will see output like:

Successfully read diagram <system> from BD file </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>

Verilog Output written to : /mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
WARNING: [xilinx.com:ip:processing_system7:5.5-1] system_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0

...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7z045'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7z045'
3 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
INFO: [Common 17-206] Exiting Vivado at Fri Apr 7 19:48:34 2023...
[Fri Apr 7 19:48:34 2023] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:28 . Memory (MB): peak = 1186.469 ; gain = 0.000 ; free physical = 241 ; free virtual = 1777
# launch_runs impl_1 -to_step write_bitstream
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.
...

Likely would need a license to run synth and impl. As mentioned at https://dzone.com/articles/create-a-bootbin-program-an-sd-card-and-boot-a-zc7, The ZC706 has an XC7Z045-2FFG900 C SoC. This chip is not supported in WebPACK (see [link]) like the chip on the ZC702. You can get a 30-day license at [link].

Next, might see 'bootgen: command not found'. This could happen if user didn't run the Xilinx Vivado settings64.sh shell script, or XiLinx SDK wasn't installed. If the SDK is installed, bootgen should be available under Vivado/2016.2/bin folder. Without SDK, make boot.bin would fail. So need to select SDK during installation as below (I only select Zynq-7000 to save space and installing time. Also, not select Acquire or Manage a License Key as I will deal with that separately):

If already have Vivado installed, then it won't allow you to re-install at same location. Would need to launch Vivado, then goto help->Add Design Tools or Devices...->Check SDK and click install.

After all this, finally can successfully build the boot.bin. With this boot.bin copied to SD card, it can successfully boot the PetaLinux (connect the Uart USB, and use root/root to login). But running "./fesvr-zynq pk hello" still get "ERROR: No cores found".

Also tried following the prompted message for the problem 5 mentioned in Risc-v on zc706 evaluation board - Part I: ERROR: [BD_TCL-109] This script was generated using Vivado <2016.2> and is being run in <2022.1> of Vivado. Please run the script in Vivado <2016.2> then open the design in Vivado <2022.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.

I opened the project file zc706_rocketchip_ZynqFPGAConfig.xpr created by 2016.2 Vivado with 2022.1 Vivado, and keep the project as Read-only while the new version Vivado prompt for choice. It would still treat the board type as error:

[Board 49-67] The board_part definition was not found for xilinx.com:zc706:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

For this, no need to update update zc706/src/tcl/zc706_rocketchip_ZynqFPGAConfig.tcl, but update the project xpr file directly as it is XML format, just update <Option Name="BoardPart" Val="xilinx.com:zc706:part0:1.0"/> to xilinx.com:zc706:part0:1.4. For above update instruction, I cannot find 'write_bd_tcl' script, but did find there is a man doc as Vivado/2022.1/doc/eng/man/write_bd_tcl. And 'Report IP' now is under menu/Report but not Tools. Open the Tcl Console (menu/Window->Tcl Console), issue command write_bd_tcl with output filename. It may prompt: ERROR: [BD 5-229] Please open or create a block design first. So need to select from left Flow Navigator->IP INTEGRATOR-> Open Block Design before running the write_bd_tcl command.

CodeFormer: AI Face Enhancement, 图片人脸智能增强

2023-03-04T20:50:00.005-05:00

最近看到这个由周尚长博士领队的几位南洋理工大学S-Lab成员开发的开源程序，用来恢复和增强照片中的人脸，效果惊人。可以点进以下3分半的you-tube看一下就知我所言不虚(包括1927 Fifth Solvay International Conference群英会的照片)。

Face Restoration

Face Color Enhancement and Restoration

Face Inpainting

https://shangchenzhou.com/projects/CodeFormer/ 是项目主页，有些简单介绍。code的github网址是：https://github.com/sczhou/CodeFormer，附有简单的安装使用说明，除了要git clone代码，和下载样本数据外，主要是要设置conda。关于conda, 可参见：学习TensorFlow - 设置Python环境。Miniconda就足够了（参见https://stackoverflow.com/questions/45421163/anaconda-vs-miniconda）

注意，CUDA不是必须的，像我的电脑是AMD APU，不支持nVida的CUDA，也可以完美的运行CodeFormer。

当你用CodeFormer转化自己的照片时，最初可能并不会注意到转化后的照片有什么不一样，记住，一定要zoom in，放大再放大，看细节,一定有惊喜。

除了增强照片，Codeformer还支持video的人脸增强(需要引入FFMpeg)。有空要研究研究怎样加入AMD ROMc的支持，加快在我的AMD计算机上的处理速度。

Setup ssh tunnel/port forward on Windows

2023-01-04T11:59:00.006-05:00

Reference link:

https://docs.oracle.com/cd/E24628_01/install.121/e22624/preinstall_req_cygwin_ssh.htm

https://linuxize.com/post/how-to-setup-ssh-tunneling/

Make sure for Cygwin, has openssh installed. Then run

ssh-host-config

*** Query: Enter the value of CYGWIN for the daemon: [] binmode ntsec

Then run this to start the service: cygrunsrv -S sshd

May need to change Windows firewall setting to open the port 22.

SSH tunneling or SSH port forwarding is a method of creating an encrypted SSH connection between a client and a server machine through which services ports can be relayed.

There are three types of SSH port forwarding:

Local Port Forwarding. - Forwards a connection from the client host to the SSH server host and then to the destination host port.
Remote Port Forwarding. - Forwards a port from the server host to the client host and then to the destination host port.
Dynamic Port Forwarding. - Creates a SOCKS proxy server that allows communication across a range of ports.

RISC-v on ZC706 Evaluation Board - Part II

2022-12-30T15:35:00.005-05:00

With RISC-v on ZC706 Evaluation Board - Part I, I was successfully building the boot.bin. I thought I got the work done, but realized it was not when I tried the binary I made: after replaced the 'boot.bin' on the SD card with the one I built, the Init LED turns to green for about 1 second, then turns to red, no output from UART port, so something is wrong. Actually there is a warning while making the boot.bin:

[WARNING]: Partition FSBL.elf.0 range is overlapped with partition rocketchip_wrapper.bit.0 memory range
[INFO] : Bootimage generated successfully

Would need to check the partition layout.

Beside this problem, I'm seeing another issue when playing more, with the fetched SD binaries: running "./fesvr-zynq pk hello" got "ERROR: No cores found", same error for any command with fesvr-zynq. Search the symptom returned same issue:

https://github.com/chipsalliance/rocket-chip/issues/1390

https://github.com/ucb-bar/fpga-zynq/issues/87

Likely there is an update for zedboard but not for zc706. So likely will have to build this fesvr-zynq by myself. Run 'make fesvr-zynq' lead me realized that all sub-modules of rocket-chip/riscv-tools didn't get cloned, especially 'riscv-fesvr' which is needed for making fesvr-zynq. With that repo cloned, the build did make some progress, but eventually would complain cannot find 'arm-xilinx-linux-gnueabi-g++'. Though I did find the executable under Xilinx Vitis, running environment setup script, or even adding the path of the executable won't help, as it needs the PetaLinux build environment, which seems hasn't been fully integrated to Xilinx Vitis. Have to download PetaLinux Tools from Xilinx site.

Will update this once get some progress on this.

Below is quoted from https://github.com/ucb-bar/fpga-zynq

Overview of System Stack

Our system will allow you to run a RISC-V binary on a rocket core instantiated on a supported Zynq FPGA. This section will outline the stack of all of the parts involved and by proxy, outline the rest of the documentation. Going top-down from the RISC-V binary to the development system:

Target Application (RISC-V binary) will run on top of whatever kernel the rocket chip is running. Compiled by riscv-gcc or riscv-llvm.

RISC-V Kernel (proxy kernel or RISC-V Linux) runs on top of the rocket chip. The proxy kernel is extremely lightweight and designed to be used with a single binary linked against Newlib while RISC-V Linux is appropriate for everything else.

Rocket Chip (rocket core with L1 instruction and data caches) is instantiated on the FPGA. Many of its structures will typically map to various hard blocks including BRAMs and DSP slices. It communicates to the host ARM core on the Zynq via AXI.

Front-end Server (riscv-fesvr) runs on the host ARM core and provides an interface to the rocket chip running on the FPGA (connected via AXI).

Zynq ARM Core (actually dual Cortex A9) runs Linux and simplifies interfacing with the FPGA.

FPGA Board (Zybo, Zedboard, or ZC706) contains the Zynq FPGA and several I/O devices. At power on, the contents of the SD card are used to configure the FPGA and boot Linux on the ARM core.

External Communication (TTY over serial on USB or telnet/ssh over ethernet) allows the development system to communicate with the FPGA board.

Development System (PC with SD card reader) generates the images to configure the FPGA.

RISC-v on ZC706 Evaluation Board - Part I

2022-12-27T15:23:00.008-05:00

Continue my journey with RISC-v on FPGA. This time, I got a Xilinx Zynq-7000 SoC ZC706 Evaluation kit. The board is at least 7 years old. The FPGA has two Cortex-a9 cores. And there is https://github.com/ucb-bar/fpga-zynq which has everything needed to get RISC-v running on several Zynq FPGA boards, including ZC706. Again, this project has no update for more than four years now, so can foresee something might be out-of-date. Making this blog just for reference.

The fpga-zynq github repo has pretty good documentation. It's very easy to follow the Quick Instruction, just fetch images and load them to SD card. Setup the boot mode of the board, and all done. The only issue I had run into is related to the SD card. There are several links for FPGA boot from SD issue, like https://support.xilinx.com/s/question/0D52E00006hpPfLSAU/sd-card-boot-problems-zc706-board and https://support.xilinx.com/s/article/59476. In general, need to make sure all needed files are properly copied to SD card. For my case, the SD card reader I used first has some weird issue. After I used a newer SD card reader, everything goes very smoothly.

For the 2nd step, pushing Rocket modification to FPGA, I got several problems.

Problem 1: the instruction mentioned user can pick own rocket-chip directory by override ROCKET_DIR. Since the freedom repo for Arty A7 contains rocket-chip repo, I was thinking to re-use that to reduce the time and disk usage. However, the 'make rocket' command will run into this error:

module not found: edu.berkeley.cs#chisel3_2.12;3.2-SNAPSHOT

The error is like https://github.com/ucb-bar/chiseltest/issues/72 and edu.berkeley.cs#chisel_2.11;3.1-SNAPSHOT: not found · Issue #518 · chipsalliance/chisel3 · GitHub. One post mentioned need to update the dependency from chisel2 to chisel3. I cannot figure out a quick way to get around this, so gave up on this. Instead, remove the setting of ROCKET_DIR. 'make init-submodules' will download rocket_chip repo, and the not found of edu.berkeley.cs:chisel3_2.12:3.3-SNAPSHOT is gone.

Problem 2: 'make rocket' successfully created rocket_chip.stamp file, but reported no rule to make testchipip.stamp. This is a weird one, as the Makefile and common/Makefrag file does not have testchipip.stamp as target. Turns out due to the line-ending of generate-pkg-mk.sh file, the shell script failed to finish some work which leads to issue for EXTRA_PACKAGES=testchipip. One problem is the make command line doesn't generate meaningful message pointing to the shell script problem. I figured out that by turning on -d option for make, and run the script manually. For fixing this, do: "git config --global core.autocrlf false" then do git checkout to apply the setting.
Problem 3: Seeing error
```
Missing dependency 'object java.lang.Object in compiler mirror', 
required by /.m2/repository/org/scala-lang/scala-library/2.10.4/scala-library-2.10.4.jar(scala/package.class)
```
JDK version not compatible with scala. As replied for https://stackoverflow.com/questions/53942248/maven-error-missing-dependency-java-lang-object-required-by-scala, each version of scala only works with certain version of JDK (refer to docs.scala-lang.org/overviews/jdk-compatibility/overview.html). For this case, have to stick with JDK8:

sudo apt install openjdk-8-jdk-headless
sudo update-alternatives --install "/usr/bin/java" "java" "/usr/lib/jvm/java-8-openjdk-amd64/bin/java" 1

sudo update-alternatives --config java

Problem 4: "make project" will need to invoke Vivado. On Windows, this can be achieved by running under Cygwin with Vivado executable added to PATH. However, on both Windows and Linux, I'm seeing same error as:
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:zc706:part0:1.0. The project's board_part property was not set, but the project's part property was set to xc7z045ffg900-2. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
Per this, this and this, as the instruction/repo is for Vivado 2016 but I'm using 2022 version, would need to update the tcl script for creating Vivado project, modify the line like this:
1. set_property board_part xilinx.com:zcu102:part0:3.0 [current_project]
to: xilinx.com:zcu102:part0:3.1
For my case, would need to update zc706/src/tcl/zc706_rocketchip_ZynqFPGAConfig.tcl, which has line as: set_property "board_part" "xilinx.com:zc706:part0:1.0" $obj
Run get_board_parts within the tcl console shows xilinx.com:zc706:part0:1.4. So update the tcl script, run "rm -rf zc706_rocketchip_ZynqFPGAConfig" first, then run "make project" again.
Then run into problem 5:
ERROR: [BD_TCL-109] This script was generated using Vivado <2016.2> and is being run in <2022.1> of Vivado. Please run the script in Vivado <2016.2> then open the design in Vivado <2022.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
This error is from zc706/src/tcl/zc706_bd.tcl. With 2022.1, "Report" is a separate menu item beside tools, and it only shows up after a project is opened. Really don't want to spend hours to install the 2016.2 version. So I just modified the zc706_bd.tcl to set the version as 2022.1 which matches the version I'm using. With that, there is some critical warning, like this: "CRITICAL WARNING: [BD 41-737] Cannot set the parameter PCW_M_AXI_GP0_FREQMHZ on /processing_system7_0. It is read-only.", but the project (.xpr) file did get created successfully.

Run "make fpga-images-zc706/boot.bin" will do synthesis and implementation with the project. This somehow not working for me, because of the bit file is missing. Likely this is due to my Vivado installation does not have valid license for creating bit for zynq. Opened the project from Vivado which has valid license, and generate bit file there. It got successfully generated on both Linux and Windows Vivado. However, when run "make fpga-images-zc706/boot.bin" again, the boot.bin would be successfully generated on Linux but not on Windows. Error for Windows/Cygwin run is like this:
ln -sf ../../zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.runs/impl_1/rocketchip_wrapper.bit fpga-images-zc706/boot_image/rocketchip_wrapper.bit
cd fpga-images-zc706; bootgen -image boot.bif -w -o boot.bin
...
[ERROR] : Cannot read BIT file - boot_image/rocketchip_wrapper.bit
The bit file under impl_1 did exist, however, 'ln -sf' may create a junction point on NTFS, which might not work for Xilinx Windows bootgen. To get around this, delete the symbolic link, copy the bit file directly to fpga-images-zc706/boot_image folder, then CD to fpga-images-zc706 folder, and run "bootgen -image boot.bif -w -o boot.bin" directly (don't try the make command, as it will create the soft symbolic link again), and this works under Cygwin.

So finally I got the binary built on both Linux and Windows/Cygwin. Lesson learned is: for FPGA development, better do everything on Linux but not Windows: too many hassle.

At this point, I thought I had it completed, but in fact, it is not. So <to be continue>

Program Arty A7 FPGA to be a RISC-V processor - Part IV

2022-12-01T18:01:00.004-05:00

So still fighting with the "ERROR: [Synth 8-439] module 'BootROM' not found" issue. More internet search did bring back a clue from https://github.com/sifive/freedom/issues/34, richardxia commented Sep 27, 2017: BootROM uses Chisel's sequential memory feature, so it does not refer to an existing Verilog module. You will need to use the vlsi_rom_gen script from rocket-chip to generate the Verilog file from the ROM parameters. See our Makefile rule for handling this: freedom/bootrom/xip/Makefile, Line 38 in 22ee433: $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@

But, it didn't explain how this is invoked during the build. In the Makefile it has a line as:

export BOOTROM_DIR := $(base_dir)/bootrom/xip

In common.mk, target 'romgen' would run make under $BOOTROM_DIR, and target 'bit' is depends on 'romgen', and target 'mcs' is depends on 'bit'. So it should be built while run make ... mcs. So I did a clean build with log captured, and found build error as:

java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp /mnt/ext4/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar firrtl.Driver -i /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir -o /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v -X verilog
OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0
Total FIRRTL Compile Time: 55117.1 ms
make -C /mnt/ext4/freedom/bootrom/xip romgen
make[1]: Entering directory '/mnt/ext4/freedom/bootrom/xip'
dtc -I dts -O dtb -o /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dtb /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dts
/mnt/ext4/riscv/bin/riscv64-unknown-elf-gcc -march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"/mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dtb"' -static -nostdlib -o /mnt/ext4/freedom/builds/e300artydevkit/xip.elf xip.S
/mnt/ext4/riscv/bin/riscv64-unknown-elf-objcopy -O binary /mnt/ext4/freedom/builds/e300artydevkit/xip.elf /mnt/ext4/freedom/builds/e300artydevkit/xip.bin
od -t x4 -An -w4 -v /mnt/ext4/freedom/builds/e300artydevkit/xip.bin > /mnt/ext4/freedom/builds/e300artydevkit/xip.hex
/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.conf /mnt/ext4/freedom/builds/e300artydevkit/xip.hex > /mnt/ext4/freedom/builds/e300artydevkit/rom.v
Traceback (most recent call last):
File "/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen", line 90, in iterate_by_n
    batch += (next(it),)
StopIteration

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
File "/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen", line 138, in <module>
    main()
File "/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen", line 134, in main
    **parse_line(line))
File "/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen", line 113, in parse_line
    kwargs = {key: try_cast_int(val)
File "/mnt/ext4/freedom/rocket-chip/scripts/vlsi_rom_gen", line 113, in <dictcomp>
    kwargs = {key: try_cast_int(val)
RuntimeError: generator raised StopIteration
make[1]: *** [Makefile:38: /mnt/ext4/freedom/builds/e300artydevkit/rom.v] Error 1
make[1]: Leaving directory '/mnt/ext4/freedom/bootrom/xip'
make: *** [common.mk:68: /mnt/ext4/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.v] Error 2

And if re-run the make command, the error would be hidden, might because of rom.v file was already generated, even it was error out for previous make run. To fix that, as mentioned https://github.com/chipsalliance/rocket-chip/issues/1991, need to update rocket-chip/scripts/vlsi_rom_gen line 97, replace 'raise' with 'return', then re-do a clean build. Eventually now it is moving forward. And make .. mcs will have the bit file generated. The bit file was generated under builds/e300artydevkit/obj/ folder. And Vivado project file is also available under builds/e300artydevkit, as E300ArtyDevKitFPGAChip.xpr. It can be opened with Vivado, to view all the settings.

Program Arty A7 FPGA to be a RISC-V processor - Part III

2022-11-23T15:25:00.008-05:00

Since having lot of problem to follow https://digilent.com/reference/programmable-logic/arty-a7/reference-manual instruction on Windows/WSL/Cygwin, so I moved to do that on Linux/Ubuntu. Most thing goes smoothly. Do need to update several .gitmodules file to get everything synced, i.e. replace git://github.com to https://github.com.

When start to build the toolchain, I hit the first problem is while building riscv-openocd:

Multiple definitions of bitbang_swd originating from jtag/drivers/bitbang.h

Per https://github.com/riscv/riscv-openocd/issues/480, this likely is due to newer GCC 10+ which defaulting to -fno-common. I'm using GCC 11.3.0. So just as suggested, add the 'extern' keyword in front of the const swd_driver struct in bitbang.h.

Then hit this one for compiling riscv-fesvr ../fesvr/dtm.cc:

'runtime_error' is not a member of std

According to https://github.com/Azure/azure-storage-fuse/issues/421, it may relate to g++ version: According to https://en.cppreference.com/w/cpp/error/runtime_error, the include should not be exception.h but <stdexcept>. So the fix is adding #include <stdexcept> to dtm.cc.

Similar need to be done for riscv-isa-sim/riscv/devices.h.

With that, the toolchain build is OK. And make for verilog is done without any issue. However, when run

make -f Makefile.e300artydevkit mcs

Seeing this: ERROR: [Synth 8-439] module 'BootROM' not found [/path_of_freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v:242627]

Make -f Makefile.e300artydevkit mcs fails - module BootRom not found · Issue #96 · sifive/freedom · GitHub someone says re-sync repo solved the problem for him. My Vivado is 2022.1 build, and Digilent's instruction is using 2017 build. Hopefully the new version Vivado is not the problem.

By looking into the make log (there is log file under builds folder), the BootROM module is referenced in the .v file, which is coming from the .fir file as 'extmodule BootROM'. So likely a dependency is missing.

Then I went back to check files in the repo, and noticed in the root README.md, it mentioned two things:

As of March 1 2021, SiFive is archiving the freedom repository. The code here is not being actively maintained, and we can't continue to provide updates while the fpga boards, software ecosystems and other dependencies change.

Install sbt, varilator (probably typo of verilator) and scala which are required for building from Chisel

Per https://www.chisel-lang.org/: The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.

sbt home site: https://www.scala-sbt.org/. Per Wikipedia:

sbt is an open-source build tool for Scala and Java projects, similar to Apache's Maven and Gradle.

And the keyword extmodule is from Chisel. So likely, would need to install them as the README said. The instruction for installing sbt might need to be updated as it doesn't work with new Ubuntu. Refer to https://www.scala-sbt.org/download.html. Not sure why the README.md specified verilator_3_922. Ubuntu has this package, so I run sudo apt install verilator directly, same for scala.

With that, now running make mcs will ask for python. I installed python-is-python3 package, and now seeing a new error, same as described as https://github.com/chipsalliance/rocket-chip/issues/1991:

Traceback (most recent call last):
  File "rocket-chip/scripts/vlsi_rom_gen", line 90, in iterate_by_n
    batch += (next(it),)
StopIteration

As the ticket said, most likely due to I had Python3 but not Python (2.7) installed. Interestingly, the problem is gone after 2nd run of make, and then back to the no BootROM module issue.

Will chasing down the cause. <to be continue>

Program Arty A7 FPGA to be a RISC-V processor - Part II

2022-11-23T11:37:00.004-05:00

When I started on this journey by following instruction from https://digilent.com/reference/programmable-logic/arty-a7/start, I installed Xilinx Vivado on Windows PC as that is the primary working environment. Then when I started building RISC-v, I realized the instruction is all Linux oriented, so I decided to use WSL2 environment to build. The toolchain was successfully built. "make -f Makefile.e300artydevkit verilog" is also OK. But running into problem with "make -f Makefile.e300artydevkit mcs" runs into problem, as it needs to invoke vivado, which I haven't installed, and do not plan to install it under WSL2, simply because it takes too much disk space, and I'm not sure the sure the GUI would work well under WSL2.

Farther looking into the print out from the make mcs output, turns out it is running this from common.mk:

bit := $(BUILD_DIR)/obj/$(MODEL).bit
$(bit): $(romgen) $(f)
        cd $(BUILD_DIR); vivado \
                -nojournal -mode batch \
                -source $(fpga_common_script_dir)/vivado.tcl \
                -tclargs \
                -top-module "$(MODEL)" \
                -F "$(f)" \
                -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
                -board "$(BOARD)"

# Build .mcs
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
$(mcs): $(bit)
        cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
So it is possible to utilize the Vivado Windows installation, either still do the make under WSL2, or run the make with GNU shell under Windows (such as Cygwin).

Approach A: Run make under WSL2, install missing Vivado Linux executable

For Windows Vivado installation, it also include Linux vivado shell script under the bin folder. So would need to add the path to the bin like below:

export PATH=$PATH:/mnt/c/Xilinx/Vivado/2022.1/bin

However, Windows Vivado installation won't have Linux executable installed. Would see error like:

WARNING: /mnt/c/Xilinx/Vivado/2022.1/tps/lnx64/jre11.0.11_9 does not exist.
ERROR: Could not find 64-bit executable.
ERROR: /mnt/c/Xilinx/Vivado/2022.1/bin/unwrapped/lnx64.o/vivado does not exist
So would need to extract these missing binaries from installation package.

Approach B: Run make using Cygwin

My freedom.git was synced to my WSL2 home folder. So first thing is find out the Windows path to it. Information can be found from https://superuser.com/questions/1185033/what-is-the-home-directory-on-windows-subsystem-for-linux. For my WSL2 installed on Windows 11, under %LOCALAPPDATA%\Packages\Packages\CanonicalGroupLimited.UbuntuonWindows_79rhkp1fndgsc\LocalState is only a 'ext4.vhdx' file, which likely is a virtual disk file. So the way to access it from Cygwin would be map it as a driver, with command like this: net use U: \\wsl.localhost\Ubuntu

Then from Cygwin, cd U: should change CWD to the root dir of WSL2 Ubuntu. However, the make command might still fail with error like this:

Sourcing tcl script 'C:/Users/$win_user/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source /cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl
couldn't read file "/cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl": no such file or directory

To get around this, I moved the freedom folder to be under /mnt/c, which is the Windows C: drive. And this time, it gave me a new error when running make under Cygwin:

Cannot find a jar file even the file exist. So for now, give up on this, until later have some time. Probably can do that directly from Vivado?

Program Arty A7 FPGA to be a RISC-V processor - Part I

2022-10-19T23:18:00.020-04:00

This is a note for things encounter while following instruction to program a Digilent Arty A7 board as RISC-V core. As https://digilent.com/reference/programmable-logic/arty-a7/reference-manual described: The Arty A7, formerly known as the Arty, is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx.

https://digilent.com/reference/programmable-logic/arty-a7/start has tutorials Installing Vivado, Vitis, and Digilent Board Files and Running a RISC-V Processor on the Arty A7. The first link has instruction for how to install software/files for the FPGA development. The second link is for how to program Arty A7 as RISC-v core.

For installing Vivado/Vitis, software package is huge. Xilinx download page recommends to use the web installer. However, people like me was hitting "Peer not authenticated" issue as mentioned here. The solution is download the Xilinx Unified Installer 2022.1 SFD gzip file, extract and install. The gzip file is 73.8G, download and extract would need a lot of hard disk space. At least, it works.

For programming Arty A7 as RISC-V, I'm getting many trouble. First, download SiFive Freedom processor with git command:

git clone --recursive https://github.com/sifive/freedom.git

this would take quite some time to download the git plus a bunch of sub-modules. And may fail with some sub-modules as there are so many of them, and either there is network issue, or the repo server URL was change. If the clone isn't success, then have to fix that, otherwise, won't be able to build. To sync missing sub-module, refer to Git - Submodules (git-scm.com) May run:

# copy the new URL to your local config
$ git submodule sync --recursive
# update the submodule from the new URL
$ git submodule update --init --recursive

If seeing not empty warning, might need to clean those sub-folder first. Might see different problem like:

Submodule 'env' (git://github.com/ucb-bar/riscv-test-env.git) registered for path 'rocket-chip/torture/env'

Cloning into '/home/$user/freedom/rocket-chip/torture/env'...
fatal: unable to connect to github.com:
github.com[0: 140.82.114.3]: errno=Connection timed out

cd to freedom/rocket-chip/torture and check the '.gitmodules' would get:

cat .gitmodules
[submodule "env"]
path = env
url = git://github.com/ucb-bar/riscv-test-env.git

Per this post, either need to make sure to have SSH key setup, or use https instead of SSH protocol for the git url. So manually run: git clone https://github.com/ucb-bar/riscv-test-env.git env

Or run this to update the .gitmodules file:

sed s#git://github.com#https://github.com#g -i .gitmodules
git submodule sync

For problem like: "server certificate verification failed. CAfile: none CRLfile: none", try this as mentioned in this stackoverflow post: sudo apt update ; sudo apt-get install apt-transport-https ca-certificates -y ; sudo update-ca-certificates

Once git sync is OK, the first step is building the toolchain. Change working directory to rocket-chip/riscv-tools, and check README.md there: would need to set RISCV environment variable first, like this: export RISCV=/mnt/c/develop/riscv, also, several packages are needed for building the toolchain. Run the build.sh script to build, and it will take some time.

Next step is building Verilog installation. Please note the instruction

make -f Makefile.e300artydevkit Verilog

should have the target 'Verilog' as all little case 'verilog' (which is in common.mk). There is several other cases in the Digilent instruction which should use all little case as well, such as Xilinx=>xilinx

< to be continue >

Install multiple Ubuntu instances in WSL2

2022-09-21T22:03:00.003-04:00

Yes, there are probably many post about this, such as https://cloudbytes.dev/snippets/how-to-install-multiple-instances-of-ubuntu-in-wsl2 and https://stackoverflow.com/questions/51584765/how-do-you-install-multiple-separate-instances-of-ubuntu-in-wsl. Still want to make this post about a special case not covered anywhere else.

Run wsl -l can show all installed distribution.

If want to remove one of the distribution, run: wsl --unregister <DistributionName>

Recently I'm playing with ROS Kinetic. Unfortunately, as mentioned http://wiki.ros.org/kinetic/Installation/Ubuntu, only old Wily (15.10) and Xenial (16.04 LTS) are supported. It's possible to get it setup with VirtualBox or VMware VM, but I'd like to go with WSL2 on Windows 11, as mentioned in my the other post, it is possible to enable Ubuntu GUI with the Windows 11 build 22000+. One problem here is the Xenial Ubuntu is no longer available from Microsoft Store, so would need to use WSL2 very useful 'import' feature. For this, would need a tar.gz file of the Ubuntu distribution, the ISO image file doesn't work with WSL import. Another problem now, seems there is no tar for the Xenial Desktop image, but the base image is available such as the amd64 one as ubuntu-base-16.04.6-base-amd64.tar.gz, and it is pretty small, just 41MB. Using command like this to import it:

wsl --import xenial c:\Users\%USERNAME%\wsl_xenial .\Downloads\ubuntu-base-16.04.6-base-amd64.tar.gz

(Note: for imported distro, if run wsl --unregister, it will delete distro file). There is no Ubuntu desktop and only user root is created. To add new user, run following command with the root account to add the user and add it to sudo group:

adduser newuser

usermod -aG sudo newuser

Try this to verify the user group and switch to it:

groups newuser

su - newuser

Type 'exit' to switch back to root, and run 'apt update' and 'apt install sudo', so later the new user can do apt install with sudo command. This is the minimum for installing other package as new user.

To get the desktop environment, run: 'sudo apt install ubuntu-desktop', which installs most common packages. On WSL/Windows OS side, need to follow https://learn.microsoft.com/en-us/windows/wsl/tutorials/gui-apps, installing the AMD/nVidia/Intel's Virtual GPU (vGPU) driver first, then run: 'wsl --update' and 'wsl --shutdown' for a clean restart. May install gedit and run it to verify the GUI. Per my testing, with Ubuntu 20.04 LTS the GUI works fine. However, doesn't work for Ubuntu 16.04 Xenial, seeing segment fault and probably core dump. Tried Diagnosing "cannot open display" type issues with WSLg but not much luck. So leave it aside for now.

我的小鸡们

2022-07-10T16:36:00.006-04:00

六月18日星期周六，对我们全家来说是悲伤的一天，来到我们家十一天的小芦花鸡大毛不幸在我们的后院失踪了，而且最可能是被鹰之类的飞禽捉走了。本来它们是在纸箱里，上面盖着。因为味有点大，太太把纸箱放后院deck上。风大把盖子吹掉了，小鸡就自己跑了出来，可我们不知道，不然一定会看着它们的，因为以前就有小鹰虎视眈眈的站fence上看我们的小鸟。
六月7日，两只小芦花鸡刚刚落户我们家，大概有一周多大，浑身黄白棕黄色的毛，一只颈背棕色毛多的，我们给它取名一撮毛，另一只颈两侧各有些棕毛，我们叫它俩撮毛，后来就简称大毛二毛。大毛二毛很招人喜爱，总是小声小气的鸡鸡个不停，甚至在边吃饭睡觉时也会唧唧，即像在呼唤同伴，又像在表达很好很舒服很好吃。失去了大毛，让我想起了鲁迅《祝福》里的祥林嫂，好在很快，我们又收养了新的小鸡，给了我们一些抚慰。
失去大毛那天，太太带着孩子去买回两只新小鸡，它们是那么小，恐怕刚出生一两天而已，刚来时，站着就要睡着了，也不大吃东西，好像不知道怎么吃。我们叫它俩团团和圆圆，寄予小鸡一家团圆。为了不再老让孩子们想起大毛伤心，我们叫二毛为芦花。

团团圆圆一来就把芦花当作妈妈，总往芦花的翅膀和肚子下钻。好在芦花很nice,从开始觉得很wierd，到后来就顺其自然，带着两个小妹妹吃饭睡觉草地里跑来跑去。鸡食很让我们发愁，不知道它们爱吃什么，于是给它们吃麦片燕麦片，玉米面拌菜，还有苍蝇。天好时我们经常在后院坐板凳上，地上铺着小鸡pupu的报纸，举着苍蝇拍打苍蝇。小鸡们知道啪一声响就有好吃的，所以经常等在身旁，甚至迫不及待的自己追苍蝇，当然总是一无所获。它们快乐的长大着。为了区分两只小的，我们在圆圆小鸡翅膀上mark黑颜色，就叫它小黑。后来我们又从别人那买回一只毛黑一点的小鸡，主人说5月底买的，叫Fluffy,可个头比芦花还小，它以前常被同养的两只小鸭子欺负，胆子很小，好在很快就和芦花团团圆圆和睦相处,我叫它毛毛。它也很快学会吃苍蝇。六月28日周二，我因有事去了办公室，不幸happens again:太太把小鸡放在纸箱里，然后放deck上。为了透气，我在纸箱上给大毛二毛开了些小窗口，可团团圆圆小，可以从窗口跑出来，太太从后院进屋，随手关拉门，没想到从纸箱外逃出来的小圆圆跟在后面，被挤，不幸。为了不让Emily伤心，我急忙从办公室赶回，几经周折，去卖鸡家又买了个小鸡，找不到大一点的，新小鸡叫声响亮，可不大会吃，总想睡觉。因太小，没法骗小孩，只好说farmer要求把小圆圆换走了。这个小家伙，我叫它球球，因为它跑起来像个滚动的棉花球。它长的好像很慢，都过了一个多星期，它还和刚来时差不多大。它睡觉喜欢钻到芦花的翅膀或肚子下，有时芦花已经趴下，小球球会跳到芦花背上，一旦芦花站起来，小球就有机会钻了。

上周日(Jul 3），太太又从别人那买回两只小鸡，有大毛二毛来时大。这样我们就有6只小鸡了。
芦花很喜欢在后院跑，每次它都是最难捉回来的。它甚至听得懂它的名字，每次听到我们喊芦花，就知道有苍蝇吃了，会从院子的不知那个角落连跑带飞的奔到我们打苍蝇的地方来。后来可能因小鸡太多了，小的小鸡时常在我们身旁等苍蝇吃，芦花再从远处赶来常吃不到，它就不大理会名字被叫到了。芦花很早就学会玩土洗澡了，有时就趴在我们种的西红柿旁的土地里，享受泥土和阳光浴。除了苍蝇，芦花和小鸡们很喜欢吃面条，也喜欢米饭。看小鸡们抢食物吃有时很好笑，小的小鸡抢到好吃的会飞快的在其它鸡面前钻来转去。芦花看着很大，可前几天我们给它称了，却还不到一磅。芦花不在外边跑时很乖，轻轻push它，它就肯安静地趴在我们的手和胳膊上。我们都在想芦花再大一点，就会给我们下蛋了。
8日周五早，Rogers的cell phone和无线网同时down了。今天,六只小鸡一早就又被放出来，吃了些菜拌玉米面，喝了些水，在后院撒欢。突然芦花有些异样，站在草地里不动，我以为它在pupu，果然它拉了一点黑稀东西，可还是很不舒服，没过多久它就开始趴下了，连我走过去摸它，它也没再像以前那样run away。我抚摸了它，没多久它变得更加痛苦，头颈开始使劲扭动，很吓人，又让我们手足无措，不知怎样才能帮它，Rogers的网络还没回来，电话是好了，可我们都不知打给谁。我只能帮它按摩腹部，有那么一刻，芦花又站起来，跑开了，让我以为一切转危为安了，可没多久芦花又趴下了。眼睛也不愿睁开了。生命在慢慢逝去。在最后的一刻里，芦花再次从我的手足挣扎出去，跑到了它心爱的西红柿旁的土地里。我把它再次抱回手里没多久，它终于解脱了，安详的躺在我的胳膊上。

我们把它埋在香椿树和桑树下，离小圆圆埋葬的地方很近，希望它在天堂与一撮毛还有小圆圆团聚。
生命有时是如此的脆弱，我们在不知不觉中付出了关爱，在那一刻被残忍的剥夺了。在我们眼前耳边缠绕着它们的身影和声音，我们恐怕不再有勇气去收养新的小鸡。
愿小芦花安息