Technical Notes

Standard Structure of C Program

2016-02-04T22:18:00.001+05:45

General/Standard structure of a C program illustrate the placement of specific part of the program in the program. As we know, there always exist, input, process and then output. We cannot break this rule, in the same way we cannot break the rule of structure of standard C program, which also helps in reducing the error of the program written. However, some changes can be made then described below:

The #include directives
Header files
The pre-processor directives
The void main() function
Variable initialization and declaration
Statements and Functions (if any)
The getch() function

The #include directives

The #include directives are used to include library files or external files that contains system functions or user-defined functions. The structure that it uses is:

#include <filename>

For example:

#include <stdio.h>

Here, we all know what is "#include".

"<>" is format that we use.

"stdio.h" is the library file which contains various system default functions like "scanf()", "printf()", etc.

more coming soon.....

Setup New PC @ Home

2015-12-25T22:54:00.000+05:45

Using the pre-setup PC is common. At the time of buying most of the store provide us this services. Among all those software, the product you buy is genuine but you will not be sure about other additional simple applications are genuine or cracked version. Sometime you might have to think; "if I can get this free of cost why to pay?" The thing is some store-keeper might charge you for free software.
This article is simply about the genuine free small applications that you might need for daily work in your PC. Some of them are anti-virus, image-file handling, music, browsers, etc. I am not only concern about using the genuine products that gives free updates but also concerned to the quality software. Yes, I am talking about the software that I am using for past 6 years.
The most important software that we deal at first is Anti-Virus.

Anti-Virus

MICROSOFT SECURITY ESSENTIALS

Photo Editing Tools

MICROSOFT PHOTO GALLERY

Coming soon...

WAP | Programming In C [Question 1]

2015-10-10T16:10:00.001+05:45

Question 1 | WAP to find the number and sum of all the integers in between n1 & n2 that is divisible by 7, where n1<n2 and n1 and n2 are read from keyboard.

Solution :-

#include<stdio.h>
#include<conio.h>
void main()
{
int n1, n2, i, sum=0;
st:
printf("Enter first number:\t");
scanf("%d", &n1);
printf("\nEnter second number:\t");
scanf("%d", &n2);
if(n1<n2)
{
printf("\nThe list of numbers in between n1 and n2\n");
for(i=n1; i<=n2; i++)
{
if((i%7)==0)
{
printf("%d\n", i);
sum=i+sum;
}
printf("\nSum = %d", sum);
}
}
else
{
printf("\nThe first number must be less than second number");
goto st;
}
getch();
}

Arithmetic Pipeline

2015-05-16T22:18:00.001+05:45

Subject | Computer Organization

An arithmetic pipeline is similar to an assembly line in a factory. Data enters a stage of pipeline, which performs some arithmetic operation on data. The results are then passed to the next stage, which performs its operation and so on until the final computation has been performed.

Each stage performs only its specific function, it does not have to be capable of performing the task of any other stage. An individual stage might be an adder or multiplier or other hardware to perform some arithmetic function.

Arithmetic pipeline for floating point add/subtract operations

Variations on arithmetic pipeline are Fixed arithmetic pipeline.
is not very useful. Unless the exact function performed by the pipeline is required, the CPU cannot use the fixed arithmetic pipeline. Configurable arithmetic pipeline.
is better suitable as it uses multiplexer as its input. The control unit of CPU sets the select signals of the multiplexer to control flow of data (i.e. pipeline is configurable). Vectored arithmetic unit.
A CPU may include a vectored arithmetic unit. A vectored arithmetic unit contains multiple functional units to perform addition, multiplication, shifting, division etc) to operate different arithmetic operations in parallel.
Used to implement floating point operations, multiplication of fixed point numbers and similar computations encountered in scientific operations.
Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously.

Introduction | Programming In C

2014-12-15T23:31:00.000+05:45

Subject | Programming In C

Prerequisite | Algorithm, Flowchart, Introduction to Programming Concept

C is a high-level programming language which was first developed in 1972 by Dennis Ritchie at AT&T Bell Labs.

Features of C:

High-level programming language.
General-purpose programming language.
Function-oriented programming language.
Procedure-oriented programming language.

There are three types of programming language as described below:

Machine Level Programming Language.
Assembly Level Programming Language.
High Level Programming Language.

High Level Programming Language

High-level programming language is the human understandable language, especially English. Each high-level programming language needs a compiler or an interpreter to translate instructions written in the high-level programming language for a computer to understand and execute the program. High-level programming language, including C, have the following advantages:

Readability: Programs are easy to read.
Maintainability: Programs are easy to maintain.
Portability: Programs are easy to port across different computer platforms.

Standard Structure of a C Program

The #include directives
Header files
The pre-processor directives
The void main() function
Variable initialization and declaration
Statements and Functions (if any)
The getch() function

more.....

Instruction Pipeline

2014-04-29T13:14:00.000+05:45

Subject | Computer Organization

An instruction pipeline consecutive instruction from memory while previous instructions are being executed in other segments. In most general case, the computer needs to process each instruction with the following sequence of steps:

Fetch instruction from memory.
Decode the instruction.
Calculate effective address.
Fetch operand from memory.
Execute instruction.
Store the result in memory.

The first step in applying pipe-lining techniques to instruction processing is to divide the task into steps that may be performed with independent hardware. The most obvious division is between the FETCH cycle (fetch and interpret instructions) and the EXECUTE cycle (fetch operands, execute instruction and save the result). If these two activities are to run simultaneously, they must use independent registers and processing circuits, including independent access to memory (separate MAR and MBR).

Example: four segment instruction pipeline

Figure | Four Segment Instruction Pipeline

The above figure shows operation of 4-segment instruction pipeline. The four segments are represented as

FI: segment 1 that fetches the instruction.
DA: segment 2 that decodes the instruction and calculates the effective address.
FO: segment 3 that fetches the operands.
EX: segment 4 that executes the instruction.

The space time diagram for the 4-segment instruction pipeline is given below:

Figure | Timing Diagram for 4 - Segment Instruction Pipeline

Problems with instruction pipeline (Pipeline Hazards).

A pipeline hazard occurs when the instruction pipeline deviates at some phases, some operational conditions that do not permit the continued execution. The major pipeline hazards are described below:

Resource hazard (Resource conflict).
Data hazard (data dependency).
Branch hazard (branch difficulties).

1. Resource hazard

It is caused by the access to shared memory by 2 segments at the same time. This can be resolved by using separate instruction and data memories.

2. Data Hazard

It arises when instructions depend on the result of previous instruction but the previous instruction is not available yet. [//for example an instruction in segment k<sub>n</sub> may need to fetch an operand that is being generated at same time by the previous instruction in the segment]. The most common techniques used to resolve data hazard are:

(a) Hardware interlock - a hardware interlock is a circuit that detects instructions whose source operands are destinations of instructions farther up in the pipeline. It then inserts enough number of clock cycles to delays the execution of such instructions.

(b) Operand forwarding - This method uses a special hardware to detect conflicts in instruction execution and then avoid it by routing the data through special path between pipeline segments.

for example, instead of transferring an ALU result into a destination result, the hardware checks the destination operand, and if it is needed in next instruction, it passes the result directly into ALU input, bypassing the register.

c) Delayed load - It is software solutions where the compiler is designed in such a way that it can detect the conflicts; re-order the instructions to delay the loading of conflicting data by inserting no operation instruction.

3. Branch hazard

It arises from branch and other instruction that change the value of program counter (PC). The conditional branch provides plenty of instruction branch line and it is difficult to determine which branches will be taken or not taken. A variety of approaches have been used to deal with branch hazard and they are described below.

(a) Multiple streaming - It is a brute-force approach which replicates the initial portions of the pipeline and allows the pipeline to fetch both instructions, making use of two streams (branches).

This method has a number of disadvantages:

With multiple pipelines, there are contention delays for access to the registers and to memory.
Additional branch instruction may enter the pipeline before the original branch decision resolved.

(b) Prefetch branch target - When a conditional branch is recognized, the target of the branch is prefetched, in addition to the instruction following the branch. This target is then saved until the branch instruction is executed. If the branch is taken, the target has already been prefetched.

(c) Loop buffer - A loop buffer is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence. If a branch is to be taken, the hardware first checks whether the branch target is within the buffer. If so, the next instruction is fetched from the buffer.

This method has a number of advantages:

Suitable to deal with iterations and loops.
With the use of prefetching, the loop buffer will contain some instruction sequentially ahead of current instruction fetch address.
If branch occurs to a target just a few location ahead of address of the branch instruction, the target will already in buffer.

(d) Branch prediction - uses additional logic to prediction the outcomes of a (conditional) branch before it is executed. The popular approaches are - predict never taken, predict always taken, predict by opcode, taken/not taken switch and using branch history table.

(e) Delayed branch - This technique is employed in most RISC processors. In this technique, compiler detects the branch instructions and re-arranges the instructions by inserting useful instructions to avoid pipeline hazards.

Optical Memory | External Memory

2014-04-27T10:00:00.000+05:45

Subject | Computer Organization

Advent of CDs in the early 1980s revolutionized the audio and computer industries. In recent years optical disks have much higher recording densities than conventional magnetic disks.

A CD is prepared by using a high-power infrared laser to burn 0.8-micron diameter holes in a coated glass master disk. From this master, a mold is made. Molten polycarbonate resin is injected into the mold to form a CD. Then a very thin layer of reflective aluminum is deposited on the polycarbonate, topped by a protective acrylic and finally a label. The depressions in the polycarbonate substrate are called pits; the unburned areas between the pits are called lands.

Fig: CD Operation

Information is retrieve from a CD by a low-powered laser housed in an optical-disk player. CD is operated using constant linear velocity. The laser shines through clear polycarbonate while a motor spins the disk past it. Intensity of the reflected lights changes when the lights encounter the pits and the lands. Pits reflect low intensity light and land reflect high intensity light. The changes between pits and lands are detected by photo-sensor. The beginning or end of the pits is recorded as 1 and when no change in elevation occurs between the interval, 0 is recorded.

The advantages of optical disks over traditional magnetic tapes are:

Optical disks can be mass replicated inexpensively.
Optical disks are removable.

Some of the disadvantages of the optical disks are:

Read only drives cannot be updated.
They have an access time is longer than the magnetic disks.

Some of the examples of optical disk products are:

Compact Disk (CD): a non erasable disk used to store digitized audio information of more than 60 minutes of uninterrupted playing time.
CD Read only Memory (CD-ROM): a non erasable disk used to store computer data more than 650 MB of size.
CD Recordable (CD-R): similar to CD-R but user can write data once.
CD Rewritable (CD-RW): similar to CD-R but user can rewrite data multiple times.
Digital Versatile Disk (DVD): can store huge amount of data from 4GB to more 17GB (in case of dual layer/double sided). The basic DVD is read only i.e. DVD-ROM.
DVD-R: similar to DVD-R. User can write to disk only one time. Only one sided disk can be used.
DVD-RW: similar to DVD-R but user can write rewrite data multiple times. Only one-sided disks can be used.
Blue Ray DVD: provides greater storage capacity using a 405nm (blue-violet) laser. A single layer on a single disk can store 25GB data.

Memory Hierarchy

2014-04-27T09:47:00.000+05:45

Subject | Computer Organization

Major design objective of any memory system is to provide adequate storage capacity at acceptable level of performance and reasonable cost.

Four interrelated ways to meet this goal are:

Use a hierarchy of storage devices.
Develop automatic space allocation methods for efficient use of the memory.
Through the use of virtual memory techniques, free the user from memory management tasks.
Design the memory and its related interconnection structure so that the processor can operate at or near its maximum rate.

The main goal of the memory hierarchy is to match the processor speed with the rate of information transfer from the lowest element in the hierarchy. The basis of the memory hierarchy is given below:

Registers internal to the CPU for temporary data storage (small in number but very fast).
External storage for data and programs (relatively large and fast).
External permanent storage (much larger and much slower).

This is elaborated in figure below:

Fig: Memory Hierarchy

Characteristics of the memory hierarchy are:

Consists of distinct "levels" of memory components.
Each level characterized by its size, access time, and cost per bit.
As one goes down the hierarchy, the following occur:

Decrease in cost per bit.
Increasing capacity.
Increasing access time.
Decreasing frequency of access of the memory by the processor.

The basis for validity of condition 3(d) is a principle called Locality of Reference. Memory references made by the processor, for both instructions and data, tend to cluster together. Generally these clusters are kept in high speed memory to reduce the average delay in accessing data. Over a long period of time, the clusters being referenced will change but in short period of time, processor is primarily working with fixed clusters of memory reference. Memory management must deal with this situation.

RISC and CISC

2014-04-25T08:09:00.001+05:45

Subject | Computer Organization

A. Some features of RISC machines are:

Instruction set :- simple and few instructions.
Instruction format :- fixed length instructions format are used and they can be easily decoded.
Pipelining :- single cycle instruction execution so very fast. RISC instruction stages are comparatively smaller than those of CISC, thus RISC architecture permits heavy pipelining while executing instructions.
Addressing modes :- few addressing modes as compared to CISC.
General purpose registers :- RISC machines uses relatively large number of registers.
Micro-program :- do not use micro-program to interpret the instructions.
Memory access :- Memory access is limited to LOAD and STORE instruction for RISC architecture devices.
Control system :- control system is hardwired and memory lines are accessed making system faster. Major complexity is to design the computer with simple hardware architecture.
Usage :- used in scientific and research oriented tasks where processor speed should be very high.
Example: R4400SC (MIPS), PA7100 (HP), PowerPC (IBM), SuperSparc (SUN) etc.

B. Some features of CISC machines are:

Instruction set :- simple to complex instructions and uses multiple instructions.
Instruction format :- variable length instruction formats are used, so special decoding package is needed.
Pipelining :- CISC instruction stages are comparatively larger than those of RISC ones. This directly affects pipelining performance.
Addressing modes :- large variety of addressing modes, 5 to 20 different modes are found in CISC.
General purpose registers :- CISC machines uses limited number of registers.
Micro-program :- heavily uses micro-program to interpret the instructions.
Memory access :- Instruction execution generation in CISC needed to access memory frequently which makes it slow. Instructions manipulate operands in memory.
Control system :- Almost all CISC devices are micro programmed so no issues regarding control memory is to be dealt. The main complexity is to design the micro-program.
Usage :- used in general purpose applications where speed of processor is not primary. CISC machines are preferable in such case due to their lower costs.
Example: System/360 through z/Architecture, PDP-11, VAX, Motorola 68k, and Intel x86 series, Pentium series etc.

Vector Processing

2014-04-25T07:34:00.001+05:45

Subject | Computer Organization

Vector processing deals with computations which involve large vectors and matrices.

Following are representative application areas where vector processing is used are:

Long range weather forecasting
Petroleum explorations
Seismic data analysis
Medical diagnosis
AI and expert systems
Aerodynamic and space flight simulations, etc.

A vector is an ordered set of a one dimensional array of data items. A computer capable of vector processing eliminates the overhead associated with time it takes to fetch and execute the instructions in the program loop. It allows operations to be specified with a single vector instruction of the form C(1:100) = A(1:100) + B(1:100).

The vector instruction includes the initial address of the operands, the length of vectors and the operations to be performed, all in one composite instruction.

A possible instruction format for a vector instruction is given below.

Figure: Instruction Format For Vector Processor

This is essentially a 3 address instruction with 3 fields specifying the base address of the operands and an address field that gives the length of the data items in the vectors.
This assumes that vector operands reside in the memory.

Some examples where vector processing is implemented are

Processing of vector units
Matrix multiplication
Memory interleaving
Super-scalar processors
Supercomputers

1. Processing of vector units

2. Matrix multiplication

Implemented using source registers, multiplier pipeline and adder pipeline.

3. Memory interleaving

In interleaved memory, different sets of addresses are assigned to different memory modules. A vector processor that uses an n-way interleaved memory can fetch n operands from n different modules. Thus effective memory cycle time can be reduced by a factor close to the numbers of modules.

4. Super-scalar processors

Super-scalar processor fetches, executes and returns the results from more than one instruction during a single pipeline stage. In scalar processor, processor processes one data item at a time, whereas in a vector processor, a single instruction operates simultaneously on multiple data items.

In super-scalar processor, there are several functional units of same type, along with additional circuitry to dispatch instructions. Examples of super-scalar processors are CDC 6600, Intel i960CA, AMD 2900 series, Pentium series etc.

5. Supercomputers

A commercial computer system with vector instructions and pipeline floating-point arithmetic operations is referred as a supercomputer. Supercomputers Cray I, Cray II, VP 200, Blue Gene etc.

Advanced DRAM organization

2014-04-25T07:17:00.000+05:45

Subject | Computer Organization

The traditional DRAM is constrained both by its internal architecture and by its interface to processor's memory bus. The new enhancements (most common) on DRAM architecture are:

Synchronous DRAM (SDRAM)
Rambus DRAM (RDRAM)
Double Data Rate DRAM (DDR DRAM)
Cache DRAM (CDRAM)

1. Synchronous DRAM (SDRAM)

Exchange data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.
One word of data is transmitted per clock cycle (single data rate).[All control, address, & data signals are only valid (and latched) on a clock edge.]
Typical clock frequencies are 100 and 133 MHz.
SDRAM has multiple-bank internal architecture that improves opportunities for on-chip parallelism. Generally it uses dual data banks internally. It starts access in one bank then next, and then receives data from first then second.
SDRAM performs best when it is transferring large blocks of data serially, such as for applications like word processing, spreadsheets and multimedia.

2. Rambus DRAM (RDRAM)

RDRAM chips are vertical packages with all pins on one side. The chip exchanges data with the processor over 28 wires no more than 12 cm long. The bus can address upto 320 RDRAM chips.
Entire data blocks are access and transferred out on a high-speed bus-like interface (500 Mbps to 1.6 Gbps).
It has tricky system level design where the bus itself defines impedance, clocking and signaling very precisely.
More expensive memory chips.
Concurrent RDRAMs have been used in video games, while Direct RDRAMs have been used in computers.

3. Double Data Rate DRAM (DDR DRAM)

Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. That is DDR SDRAM can send data twice per clock cycle - once on the rising edge of the clock pulse and once on the falling edge.
There has been improvement in DDR DRAM technology. The later generations (DDR2 and DDR3) increases the data rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.
DDR can transfer data at a clock rate in the range of 200MHz to 600 MHz, DDR2 can transfer in the range of 400MHz to 1066MHz and DDR3 can transfer in the range of 800MHz to 1600 MHz.

4. Cache DRAM (CDRAM)

Integrates a small SRAM cache onto a generic DRAM chip.
The SRAM on CDRAM can be used in two ways

It can be used as true cache.
It can be used as buffer to support the serial access of a block of data.

This architecture achieves concurrent operation of DRAM and SRAM synchronized with an external clock. Separate control and address input terminals of the two portions enable independent control of the DRAM and SRAM, thus the system achieves continuous and concurrent operation of DRAM and SRAM.
CDRAM can handle CPU, direct memory access (DMA) and video refresh at the same time by utilizing a high-speed video interface.
CDRAM can replace cache and main memory, and it is has already been proven that a CDRAM based system has a 10 to 50 percent performance advantage over a 256kbyte cache based system.

Assignment

Memory Management Hardware

[Hint: See Computer system architecture, M. Morris Mano, Chapter 12, section 7]

Direct Memory Access (DMA)

2014-04-24T20:46:00.001+05:45

Subject | Computer Organization

The data transfer technique in which peripherals manage the memory buses for direct interaction with main memory without involving the CPU is called direct memory access (DMA). Using DMA technique large amounts of data can be transferred between memory and the peripheral without severely impacting CPU performance.
During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes over the buses to manage the transfer directly between the I/O device(s) and main memory. The structure of DMA controller is described below.

Figure: Block Diagram of DMA Controller

The control unit communicates the CPU via data bus and control lines.
The DMA controls/relinquishes the system bus using BR (Bus Request) and BG (Bus Grant) signals. DMA operates read and write operations via RD (Read) and WR (Write) signals. DMA sends request and acknowledge to I/O devices via DMA request and DMA acknowledge signals.
The registers in DMA are selected by CPU through the address bus by enabling DS (DMA Select) and RS (Register Select) inputs.
All registers in the DMA appear to the CPU as I/O interface registers. The address register contains an address to specify the desired location in memory. It is incremented after each word that is transferred to the memory. The word count register holds the number of words to be transferred. It is decremented by one after each word transfer and internally tested for zero. The control register specifies the mode of transfer.
The DMA transfer operation is described below:

Figure: Direct Memory Access Technique

The DMA request CPU to handle control of buses to the DMA using bus request (BR) signal. The CPU grants the control of buses to DMA using bus grant (BG) signal after placing the address bus, data bus and read and write lines into high impedance state (which behave like open circuit).

CPU initializes the DMA by sending following information through the data bus.

Starting address of memory block for read or write operation.
The word count which is the no. of words in the memory block.
Control to specify the mode of transfer such as read or write.
A control to start the DMA transfer.

The DMA takes control over the buses directly interacts with memory and I/O units and transfers the data without CPU intervention. When the transfer completes, DMA disables the BR line. Thus CPU disable BG line, takes control over the buses and return to its normal operation.

The DMA transfer operation is illustrated below:

Fig: Illustration for DMA transfer in a computer system

DMA Transfer Modes

There are 3 different modes of DMA data transfer. They vary by how DMA controller determines when to transfer data (but actual data transfer process remains the same in all three cases).

(a) Burst Mode

Entire block of data is transferred in one continuous sequence.
Once the DMA controller is granted access to the system bus by CPU, it transfer all bytes of data in the data block before relinquishing control of system buses back to the CPU.
This mode is useful for loading programs or data files into memory, but it keeps CPU idle for relatively long period of time.

(b) Cycle Stealing Mode

DMA controller obtains access to system bus as in burst mode; transfers one byte of data and returns the control of the system bus to CPU. It continually issues requests using Bus Request (BR) signals, transferring one byte of data per request, until it has transferred its entire block of data. (steals one CPU cycle).
The data block is not transferred as quickly as in burst mode, but the CPU is not idled for long period of time as in burst mode.

(c) Transparent Mode

DMA controller only transfers data when CPU is performing operations that do not use system buses.
The main advantage of this mode is that CPU never stops executing its program.
The main disadvantages of this mode are

Hardware needed to determine when the CPU is not using the system buses can be quite complex and relatively expensive.
Requires highest time to transfer a block of data as compared to above two modes.

Program Control | Control Unit Design

2014-04-24T06:35:00.000+05:45

Subject | Computer Organization

When a program control type of instruction is executed, the instruction may change the address value in the program counter and cause the flow of control to be altered. Program control is affected by following parameters.

Status bit registers
Conditional branch instruction
Subroutine call and return
Program interrupt

1. Status bit registers

Usually status bit registers are supplemented to ALU circuit to store and further analysis of status bit conditions.
Status bit are also called condition code bit or flag bit.

2. Conditional branch instruction

The conditional branch specifies a condition. If condition is met, the PC is loaded with branch address and the next instruction is taken from this address. If condition is not met, PC remains the same and next instruction in the sequence is executed.
Using condition branch instruction, we can control loop and iteration problems too.

3. Subroutine call and return

A subroutine is self-contained sequence of instructions that perform specific tasks. Each time a subroutine is called, a branch is executed to the beginning of the subroutine to start executing its set of instruction. After a subroutine has been executed, a branch is made back to the main program.
A recursive subroutine is a subroutine that calls itself.
Subroutines are very helpful to decompose large problems into smaller problems.

4. Program interrupts

Program interrupts refers to the transfer of program control from a currently running program to another service program as a result of external or internal generated request.
Program interrupt is similar to subroutine call and return except.

Interrupts are initiated by internal/external request not from execution of an instruction.
Address of interrupt service program is determined by hardware not from address field of an instruction.
Interrupt stores all into related to CPU not the PC only.

Register Organization & Its Design Issues | Computer Organization

2014-04-23T22:57:00.000+05:45

Subject | Computer Organization

1. User visible registers

These enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
We can characterize these in the following categories.

General purpose: Can be assigned to a variety of function by the programmer. Sometimes they are use within the instruction set is orthogonal to the operation i.e. any general purpose register can contain the operand for any opcode.
Data register: May be used only to hold data and cannot be employed in the calculation of operand address.
Address register: may be somewhat general purpose or they may be devoted to a particular addressing mode.
Condition code register (flags): They are set by the CPU as a result of operation. (For example, arithmetic operation may produce +ve, -ve, zero or overflow result.) In addition to the result being stored in the register or memory a condition code is also set. Condition code bit are collected into one or more registers. Usually they form part of status register.

2. Control and status register:

There are employed to control the operation of CPU.
Four registers are essential to instruction execution:

Program counter (PC): contains address of an instruction to be fetched.
Instruction register (IR): contains the instruction most recently fetched.
Memory address register (MAR): contains the address of a location in memory.
Memory buffer register (MBR): contains a word of data to be written to memory or the word most recently read.

All CPU designs include a register or set of register often known as program status word (PSW). PSW typically contain condition code pulse other status information. Common flags include the following: sign, zero, carry, equal, overflow and interrupt enable/disable.

Design issues for register organization in CPU

(a) Number of register

Fewer register result in more memory reference, more register do not noticeably reduce memory reference. Generally 8 to 32 register usage appears to be optimum.

(b) General purpose registers Vs Special purpose registers

In special purpose register, the operand specifier must only identify one of a set of specified registers rather than one out of all registers, but it limits the programming flexibility.

No final and best solution can be drawn but the current trend seems towards the use of special purpose registers.

(c) Register length

The length of register should be at least long enough to hold the largest address. Data register should hold the value of most data types.

(d) Allocation of control information

The allocation of control information between the register and memory is also one of the main design challenges. Generally, we dedicate the first few hundreds or thousands of main memory location for control purpose.

CPU Instruction Set | Central Processing Unit

2014-04-23T08:03:00.001+05:45

Subject | Computer Organization

The operation of CPU is determined by the instructions it executes. These instructions are referred as machine instruction and collection of different instructions are called CPU instruction set.

The elements of machine instruction are:

1. Operation code

Specifies the operation to be performed. The operation is specified by a binary code called opcode.

2. Source operand reference

Specifies the operands that are input for the operation.

3. Result operand reference

The operation may produce a result; it specifies the location for the result.

4. Next instruction reference

This tells the CPU where to fetch the next instruction after the execution of current instruction. Commonly, the next instruction to be fetched is located in main memory, in the case of virtual memory it is either in main memory or secondary memory.

The source and result operand can be in main memory, virtual memory, CPU register or in the I/O device.

Instruction execution follows a set cycle which is given in figure below.

Fig: Instruction cycle state diagram

Instructions address calculation - determine the address of the next instruction to be executed. Usually this involves adding a fixed number to the address of the previous instruction.
Instruction fetch- read instruction from memory into the processor.
Instruction operation decoding - analyze instruction to determine type of operation to be performed and operand(s) to be used.
Operand address calculation - if the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand.
Operand fetch - fetch the operand from memory or read it in from I/O.
Data operation-perform the operation indicated in the instruction.
Operand store - write the result into memory or out to I/O.

Types of Instruction

A. According to number of address field

3-address instruction
3-address instruction
1-address instruction
0-address instruction (stack operation)

B. According to operation

Data transfer instruction
Arithmetic instruction
Logical instruction
Conversion/Translation instruction
I/O Instruction
System control instruction
Transfer of control instruction

Memory Management

2014-04-23T07:21:00.001+05:45

Subject | Computer Organization

The high-level scheduler will admit as many jobs as possible (constrained by system resources such as available memory). Despite many jobs in the system, the speed of the CPU (compared to peripherals) might be such that all jobs are waiting for (slow) I/O and thus the CPU is idled (no jobs in the ready queue). We can solve this problem using memory management techniques.

The tasks of managing the memory resources and allocating the memory to the system and/or user by the OS can be described as memory management. According to A. Listner and R. Eager (1993), there are 5 requirements that must be satisfied for memory management.

1. Relocation

In many scenarios, processes taken out from main memory to secondary memory is to be placed back to the previous location of main memory. This may not possible in most of the cases it is not possible, thus, they must be relocated to a different location.

2. Protection

One process must be blocked to overwrite the memory used by another process. So a protection strategy is required and the protection must be maintained by the processor because the OS cannot keep track of all the references made by all the processes of many programs.

3. Sharing

Any protection mechanism must have the flexibility to allow several processes to access the same portion of main memory. The memory management system must allow controlled access to shared areas of memory without compromising essential protection.

4. Logical Organization

The logical organization of memory closely mirrors the actual machine hardware; it does not correspond to the way in which the programs are typically constructed.

5. Physical organization

Usually main memory is faster but volatile as compared to the secondary memory. In this two-level scheme, organization of flow of information between them is major system concern.

Memory management techniques

Some of the memory management techniques are described below:

Swapping
Partitioning
Paging
Segmentation

Types of Operating System

2014-04-23T00:02:00.000+05:45

Subject | Computer Organization

Operating System

Classification On The Basis Of Services.

1. Mainframe OS

It is used in mainframe computers. The mainframe OS is heavily oriented toward processing of many jobs at once and typically offers 3 kinds of services:

Batch: processes routine jobs without interactive user present. Claims processing in an insurance company or sales reporting for a chain of stores are typically done in batch mode.
Transaction processing: handles large number of small requests such as cheque processing in bank or online ticket reservations.
Time sharing: allows multiple remote users to run jobs on a computer at once such as searching different information from a database.

Examples: OS/390

2. Server OS

It can serve many requests of client computers linked with it. It can provide print service, file service, and web service etc to multiple users at once.

Examples: Windows server family, Linux, Unix etc.

3. Multiprocessor OS

It is variation of Server OS with special features for communication and connectivity.

4. Personal Computer OS

It the mostly used by the normal people and has many capabilities ranging from text editing to video editing, gaming, video conference, multimedia features etc. They are specially the client computers in network environment.

Some examples are Windows 98/XP/VISTA/7, Linux, MAC OS etc.

5. Real-time OS

Time is the key factor for executing the task. In the Soft Real Time OS, missing of some actions in certain instant of time is acceptable such as systems used for digital audio and multimedia processing fall under this category. In the Hard Real Time OS, some action must occur at certain instant of time precisely such as motherboard assembly by the robot.

Example: VxWorks, QNX etc.

6. Embedded OS

It runs on electronics devices that cannot be thought as computers such as TV sets, microwave ovens, mobile telephones etc. They have characteristics similar to Real-time OS but with limited size, speed and memory.

Example: Windows CE (Consumer Electronics), Palm OS etc.

7. Smart-card OS

It can run on smart cards. They have very severe processing power and memory constraints. They can handle single or few functions. They are Java oriented. The ROM on the Smart Card holds and interpreter for Java Virtual Machine (JVM). Small programs called Java applets are used and they are interpreted by JVM.

Classification On The Basis Of Task Processing.

1. Serial Processing System

In this system the users have to access the computer in series (waiting in a queue). A single program called job could involve loading the compiler plus high level language program (source program) into memory, saving the compiled program (object program) and then loading and linking together the object program and common functions. Each of these step involve mounting and dismounting of tapes or cards. Over times various system software were developed to attempt to make serial processing more efficient. These include common libraries, linkers, loaders, debuggers and I/O driver routines that were available as common software for all users. Efficient processor utilization is the biggest issue here.

2. Batch System

To improve the CPU utilization batch systems were developed. With such a system called monitor the user no longer has direct access to the CPU. The user submits the jobs on cards or tapes to a computer operator, who batches the jobs together sequentially and places the entire batch on an input device, for use by the monitor. The processor fetches the jobs and executes them in a sequence. Some of the important features of this system are memory protection for the monitor, timer for preventing a single job to monopolize the system, privileged instruction that can be executed by monitor only and interrupts for more control over user programs.

3. Multi-programmed Batch System

Since I/O devices are slower than processor, the processor remains idle in simple batch system to maximize the processor utilization, multi-programmed batch systems were developed. In this system when a job waits for I/O, the processor switches to the other job which is not waiting for I/O. Furthermore, it can switch two or more jobs to make itself busy. This system is also called multitasking system and it is the main theme of all modern OSes.

Figure: Uni-programming

Figure: Multi-programming with two programs

4. Time Sharing System

In many jobs such as transaction processing, it is desirable to provide a mode in which the user interacts directly with the computer. The time sharing system is variation on multi-programmed system where the processor is allowed to handle the multiple interactive jobs. (instead of batch jobs in multi-programmed system). The processor's time shared among the multiple users. Processor executes jobs from multiple users with a short burst or quantum of computations. The main objective of time sharing system is to reduce the response time of the processor.

Operating System

2014-04-21T14:39:00.003+05:45

Subject | Computer Organization

Operating System Overview

An operating system is a program that controls the execution of application programs and acts s interface between the users of a computer hardware.
OS can be viewed as:

1. Resource Manager

In resource manager view, the OS manages the different parts (such as processor, memories, timers, I/O devices etc) in efficient way. OS can manage the resources for a single user, different tasks and/or multiple users.

2. Extended Machine

In extended machine view, OS hides all system complexities, hardware details, services to the user. User can easily run or program their application without worrying about underlying hardware specification, timings and execution details.

Figure: General Computer System

The OS typically provides the following services:

Process Management

A process is a program in execution. OS is responsible for creation, execution and termination of various processes created by the system and the users. It also manages the threads (which are building blocks of process) in both user space and kernel level. OS manages the execution of processes by various inter-process communication (IPC) methods such as message passing, scheduling etc.

Memory Management

OS is responsible for managing the primary and secondary memories attached to a computer system. OS can use various methods (such as swapping, paging, segmentation) to manage the programs/files that resides on primary memory. It also allows to the users to manage the secondary memory by hiding underlying complexities. Many OS comes with built-in tools for partitioning, formatting, reallocation of memory addresses of secondary memories.

I/O management

OS hides the computation of clocking, interrupts, delays, response times, time syncing, power management, communication between CPU and memory system and recognizing devices using device drivers and gives users the platform for interacting with computer hardware.

File management

File contains data and/or information. The file can be created by user and system itself. OS helps us to create, modify and delete the files/directories. It also manages the various attributes such as hidden, shared, permission level, access controls of file/directories using various attributes associated with the file/directories.

Error Detection and recovery

OS can detect the errors in various levels and tasks such as power failure, bad sections in HDD, unstable state, unreadable files, malfunctioning device and device drivers, communication errors etc. It can generate and present log of unsolved problems; the logs can be used to troubleshoot the problems by the users.

Network Management

The OSes which can provide network features can manage the network issues related to the computer. It can find establish and disconnect the network connection between two or more computers, transfer data over the network, find the shared resources and computers in a network, manage the sent/received requests etc.

Security management

Security management is one of the key services provided by the OS. The security can be limited to one single computer or whole computer network system. It authenticates and validates the user log-in, verifies the user/group access to the local and shared resources according the security schemes applied by the system itself and/or by the user(s) of the computer.

Some Solved Questions - 1 | Programming In C

2014-04-21T02:41:00.001+05:45

Subject: Programming In C

Write a program to display "HelloWorld" 10 times.

#include <stdio.h>
#include <conio.h>
void main()
{
for (int i=1; i<=10; i++)
{
printf ("HelloWorld\n");
}
getch();
}

Write a program to display all the numbers between 1 to 100.

#include <stdio.h>
#include <conio.h>
void main()
{
for (int i=1; i<=100; i++)
{
printf ("%d\n", i);
}
getch();
}

Write a program to display odd numbers between 1 to 100.

#include <stdio.h>
#include <conio.h>
void main()
{
for (int i=1; i<=100; i++)
{
if ((i%2)!=0)
{
printf ("%d\n", i);
}
}
getch();
}

Write a program to display even numbers between 1 to 100.

#include <stdio.h>
#include <conio.h>
void main()
{
for (int i=1; i<=100; i++)
{
if ((i%2)==0)
{
printf ("%d\n", i);
}
}
getch();
}

Write a program to display square of even numbers between 1 to 100.

#include <stdio.h>
#include <conio.h>
#include <math.h>
void main()
{
int i, b;
for (i=1; i<=100; i++)
{
if ((i%2)==0)
{
b = i^2; //i^2 = i*i
printf ("Square of %d = %d\n", i,b);
}
}
getch();
}

Write a program to display cube of odd numbers between 1 to 100.

#include <stdio.h>
#include <conio.h>
#include <math.h>
void main()
{
int i, b;
for (i=1; i<=100; i++)
{
if ((i%2)!=0)
{
b = i^3; //i^2 = i*i*i
printf ("Cube of %d = %d\n", i,b);
}
}
getch();
}

Introduction | Computer Graphics

2014-04-20T07:14:00.002+05:45

Subject | Computer Graphics

Computer Graphics is the art of creating pictures with a computer.

It makes communication between human and computer more pictorial.

Computer graphics has given us the mouse "the input device" what you see is what you get; for representation in computer.

Today every user of a computer benefits from Computer Graphics, even in applications such as word-processor, spreadsheets, database and project planners.

History of Computer Graphics

1945, Dr. Vannevar Bush, designer of early calculator, wrote an article describing his vision of a personal desktop computer for non-numerical application.
1950, Simple picture, - SAGE (Scalable Advanced Graphic Environment), was the first to command and control CRT (Cathode Ray Tube) - Display, with the use of lightpen.
1960, Dovylas Engebart, invent the mouse.
1963, Iran E Sutherland, sketchpad - Developed interactive technique for used lightpen and keyboards for selecting, pointing, drawing, editing objects on CRT.
Mid-60's, MIT, NASA (National Aeronetic and Space Administration), developed multiple time shared graphics console for many phase of car-design.
Early-70's, ADIS (Alcohol and Other Drug Information Services), graphics package was developed - capable to read/write a single pixel on screen to draw line and text to display. The output was directed to rectangular area of the screen called the window.
1974, cheap memory and cheap display available in market.
Late-70's, Evans and Sutherland (flight simulators) created economic ratergraphics and displays.
1979, Robert Sproull, presented a design of Rastergraphics packages into programming environment.
Early-80's, Graphic Work Station (Silicon Graphics), photorealism (raytracing and radio city).
Early-90's, interactive 3D-system.

Application of Computer Graphics

Computer Aided Design (CAD)
Presentation Graphics
Computer Art
Entertainment.
Education and training
Visualization
Image processing
Graphical User Interface

Computer Aided Design (CAD).

Assist the design process.

Architectural engineering, electronic roadways.

CAD usually allow, a structure to be built up from several.

Presentation Graphics.

Often called Business graphics.
Enable to create highly stylized images for slide shows and reports.
Creating various types of charts and graphs.
For inverting text in a variety of fonts for effective presentation.

Computer Art.

Artist use a variety of computer methods using special purpose hardware, artist pain brush program, CAD package, Animation packages.
Demonstration a picture of cartoon.

Entertainment.

Making motion pictures, music videos and television programs.
Live actions.
Morphing (transformation of one person or object into another).

Education and Training.

Electronic publication use videos, sounds and pictures to present some ideas.
Publication in internet for distributing information world wide.
Inter-user, can send real time videos and audio using a personal computer.
Live broadcast of conference.

Visualization.

Producing graphical representation of scientific, engineering and medical data sets is called visualization.
Use Computer Graphics to explore data and present information.

Image processing.

For multi-perspective vision i.e., more cameras spread around a room.
Modify and interpret existing picture.
In medical, pictures enhancement (improve for good quality).
Use in Computer Aided Surgery.

Graphical User Interface.

Display multiple-windows area.
Menus, and icons for fast selection of processing options.

Number Systems

2014-04-20T06:16:00.000+05:45

Four Number Systems and its numbers from 0 to 100 is tabulated below:

Decimal Number System	Binary Number System	Octal Number System	Hexa-decimal Number System
0	0	0	0
1	1	1	1
2	10	2	2
3	11	3	3
4	100	4	4
5	101	5	5
6	110	6	6
7	111	7	7
8	1000	10	8
9	1001	11	9
10	1010	12	A
11	1011	13	B
12	1100	14	C
13	1101	15	D
14	1110	16	E
15	1111	17	F
16	10000	20	10
17	10001	21	11
18	10010	22	12
19	10011	23	13
20	10100	24	14
21	10101	25	15
22	10110	26	16
23	10111	27	17
24	11000	30	18
25	11001	31	19
26	11010	32	1A
27	11011	33	1B
28	11100	34	1C
29	11101	35	1D
30	11110	36	1E
31	11111	37	1F
32	100000	40	20
33	100001	41	21
34	100010	42	22
35	100011	43	23
36	100100	44	24
37	100101	45	25
38	100110	46	26
39	100111	47	27
40	101000	50	28
41	101001	51	29
42	101010	52	2A
43	101011	53	2B
44	101100	54	2C
45	101101	55	2D
46	101110	56	2E
47	101111	57	2F
48	110000	60	30
49	110001	61	31
50	110010	62	32
51	110011	63	33
52	110100	64	34
53	110101	65	35
54	110110	66	36
55	110111	67	37
56	111000	70	38
57	111001	71	39
58	111010	72	3A
59	111011	73	3B
60	111100	74	3C
61	111101	75	3D
62	111110	76	3E
63	111111	77	3F
64	1000000	100	40
65	1000001	101	41
66	1000010	102	42
67	1000011	103	43
68	1000100	104	44
69	1000101	105	45
70	1000110	106	46
71	1000111	107	47
72	1001000	110	48
73	1001001	111	49
74	1001010	112	4A
75	1001011	113	4B
76	1001100	114	4C
77	1001101	115	4D
78	1001110	116	4E
79	1001111	117	4F
80	1010000	120	50
81	1010001	121	51
82	1010010	122	52
83	1010011	123	53
84	1010100	124	54
85	1010101	125	55
86	1010110	126	56
87	1010111	127	57
88	1011000	130	58
89	1011001	131	59
90	1011010	132	5A
91	1011011	133	5B
92	1011100	134	5C
93	1011101	135	5D
94	1011110	136	5E
95	1011111	137	5F
96	1100000	140	60
97	1100001	141	61
98	1100010	142	62
99	1100011	143	63
100	1100100	144	64

Exception Handling

2014-04-20T06:03:00.001+05:45

Subject | Object Oriented Programming C++

Introduction

An exception is an unusual event that happens in a program under certain circumstances, which are beyond the control of the program.

Exceptions mainly occur in memory and file operations.

Exception handling is a C++ feature that enables program to intercept and process exceptional conditions - errors; usually - in an orderly, organized and consistent manner.

Allows one section of a program to sense (catch) and dispatch (throwing exception) error conditions, and another section to handle them.

Using C++ exception handling, the program can automatically invoke error-handling routines when an error occurs.

The reasons why exceptions occur are numerous. Some of the more common causes are:

falling short of memory.
inability to open a file.
exceeding the bounds of an array.
attempting to initialize an object to an impossible value.

Strategies of handling exceptions could be:

displaying the error messages on the screen.
displaying a dialog box in case of a GUI environment.
requesting the user to supply better data.
terminating the program execution.

Types of Exception:

Synchronous exceptions (C++).
Asynchronous exceptions

The exception handling mechanism suggests a separate error handling code that performs the following tasks:

Find the problem (Hit the exception).
Inform that an error has occurred (Throw the exception).
Receive the error information (Catch the exception).
Take corrective actions (Handle the exceptions).
The error handling code basically consists of two segments one to detect errors and to throw exceptions, and the other to take appropriate actions.

The general form of these two blocks are as follows:

void main()

{

------------

try

{

------------

throw exception;

------------

}

catch (type arguments)

{

------------

}

------------

}

Note that exceptions are objects used to transmit information about a problem.

If the type of object thrown matches the argument type in the catch block is executed for handling the exception or else, the program is aborted with the help of the abort() function which is invoked by default.

// division by zero : try block throwing an exception.

void main()

{

int a, b;

cout << "Enter two integers:";

cin >> a >> b;

int x = a - b;

try

{

if(x!=0)

{

cout << "\n Result (a/x) = " << a/x << "\n";

}

else

{

throw(x);

}

catch(int i)

{

cout << "Exception caught: x = "<< x <<" \n";

cout << "END";

}

output of the above program.

Enter two integers: 8 4

x = 8 - 4 = 4

Result(a/x) = 8/4 = 2

END

Enter two integers: 4 4

x = 4 - 4 = 0

Exception caught: x = 0

END

Template | Polymorphism

2014-04-20T05:56:00.001+05:45

Subject | Object Oriented Programming C++

Introduction

enables us to define generic classes and functions and thus provide support for generic programming.
Generic programming is an approach where generic types are used as parameters in algorithms so that they work for a variety of suitable data types and data structures.
A template can be used to create a family of classes and functions.

For example: a class template for array class would enable us to create arrays of various data types such as int array and float array. Similarly, we can define a template for a function, say mul(), that would help us create various versions of mul() for multiplying int, float, and double type values.

Since, a template is defined with a parameter that would be replaced by a specified data type at the time of actual use of the class or function. The templates are also called parameterized classes or functions.
Templates are a mechanism that make it possible to use one function or class to handle many different data types.
By using templates, we can design a single class/function that operator on data of many types, instead of having to create a separate class/function for each type.
When used with function, they are known as function templates. When used with classes, they are called class templates.

Function templates

//a function that returns the minimum of two numbers.

template < class T >

T min ( T a, T b )

{

return ( a<b ) ? a:b;

}

void main()

{

int i=10, j=20;

cout<<endl<<min(i,j);

float a=3.14, b=-6.28;

cout<<endl<<min(a,b);

char ch='A', dh='Z';

cout<<endl<<min(ch, dh);

double d=1.1, e=1.11;

cout<<endl<<min(d,e);

}

Templates can thus significantly reduce source code size and increase code flexibility without reducing type safety.

General form/syntax (function template)

template<class T> T function_name

(T formal arguments)

{

---------

return(T);

}

template<class T>

T function_name (T formal arguments)

{

----------

return(T);

}

Class templates

The concept of templates can be extended to classes. Glass templates are usually used for data storage (container) classes.

//stack class template

const int MAX=10;

template<class T>

class stack

{

private:

T stk[MAX];

int top;

public:

stack(){top= -1;}

void push(T data){

if(top = MAX-1)

cout<<"stack full";

else{

top++;

stk[top] = data;

}

Pipelining

2013-07-18T11:34:00.000+05:45

Subject | Computer Organization

Pipelining is a technique of decomposing a sequential process into sub operations with each sub operation being executed in a special dedicated segment that operates concurrently with all other segments.
The several computations can be in progress in distinct segments at the same time. The overlapping of computation is made possible by associating a register with each segment in the pipeline.
Simple way of viewing the pipeline structure is to imagine that each segment consists of an input register followed by a combinational circuit. The output of combinational circuit in a given segment is applied to the input of next segment. A clock is applied to all registers after enough time has elapsed to perform all segment activity. In this way the information flows through pipeline one step at a time.

Figure | General Structure of Pipeline System

General Consideration

Task - refers to the total operation performed by going through all the segments in the pipeline.
Space time diagram - shows the segment utilization as a function of time. The horizontal axis displays the time in clock cycles and the vertical axis gives the segment number. The general equation for completing n tasks using a k-segment pipeline requires k+(n-1) clock cycles.
Speed up ratio - is the ratio of time required to process task in non pipeline environment over the pipeline environment.

This implies that theoretical maximum speed up ratio that a pipeline can provide is K (no. of segments in pipeline). But the pipeline cannot operate in its theoretical rate because

Different segment meet at different time to complete their sub operation. The clock cycle must be chosen equal to the time delay of the segment with the maximum propagation delay.
It is not always correct to assume a non pipeline circuit has the same time delay as that of a pipeline circuit.

Parallel Processing

2013-07-16T13:20:00.000+05:45

Subject | Computer Organization

Parallel processing is a term used to denote large class of techniques that are used to provide simultaneous data processing task for the purpose of increasing the computational speed of a computer system.
To achieve parallel processing, the system may have two or more ALU's (//to execute two or more instructions at the same time) or two or more processors (//that operate concurrently) or both.
The purpose of parallel processing is to speed up the computer processing capability and increase its throughput (i.e., amount of processing that can be accomplished during a given interval of time).
Parallel processing can be viewed from various level of complexity. At lowest level, we distinguish between parallel and serial operations by the type of registers used. The highest level can be achieved by having a multiplicity of functional units that perform identical or different operations simultaneously.

The figure below shows one possible way of separating the execution unit into eight functional units operating in parallel.

Figure | Processor with Multiple Functional Units

The operands in the registers are applied to one of the units according to the operation specified by the instructions.
All units are independent to each other.
A multinational organization is usually associated with a complex control unit to co-ordinate all the activities among the various components.

Parallel processing can be classified according to internal organization of processors, interconnection structure between processors, flow of information of the system or number of instructions and data files (Flynn's classification).
Following are some representative application of parallel processing computers: Numerical weather forecasting, Computational aerodynamics, Remote sensing application, Genetic engineering, Weapon research and defenses etc.
Parallel processing can be achieved through:

Pipeline processing: is an implementation technique where arithmetic sub operations or the phases of computer instruction cycle overlap in execution.
Vector processing: deals with computations involving large vectors and matrices.
Array processors: perform computations on large array of data.

Vector Processing

Vector processing deals with computations which involve large vectors and matrices.

Following are representative application areas where vector processing is used are:

Long range weather forecasting.
Petroleum explorations.
Seismic data analysis.
Medical diagnosis.
AI and expert systems.
Aerodynamic and space flight simulations etc.

The vector instruction includes the initial address of the operands, the length of vectors and the operations to be performed, all in one composite instruction.

A possible instruction format for a vector instruction is given below.

Fig: Instruction format for vector processor

oThis is essentially a 3 address instruction with 3 fields specifying the base address of the operands and an address field that gives the length of the data items in the vectors.

oThis assumes that vector operands reside in the memory.

Some examples where vector processing is implemented are

Processing of vector units
Matrix multiplication
Memory interleaving
Superscalar processors
Supercomputers

1. Processing of vector units

2. Matrix multiplication - Implemented using source registers, multiplier pipeline and adder pipeline.

3. Memory interleaving - In interleaved memory, different sets of addresses are assigned to different memory modules. A vector processor that uses an n-way interleaved memory can fetch n operands from n different modules. Thus effective memory cycle time can be reduced by a factor close to the numbers of modules.

4. Superscalar processors - superscalar processor fetches, executes and returns the results from more than one instruction during a single pipeline stage. In scalar processor, processor processes one data item at a time, whereas in a vector processor, a single instruction operates simultaneously on multiple data items.

In superscalar processor, there are several functional units of same type, along with additional circuitry to dispatch instructions. Examples of superscalar processors are CDC 6600, Intel i960CA, AMD 2900 series, Pentium series etc.

5. Supercomputers - a commercial computer system with vector instructions and pipeline floating-point arithmetic operations is referred as a supercomputer. Supercomputers Cray I, Cray II, VP 200, Blue Gene etc.

Array Processing

Array processor performs computations on large arrays of data. The basic array processors are: attached array processor and SIMD array processor

a) Attached array processor

oIt is an auxiliary processor attached to a general purpose computer and its purpose is to enhance the performance of a computer by providing vector processing for complex scientific operations.

oIt achieves high performance with multiple functional units. It includes an arithmetic unit containing one or more pipelined floating point adders and multipliers.

oThe figure below shows interconnection of an attached array processor to a host computer.

Fig: Attached array processor interfacing

oHost computer is a general purpose computer and attached array processor is a back-end machine driven by the host computer. The array processor is connected through an I/O interface unit. The host computer treats the array processor as an external interface device.

oThe data for the attached processor are transferred through a high-speed bus.

b) SIMD array processor

oIt has a single instruction, multiple data organization and it manipulates vector instructions by means of multiple functional units responding to a common instruction. The figure below shows block diagram of SIMD array processor.

Fig: SIMD array processor

oIt contains a set of identical processor elements (PEs), each having a local memory M. each processor elements include an ALU, a floating point arithmetic unit and working registers. The master control unit controls the operation in the processor elements. The main memory is used for storage of the program. The function of master control unit is to decode the instructions and determine how the instruction is to be executed.

oScalar and program control units are directly executed within the master control unit. Vector instructions are broadcasted to all PEs simultaneously.

oILLIAC IV (developed by University of Illinois) is an example of SIMD array processor.

Assignments For Learners:

Flynn's Classification
Interconnection Structure