Cadence Blogs

Cadence EDA360 Theater – Customers, Partners Speak Out at DAC 2012

rgoering — Tue, 29 May 2012 13:00:00 GMT

Sometimes it's best to let other people do the talking. That's the approach Cadence has taken this year at the Design Automation Conference (DAC 2012) at the EDA360 Theater at the Cadence booth (#1930). This theater will feature three days of presentations by customers and partners in an informal, interactive setting, and all DAC attendees are welcome to attend.

The sessions, mostly a half hour in length, will include customer representatives from AMD, Broadcom, Fujitsu, LSI, Maxim, STMicroelectronics, and Xilinx. They will include partner representatives from ARM, Dini Group, Duolog, GLOBALFOUNDRIES, LeCroy, Oski, Samsung, SMIC, TSMC, and TowerJazz.

Here's the schedule at the time of this writing:

MONDAY JUNE 4

TUESDAY JUNE 5

WEDNESDAY JUNE 6

Note: The above schedules are subject to change.

For a complete list of Cadence activities at DAC, including breakfasts, lunches, demos, speakers, and the Denali Party, click here. To view the ChipEstimate.com "IP Talks!" presentations, click here. See you at DAC 2012!

Richard Goering

12 Hot EDA Topics – 78 DAC Demo Sessions

rgoering — Thu, 24 May 2012 23:30:00 GMT

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference (DAC 2012) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday, June 4, and from 9:00 am to 5:00 pm Tuesday and Wednesday, June 5 and 6. There is also a Cadence demo at the ARM Pavilion, as noted at the end of this post.

A complete demo suite schedule is available here. Below, to better help you find demos of interest, I've grouped them according to 12 general categories. These categories also happen to be hot topics in today's EDA industry.

To register for demos, click here.

1. Package/Board Aware IP

Monday 10 am, Tuesday 10 am -- Optimizing Packaged ICs for System-Level Electrical Compliance using Package-Board-Aware IP

2. 3D-IC

Tuesday 5 pm, Wednesday 10 am -- Exploring 3D-IC using IC Package-Driven Silicon Interposer Technology

Monday 10 am, Tuesday 12 noon, Wednesday 9 am -- Realizing 3D-IC Design using an Integrated IC Design Solution

3. HW/SW Integration and Co-Development

Monday 11 am, Tuesday 1 pm, Tuesday 4 pm, Wednesday 2 pm -- Virtual Prototyping for Early Software Development and System Validation using the Cadence System Development Suite

Monday 2 pm, Monday 5 pm, Tuesday 11 am, Wednesday 12 noon -- System Development Suite: HW/SW Integration and Early Software Development using the Cadence Rapid Prototyping Platform

4. Verification IP (VIP)

Monday 4 pm, Wednesday 11 am -- Accelerating SoC Development, Verification, and HW/SW Validation using the Cadence Verification IP Catalog (Featuring Accelerated Verification IP)

Monday 12 noon, Tuesday 2 pm -- Shortening IP Integration and Verification Time for SoC Development with Third-Generation Protocol Compliance using the Cadence Verification IP Catalog

Wednesday 3 pm, Tuesday 5 pm -- Verifying Advanced Memory Interfaces and Addressing System Integration within Your Existing SoC Environment using the Cadence Verification IP Catalog (Featuring Memory Models)

5. Functional Verification

Monday 2 pm, Tuesday 1 pm, Wednesday 11 am -- To UVM and Beyond! UVM-Based Advanced Verification Topics

Monday 3 pm, Tuesday 12 noon, Wednesday 1 pm, Wednesday 5 pm -- Extending Metric-Driven Verification to TLM and Leveraging High-Level Synthesis for Multi-Level Verification and Faster Hardware Design and IP Development

Monday 1 pm, Tuesday 3 pm, Wednesday 4 pm -- Leveraging the Best of Acceleration and Emulation for Rapid SoC Development and Verification

Monday 1 pm, Tuesday 12 noon, Wednesday 10 am -- Improving Debug Productivity using the New Incisive Debug Analyzer for e and SystemVerilog Testbench Verification

Wednesday 10 am -- Increasing Productivity using a Comprehensive Formal Verification Solution: Encounter Conformal Technology

6. Custom/Analog Design

Monday 9 am, Tuesday 5 pm, Wednesday 1 pm --- Addressing Throughput and Usability During the Characterization of Standard Cells, Complex I/O, and Memories

Monday 10 am, Tuesday 3 pm, Wednesday 12 noon -- Detecting and Fixing Layout-Dependent Effects using Virtuoso Technology

7. Mixed-Signal Design and Verification

Monday 9 am, Wednesday 2 pm -- Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow

Monday 12 noon, Tuesday 2 pm -- Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation

Monday 3 pm, Wednesday 4 pm -- Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs

8. Low Power Design

Monday 5 pm, Tuesday 10 am, Wednesday 3 pm -- Optimizing Power, Reducing Energy, and Meeting Schedule using an Advanced Low-Power Solution

Monday 9 am, Tuesday 1 pm -- Meeting Power Targets using a Digital Front-End Design and Verification Solution

9. 28nm/20nm and Beyond

Monday 11 am, Tuesday 4 pm, Wednesday 4 pm -- Managing Double Patterning Complexity within the Virtuoso Environment

Monday 1 pm, Wednesday 5 pm -- Realizing the Power, Performance, and Area Potential of 28/20nm Design using Encounter Digital Implementation System

Monday 2 pm, Tuesday 4 pm -- Accelerating Giga-Scale Design Schedules using Encounter Digital Implementation System

10. ECO Automation

Monday 4 pm, Tuesday 11 am, Wednesday 5 pm -- Maximizing ECO Automation and Improving Turnaround Time using Functional and Multi-Mode, Multi-Corner (MMMC) Signoff-Driven ECO Flow

11. Advanced Signoff Analysis

Monday 5 pm, Tuesday 9 am, Wednesday 3 pm -- Meeting Yield and Quality Requirements with Advanced Physical Design Signoff: Custom and Digital DFM and Physical Verification

Monday 3 pm, Tuesday 10 am, Wednesday 1 pm -- Achieving Faster Timing and Power Closure using an Advanced Digital Signoff Analysis Solution

Monday 4 pm, Tuesday 11 am, Wednesday 2 pm -- Achieving Faster Turnaround Time and Predictable Convergence using an Extracted View-Driven Electrical Signoff Flow

12. Integrating ARM Cores

Monday 11 am, Tuesday 2 pm, Wednesday 11 am -- Implementing Low-Power and High-Performance ARM® Cortex^TM Processor-Based SoCs (2 part, 2 hour presentation)

An overall view of Cadence activities at DAC 2012, including conference speakers, breakfasts, lunches, and the Denali Party, is available here.

ARM Pavilion Demo -- System-to-Silicon Solution for big.LITTLE Processor Based SoCs

In addition to the demos listed above at the Cadence booth, Cadence is offering a demo at the ARM Connected Community Pavilion (booth 802) at the Cadence "big.LITTLE System-to-Silicon" pod. The demo summarizes the System Development Suite and implementation capabilities for big.LITTLE, and highlights NIC-400 interconnect performance analysis and verification. It includes coherent fabric verification and architectural exploration. Times are:

Monday: Noon, 3 pm, and 4 pm
Tuesday: 9-Noon and 3 pm
Wednesday: 9-11 am and 3 pm

Why this demo? Multi-core heterogeneous SoCs have complex traffic interactions that impact overall system performance. Verification of these complex interconnects, with cascaded sub-system fabrics, is difficult, especially while making rapid changes to tune performance. The demo will show an automated solution for performance analysis and verification automation.

Richard Goering

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform

jasona — Thu, 24 May 2012 20:31:00 GMT

There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical USB devices. The Cadence SystemC Virtual Platform for Zynq uses either technique. One of the drawbacks I learned when using physical USB devices is the need for root permission to access the Linux device node from user space. This is required to open...(read more)

Get Started on UVM-e with Free Introductory Video Tutorials

teamspecman — Thu, 24 May 2012 17:03:00 GMT

One of the many requests that we get from Specman/e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM-e basic tutorials. Check them out.

These e-based videos are targeted for design and verification engineers who are interested in learning about the basic concepts of UVM-e and the benefits that the e language provides.

As you may know, e is an IEEE 1647 standard hardware verification language (HVL) that is tailored to implementing highly flexible and reusable verification testbenches, leading to a significant productivity improvement. e is one of the most mature verification languages, used by specialists for advanced verification. It is, therefore, the most mature in its coupling to overall verification methodology, technology, and verification IP (VIP), and it can scale to the most complex block/unit, chip, system, and project levels.

These videos provide the basics of Aspect Orient Programming (AOP) capabilities, constrained randomization, scoreboarding, etc....

So, relax, make yourself comfortable and enjoy these videos. Hopefully, these videos will excite you enough to try out the e language on your new or existing verification project and join the elite team of Specmaniacs.

Here's a list of You Tube e videos for your enjoyment!

TeamSpecman

DAC 2012: “IP Talks!” Reveals Latest in Semiconductor IP

rgoering — Thu, 24 May 2012 13:00:00 GMT

If you want to know what's new in the world of semiconductor intellectual property (IP), the place to be is at the IP Talks! presentations at the Cadence ChipEstimate.com booth at the Design Automation Conference (DAC 2012) June 4-6. Over this three-day period, from 10:00 am to 4:30 pm each day, you can attend any of 30-plus half-hour presentations from IP providers and foundries about their latest solutions.

IP Talks! presenters include (in alphabetical order) ARM, Cadence, CAST, GLOBALFOUNDRIES, Open-Silicon, Samsung, Synopsys, Silicon-IP, True Circuits, TSMC, and Xilinx. Talks will be held on the main stage in booth #1202. A full schedule is located here. As shown in the schedule, there are three presentations on Cadence verification IP (VIP) and two on Cadence design IP.

Of special note is the IP Talks! keynote speech at 11:30 am Monday, June 4, by John Heinlein, vice president of marketing for ARM's Physical IP division. He also gave the keynote last year, and talked about the "Internet of Things" as the next big wave in computing - and the source of some new demands and challenges. A blog post about this 2011 keynote speech is located here, and a photo from the talk is below.

John Heinlein keynote at IP Talks! at DAC 2011

Also at the ChipEstimate.com booth, you can see demonstrations of IP exploration and chip estimation, and discover how to estimate your next chip's size, power, and cost. One more incentive - if you come to the IP Talks! keynote, or to any talk given at 11:30 am or 3:30 pm, you can win a Bose headset or a Kindle Fire. The talks are followed by free cocktail events at 5:00 pm Monday-Wednesday.

Richard Goering

Modeling Oscillators with Arbitrary Phase Noise Profiles

Tawna — Thu, 24 May 2012 13:00:00 GMT

When you need to include noisy oscillators in SpectreRF transceiver simulations, you have at least 3 options: 1) Semi-autonomous simulation is the most accurate approach, recommended whenever the transistor-level model of the oscillator is available. 2) rfLib/osc model is less accurate but it’s well-suited for "what-if" design exploration. Since rfLib/osc uses Leeson’s noise formula, it doesn’t allow for arbitrary specification of phase noise profiles as a function of...(read more)

Managing Inherited Connections with CPF in Virtuoso

AndreasLenz — Wed, 23 May 2012 17:10:00 GMT

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

Why use CPF?

The Common Power Format (CPF) describes the design power intent for the whole flow, including digital implementation in Encounter, custom/analog implementation in Virtuoso Schematic Editor, and further into simulation. In Virtuoso Schematic XL, CPF creates the inherited connections for you in an automated way. You may want to reuse the same CPF that was used for your digital block implementation in Encounter.

What might CPF contain?
- Power domains with their shutoff conditions if applicable
- Power and ground nets
- Technology for low power: isolation cells, level-shifters (need to be registered as special cell in Virtuoso)
- Isolation, shifting and retention policy
- Power modes and analysis views
- Library sets
- Global connection

What does CPF not contain?

CPF is not a command file. It doesn't contain power domain coordinates, power routing details, number of power switches, or implementation details.

How can I handle the inherited connections ?

Within the Virtuoso IC 6.1.5 release it is possible to describe your low power intent through a CPF file. This posting describes the method according to the use model described above. Further information, including supported CPF commands, is available in the Virtuoso Schematic XL User Guide.

What are the requirements?

A consistent power intent for the analog and digital parts of your design is required. You could have explicit power pins and implicit net sets and net expressions defined in parallel. CPF will update or create the net sets and expressions.

All of the power and ground nets (PG nets) in your design should have the signal type Power or Ground. The default signal type is Signal. This might be the case if you take a closer look at your standard cell library. Power and Ground nets are very often defined as type signal. Another requirement is that your standard cell power connection must be described as an inherited connection. Before you start, make sure that the CPF created is verified for correctness using the Cadence Conformal Low Power product.

And as mentioned before, you need Schematics XL to make use of CPF.

Step by Step introduction

Setup Schematics XL

After Verilog import Open Check - Rules Setup - Inherited Connections and enable the CPF nets error switch.

To verify the signal types choose Options - Check and enable "set Signal Type from Net and Type Registration."

Applying the right signal type

As mentioned above, we need to make sure to set the right signal type. Descend in the hierarchy by double clicking on a symbol until the standard cells occur. Are your PG nets defined as inherited connections, but the signal type is Signal? If so you need to change it. Because your standard cell library usually is set to read only, we need to change the cells in your design using the register API to provide a complete list of all your PG nets (don't miss the std cell PG nets):

ciRegisterNet("power" list("VDD" "vdd" "VDD!" "VDDA" "VDDD" ....) )

ciRegisterNet("ground" list("VSS" "vss" "VSS!" "GND" "gnd" ....) )

Now check if the PG Signal type gets applied correctly:

ciGetNetNames("power") ciGetNetNames("ground")

Finally we use the Check - Hierarchy command to propagate the changes to the schematic. Don't enable save schematics since you may don't have write access to the Library

Shortcut: schHiCheckHier()

Import the CPF file

Open "File - Import Power Intend" or type schHiAddCPFNetSets() in the CIW command line to open the CPF import form. Library, Cell and View Name are already filled in. The View Name List may be changed by adopting by editing "Options - Check - Views to check.

Specify your CPF File name

Use ‘Register Special Low Power cells' for Isolation cells , Level shifter cells, Power switches, ...Use ‘Remove existing Power Intend' if you are not sure which power is defined and you want to rebuild the power connection. The alternative is to use "Edit - Power Intend - Remove netSet properties." The progress is logged in CIW and CDS.log files.

Again, the last step is to propagate the power intent through the hierarchies and we use "Check - Hierarchy."

Verify the power intent

After importing and applying the CPF file you may want to verify the created power intent. To verify the created power domains, rules, mappings ... Enable "Window - Assistant - Power Intend Export" for a review.

To verify the created inherited connections on a specific instance open "Edit- Net Expressions - Available properties" and select a block or instance.

If you want to verify the evaluated names from net expressions open "Edit- Net Expressions - Evaluated Names." In case you want to review which instances are connected to a PG net, use the Search assistant to search for a net and check the User properties.

Kind Regards,

Andreas Lenz

User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)

rgoering — Wed, 23 May 2012 13:00:00 GMT

Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs. At CDNLive! Silicon Valley 2012 Koen Lampaert, associate technical director at Broadcom, shared the results of two experiments his company ran with CCOpt.

Acquired from Azuro last year, and now available with the Encounter Digital Implementation System 11.1, the Cadence CCOpt technology uses a timing window-driven engine to optimize timing paths and clocks simultaneously. It's thus a departure from the traditional CTS approach, which focuses on minimizing skew. Potential benefits include a 10% improvement in performance and total power, 30% reduction in clock power and area, and 30% reduction in IR drop. For more information about CCOpt and how it works, see the references at the end of this post.

Broadcom has been using CCOpt for its processor designs for about two years. In the experiments described at CDNLive!, the first design was an ARM Cortex-A9 block-level core, while the second was a hierarchical dual-core Cortex-A9 design including cache. Both are taped-out cores, according to Lampaert, and they run in the GHz range. They were originally 40nm designs, but since then Broadcom has moved to more advanced nodes.

Automating Custom Design "Tricks"

Lampaert is part of the team that designs ARM microprocessors at Broadcom, and it's not an easy task. "The main challenge is that we have to design a lot of these processors," he said. "Because every business unit has its own requirements, we have to do a specific core for each business unit. Our design schedules are very tight, on the order of 6 months or so for an entire processor. So, people expect custom performance on an ASIC design schedule."

Consequentially, Lampaert said, his group has been "looking into ways of automating the tricks that designers usually apply manually." And that's a capability that CCOpt provides.

In traditional CTS, Lampaert said, designers defined the target skew and defined the buffers and inverters the tool was allowed to use. Sometimes they manually defined "useful" skews (a technique for slack redistribution) and asked the tool to implement them. However, he noted, "it is very time consuming and difficult to determine what the exact skew should be. The minute you change something in your design, you have to redo the exercise. It's really something that has to be automated."

A traditional flow will run CTS and then follow it up with a separate optimization step to fix any problems. With CCOpt, in contrast, the CTS and the optimization occur simultaneously, Lampaert noted. "It shifts the problem from just looking at a critical path to looking at an entire portion of the design. It looks at a chain of critical paths and optimizes across the entire chain. And that's the way custom designers have always looked at it. It's just that, in the ASIC design flow, that was kind of lost."

Results of CCOpt Runs

The first Broadcom experiment compared a "base run" without CCOpt to a run with CCOpt. With CCOpt, there was a 6% performance improvement versus the incumbent flow. The drop in failing endpoints from 42 to 1, Lampaert said, shows that it was a lot easier to close timing with CCOpt. Power was the same, so the main message here is that CCOpt provided higher performance without increasing power consumption.

Experiment #1 - Block-level Cortex-A9 processor core

Not shown in the above table is the IR drop reduction. Average IR drop went from 25mV without CCOpt to 21mV with CCOpt, and sigma IR drop went from 4mV without CCOpt to 3.5mV with CCOpt.

The second Broadcom experiment ran a similar comparison on a hierarchical dual-core design. Here the performance increase was 8% over the incumbent flow. The number of failing endpoints dropped dramatically, total negative slack improved, and power was essentially the same compared to the conventional flow.

Experiment #2 - Hierarchical dual-core design

Lampaert's presentation noted several other aspects of CCOpt, including a critical chain analysis report, clock tree visualization, and an ability to selectively add margin to endpoints. CCOpt is "fairly easy to use," he said. "Once you set up the libraries and the input it doesn't require a lot of intervention." In the future, he would like to see CCOpt technology extend into physical synthesis and routing.

CDNLive! Silicon Valley 2012 proceedings are available here for conference attendees.

Richard Goering

Further Information on Clock Concurrent Optimization

Industry Insights blog: Why Cadence Bought Azuro - A Closer Look

Industry Insights blog: Q&A: Former Azuro CEO Explains Clock Concurrent Optimization

Chip Design Magazine article: Clock Concurrent Optimization Reshapes IC Physical Design Flow

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

stacyw — Tue, 22 May 2012 23:26:00 GMT

This post isn't directly about tips and tricks for getting the most out of Virtuoso, but it is about a new source of information and hands-on guidance to help you put those tips and tricks into action.

They're called Rapid Adoption Kits, or--to use the obligatory Three Letter Acronym (TLA)--RAKs.

What is a Rapid Adoption Kit?

RAKs are collateral packages for a particular product area or flow which are designed to help you learn to use the tools as quickly and efficiently as possible. They center around a hands-on workshop database with a step-by-step manual so you can dive right in and start pushing buttons. They're easy to set up and let you move at your own pace.

Depending on the subject, other material may be included, such as videos or application notes.

Where can you find them?

Go to http://support.cadence.com and select Resources->Rapid Adoption Kits from the menus at the top. For Virtuoso, click on Virtuoso Custom IC and Sign-off Flow.

What's available?

As of today, there are 3 RAKs available.

Layout Design in IC 6.1.5

This material highlights new features and explores some basic functionality with Virtuoso Schematic Editor L/XL and Virtuoso Layout Suite L/XL in the 6.1.5 release. You will take a design from concept through implementation and learn how Virtuoso 6.1.5 capabilities can help you generate designs more efficiently

IC 6.1.5 Constraint Driven Custom Design

What you will learn: Use the Constraint Management System; use the Circuit Prospector for assisted constraint capture; verify constraints to ensure that design intent is met in layout; use the module generation (MODGEN) capability for precision Pcell-based array generation; perform constraint-driven wire editing; perform constraint-aware editing; perform special net automated routing (differential pair, shielding, etc.); perform full custom/analog placement.

Virtuoso Visualization & Analysis (ViVA)

What you will learn: View, configure, and export design data in a variety of formats quickly and easily; interactively analyze and annotate waveform data for design documentation; create and evaluate complex mathematical expressions, and save them for later reuse; how to efficiently handle gigabyte transient data files.

More Rapid Adoption Kits will be rolling out as time goes on. Give one a spin and let us know what you think!

Stacy Whiteman

What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to See!

Jerry GenPart — Tue, 22 May 2012 18:51:00 GMT

Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16.0, bond wires were implemented as true 3-dimensional objects in the database, and their CV were set according to their profiles.

The 16.5 release has made improvements to increase the designer’s efficiency in setting the CV attributes.

Read on for more details …

Setting the wire profile visibility in Visibility tab

With the new profile-based model, users are able to set the wire visibility in the Visibility tab. The following snapshots portray the Color form and the corresponding Visibility tab that lists wire profiles:

The list of profiles starts after the last displayed layer. The profile list is the same as that in the Color form (i.e. the profiles in the database are listed in alphabetical order). If there are no profiles, nothing is listed after the layer list. The visibility tab is scrollable such that if there are a lot of profiles to be listed, they can all be accessed through the scroll bar. The workings of the check-boxes are the same as those for the layers - the result of setting or unsetting visibility is seen directly on the canvas. There is also a check-box at the top of the profile to quickly set or unset the visibility of all profiles.

Eliminate WIRE subclass visibility setting

Since 16.0, users have found indirect ways to affect the visibility of wires without going through the profile interface. In 16.5, we made the following changes in various areas of the tool:

Hide the WIRE subclass check-box in the Color form and the Color command form so that users cannot directly manipulate the visibility of this subclass.
Ensure that changes in WIRE subclass visibility from other applications get reflected to the profile visibility as well.

Setting Wire DRC visibility in Visibility tab

You can now set the visibility setting of the Wire DRC directly in the Visibility tab. This check-box is similar to the one in the Color Form:

Being able to toggle this check-box in the Visibility tab allows for faster access to display or undisplay Wire DRCs in the canvas; toggling it OFF (background color) will undisplay all the Wire DRC markers (regardless of profiles), and toggling it ON (with the selected Wire DRC color) will show all those markers.

I look forward to your comments.

Jerry "GenPart" Grzenia