<?xml version="1.0" encoding="UTF-8"?>
<?xml-stylesheet type="text/xsl" media="screen" href="/~d/styles/rss2full.xsl"?><?xml-stylesheet type="text/css" media="screen" href="http://feeds.feedburner.com/~d/styles/itemcontent.css"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:media="http://search.yahoo.com/mrss/" xmlns:itunes="http://www.itunes.com/dtds/podcast-1.0.dtd" xmlns:feedburner="http://rssnamespace.org/feedburner/ext/1.0" version="2.0"><channel><title>Cadence Custom IC Design Blogs</title><link>http://www.cadence.com/Community/blogs/cic/default.aspx</link><description>The Custom IC Design blog is tailored...</description><dc:language>en</dc:language><generator>CommunityServer 2007.1 (Build: 20917.1142)</generator><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="self" type="application/rss+xml" href="http://feeds.feedburner.com/cadence/community/blogs/cic" /><feedburner:info uri="cadence/community/blogs/cic" /><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="hub" href="http://pubsubhubbub.appspot.com/" /><itunes:explicit>no</itunes:explicit><itunes:subtitle>The Custom IC Design blog is tailored...</itunes:subtitle><feedburner:emailServiceId>cadence/community/blogs/cic</feedburner:emailServiceId><feedburner:feedburnerHostname>http://feedburner.google.com</feedburner:feedburnerHostname><feedburner:feedFlare href="http://add.my.yahoo.com/rss?url=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://us.i1.yimg.com/us.yimg.com/i/us/my/addtomyyahoo4.gif">Subscribe with My Yahoo!</feedburner:feedFlare><feedburner:feedFlare href="http://www.newsgator.com/ngs/subscriber/subext.aspx?url=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://www.newsgator.com/images/ngsub1.gif">Subscribe with NewsGator</feedburner:feedFlare><feedburner:feedFlare href="http://feeds.my.aol.com/add.jsp?url=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://o.aolcdn.com/favorites.my.aol.com/webmaster/ffclient/webroot/locale/en-US/images/myAOLButtonSmall.gif">Subscribe with My AOL</feedburner:feedFlare><feedburner:feedFlare href="http://www.bloglines.com/sub/http://feeds.feedburner.com/cadence/community/blogs/cic" src="http://www.bloglines.com/images/sub_modern11.gif">Subscribe with Bloglines</feedburner:feedFlare><feedburner:feedFlare href="http://www.netvibes.com/subscribe.php?url=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://www.netvibes.com/img/add2netvibes.gif">Subscribe with Netvibes</feedburner:feedFlare><feedburner:feedFlare href="http://fusion.google.com/add?feedurl=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://buttons.googlesyndication.com/fusion/add.gif">Subscribe with Google</feedburner:feedFlare><feedburner:feedFlare href="http://www.pageflakes.com/subscribe.aspx?url=http%3A%2F%2Ffeeds.feedburner.com%2Fcadence%2Fcommunity%2Fblogs%2Fcic" src="http://www.pageflakes.com/ImageFile.ashx?instanceId=Static_4&amp;fileName=ATP_blu_91x17.gif">Subscribe with Pageflakes</feedburner:feedFlare><item><title>SKILL for the Skilled: Part 9, Many Ways to Sum a List </title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/F35WlUO-m7Y/skill-for-the-skilled-many-ways-to-sum-a-list-part-9.aspx</link><pubDate>Wed, 22 May 2013 16:00:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1321818</guid><dc:creator>Team SKILL</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1321818</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/05/22/skill-for-the-skilled-many-ways-to-sum-a-list-part-9.aspx#comments</comments><description>In the previous postings of &lt;i&gt;SKILL for the Skilled&lt;/i&gt;, we&amp;#39;ve looked at different ways to sum the elements of a list of numbers. In this posting, we&amp;#39;ll look at at least one way to NOT sum a list. &lt;p&gt;In&amp;nbsp;my &lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2013/04/23/skill-for-the-skilled-many-ways-to-sum-a-list-part-8.aspx"&gt;most&amp;nbsp;recent posting&lt;/a&gt;, the particular subject was how to use SKILL++ to define a &lt;code&gt;make_adder&lt;/code&gt; function. I commented in that article that the same thing would not work in traditional SKILL. In this posting, I&amp;#39;d like to walk through some of the issues you would encounter if you actually tried to implement this&amp;nbsp;in traditional SKILL. Understanding why it does not work in the traditional SKILL dialect may shed some light on why it does work in the SKILL++ dialect. &lt;/p&gt;&lt;p&gt;Remember, these are not bugs in any sense in SKILL. The fact simply is that in some subtle ways traditional SKILL and SKILL++ behave differently. You can exploit the differences to your advantage, depending on your particular application. &lt;/p&gt;&lt;p&gt;Recall, here is the definition of &lt;code&gt;make_adder_8a&lt;/code&gt; as you might type it into the CIWindow. &lt;/p&gt;&lt;pre&gt;(unless (theEnvironment)
   (toplevel &amp;#39;ils))

(defun make_adder_8a ()   ; 1.1
  (let ((sum 0))          ; 1.2
    (lambda (n)           ; 1.3
      sum = sum + n)))    ; 1.4
&lt;/pre&gt;&lt;h4&gt;Try it in traditional SKILL&lt;/h4&gt;What happens if you try to define the &lt;code&gt;make_adder_9a&lt;/code&gt; in traditional SKILL? Here is what will happen when you try to call the function. &lt;pre&gt;(when (theEnvironment)
  (resume))

(defun make_adder_9a ()  ; 2.1
  (let ((sum 0))         ; 2.2
    (lambda (n)          ; 2.3
      sum = sum + n)))   ; 2.4
&lt;/pre&gt;&lt;p&gt;You see immediately that something very subtle is &lt;i&gt;different&lt;/i&gt;. &lt;/p&gt;&lt;pre&gt;C = (make_adder_9a)
&lt;i&gt;  ==&amp;gt; funobj@0x1e666390&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;The &lt;code&gt;make_adder_9a&lt;/code&gt; function, when defined in traditional SKILL, returns an object which is printed something like &lt;code&gt;funobj@0x1e666390&lt;/code&gt;. Contrast that with the SKILL++ version of the function &lt;code&gt;make_adder_8a&lt;/code&gt; defined above, which returned an object which was printed as &lt;code&gt;funobj:A&lt;/code&gt;. What happens if we try to call the function we just created? &lt;/p&gt;&lt;pre&gt;(C 1)
&lt;i&gt;
*Error* eval: undefined function - C
&amp;lt;&amp;lt;&amp;lt; Stack Trace &amp;gt;&amp;gt;&amp;gt;
C(1)
&lt;/i&gt;
&lt;/pre&gt;A drastic difference is obvious when you try to call the function, &lt;code&gt;C&lt;/code&gt;. You have an error message indicating that &lt;code&gt;C&lt;/code&gt; is not a function. This can be confusing to the beginner SKILL++ programmer. The reason for this is that the CIWindow is in SKILL listening mode. A similar thing happens if loading code from a file with a .il file name extension as opposed to a .ils extension. &lt;p&gt;For a discussion of changing the CIWindow listening mode between SKILL and SKILL++, see &lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2013/04/23/skill-for-the-skilled-many-ways-to-sum-a-list-part-8.aspx"&gt;SKILL for the Skilled: Part 8, Many Ways to Sum a List,&lt;/a&gt;&amp;nbsp;or consult the Cadence SKILL documentation for the &lt;code&gt;toplevel&lt;/code&gt; and &lt;code&gt;resume&lt;/code&gt;. &lt;/p&gt;&lt;h4&gt;Setting a variable in SKILL&lt;/h4&gt;When the CIWindow is in SKILL listening mode an expression such as &lt;pre&gt;C = (make_adder_9a)
&lt;/pre&gt;modifies (or initially defines) a global variable named &lt;code&gt;C&lt;/code&gt; to be the value returned from the &lt;code&gt;make_adder_9a&lt;/code&gt; function. An expression such as &lt;pre&gt;(defun C ()
  (println &amp;#39;(1 2 3 4)))
&lt;/pre&gt;defines a global function named &lt;code&gt;C&lt;/code&gt;. Critically important to how traditional SKILL works is that the variable &lt;code&gt;C&lt;/code&gt; and the function C are different and independent. Either one can be referenced, or modified independent of the other. This is both a feature of SKILL as well as a point of confusion. &lt;p&gt;In SKILL mode the following expressions are semantically equivalent in setting the value of the variable &lt;code&gt;C&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;C = (make_adder_9a)
(setq C (make_adder_9a))
(set &amp;#39;C (make_adder_9a))
&lt;/pre&gt;&lt;p&gt;The following expressions are equivalent in defining the function &lt;code&gt;C&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;(defun C ()
  (println &amp;#39;(1 2 3 4)))

(procedure (C)
  (println &amp;#39;(1 2 3 4)))

(putd &amp;#39;C
  (lambda ()
    (println &amp;#39;(1 2 3 4))))
&lt;/pre&gt;&lt;h4&gt;Setting a variable in SKILL++&lt;/h4&gt;By contrast when the CIWindow is in SKILL++ mode, an expression such as &lt;code&gt;A = (make_adder_8a)&lt;/code&gt; (shown above) not only sets the global variable named &lt;code&gt;A&lt;/code&gt;, but also defines a global function named &lt;code&gt;A&lt;/code&gt;. If you then proceed to evaluate an expression such as &lt;pre&gt;(defun A ()
  (println &amp;#39;(1 2 3 4)))
&lt;/pre&gt;&lt;p&gt;the global variable, &lt;code&gt;A&lt;/code&gt; and the global function &lt;code&gt;A&lt;/code&gt; will be modified to something new, and the old value will be lost (unless of course you have saved a reference to it). &lt;/p&gt;&lt;p&gt;SKILL++ does not support having a global variable and global function of the same name with different values. &lt;/p&gt;&lt;p&gt;In SKILL++ mode all the following expressions are equivalent in setting the global variable and simultaneously defining the global function named &lt;code&gt;C&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;(defun C ()
  (println &amp;#39;(1 2 3 4)))

(procedure (C)
  (println &amp;#39;(1 2 3 4)))

(define (C)
  (println &amp;#39;(1 2 3 4)))

(define C
  (lambda ()
    (println &amp;#39;(1 2 3 4))))

(setq C
  (lambda ()
    (println &amp;#39;(1 2 3 4))))

(putd &amp;#39;C
  (lambda ()
    (println &amp;#39;(1 2 3 4))))
&lt;/pre&gt;&lt;h4&gt;LISP-1 vs LISP-2&lt;/h4&gt;Another way to think about the different semantics of variables and functions between SKILL and SKILL++ is that SKILL++ is a &lt;i&gt;LISP-1&lt;/i&gt; and traditional SKILL is a &lt;i&gt;LISP-2&lt;/i&gt;. LISP-1 means that there is one single &lt;i&gt;name space&lt;/i&gt; for variables and functions. LISP-2 means that there are two different names spaces, one for variables and one for functions. &lt;h4&gt;Use funcall to call a function indirectly&lt;/h4&gt;To call a function, in SKILL mode, whose value is stored in a variable (global or otherwise), you need to use &lt;code&gt;funcall&lt;/code&gt;. If you use &lt;code&gt;funcall&lt;/code&gt; to call the function whose value is in the global variable &lt;code&gt;D&lt;/code&gt;, the function is indeed called but quickly encounters an error. &lt;pre&gt;D = (make_adder_9a)
&lt;i&gt;  ==&amp;gt; funobj@0x1e666390&lt;/i&gt;
(funcall D 1)
*Error* eval: unbound variable - sum
&amp;lt;&amp;lt;&amp;lt; Stack Trace &amp;gt;&amp;gt;&amp;gt;
(sum + n)
(sum = (sum + n))
funobj@0x1e666390()
funcall(D 1)
&lt;/pre&gt;&lt;p&gt;For some reason, the definition of the adder created by &lt;code&gt;make_adder_9a&lt;/code&gt;, tries to reference a global variable named &lt;code&gt;sum&lt;/code&gt;. Let&amp;#39;s ignore this error momentarily, and assume we already &lt;i&gt;accidentally&lt;/i&gt; had a global variable named &lt;code&gt;sum&lt;/code&gt; whose value happened to be &lt;code&gt;0&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;sum = 0
&lt;i&gt;  ==&amp;gt; 0&lt;/i&gt;
D = (make_adder_9a)
&lt;i&gt;  ==&amp;gt; funobj@0x1e666390&lt;/i&gt;
(funcall D 1)
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(funcall D 2)
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(funcall D 3)
&lt;i&gt;  ==&amp;gt; 6&lt;/i&gt;
(funcall D 4)
&lt;i&gt;  ==&amp;gt; 10&lt;/i&gt;
(funcall D 5)
&lt;i&gt;  ==&amp;gt; 15&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;This requirement of having to use &lt;code&gt;funcall&lt;/code&gt; when calling a function indirectly is inherent to the way traditional SKILL works. &lt;/p&gt;&lt;p&gt;From the above experiment it deceptively seems that the SKILL function &lt;code&gt;make_adder_9a&lt;/code&gt; behaves much the same as &lt;code&gt;make_adder_8a&lt;/code&gt; with the exception of the calling syntax: &lt;code&gt;(funcall D 1)&lt;/code&gt; vs &lt;code&gt;(A 1)&lt;/code&gt;. &lt;/p&gt;&lt;h4&gt;A second SKILL adder fails&lt;/h4&gt;In the previous post, we used &lt;code&gt;make_adder_8a&lt;/code&gt; to define adders &lt;code&gt;B1&lt;/code&gt;, &lt;code&gt;B2&lt;/code&gt;, and &lt;code&gt;B3&lt;/code&gt;. We saw that all three adders kept track of their partial sum independently. What happens if we try to define even one additional adder using &lt;code&gt;make_adder_8b&lt;/code&gt;? &lt;pre&gt;E = (make_adder_9a)
&lt;i&gt;  ==&amp;gt; funobj@0x1e666390&lt;/i&gt;
(funcall E 1)
&lt;i&gt;  ==&amp;gt; 16&lt;/i&gt;
(funcall E 2)
&lt;i&gt;  ==&amp;gt; 18&lt;/i&gt;
(funcall E 3)
&lt;i&gt;  ==&amp;gt; 21&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;Hey wait! Why did &lt;code&gt;(funcall E 1)&lt;/code&gt; return &lt;code&gt;16&lt;/code&gt;? Let&amp;#39;s set the global &lt;code&gt;sum&lt;/code&gt; back to &lt;code&gt;0&lt;/code&gt; and try it again. &lt;/p&gt;&lt;pre&gt;sum = 0
&lt;i&gt;  ==&amp;gt; 0&lt;/i&gt;
(funcall E 1)
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(funcall E 2)
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(funcall E 3)
&lt;i&gt;  ==&amp;gt; 6&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;OK, setting &lt;code&gt;sum&lt;/code&gt; back to &lt;code&gt;0&lt;/code&gt; fixes it. Now, look again at &lt;code&gt;D&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;(funcall D 1)
&lt;i&gt;  ==&amp;gt; 7&lt;/i&gt;
(funcall E 2)
&lt;i&gt;  ==&amp;gt; 9&lt;/i&gt;
(funcall D 3)
&lt;i&gt;  ==&amp;gt; 12&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;It seems that &lt;code&gt;D&lt;/code&gt; and &lt;code&gt;E&lt;/code&gt; are both using the same variable to keep track of the partial sum. In fact, if you print the value of the variable &lt;code&gt;sum&lt;/code&gt; you&amp;#39;ll see that its value is now &lt;code&gt;12&lt;/code&gt;. &lt;/p&gt;&lt;h4&gt;Why does this fail?&lt;/h4&gt;In SKILL mode, the two adders, &lt;code&gt;D&lt;/code&gt; and &lt;code&gt;E&lt;/code&gt;, created by two different calls to &lt;code&gt;make_adder_9a&lt;/code&gt; do not create two independent adders as did &lt;code&gt;make_adder_8a&lt;/code&gt; in SKILL++ mode. The reason for this is critical to an important difference between SKILL and SKILL++. Look at lines 1.2, 1.3, and 1.4 of &lt;code&gt;make_adder_8a&lt;/code&gt; and 2.1, 2.3, and 2.4 of &lt;code&gt;make_adder_9a&lt;/code&gt;. While these lines are textually identical, they are semantically different in that &lt;code&gt;make_adder_8a&lt;/code&gt; is SKILL++ and &lt;code&gt;make_adder_9a&lt;/code&gt; is traditional SKILL. &lt;h4&gt;Low level details of calling a SKILL function&lt;/h4&gt;Suppose &lt;code&gt;make_adder_8a&lt;/code&gt; is called twice on line 3.1 and 3.4. Each time it is called, line 1.2 allocates a new binding which associates the variable &lt;code&gt;sum&lt;/code&gt; with a location to store the value. The two functions created on line 1.3 each time &lt;code&gt;make_adder_8a&lt;/code&gt; is called (lines 3.1 and 3.2), reference those respective bindings. You can see from line 3.3, that each time make_adder_8a is called, a different function is returned. &lt;p&gt;The textual reference to &lt;code&gt;sum&lt;/code&gt; on line 1.4 references and modifies the value in the location of binding depending on which of the functions it is running from. When lines 3.4, and 3.5 are evaluted, line 1.4 references and modifies the first binding which was created as a result of evaluating line 3.1. Likewise, when lines 3.6, and 3.7 are evaluted, the same line 1.4 references and modifies the second binding which was created as a result of evaluating line 3.2. &lt;/p&gt;&lt;pre&gt;A = (make_adder_8a)      ; 3.1
&lt;i&gt;  ==&amp;gt; funobj:A&lt;/i&gt;
B = (make_adder_8a)      ; 3.2
&lt;i&gt;  ==&amp;gt; funobj:B&lt;/i&gt;
(eq A B)                 ; 3.3
&lt;i&gt;  ==&amp;gt; nil&lt;/i&gt;
(A 1)                    ; 3.4
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(A 2)                    ; 3.5
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(B 11)                   ; 3.6
&lt;i&gt;  ==&amp;gt; 11&lt;/i&gt;
(B 22)                   ; 3.7
&lt;i&gt;  ==&amp;gt; 33&lt;/i&gt;
&lt;/pre&gt;&lt;h4&gt;Low level details of calling a SKILL++ function&lt;/h4&gt;Constrast that with the very different scenaraio which what happens in &lt;code&gt;make_adder_9a&lt;/code&gt;. In this case when &lt;code&gt;make_adder_9a&lt;/code&gt; is called (lines 4.1 and 4.2), each time a binding is created (because the &lt;code&gt;let&lt;/code&gt; on line 2.2 is evaluated twice), but the local function created on line 2.3 DOES NOT any explicitly reference it. In fact both times &lt;code&gt;make_adder_9a&lt;/code&gt; is called (lines 4.1 and 4.2), the exact same function is returned as seen on line 4.3. &lt;p&gt;When &lt;code&gt;make_adder_9a&lt;/code&gt; returns the SKILL local function created on line 1.3, the call to &lt;code&gt;make_adder_9a&lt;/code&gt; returns and all references to the binding created on line 2.2 are subsequently lost. Thereafter, when the function &lt;code&gt;D&lt;/code&gt; or &lt;code&gt;E&lt;/code&gt; is called, SKILL (at calling time) searches for the currently defined variable named &lt;code&gt;sum&lt;/code&gt; which is global. &lt;/p&gt;&lt;pre&gt;D = (make_adder_9a)      ; 4.1
&lt;i&gt;  ==&amp;gt; funobj:@0x1e666390&lt;/i&gt;
E = (make_adder_9a)      ; 4.2
&lt;i&gt;  ==&amp;gt; funobj:@0x1e666390&lt;/i&gt;
(eq D E)                 ; 4.3
&lt;i&gt;  ==&amp;gt; t&lt;/i&gt;
(D 1)                    ; 4.4
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(D 2)                    ; 4.5
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(E 11)                   ; 4.6
&lt;i&gt;  ==&amp;gt; 11&lt;/i&gt;
(E 22)                   ; 4.7
&lt;i&gt;  ==&amp;gt; 33&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;Calling the functions stored in &lt;code&gt;D&lt;/code&gt; and &lt;code&gt;E&lt;/code&gt; (on lines 4.4 through 4.7) have much the same effect as directly evaluating a call to a copy of the inline function shown on lines 1.3 and 1.4. For example, lines 4.5 and 4.6 &lt;code&gt;(D 2)&lt;/code&gt; and &lt;code&gt;(E 11)&lt;/code&gt;, are equivalent to the following which has the effect of referencing and modifying the global variable named &lt;code&gt;sum&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;(funcall (lambda (n) sum = sum + n)
         2)
(funcall (lambda (n) sum = sum + n)
         11)
&lt;/pre&gt;&lt;h4&gt;Summary&lt;/h4&gt;In this article we looked at several differences between SKILL and SKILL++. &lt;ol&gt;&lt;li&gt;&lt;code&gt;funcall&lt;/code&gt; -- How to call functions indirectly. &lt;ul&gt;&lt;li&gt;SKILL -- You must use funcall: &lt;code&gt;(funcall C 1)&lt;/code&gt; &lt;/li&gt;&lt;li&gt;SKILL++ -- You may call the function directly: &lt;code&gt;(A 1)&lt;/code&gt; &lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt;name-space -- &lt;ul&gt;&lt;li&gt;SKILL -- functions and variables live in different names-spaces; the function &lt;code&gt;C&lt;/code&gt; and the variable &lt;code&gt;C&lt;/code&gt; are different. &lt;/li&gt;&lt;li&gt;SKILL++ -- supports a single name-space; function &lt;code&gt;A&lt;/code&gt; and the variable &lt;code&gt;A&lt;/code&gt; are the same. &lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt;closures -- how free variables are handled &lt;ul&gt;&lt;li&gt;SKILL -- does not support closures; a free variable is resolved at run-time and may resolve differently depending on how a function is called. &lt;/li&gt;&lt;li&gt;SKILL++ -- supports closures ; a free variable is resolved at compile time, and refers to the same allocated location no matter how the functions references them are called. &lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;/ol&gt;&lt;h4&gt;Feedback&lt;/h4&gt;Please let me know if you find any of the discussion or techniques discussed in this or previous articles useful. &lt;p&gt;Thanks for reading!&lt;/p&gt;&lt;p&gt;Jim Newton&amp;nbsp;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1321818" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=F35WlUO-m7Y:njgm19M-Uxo:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/F35WlUO-m7Y" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL/default.aspx">SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Team+SKILL/default.aspx">Team SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/programming/default.aspx">programming</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/LISP/default.aspx">LISP</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL_2B002B00_/default.aspx">SKILL++</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/summing/default.aspx">summing</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/sum+a+list/default.aspx">sum a list</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Jim+Newton/default.aspx">Jim Newton</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL+for+the+Skilled/default.aspx">SKILL for the Skilled</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/05/22/skill-for-the-skilled-many-ways-to-sum-a-list-part-9.aspx</feedburner:origLink></item><item><title>Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/dSQ7Fo6tb0w/virtuosity-10-things-i-learned-in-april-by-browsing-cadence-online-support.aspx</link><pubDate>Mon, 13 May 2013 20:41:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1323579</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1323579</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/05/13/virtuosity-10-things-i-learned-in-april-by-browsing-cadence-online-support.aspx#comments</comments><description>&lt;p&gt;I&amp;#39;ll confess: I didn&amp;#39;t learn all of this strictly by browsing &lt;a href="http://support.cadence.com/"&gt;http://support.cadence.com&lt;/a&gt; (Cadence Online Support).&amp;nbsp; I also wandered over onto &lt;a href="http://www.cadence.com/community/blogs/ii"&gt;http://www.cadence.com/community/blogs/ii&lt;/a&gt;&amp;nbsp;(Industry Insights blog) and &lt;a href="http://www.cadence.com/cadence/events"&gt;http://www.cadence.com/cadence/events&lt;/a&gt; (Cadence Events), which were well worth a look.&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;b&gt;Application&lt;/b&gt; &lt;b&gt;Note&lt;/b&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;1. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/ncelab_err.pdf" target="_blank"&gt;Demystifying NCELAB&lt;/a&gt;&lt;/p&gt;&lt;p&gt;You&amp;#39;ve gotta love any technical document that begins with the word &amp;quot;demystifying&amp;quot;.&amp;nbsp; Explains typical causes of and solutions for elaboration errors frequently encountered in running a digital or mixed-signal design using AMS Designer.&amp;nbsp; Organized by error code.&amp;nbsp; Includes descriptions, examples, solutions, and accompanying database.&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;u&gt;Videos&lt;/u&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;2. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Custom_IC_Design/vdn/Running_Monte-Carlo_simulations_with_AMS_in_ADE-XL.htm" target="_blank"&gt;Running Monte-Carlo Simulations with AMS in ADE-XL&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Computer-narrated video describing how to set up and run Monte Carlo simulations using the AMS simulator in ADE XL&lt;/p&gt;&lt;p&gt;3.&lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Training/Custom_IC_Design/ils/ConnExtractFmLabels/ConnExtractFmLabels.html" target="_blank"&gt; Virtuoso Connectivity-Driven Layout Solution Segment--Connectivity Extraction from Labels&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Video segment from a Cadence physical design training course demonstrating extracting connectivity from labels&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;u&gt;Blog&lt;/u&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;4. &lt;a href="http://www.cadence.com/Community/blogs/ii/archive/2013/04/04/cdnlive-silicon-valley-2013-proceedings-available-for-download.aspx?postID=1322320" target="_blank"&gt;CDNLive Silicon Valley 2013 Proceedings Available for Download&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Over 80 downloadable presentations from customers and partners discussing how they have used Cadence tools to solve real problems.&amp;nbsp; Custom IC, mixed signal, low power, advanced node--you name it, you can find something interesting to learn about.&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;u&gt;Rapid Adoption Kit&lt;/u&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;5. &lt;a href="http://support.cadence.com/wps/myportal/cos/!ut/p/c5/dY1bcoIwAEXX4gKchJBS-Iy8izgIlEd-mACGUknC0NYKq69dgPd8n3MBBQ8ku40D-x6VZBOoADUaDfm2FmFoQWwZEBVeHOPI1iHRQPlvGA18MgJBDejr08IZgUKqRTyeclAFnbg7Kh7c0Pk4NaE_rTROFcv6T6fvbNfN9SUl-LzxSm9bud8HiNWema_zMTtMlRp5VBUkoTmXgshyvmwjEUsrVs-c31itrlz2oj-o9s4y_13WUbPdXr4SEeZ0Sn8s_tslPEZH5A2laVU6xstq7sApUOIC5qvcPJPs_gBAWQEM/dl3/d3/L2dBISEvZ0FBIS9nQSEh/" target="_blank"&gt;Digital Mixed-Signal (DMS) Implementation Using EDI and Virtuoso&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Reaching out to our colleagues in the digital world.&amp;nbsp; Learn about design import, early timing analysis, pin optimization, AoT block design, and top-level timing analysis.&amp;nbsp; Includes database and &lt;a href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Digital_IC_Design/ApplicationPackages/download/DMS_DEMO_labs.pdf" target="_blank"&gt;detailed workshop instructions&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;u&gt;Webinars&lt;/u&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;6. &lt;a href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=771" target="_blank"&gt;TSMC-Cadence Webinars for Advanced Node Design: Addressing Layout-Dependent Effects&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Archived webinar discussing the TSMC Custom Design Reference Flow 3.0, which provides a complete layout-dependent effect (LDE) flow for circuit and layout designers working at 28nm and below.&lt;/p&gt;&lt;p&gt;7. &lt;a href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=772" target="_blank"&gt;A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Tools&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Upcoming webinar scheduled for May 23, 2013.&amp;nbsp; &lt;font size="2"&gt;Learn about how in-design design rule checking (DRC) and double patterning technology (DPT) checking can improve productivity; how to efficiently manage coloring data in front-to-back custom design flows; how local interconnect layers are supported within the Cadence Virtuoso platform, and how TSMC&amp;rsquo;s 20nm process technology and the Cadence methodology support this process.&lt;/font&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;u&gt;Solutions&lt;/u&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;8. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ILS/aepatchdb.html" target="_blank"&gt;Recommended platform patches for systems running Cadence products&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Not much description needed for this one.&amp;nbsp; Always a handy table of information to have.&lt;/p&gt;&lt;p&gt;9.&lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20088153;searchHash=fd43ecca6eaa2f333b34e9f441b3fe19" target="_blank"&gt; Fluid Guardring changes shape with newer version of Virtuoso&lt;/a&gt;&lt;/p&gt;&lt;p&gt;How to prevent Fluid Guardrings from changing shapes and spacings with changes to your Virtuoso version.&lt;/p&gt;&lt;p&gt;10. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11773268;searchHash=4e8aa8ebd2d85793e1d7e2a0b6f2c14d" target="_blank"&gt;How to keep ADE XL jobs running even if ADE XL GUI crashes&lt;/a&gt;&lt;/p&gt;&lt;p&gt;New environment variable in ADE XL, which allows you to close the ADE XL or Virtuoso session without killing jobs that are currently running.&amp;nbsp; Also works if Virtuoso crashes.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1323579" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=dSQ7Fo6tb0w:jnWxo-l5jgA:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/dSQ7Fo6tb0w" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso/default.aspx">Virtuoso</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/mixed+signal/default.aspx">mixed signal</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/AMS/default.aspx">AMS</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/custom_2F00_analog/default.aspx">custom/analog</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Rapid+Adoption+Kit/default.aspx">Rapid Adoption Kit</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/layout-dependent+effects/default.aspx">layout-dependent effects</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/20nm/default.aspx">20nm</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuosity/default.aspx">Virtuosity</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/05/13/virtuosity-10-things-i-learned-in-april-by-browsing-cadence-online-support.aspx</feedburner:origLink></item><item><title>Things You Didn't Know About Virtuoso: Delta Markers in ViVA</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/H8QA8izwUgs/things-you-didn-t-know-about-virtuoso-delta-markers-in-viva.aspx</link><pubDate>Thu, 09 May 2013 18:10:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1322677</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1322677</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/05/09/things-you-didn-t-know-about-virtuoso-delta-markers-in-viva.aspx#comments</comments><description>&lt;p&gt;This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while back who Is a CAD engineer busily supporting a large user community, but had been stumped by the question &lt;strong&gt;&amp;quot;How do I create a delta marker in VIVA?&amp;quot;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;I&amp;#39;m sure he is not alone.&amp;nbsp; Delta markers in IC6.1.5 ViVA (Virtuoso Visualization and Analysis Tool)&amp;nbsp;are very powerful, but they can be a bit hard to find and unless you read the documentation (or this blog), you may never unlock all their useful capabilities.&amp;nbsp; That&amp;#39;s what I&amp;#39;m here for...&lt;/p&gt;&lt;p&gt;Note that the method for creating delta markers changed in IC6.1.5 ISR8, so if the instructions below doesn&amp;#39;t work for you, you may need to update your Virtuoso version.&lt;/p&gt;&lt;p&gt;First, I want to direct your attention to a handy little document I put together a while ago which provides a &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/viva_bindkeys.pdf"&gt;1-page Quick Reference&lt;/a&gt; to the most useful bindkeys in ViVA.&amp;nbsp; Markers in ViVA are all about bindkeys, and for delta markers, you have to know just where and in what combination to use those bindkeys.&lt;/p&gt;&lt;p&gt;The basic summary goes like this:&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;M for point marker&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;V for vertical marker&amp;nbsp;&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;H for horizontal marker&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;A/B for a/b marker (special kind of delta marker--see below)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;&lt;div&gt;Shift-D for delta&amp;#39;s amongst selected markers (details below)&lt;/div&gt;&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;D for create 2nd marker and delta (details below)&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;strong&gt;A/B Markers&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;This is a special kind of delta marker.&amp;nbsp; To create it, press A somewhere, then B somewhere else.&amp;nbsp; You&amp;#39;ll get 2 point markers labelled A and B and a delta label between them.&amp;nbsp; Now, wherever you press A or B again, the original A or B marker will move to that spot and the delta values will update.&amp;nbsp; Only one A/B marker allowed per window, but you can click the right mouse button (RMB) on the delta dimension line and select &amp;quot;Convert A/B Marker to Delta&amp;quot; so you can keep that information on the graph and continue playing the A/B game at another location.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Shift-D&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;If you have put down a bunch of markers (point, vertical, horizontal), you can &lt;strong&gt;select 2 or more&lt;/strong&gt; of them (using Ctrl-click to select multiple markers) and &lt;strong&gt;then&lt;/strong&gt; &lt;strong&gt;press Shift-D&lt;/strong&gt; to get delta markers between all the selected markers.&amp;nbsp; The cool thing about this is that you can mix point markers with vertical or horizontal markers to get delta values from a point to a line.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Bindkey D&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;This will probably be your most commonly-used method of creating delta markers.&amp;nbsp; Simply&lt;strong&gt; select a point, vertical or horizontal marker&lt;/strong&gt; (M, V, H) and then wherever you &lt;strong&gt;press the D key&lt;/strong&gt;, you will get a 2nd marker &lt;strong&gt;of that type&lt;/strong&gt; and the delta between.&amp;nbsp; Since when you create a point, vertical or horizontal marker, it remains selected, you can use the sequence&amp;nbsp;M, D, D, D... or V, D, D, D... or H, D, D, D... to get multiple markers with delta values between them with just a few keystrokes.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;A few extra tips&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Use the menu pick &lt;strong&gt;Marker-&amp;gt;Show Delta Child Labels&lt;/strong&gt; (or RMB in a blank area of the graph-&amp;gt;Show Delta Child Labels) to toggle the visibility of the point marker labels at either end of the delta and only display the delta values. (IC6.1.5 ISR12)&amp;nbsp; Helps reduce clutter on the graph.&lt;/p&gt;&lt;p&gt;Delta values&amp;nbsp;between vertical markers&amp;nbsp;now show up in the Vertical Marker table (IC6.1.5ISR12).&amp;nbsp; Choose &lt;strong&gt;Window-&amp;gt;Assistants-&amp;gt;Vert Marker Table&lt;/strong&gt; or use the built-in MarkerTable workspace to open the marker table.&amp;nbsp; You can use Marker-&amp;gt;Export-&amp;gt;Vertical Markers to create a CSV file with all the marker values.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Watch them in action&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;If any of the above is not clear, watching this video clip should help.&amp;nbsp; Note that this short clip is part of a longer video available &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Custom_IC_Design/IC615_viva_markers/viva_615_markersCOS.htm;searchHash=9580cae608f8485b896cd38aea89b5ba"&gt;here&lt;/a&gt;, covering everything you need to know about using all types of markers in ViVA. If video fails to open, &lt;a href="http://www.youtube.com/watch?v=f6ofkBwVhzw&amp;amp;feature=youtu.be"&gt;click here.&lt;/a&gt;&lt;/p&gt;&lt;p&gt;&lt;/p&gt;&lt;p&gt;Stacy Whiteman&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1322677" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=H8QA8izwUgs:whfpiIurF4s:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/H8QA8izwUgs" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ViVa-XL/default.aspx">ViVa-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1.5/default.aspx">IC 6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+IC6.1.5/default.aspx">Virtuoso IC6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog+Design+Environment/default.aspx">Analog Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Viva/default.aspx">Viva</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog++Design+Environment/default.aspx">Analog  Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/delta+markers/default.aspx">delta markers</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/05/09/things-you-didn-t-know-about-virtuoso-delta-markers-in-viva.aspx</feedburner:origLink></item><item><title>SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with State)</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/2hG8j-eptE0/skill-for-the-skilled-many-ways-to-sum-a-list-part-8.aspx</link><pubDate>Tue, 23 Apr 2013 13:21:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1321806</guid><dc:creator>Team SKILL</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1321806</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/04/23/skill-for-the-skilled-many-ways-to-sum-a-list-part-8.aspx#comments</comments><description>&lt;p&gt;In the &lt;a href="http://www.cadence.com/Community/search/SearchResults.aspx?u=196313&amp;amp;o=DateDescending"&gt;past several postings&lt;/a&gt; to this blog, we&amp;#39;ve looked at various ways to sum a given list of numbers. In this posting&amp;nbsp;I&amp;#39;ll present yet another way to do this. This&amp;nbsp;time the technique will be markedly different than the previous ways, and will take advantage of a powerful feature of SKILL++, namely lexical closures. These closures will be used to implement data encapsulation, and we&amp;#39;ll also use lexical closures to capture computation state and continue the computation later. &lt;/p&gt;&lt;h4&gt;Put the CIWindow into SKILL++ mode&lt;/h4&gt;Before proceeding, we need to change the listening mode of the CIWindow. We would like the CIWindow to interpret&amp;nbsp;input expressions as SKILL++ rather than traditional SKILL. &lt;p&gt;Normally, when you type SKILL expressions into the CIWindow&amp;nbsp;that defines functions or defines variables, the semantics of your code is taken as traditional SKILL. If, however, you would like to have SKILL++ (Scheme) semantics, you can put the CIWindow into &lt;b&gt;SKILL++ Mode&lt;/b&gt; by calling the function &lt;code&gt;(toplevel &amp;#39;ils)&lt;/code&gt;. This function does not return immediately, but rather puts the CIWindow into a different listening mode until you call the function &lt;code&gt;resume&lt;/code&gt;, causing the &lt;code&gt;(toplevel &amp;#39;ils)&lt;/code&gt; to return. &lt;/p&gt;&lt;p&gt;You can find out which &lt;i&gt;listening mode&lt;/i&gt; the CIWindow is in either by looking at the indicate in the button left-hand corner of the CIW. If in SKILL listening mode &lt;b&gt;&amp;gt;&lt;/b&gt; will be inconspicuously displayed. The &lt;b&gt;&amp;gt;&lt;/b&gt; is a little difficult to notice because it is so inconspicuous. &lt;/p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/team%20skill/skillprompt.png" alt="FILE UNREADABLE" /&gt;&lt;p&gt;However, if in SKILL++ listening mode &lt;b&gt;ILS-&amp;gt;&lt;/b&gt; will be displayed.&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/team%20skill/schemeprompt.png" alt="FILE UNREADABLE" /&gt;&lt;p&gt;You may also determine the listening mode by calling the function &lt;code&gt;theEnvironment&lt;/code&gt; which will return either &lt;code&gt;nil&lt;/code&gt; if in SKILL mode, or non-nil, if in SKILL++ mode. &lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;pre&gt;(theEnvironment)
&lt;i&gt;  ==&amp;gt; nil&lt;/i&gt;
(toplevel &amp;#39;ils)
(theEnvironment)
&lt;i&gt;  ==&amp;gt; envobj@0x18fa2020&lt;/i&gt;
(resume)
&lt;i&gt;  ==&amp;gt; nil&lt;/i&gt;
(theEnvironment)
&lt;i&gt;  ==&amp;gt; nil&lt;/i&gt;
&lt;/pre&gt;&lt;h4&gt;Defining an adder&lt;/h4&gt;With the CIWindow in SKILL++ mode we can proceed to define a SKILL++ function. &lt;pre&gt;(unless (theEnvironment)
   (toplevel &amp;#39;ils))

(defun make_adder_8a ()   ; 1.1
  (let ((sum 0))          ; 1.2
    (lambda (n)           ; 1.3
      sum = sum + n)))    ; 1.4
&lt;/pre&gt;&lt;p&gt;This definition of &lt;code&gt;make_adder_8a&lt;/code&gt; is a 4 line function, yet does a lot in its 4 lines. It is a higher-order function, as seen in &lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2011/01/04/skill-for-the-skilled-what-is-skill.aspx"&gt;SKILL for the Skilled: What is SKILL++?&lt;/a&gt; it is a function which returns another function. It is a function which creates and returns a special kind of function called a lexical closure. In particular the &lt;code&gt;lambda&lt;/code&gt; on line 1.3 creates a unary function which when called will evaluate the expression on line 1.4. However, the expression on line 1.4, references a variable, &lt;code&gt;sum&lt;/code&gt; defined on line 1.2 and which is &lt;i&gt;external&lt;/i&gt; to the &lt;code&gt;lambda&lt;/code&gt;. In this case &lt;code&gt;sum&lt;/code&gt; is called a &lt;i&gt;free variable&lt;/i&gt;. &lt;/p&gt;&lt;p&gt;The important feature of SKILL++ which makes this magic work is that when &lt;code&gt;make_adder_8a&lt;/code&gt; gets called, the &lt;code&gt;let&lt;/code&gt; on line 1.2 creates a new &lt;i&gt;binding&lt;/i&gt; for the variable named &lt;code&gt;sum&lt;/code&gt;. A binding is a newly allocated memory location which is associated with a named variable. The initial value stored in this memory location is &lt;code&gt;0&lt;/code&gt; as indicated on line 1.2. SKILL++ then proceeds to line 1.3 where it creates an anonymous function, attaching it to this binding. The two occurrences of the name, &lt;code&gt;sum&lt;/code&gt;, on line 1.4 (within this anonymous function) are compiled as references to the binding. &lt;/p&gt;&lt;p&gt;The &lt;code&gt;make_adder_8a&lt;/code&gt; function returns the anonymous function object created on line 1.3, without evaluating the code on line 1.4. Critically this function object maintains a link to the &lt;code&gt;sum&lt;/code&gt; binding. Thereafter when the anonymous is called, the expression on line 1.4 is evaluated and its value returned. In evaluating this expression, the value of &lt;code&gt;sum&lt;/code&gt; (in this allocated binding) is referenced and updated by the expression &lt;code&gt;sum = sum + n&lt;/code&gt;, &lt;code&gt;n&lt;/code&gt; being the value passed to the anonymous function when it is called. &lt;/p&gt;&lt;h4&gt;Testing make_adder_8a&lt;/h4&gt;Let&amp;#39;s experiment with &lt;code&gt;make_adder_8a&lt;/code&gt;. Keep in mind that &lt;code&gt;make_adder_8a&lt;/code&gt; does not actually add anything, rather it creates a function which is capabile of adding. &lt;pre&gt;A = (make_adder_8a)       ; 2.1
&lt;i&gt;  ==&amp;gt; funobj:A&lt;/i&gt;
(A 1)                     ; 2.2
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(A 2)                     ; 2.3
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(A 3)                     ; 2.4
&lt;i&gt;  ==&amp;gt; 6&lt;/i&gt;
(A 4)                     ; 2.5
&lt;i&gt;  ==&amp;gt; 10&lt;/i&gt;
(A 5)                     ; 2.6
&lt;i&gt;  ==&amp;gt; 15&lt;/i&gt;
&lt;/pre&gt;&lt;h4&gt;Arduous line-by-line explanation&lt;/h4&gt;On line 2.1, &lt;code&gt;make_adder_8a&lt;/code&gt; is called, and as described above a SKILL++ anonymous function object (a closure) is created and returned. This closure is stored in the global variable &lt;code&gt;A&lt;/code&gt;. &lt;p&gt;The CIWindow prints this value as funobj:A. As mentioned before the initial value of &lt;code&gt;sum&lt;/code&gt; is &lt;code&gt;0&lt;/code&gt;. Note that &lt;code&gt;sum&lt;/code&gt; is not a global variable. Rather it is a variable which is visible only to the code on lines 1.3 and 1.4. Furthermore, notice that we have no immediate access to the variable &lt;code&gt;sum&lt;/code&gt;. We cannot query the value of &lt;code&gt;code&lt;/code&gt; and we cannot modify its value, except by calling the function we have just stored in the global variable &lt;code&gt;A&lt;/code&gt;. &lt;/p&gt;&lt;p&gt;When line 2.2, &lt;code&gt;(A 1)&lt;/code&gt; is evaluated, the expression on line 1.4 is evaluated: &lt;code&gt;sum = sum + n&lt;/code&gt; with &lt;code&gt;n=1&lt;/code&gt;; &lt;code&gt;sum&lt;/code&gt; is updated from &lt;code&gt;0&lt;/code&gt; to &lt;code&gt;1&lt;/code&gt;, and &lt;code&gt;1&lt;/code&gt; is returned and printed into the CIWindow. &lt;/p&gt;&lt;p&gt;When line 2.3, &lt;code&gt;(A 2)&lt;/code&gt; is evaluated, again the expression on line 1.4 is evaluated: &lt;code&gt;sum = sum + n&lt;/code&gt; with &lt;code&gt;n=2&lt;/code&gt;. This time, &lt;code&gt;sum&lt;/code&gt; is updated from &lt;code&gt;1&lt;/code&gt; to &lt;code&gt;3&lt;/code&gt; and &lt;code&gt;3&lt;/code&gt; is returned. &lt;/p&gt;&lt;p&gt;When lines 2.4, 2.5, and 2.6 are evaluated, &lt;code&gt;sum = sum + n&lt;/code&gt; is evaluated three times with &lt;code&gt;n=3&lt;/code&gt;, &lt;code&gt;n=4&lt;/code&gt;, and &lt;code&gt;n=5&lt;/code&gt; respectively; thus &lt;code&gt;sum&lt;/code&gt; is updated to &lt;code&gt;6&lt;/code&gt;, &lt;code&gt;10&lt;/code&gt;, and finally to &lt;code&gt;15&lt;/code&gt;. &lt;/p&gt;&lt;h4&gt;Summing a list with an adder&lt;/h4&gt;You can use an adder as created by &lt;code&gt;make_adder_8a&lt;/code&gt; to add the elements of a list incrementally. &lt;pre&gt;A = (make_adder_8a)          ; 3.1
&lt;i&gt;  ==&amp;gt; funobj:A&lt;/i&gt;
(mapcar A &amp;#39;(1 2 3 4 5))      ; 3.2
&lt;i&gt;  ==&amp;gt; (1 3 6 10 15)&lt;/i&gt;
&lt;/pre&gt;This call to &lt;code&gt;mapcar&lt;/code&gt; iterates across the given list &lt;code&gt;(1 2 3 4 5)&lt;/code&gt; and calls the function &lt;code&gt;A&lt;/code&gt; on each iteration, each time with the successive element of the list. Since each call to &lt;code&gt;A&lt;/code&gt; returns the current value of the partial sum, &lt;code&gt;mapcar&lt;/code&gt; returns not he final sum, but rather the list of partial sums computed at each step of the iteration. &lt;h4&gt;&amp;nbsp;&amp;nbsp;&lt;/h4&gt;&lt;h4&gt;Multiple SKILL++ adders in parallel&lt;/h4&gt;You can create several adders which work independent of each other. In the following example, we create two &lt;i&gt;adders&lt;/i&gt;, &lt;code&gt;A&lt;/code&gt; and &lt;code&gt;B&lt;/code&gt;. Each one internally maintains its own partial sum of the arguments given to successive calls. &lt;pre&gt;B1 = (make_adder_8a)       ; 4.1
&lt;i&gt;  ==&amp;gt; funobj:B1&lt;/i&gt;
B2 = (make_adder_8a)       ; 4.2
&lt;i&gt;  ==&amp;gt; funobj:B2&lt;/i&gt;
B3 = (make_adder_8a)       ; 4.3
&lt;i&gt;  ==&amp;gt; funobj:B3&lt;/i&gt;
(B1 1)                     ; 4.4
&lt;i&gt;  ==&amp;gt; 1&lt;/i&gt;
(B2 10)                    ; 4.5
&lt;i&gt;  ==&amp;gt; 10&lt;/i&gt;
(B3 100)                   ; 4.6
&lt;i&gt;  ==&amp;gt; 100&lt;/i&gt;
(B1 2)                     ; 4.7
&lt;i&gt;  ==&amp;gt; 3&lt;/i&gt;
(B2 20)                    ; 4.8
&lt;i&gt;  ==&amp;gt; 30&lt;/i&gt;
(B3 200)                   ; 4.9
&lt;i&gt;  ==&amp;gt; 300&lt;/i&gt;
(B1 3)                     ; 4.10
&lt;i&gt;  ==&amp;gt; 6&lt;/i&gt;
(B2 3)                     ; 4.11
&lt;i&gt;  ==&amp;gt; 60&lt;/i&gt;
(B3 30)                    ; 4.12
&lt;i&gt;  ==&amp;gt; 600&lt;/i&gt;
&lt;/pre&gt;&lt;p&gt;This works because each call to &lt;code&gt;make_adder_8a&lt;/code&gt; on lines 4.1, 4.2, and 4.3, each allocate a new closure (three in all), assign each of them respectively turn to the global variables &lt;code&gt;B1&lt;/code&gt;, &lt;code&gt;B2&lt;/code&gt;, and&lt;code&gt;B3&lt;/code&gt;. Each of these three function has its own independent binding of &lt;code&gt;sum&lt;/code&gt;, each of which is initialized to &lt;code&gt;code&lt;/code&gt;. When lines 4.4, 4.7, and 4.10 are evaluated, the &lt;code&gt;sum&lt;/code&gt; binding of &lt;code&gt;B1&lt;/code&gt; is updated, but the &lt;code&gt;sum&lt;/code&gt; bindings of &lt;code&gt;B2&lt;/code&gt; and &lt;code&gt;B3&lt;/code&gt; are not effected. Similarly when 4.5, 4.8, and 4.11 are evaluated, the &lt;code&gt;sum&lt;/code&gt; binding of &lt;code&gt;B2&lt;/code&gt; is effected. And similarly for lines 4.6, 4.9, and 4.12. &lt;/p&gt;&lt;h4&gt;Using flet as an alternative to lambda&lt;/h4&gt;If you find the use of &lt;code&gt;(lambda ...)&lt;/code&gt; to be confusing in the definition of &lt;code&gt;make_adder_8a&lt;/code&gt;, you can, as an alternative, define the same functionality using &lt;code&gt;flet&lt;/code&gt;. &lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;pre&gt;(defun make_adder_8b ()       ; 5.1
  (let ((sum 0))              ; 5.2
    (flet ((add (n)           ; 4.3
             sum = sum + n))  ; 5.4
      add)))                  ; 5.5
&lt;/pre&gt;&lt;p&gt;This implementation of &lt;code&gt;make_adder_8b&lt;/code&gt; uses &lt;code&gt;flet&lt;/code&gt; to define a local function named &lt;code&gt;add&lt;/code&gt;. The normal pattern of using &lt;code&gt;flet&lt;/code&gt; which you&amp;#39;ve seen in previous posts of &lt;i&gt;SKILL for the Skilled&lt;/i&gt; such as &lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2011/01/25/skill-for-the-skilled-continued-introduction-to-skill.aspx"&gt;Continued Introduction to SKILL++&lt;/a&gt;, is to define a local function and call it. The pattern used by &lt;code&gt;make_adder_8b&lt;/code&gt; is to define a local function and return it, allowing the function which called &lt;code&gt;make_adder_8b&lt;/code&gt; to call it, or likewise return it to its caller. &lt;/p&gt;&lt;h4&gt;Data Encapsulation and Object Orientation&lt;/h4&gt;Some programming languages present the ability to encapsulate data as part of the object model. In these languages &lt;i&gt;private&lt;/i&gt; variables are member variables within classes, and methods in/on those classes awkwardly manipulate and access these private variables. &lt;p&gt;This unholy marriage of private data to object model is limiting in practice because it is not only object oriented programs which need to hide data. In fact, a program written in any style may need to take advantage of encapsulate. In SKILL++ (and other dialects of Scheme), data encapsulation is independent from the object system, as it should be. &lt;/p&gt;&lt;p&gt;In SKILL++ the &lt;code&gt;let&lt;/code&gt; and &lt;code&gt;lambda&lt;/code&gt; primitives behave differently than in traditional SKILL. They behave in a way which allows a function to create lexical closures. These lexical closures are then able to manipulate the state of &lt;i&gt;private&lt;/i&gt; variables which they encapsulate. &lt;/p&gt;&lt;h4&gt;Summary&lt;/h4&gt;In this article, we looked at how to use lexical closures which maintain their internal state to implement counters. We looked very lightly and abstractly into how this is implemented within the SKILL++. And we traced step by step though a couple of examples of how this works in practice. &lt;p&gt;In this way SKILL++ provides data encapsulation completely independent from the object system. While SKILL++ does indeed have an extensive, full-featured, and powerful object system, in SKILL++ you are not forced to write a program in an object oriented way just to encapsulate/hide data. Encapsulation is a feature of SKILL++ which is available to you whether you are using OO, imperative, declarative, functional, or any other style you choose. &lt;/p&gt;&lt;h4&gt;More to come&lt;/h4&gt;In the next post we&amp;#39;ll look more at the differences you&amp;#39;ll see when defining these types of functions in SKILL++ vs in SKILL. &lt;h4&gt;See Also&lt;/h4&gt;&lt;p&gt;&lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2011/01/04/skill-for-the-skilled-what-is-skill.aspx"&gt;SKILL for the Skilled: What is SKILL++?&lt;/a&gt; &lt;br /&gt;as &lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2011/01/25/skill-for-the-skilled-continued-introduction-to-skill.aspx"&gt;Continued Introduction to SKILL++&lt;/a&gt; &lt;/p&gt;&lt;p&gt;Jim Newton&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1321806" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=2hG8j-eptE0:1YgpNwO4CIk:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/2hG8j-eptE0" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL/default.aspx">SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Team+SKILL/default.aspx">Team SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/programming/default.aspx">programming</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/LISP/default.aspx">LISP</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL_2B002B00_/default.aspx">SKILL++</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/closures/default.aspx">closures</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/summing/default.aspx">summing</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/sum+a+list/default.aspx">sum a list</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Jim+Newton/default.aspx">Jim Newton</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL+for+the+Skilled/default.aspx">SKILL for the Skilled</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/lexical+closures/default.aspx">lexical closures</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/04/23/skill-for-the-skilled-many-ways-to-sum-a-list-part-8.aspx</feedburner:origLink></item><item><title>Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/Htn09eTUe54/virtuosity-10-things-i-learned-in-march-by-browsing-cadence-online-support.aspx</link><pubDate>Thu, 11 Apr 2013 16:26:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1322668</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1322668</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/04/11/virtuosity-10-things-i-learned-in-march-by-browsing-cadence-online-support.aspx#comments</comments><description>&lt;p&gt;Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced custom layout.&lt;/p&gt;&lt;p&gt;Enjoy!&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;b&gt;Application Notes&lt;/b&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;1. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/Design_Tuning_with_ADEGXL.pdf" target="_blank"&gt;Design Tuning with Analog Design Environment GXL: Interactive and Automated Flows&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Walks through a detailed example using several different advanced analysis tools, including Sensitivity Analysis, Manual Tuning, and Optimization.&amp;nbsp; Includes demo database.&lt;/p&gt;&lt;p&gt;2. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/Stat_Quick_Start_615isr15.pdf" target="_blank"&gt;Statistical Analysis Quick Start (ADE XL)&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Overview and quick reference covering the statistical analysis features in ADE XL, including setup options&amp;nbsp;for Monte Carlo Sampling, defining confidence levels, using auto-stop, post-processing data using histograms, quantile plots and waveforms, and creating statistical corners.&lt;/p&gt;&lt;p&gt;3. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/AMSD_PSL_AppNoteCopyright.pdf" target="_blank"&gt;Mixed-Signal PSL Assertions in AMS Designer&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Provides an overview of writing mixed-signal PSL assertions to handle Verilog-AMS, analog values, etc.&amp;nbsp; Includes a detailed case study, accompanying example tarkit&amp;nbsp;and exercises.&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;b&gt;Rapid Adoption Kit&lt;/b&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;4. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm" target="_blank"&gt;Power, Ground and Structured Routing Implementation Flow&lt;/a&gt;&lt;/p&gt;&lt;p&gt;The flow leverages a combination of existing Virtuoso functionality, Virtuoso Routing TCL commands, and custom SKILL scripts to enable users to efficiently build custom power, ground, and structured signal routes.&amp;nbsp; The flow also supports creation of power and ground rough-in during early floorplanning. This flow is intended for analog mixed-signal designs at the chip, block, and device level in Virtuoso.&amp;nbsp; Includes demo database and&lt;a href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/StructuredRoutingUserGuide.pdf" target="_blank"&gt; detailed documentation&lt;/a&gt; providing an overview of the flow, guidelines for use in your designs and step-by-step walkthrough using the demo database.&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;b&gt;Videos&lt;/b&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;5. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Custom_IC_Design/vdn/Virtuoso_Layout_Suite_MarkNet.htm" target="_blank"&gt;Mark Nets&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This video describes the Mark Net command including Mark, Save, Unmark, Options, and Retaining Via Info.&lt;/p&gt;&lt;p&gt;6. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Custom_IC_Design/vdn/Generate_Clones_In_Virtuoso.html" target="_blank"&gt;Generating Clones in Virtuoso&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This is a demo that describes generating clones in Virtuoso. It includes topics such as creating clones as Free Objects, Group Objects, and Synchronized Family.&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;b&gt;Solutions&lt;/b&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;7. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20033396;searchHash=f114b51f1e7339238c16285c477a1b15" target="_blank"&gt;VLS-XL: Modgen: Abutting Modgen members using SKILL (Solution 20033396)&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Skill routine to use to abut all the devices in a given Modgen.&lt;/p&gt;&lt;p&gt;8.&lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20034969;searchHash=56e9df0d03ec893148331fb9ca3917c3" target="_blank"&gt; How to query directional spacing tables from techfile with SKILL? (Solution 20034969)&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Some example Skill commands showing you how to access horizontal and vertical spacing rules from the techfile.&lt;/p&gt;&lt;p&gt;9. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20040165;searchHash=92c6bb88781f2d28a22ddbc6e5f6eda0" target="_blank"&gt;How to change nport file names for corner simulation (Solution 20040165)&lt;/a&gt;&lt;/p&gt;&lt;p&gt;You have an nport with an S-parameter file.&amp;nbsp; For each corner, the nport uses a different S-parameter file.&amp;nbsp; This solution shows you how to wrap up the nport as a subcircuit library with sections you can reference just like any other model file sections.&lt;/p&gt;&lt;p&gt;10. &lt;a href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20051691;searchHash=0d7c54933f57787b82176c9b378c2294" target="_blank"&gt;How to define bindkeys for ADE L window (Solution 20051691)&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Shows you how to register bindkeys which will be active in the ADE L window.&amp;nbsp; Examples provided to create bindkeys for &amp;quot;Netlist and Run&amp;quot; and Direct Plot commands.&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1322668" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=Htn09eTUe54:4L5YNdoMRso:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/Htn09eTUe54" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso/default.aspx">Virtuoso</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/AMS+Simulation/default.aspx">AMS Simulation</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL/default.aspx">SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Space-based+Router/default.aspx">Virtuoso Space-based Router</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Analog+Design+Environment/default.aspx">Virtuoso Analog Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/VLS+XL/default.aspx">VLS XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Layout+Suite+L/default.aspx">Virtuoso Layout Suite L</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/VLS+GXL/default.aspx">VLS GXL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/VLS+L/default.aspx">VLS L</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Layout+Suite+XL/default.aspx">Virtuoso Layout Suite XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Layout+Suite+GXL/default.aspx">Virtuoso Layout Suite GXL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE/default.aspx">ADE</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE-XL/default.aspx">ADE-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE-GXL/default.aspx">ADE-GXL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1.5/default.aspx">IC 6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Monte+Carlo/default.aspx">Monte Carlo</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+IC6.1.5/default.aspx">Virtuoso IC6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog+Design+Environment/default.aspx">Analog Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/modgens/default.aspx">modgens</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Layout+Suite/default.aspx">Virtuoso Layout Suite</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog++Design+Environment/default.aspx">Analog  Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Rapid+Adoption+Kit/default.aspx">Rapid Adoption Kit</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/RAKs/default.aspx">RAKs</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/04/11/virtuosity-10-things-i-learned-in-march-by-browsing-cadence-online-support.aspx</feedburner:origLink></item><item><title>SKILL for the Skilled: Part 7, Many Ways to Sum a List</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/PyORbrxAIzE/skill-for-the-skilled-many-ways-to-sum-a-list-part-7.aspx</link><pubDate>Mon, 25 Mar 2013 13:05:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1321615</guid><dc:creator>Team SKILL</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1321615</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/03/25/skill-for-the-skilled-many-ways-to-sum-a-list-part-7.aspx#comments</comments><description>&lt;p&gt;In this episode of &lt;i&gt;SKILL for the Skilled&lt;/i&gt; I&amp;#39;ll introduce a feature of the &lt;code&gt;let&lt;/code&gt; primitive&amp;nbsp;that Scheme programmers will find familiar, but other readers may have never seen before. The feature is called &lt;i&gt;named let&lt;/i&gt;, and I&amp;#39;ll show you how to use it to sum&amp;nbsp;the numbers in a given list.&lt;/p&gt;&lt;p&gt;&lt;b&gt;Named LET&lt;/b&gt;&lt;/p&gt;There is a feature of &lt;code&gt;let&lt;/code&gt; available in SKILL++ which is not available in traditional SKILL, called &lt;i&gt;named let&lt;/i&gt;. Here is an example of how it can be used to sum a given list of numbers. &lt;pre&gt;(defun sumlist_7a (numbers)
  (let REPEAT
    ((sum_so_far 0)
     (rest       numbers))
    (if rest
        (REPEAT (plus sum_so_far (car rest))
                (cdr rest))
        sum_so_far)))
&lt;/pre&gt;In this example, the &lt;i&gt;named let&lt;/i&gt; defines a local function named, &lt;code&gt;REPEAT&lt;/code&gt; and calls it once with the two arguments, &lt;code&gt;0&lt;/code&gt; and &lt;code&gt;numbers&lt;/code&gt;. Of course, &lt;code&gt;REPEAT&lt;/code&gt; is by no means a reserved word; you can name the local function any valid variable name. Within the body of the &lt;i&gt;named let&lt;/i&gt; you may call the local function with two arguments. You may recursively call the function zero, one, or more times as your algorithm requires. &lt;p&gt;&lt;b&gt;Testing the function&lt;/b&gt;&lt;/p&gt;If we enable tracing of &lt;code&gt;sumlist_7a&lt;/code&gt; and &lt;code&gt;REPEAT&lt;/code&gt;, we can see what happens when calling &lt;code&gt;sumlist_7a&lt;/code&gt;. We can see that the local function, &lt;code&gt;REPEAT&lt;/code&gt; is called recursively several times, and that the implementation does in fact return the correct sum of the given list of numbers. &lt;pre&gt;(trace sumlist_7a)
(trace REPEAT)
(sumlist_7a &amp;#39;(1 2 3 4 5))
|sumlist_7a((1 2 3 4 5))
||(REPEAT 0 (1 2 3 4 5))
|||(REPEAT 1 (2 3 4 5))
||||(REPEAT 3 (3 4 5))
|||||(REPEAT 6 (4 5))
||||||(REPEAT 10 (5))
|||||||(REPEAT 15 nil)
|||||||REPEAT --&amp;gt; 15
||||||REPEAT --&amp;gt; 15
|||||REPEAT --&amp;gt; 15
||||REPEAT --&amp;gt; 15
|||REPEAT --&amp;gt; 15
||REPEAT --&amp;gt; 15
|sumlist_7a --&amp;gt; 15
15
&lt;/pre&gt;&lt;p&gt;&lt;b&gt;Equivalent to labels&lt;/b&gt;&lt;/p&gt;&lt;p&gt;The &lt;i&gt;named let&lt;/i&gt; is more or less equivalent to a declaration and call of a local function as if by using &lt;code&gt;labels&lt;/code&gt;. If you recall, this is exactly what was shown in &lt;code&gt;sumlist_3b&lt;/code&gt; in &lt;i&gt;SKILL for the Skilled: Many Ways to Sum a List (Part 3)&lt;/i&gt;. &lt;/p&gt;&lt;p&gt;(defun sumlist_3b (numbers)&lt;br /&gt;&amp;nbsp; (labels ((sum (sum_so_far rest)&lt;br /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (if rest&lt;br /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (sum (plus (car rest) sum_so_far)&lt;br /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (cdr rest))&lt;br /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; sum_so_far)))&lt;br /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; (sum 0 numbers)))&lt;/p&gt;&lt;p&gt;If you trace &lt;code&gt;sumlist_3b&lt;/code&gt; and &lt;code&gt;sum&lt;/code&gt; you&amp;#39;ll see that it executes pretty much the same thing as &lt;code&gt;sumlist_7a&lt;/code&gt;. &lt;/p&gt;&lt;pre&gt;(trace sumlist_3b)
(trace sum)
(sumlist_3b &amp;#39;(1 2 3 4 5))
|sumlist_3b((1 2 3 4 5))
||(sum 0 (1 2 3 4 5))
|||(sum 1 (2 3 4 5))
||||(sum 3 (3 4 5))
|||||(sum 6 (4 5))
||||||(sum 10 (5))
|||||||(sum 15 nil)
|||||||sum --&amp;gt; 15
||||||sum --&amp;gt; 15
|||||sum --&amp;gt; 15
||||sum --&amp;gt; 15
|||sum --&amp;gt; 15
||sum --&amp;gt; 15
|sumlist_3b --&amp;gt; 15
15
&lt;/pre&gt;&lt;p&gt;&lt;b&gt;Illusion of jumping to the top&lt;/b&gt;&lt;/p&gt;&lt;p&gt;The illusion (or abstraction) presented by the &lt;i&gt;named let&lt;/i&gt; is that of being able to &lt;i&gt;jump&lt;/i&gt; back to the top of the &lt;code&gt;let&lt;/code&gt; form, and evaluate it again with different initialization values. &lt;/p&gt;&lt;p&gt;Consider this simple &lt;code&gt;let&lt;/code&gt; example. &lt;/p&gt;&lt;pre&gt;(let loop
   ((a 10)
    (b 0))
 (println (list a b))
 (when (plusp a)
   (loop (sub1 a) 
         (add1 b))))
&lt;/pre&gt;Which prints the following output. &lt;pre&gt;(10 0)
(9 1)
(8 2)
(7 3)
(6 4)
(5 5)
(4 6)
(3 7)
(2 8)
(1 9)
(0 10)
&lt;/pre&gt;&lt;p&gt;&lt;b&gt;Doesn&amp;#39;t work in traditional SKILL&lt;/b&gt;&lt;/p&gt;&lt;p&gt;If you try to evaluate a named let in traditional SKILL (e.g., with a .il file extension), you&amp;#39;ll get an error something like the following, which basically means that SKILL let expects a list as its first operand and you have given the symbol &lt;code&gt;loop&lt;/code&gt; instead. &lt;/p&gt;&lt;pre&gt;*Error* let: local bindings must be a proper list - loop&lt;/pre&gt;&lt;p&gt;&lt;b&gt;let is syntactic sugar for lambda&lt;/b&gt;&lt;/p&gt;&lt;p&gt;In SKILL++ the normal &lt;i&gt;let&lt;/i&gt; has the same semantics as calling an unnamed function with particular parameter values. For example: &lt;/p&gt;&lt;pre&gt;(let ((a X)
      (b Y)
      (c Z))
  (expr1 a b)
  (expr2 b c))
&lt;/pre&gt;Is semantically the same as the following arguably less readable expression. The expression uses &lt;i&gt;funcall&lt;/i&gt; to call a nameless function, defined by the &lt;code&gt;(lambda (a b c) ...)&lt;/code&gt;; in particular to call it with the three values &lt;code&gt;X&lt;/code&gt;, &lt;code&gt;Y&lt;/code&gt;, and &lt;code&gt;Z&lt;/code&gt;. In fact the two code snippets are simply syntactical transforms of each other. &lt;pre&gt;(funcall (lambda (a b c)
           (expr1 a b)
           (expr2 b c))
         X
         Y
         Z)
&lt;/pre&gt;When you look at the equivalent &lt;code&gt;lambda&lt;/code&gt; form of &lt;code&gt;let&lt;/code&gt; it is immediately clear that the expressions within the lambda are not able to make recursive calls to this unnamed function. This limitation is solved by the &lt;i&gt;named let&lt;/i&gt;. &lt;p&gt;&lt;b&gt;Named let and tail-call optimization&lt;/b&gt;&lt;/p&gt;&lt;p&gt;The illusion of &lt;i&gt;jumping&lt;/i&gt; back to the top in sort of a &lt;code&gt;goto&lt;/code&gt; fashion is indeed what happens if tail-call-elimination is enabled via the &lt;i&gt;optimizeTailCall&lt;/i&gt; status flag explained in &lt;i&gt;SKILL for the Skilled: Many Ways to Sum a List (Part 4)&lt;/i&gt;. &lt;/p&gt;&lt;p&gt;&lt;b&gt;Summary&lt;/b&gt;&lt;/p&gt;&lt;p&gt;In this post I&amp;#39;ve shown some examples of how to used the &lt;i&gt;named let&lt;/i&gt; construct of SKILL++. This construct converts the conventional &lt;code&gt;let&lt;/code&gt; into a loop --- a loop which can be repeated by &lt;i&gt;calling&lt;/i&gt; the label as a function, providing the next iteration&amp;#39;s variable values. &lt;/p&gt;&lt;p&gt;&lt;b&gt;More to come&lt;/b&gt;&lt;/p&gt;&lt;p&gt;In upcoming posts we&amp;#39;ll continue to survey the SKILL++ language using the example of summing a list. &lt;/p&gt;&lt;p&gt;&lt;b&gt;See Also&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2012/09/18/unfinished-skill-for-the-skilled-many-ways-to-sum-a-list-part-3.aspx?postID=1314708"&gt;SKILL for the Skilled: Many Ways to Sum a List (Part 3)&lt;/a&gt; &lt;br /&gt;&lt;a href="http://www.cadence.com/Community/blogs/cic/archive/2012/10/15/unfinished-skill-for-the-skilled-many-ways-to-sum-a-list-part-4.aspx?postID=1314709"&gt;SKILL for the Skilled: Many Ways to Sum a List (Part 4)&lt;/a&gt; &lt;br /&gt;&lt;a href="http://en.wikipedia.org/wiki/Scheme_%28programming_language%29"&gt;Scheme&lt;/a&gt; In particular see the discussion of &lt;a href="http://en.wikipedia.org/wiki/Scheme_%28programming_language%29#Block_structure"&gt;named let&lt;/a&gt; &lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1321615" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=PyORbrxAIzE:E4N1-_HO4Io:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/PyORbrxAIzE" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL/default.aspx">SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Team+SKILL/default.aspx">Team SKILL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/programming/default.aspx">programming</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/LISP/default.aspx">LISP</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL_2B002B00_/default.aspx">SKILL++</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/summing/default.aspx">summing</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/sum+a+list/default.aspx">sum a list</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Jim+Newton/default.aspx">Jim Newton</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/SKILL+for+the+Skilled/default.aspx">SKILL for the Skilled</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/03/25/skill-for-the-skilled-many-ways-to-sum-a-list-part-7.aspx</feedburner:origLink></item><item><title>Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/Twug0DK4jHE/virtuosity-10-things-i-learned-in-february-by-browsing-cadence-online-support.aspx</link><pubDate>Mon, 18 Mar 2013 20:53:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1321460</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1321460</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/03/18/virtuosity-10-things-i-learned-in-february-by-browsing-cadence-online-support.aspx#comments</comments><description>&lt;p&gt;February was a big month for RAKs (Rapid Adoption Kits)!&amp;nbsp; If you haven&amp;#39;t checked out the listings under &lt;strong&gt;Resources-&amp;gt;Rapid Adoption Kits&lt;/strong&gt; yet, you&amp;#39;re missing out.&amp;nbsp; You&amp;#39;ll find databases with detailed instructions, documentation and videos on many tools, features and flows.&amp;nbsp;&amp;nbsp; They&amp;#39;ve become very popular and we&amp;#39;re adding more all the time.&lt;/p&gt;&lt;p&gt;We&amp;#39;re also featuring content on routing, schematic PCells, ADE XL job distribution, advanced node layout techniques and a new course on high-performance circuit simulation.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Rapid Adoption Kits&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;1. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Creating Custom Connect Rules for AMS Simulation in ADE&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Outlines the process used to create custom connect rules for mixed-signal simulation in ADE using AMS Designer.&amp;nbsp; Includes a database example and &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/AMS-ADE_custom_connect_rules_v1.0.pdf"&gt;step-by-step manual&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;2. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Spectre Device Checks&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Describes the usage of the Spectre device checking feature.&amp;nbsp; Spectre device checking is used to monitor if devices in your circuit are violating user-defined conditions.&amp;nbsp; For example, checking to insure that low voltage devices are not inadvertently used in high voltage conditions.&amp;nbsp; Checks can show warnings or cause the simulation to stop on an error.&amp;nbsp; This is a very powerful feature, but can be somewhat confusing to set up, so this database and &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/spectre_device_checks_v1.pdf"&gt;step-by-step manual&lt;/a&gt; will be extremely useful.&lt;/p&gt;&lt;p&gt;3. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Using Spectre Save-Recover&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Spectre and Spectre Accelerated Parallel Simulator (APS) have the capability to save a simulation state and restart the simulation from the saved state file. The simulation state for long simulations can be periodically saved to allow recovery from unforeseen circumstances, such as power outages or disk full issues. The save/recover methodology can also be used to restart simulations with different parameters or inputs. This example will illustrate using Spectre/APS Save-Recover from both ADE and command line based simulation.&amp;nbsp; Includes database and detailed &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/spectre-aps_save-recover_v1.pdf"&gt;manual&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;4. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Basics of Inherited Connections&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Often times in design, the same cells need to be used in different parts of the circuit&amp;nbsp;that use different power supply voltages. Inherited connections provide a mechanism to selectively override net connections by placing properties on the parent instance. Therefore the same cell can be used with different power supplies without the need for explicit power and ground pins. This &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/inherited_connections_basics_v1.pdf"&gt;document&lt;/a&gt; describes how inherited connections work with a sample design which shows how power and ground connections for the same cell can be different in the schematic hierarchy.&amp;nbsp;&amp;nbsp;&amp;nbsp;It also&amp;nbsp;outlines the process used to resolve inherited connections.&amp;nbsp;&amp;nbsp;Includes an example database.&lt;/p&gt;&lt;p&gt;5. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Passing Parameters in the Schematic Hierarchy with pPar&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Schematics can be parameterized with pPar parameters to allow passing parameters from a parent instance to the lower level schematic (the child). This mechanism facilitates defining high level parameters to define the functionality of the circuit.&amp;nbsp; Includes database and detailed &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/Passing_Parameters_in_the_Schematic_Hierarchy_with_pPar_v1.pdf"&gt;manual&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Application Notes&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;6. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/job_policy_setup_COS.pdf"&gt;ADE XL Job Policy Setup&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This document (and the complementary &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=dt;q=ccic_design_entry/ADE_XL_SF.pdf"&gt;ADE XL Simulation Flow&lt;/a&gt; document) are essential to getting the most out of the powerful job distribution capabilities in ADE XL.&amp;nbsp; You&amp;#39;ll learn about the different types of job distribution available, their options, how they work and how to set them up.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Solutions&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;7. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11856818;searchHash=e3026bbb89bf528dd05e88bcef858fcf"&gt;How to set non-uniform Routing Tracks with IC6.1.5 VSR-RIDE and do routing&lt;/a&gt;&lt;/p&gt;&lt;p&gt;For IC6.1.5 users who wish to do gridded track based routing, this document will demonstrate how to set up the Tcl/tk commands in a script that can be run within Virtuoso Layout GXL or through the Routing Integrated Development Environment (RIDE).&amp;nbsp; Tracks can be setup for all routing layers of just selected routing layers.&lt;/p&gt;&lt;p&gt;8. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20006301;searchHash=403dd52c18adea4c1c35d2b22de797fb"&gt;Schematic PCell Example with inherited connection.&amp;nbsp; netExpression added to wire and label display&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Includes sample&amp;nbsp;SKILL code and testcase database to create a schematic PCell with inherited connections.&lt;/p&gt;&lt;p&gt;9. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20024545;searchHash=5246dab458f48511a0c1d5888ed33f53"&gt;How to enable the color engine in ICADV12.1 and later versions like upcoming IC6.1.6&lt;/a&gt;&lt;/p&gt;&lt;p&gt;The Virtuoso Layout environment for advanced node design includes features to support metal coloring for double-patterning technologies.&amp;nbsp; This solution shows you how to enable those features.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Course Announcement&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;10. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=Training/Datasheets/high-performance-simulation-using-spectre-simulators-v12.1-(ilt).html"&gt;High-Performance Simulation using Spectre Simulators v12.1&lt;/a&gt;&lt;/p&gt;&lt;p&gt;In this course, you use the enhanced technologies of Virtuoso Spectre Circuit Simulator, including the Accelerated Parallel Simulator (APS), to run fast and accurate analog simulations on large, complex, mixed-signal designs providing a significant performance gain over baseline Spectre simulation. &lt;/p&gt;&lt;p&gt;You explore the use of multithreading options, APS, Fast APS and APS in distributed mode. You verify the circuit performance and identify the potential failure modes by running dynamic checks with Spectre and APS and then examine the results by viewing the appropriate XML file. You run Spectre APS stitching of DSPF, SPEF, and DPF files and a postlayout simulation. You run high-capacity EMIR simulation using Spectre APS. &lt;/p&gt;&lt;p&gt;Stacy Whiteman&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1321460" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=Twug0DK4jHE:M54rEYsR_y4:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/Twug0DK4jHE" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/APS/default.aspx">APS</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Analog+Design+Environment/default.aspx">Virtuoso Analog Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1/default.aspx">IC 6.1</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Layout+Suite+GXL/default.aspx">Virtuoso Layout Suite GXL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Spectre/default.aspx">Spectre</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/advanced+node/default.aspx">advanced node</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE/default.aspx">ADE</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE-XL/default.aspx">ADE-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog+simulation/default.aspx">Analog simulation</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/AMS/default.aspx">AMS</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1.5/default.aspx">IC 6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+IC6.1.5/default.aspx">Virtuoso IC6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog++Design+Environment/default.aspx">Analog  Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC615/default.aspx">IC615</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/variability/default.aspx">variability</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Rapid+Adoption+Kit/default.aspx">Rapid Adoption Kit</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/RAKs/default.aspx">RAKs</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Advanced+Node/default.aspx">Virtuoso Advanced Node</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuosity/default.aspx">Virtuosity</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/03/18/virtuosity-10-things-i-learned-in-february-by-browsing-cadence-online-support.aspx</feedburner:origLink></item><item><title>Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/chOl5o5UiUw/virtuosity-10-things-i-learned-in-january-by-browsing-cadence-online-support.aspx</link><pubDate>Fri, 15 Feb 2013 16:56:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1319795</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1319795</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/02/15/virtuosity-10-things-i-learned-in-january-by-browsing-cadence-online-support.aspx#comments</comments><description>&lt;p&gt;&lt;u&gt;&lt;strong&gt;&lt;/strong&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;This month&amp;#39;s highlighted content includes&amp;nbsp;helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more.&lt;/p&gt;&lt;p&gt;Enjoy and don&amp;#39;t forget to leave feedback at the top of the individual content pages in COS (&lt;a target="_blank" href="http://support.cadence.com"&gt;Cadence Online Support&lt;/a&gt;) to let us know what information you find most useful.&lt;/p&gt;&lt;p&gt;&lt;u&gt;&lt;strong&gt;Rapid Adoption Kits&lt;/strong&gt;&lt;/u&gt;&lt;/p&gt;&lt;p&gt;1. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;Guidelines on Modeling Analog Circuits with wreal&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This material illustrates wreal modeling concepts by migrating a Verilog-A based model of an AM modulation-demodulation system to a wreal model with Verilog-AMS. The wreal equivalent of each block is created to build up an all digital simulation for the system.&amp;nbsp;&amp;nbsp;Guideline steps for creating wreal Verilog-AMS models are developed and used for developing the wreal models.&amp;nbsp; The RAK includes a workshop database and &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/Guidelines_on_Wreal_Models_v2_1.pdf"&gt;detailed manual&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;2. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm"&gt;IC6.1.5 VSR (Virtuoso Space-based Router) Workshop&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This workshop highlights interactive, assisted and automatic routing features available in Virtuoso Space-based Router (VSR). During the course of the workshop you will be able to apply these features to do some device and block level routing and analyze your results in R-IDE (Routing Integrated Development Environment).&amp;nbsp; The RAK includes a workshop database and &lt;a target="_blank" href="http://support.cadence.com/wps/PA_DocumentViewer/wp/ProductInformation/Custom_IC_Design/ApplicationPackages/download/IC615VSRWorkshop.pdf"&gt;detailed manual&lt;/a&gt;.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Application Notes&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;3. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/AppNote_AMSDesignerIncisiveUseModel_11_1.pdf"&gt;AMS Designer INCISIVE Command-line Flow Use Model&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This document provides an overview of how to run mixed-signal simulations from the command-line interface of the AMS Designer simulator using the &amp;quot;&lt;em&gt;irun&lt;/em&gt;&amp;quot; command.&amp;nbsp; It includes information on setup files, options, command syntax and mixed-language specifics, as well as examples and pointers to the workshop database and other references.&lt;/p&gt;&lt;p&gt;4. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/appNote_Calibrated_Verification.pdf"&gt;Calibrated Verification with ADE XL&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This document focuses on a topic about which I am frequently asked by customers--how to use ADE XL to verify&amp;nbsp;digitally calibrated high-performance circuits.&amp;nbsp; It covers the details of the ADE XL features supporting this technique, including the use of calcVal expressions and pre-run Ocean scripts.&amp;nbsp; Detailed worked examples are given, complete with accompanying database.&lt;/p&gt;&lt;p&gt;5. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Digital_IC_Design/OARefLibImport.pdf"&gt;Open Access Reference Library Import&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Recommendations on how to import a standard cell or IP reference library for use in OpenAccess mixed-signal design using&amp;nbsp;the Incremental Technology Database (ITDB)&amp;nbsp;and LEF Import.&lt;/p&gt;&lt;p&gt;6. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ApplicationNotes/Custom_IC_Design/ADE_XL_Quick_Start_615isr12.pdf"&gt;ADE XL Quick Start&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Given that the &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=adexl/adexl6.1.5/adexlTOC.html"&gt;ADE XL User Guide&lt;/a&gt;&amp;nbsp;is now 846 pages, this document is intended as a quick reference tutorial&amp;nbsp;in using the basic functionality in ADE XL, including setting up tests, running simulations, basic post-processing, sweeps and corners.&amp;nbsp; &lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Solutions&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;7. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11855144;searchHash=f9906b4b410a52c796078332d80dce77"&gt;New AHDL Linter in AMS Designer 12.2&lt;/a&gt;&lt;/p&gt;&lt;p&gt;Detailed information on how to use the AHDL linter feature in AMS Designer which enables you to detect modeling issues in Verilog-A and VerilogAMS (AHDL) &amp;nbsp;languages.&lt;/p&gt;&lt;p&gt;8. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11807078;searchHash=0ef2e56d94f9862c30515003b41c4c58"&gt;Virtuoso Encounter Mixed-Signal Flow: Quick Reference to Basics and Most Referred Solutions&lt;/a&gt;&lt;/p&gt;&lt;p&gt;This is a concise and handy reference document for using Virtuoso and Encounter to manage mixed-signal design flows that allow the mixing of digital and analog content throughout the design hierarchy.&amp;nbsp; It includes information on design and technology data requirements, environmental configuration and&amp;nbsp;an extensive list of links&amp;nbsp;to helpful solutions, reference documents and application notes.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Video&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;9. &lt;a target="_blank" href="http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Design_for_Manufacturing/CCP_Introduction_COS.htm"&gt;Cadence Chemical Mechanical Polishing (CMP) Predictor - An Introduction&lt;/a&gt;&lt;/p&gt;&lt;p&gt;An introduction to the Cadence Chemical Mechanical Polishing Predictor.&amp;nbsp; It also describes the extraction process, simulation flow and steps to monitor the job status and view extraction results.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Blog&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;10. &lt;a target="_blank" href="http://www.cadence.com/Community/blogs/cic/archive/2013/01/28/Introduction-to-Cadence-Virtuoso-Advanced-Node-Design-Environment.aspx?postID=1311638"&gt;Introduction to Cadence Virtuoso Advanced Node Design Environment&lt;/a&gt;&lt;/p&gt;&lt;p&gt;An introduction to the new features that are available in Cadence&amp;#39;s Virtuoso Advanced Node design environment which support the complex requirements inherent in advanced process technologies at 22nm and below.&lt;/p&gt;&lt;p&gt;Stacy Whiteman&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1319795" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=chOl5o5UiUw:6JBlhT3b0Y0:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/chOl5o5UiUw" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso/default.aspx">Virtuoso</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/AMS+Simulation/default.aspx">AMS Simulation</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Space-based+Router/default.aspx">Virtuoso Space-based Router</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Encounter/default.aspx">Encounter</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/mixed+signal/default.aspx">mixed signal</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE-XL/default.aspx">ADE-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/wreal/default.aspx">wreal</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog++Design+Environment/default.aspx">Analog  Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Rapid+Adoption+Kit/default.aspx">Rapid Adoption Kit</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/interoperability/default.aspx">interoperability</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/calibration/default.aspx">calibration</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/02/15/virtuosity-10-things-i-learned-in-january-by-browsing-cadence-online-support.aspx</feedburner:origLink></item><item><title>Things You Didn't Know About Virtuoso: Drag and Drop</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/0IY0Tf-NbAU/things-you-didn-t-know-about-virtuoso-drag-and-drop.aspx</link><pubDate>Wed, 13 Feb 2013 14:00:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1319703</guid><dc:creator>stacyw</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1319703</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/02/13/things-you-didn-t-know-about-virtuoso-drag-and-drop.aspx#comments</comments><description>&lt;p&gt;I love it when I&amp;#39;m sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says &amp;quot;Wait, why are you doing it that way?&amp;nbsp; Why don&amp;#39;t you just...&amp;quot;.&amp;nbsp; Immediately my mind says &amp;quot;blog time!&amp;quot;&amp;nbsp; &lt;/p&gt;&lt;p&gt;One such sequence of events happened recently around the concept of &amp;quot;drag and drop.&amp;quot;&amp;nbsp; For those of us who have been around for a while, the idea of dragging objects, particularly text or something non-drawing related, just never springs to mind.&amp;nbsp; I&amp;#39;ll complain all day about having to re-type something or execute a long series of mouse clicks&amp;nbsp;before I even try to just grab it and drag it where I want it to go.&lt;/p&gt;&lt;p&gt;So let&amp;#39;s play a little game.&amp;nbsp; Where are all the places in ADE L/XL/GXL and ViVA that you can perform some useful function by dragging something?&amp;nbsp; I&amp;#39;m sure I&amp;#39;ll miss a few, so feel free to leave additional discoveries in the comments.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;In general&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;Drag the &lt;a target="_blank" href="http://www.cadence.com/Community/blogs/cic/archive/2009/06/09/Things-You-Didn_2700_t-Know-About-Virtuoso_3A00_-Managing-Your-Real-Estate-_2D00_-Part-1.aspx"&gt;assistants/subwindows to rearrange, undock&amp;nbsp;or tab them&lt;/a&gt;&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag the toolbars&amp;nbsp;to&amp;nbsp;rearrange, resize or move them to other edges of the window&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;ADE L&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;Drag the rows&amp;nbsp;in the different subwindows to reorder them (Design Variables, Outputs, Analyses)&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;ADE XL&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;Drag the rows in the Output Setup panel up and down to reorder them (within the same test)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag the columns in the Output Setup panel to rearrange them (sadly it isn&amp;#39;t saved, but it can&amp;nbsp;be very&amp;nbsp;handy&amp;nbsp;while you&amp;#39;re setting things up)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag an output expression over to a Global Variable to have that variable value be taken from the result of&amp;nbsp;one test and used as input to a different test (also referred to as &lt;a target="_blank" href="http://www.cadence.com/Community/blogs/cic/archive/2010/08/25/things-you-didn-t-know-about-virtuoso-outputs-setup-in-ade-xl.aspx"&gt;combinatorial variable expressions&lt;/a&gt;)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;In the Detail-Transpose results view, drag columns (inputs or outputs) around for easier comparison of measured values.&amp;nbsp; RMB on the columns in this view to hide them.&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;strong&gt;&lt;u&gt;Calculator&lt;/u&gt;&lt;/strong&gt;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;Drag an output expression from the Outputs Setup panel in ADE XL into the calculator buffer to create &lt;a target="_blank" href="http://www.cadence.com/Community/blogs/cic/archive/2010/08/25/things-you-didn-t-know-about-virtuoso-outputs-setup-in-ade-xl.aspx"&gt;combinatorial output expressions&lt;/a&gt; using results from multiple tests&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag an expression from the Stack to the Buffer&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag an expression from the Expression Editor to the Buffer.&amp;nbsp; Don&amp;#39;t know about the &lt;a target="_blank" href="http://support.cadence.com/wps/myportal/cos/!ut/p/c5/dY1bDoIwFAXX4gLIveVR9BNJgICQKAqlPwSRIFpog29Wry6AM98zBzj8GKpn11b3Tg6VAAaclkT3XRKZuEJzRVHPvDg2I9dAh0D-N2iJM3MQCuD2bGGrQzbIsf897YGhWaYXVOE-NV6fetoQubxFqUrItom8dS0o1rlwi6ydOk9TQc65EN3uYKlGvM6qbySn6sRCv5B-yK48PEpLG2X23rTuo-cHG5JA9g2o6zB5S2fxBe0D6EM!/dl3/d3/L2dBISEvZ0FBIS9nQSEh/"&gt;Expression Editor&lt;/a&gt;?&amp;nbsp; Time to learn!&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag&amp;nbsp;one or more expressions&amp;nbsp;from the Stack to the Expression Editor.&amp;nbsp; &lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag one or more expressions from the Stack, Buffer or Expression Editor and--wait for it--drop it into any text area outside of Virtuoso.&amp;nbsp;&amp;nbsp;Text editor, command line or it will&amp;nbsp;even create a text file on your desktop.&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag an expression from the Stack, Buffer or Expression Editor into any text field in a calculator function form. (This is the one that inspired the &amp;quot;aha&amp;quot; moment I mentioned in the first paragraph.)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Bonus Tip: Double-click on any Stack item to move it into the Buffer and push the contents of the Buffer onto the Stack&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;u&gt;&lt;strong&gt;ViVA Graph&lt;/strong&gt;&lt;/u&gt;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;&lt;div&gt;Drag traces from one subwindow to another.&amp;nbsp; (Hold Ctrl while dragging to copy instead of move)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag traces from one strip to another (Hold Ctrl to copy)&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag a whole strip up or down to reorder&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag traces from the graph to the Subwindows Assistant (&lt;strong&gt;Window-&amp;gt;Assistants-&amp;gt;Subwindows&lt;/strong&gt; if you haven&amp;#39;t seen this).&amp;nbsp; Here you can drop them in an empty area to create a new subwindow or into one of the existing subwindow thumbnails to put them there&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag signals from the Results Browser onto the graph or the Subwindows Assistant&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Drag a signal from the Results Browser into the Calculator Buffer&lt;/div&gt;&lt;/li&gt;&lt;li&gt;&lt;div&gt;Pretty much anything having to do with markers (point/A/B/delta, vertical or horizontal markers and their intercept bubbles) can be moved and rearranged by dragging&lt;/div&gt;&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;So there you have it. What have I missed?&amp;nbsp; As always, your feedback is welcome.&lt;/p&gt;&lt;p&gt;Stacy Whiteman&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1319703" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=0IY0Tf-NbAU:DqDXGegYmVA:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/0IY0Tf-NbAU" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso/default.aspx">Virtuoso</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ViVa-XL/default.aspx">ViVa-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1/default.aspx">IC 6.1</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE/default.aspx">ADE</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/ADE-XL/default.aspx">ADE-XL</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/IC+6.1.5/default.aspx">IC 6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+IC6.1.5/default.aspx">Virtuoso IC6.1.5</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Analog+Design+Environment/default.aspx">Analog Design Environment</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Viva/default.aspx">Viva</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/VIrtuoso+drag+and+drop/default.aspx">VIrtuoso drag and drop</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/drag+and+drop/default.aspx">drag and drop</category><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/02/13/things-you-didn-t-know-about-virtuoso-drag-and-drop.aspx</feedburner:origLink></item><item><title>Introduction to Cadence Virtuoso Advanced Node Design Environment</title><link>http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/KSqmBEN6a1g/Introduction-to-Cadence-Virtuoso-Advanced-Node-Design-Environment.aspx</link><pubDate>Mon, 28 Jan 2013 13:00:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1311638</guid><dc:creator>Hiro Ishikawa</dc:creator><slash:comments>0</slash:comments><wfw:commentRss>http://www.cadence.com/Community/blogs/cic/rsscomments.aspx?PostID=1311638</wfw:commentRss><comments>http://www.cadence.com/Community/blogs/cic/archive/2013/01/28/Introduction-to-Cadence-Virtuoso-Advanced-Node-Design-Environment.aspx#comments</comments><description>&lt;p&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig6.png"&gt;&lt;/a&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig7.png"&gt;&lt;/a&gt;What can designers do about advanced node technology?&amp;nbsp;This is an introduction to the Cadence Virtuoso Advanced Node design environment, &lt;a href="http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=012813_virtuoso_12_1"&gt;announced&lt;/a&gt; Jan. 28, 2013, as&amp;nbsp;a custom/analog&amp;nbsp;design development environment for leading edge-advanced node technology. &lt;/p&gt;&lt;p&gt;&lt;b&gt;Problems of Advanced Node Design&lt;/b&gt;&lt;/p&gt;&lt;p&gt;When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no one could have anticipated from previous design work.&amp;nbsp; New tools in the design flow need not require a completely new design flow. &amp;nbsp;You should maximize the effectiveness of the current design environment.&amp;nbsp; Then, you need to handle new problems appropriately and accordingly.&lt;/p&gt;&lt;p&gt;Generally speaking, you will need to pay special attention to the following things with advanced node design.&lt;/p&gt;&lt;ul&gt;&lt;li&gt;Multiple Patterning&lt;/li&gt;&lt;li&gt;Layout Dependent Effects (LDE)&lt;/li&gt;&lt;/ul&gt;&lt;blockquote&gt;&lt;blockquote&gt;&lt;p&gt;o Length Of Diffusion (LOD) / STI Stress&lt;br /&gt;o Well Proximity Effect&lt;br /&gt;o Interconnect R, C, and inductance&lt;/p&gt;&lt;/blockquote&gt;&lt;/blockquote&gt;&lt;ul&gt;&lt;li&gt;Use of Local Interconnect Layers&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig1(a).png" border="0" width="297" height="176" alt="" /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 1 (a) Length Of Diffusion (LOD)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig1(b)b.png"&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig1(b)b.png" border="0" alt="" /&gt;&lt;/a&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 1 (b) Interconnect layers&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig1(c).png" border="0" width="297" height="256" alt="" /&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 1 (c) WPE (Well Proximity Effects)&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 1(c)&lt;/b&gt; shows the WPE (Well Proximity Effect), one of the LDEs. The performance of the devices is different for 26db (~12x) depending on the placement locations of the devices from the edge of the well.&lt;/p&gt;&lt;p&gt;For advanced node design, those problems must be evaluated and considered in the design flow.&lt;/p&gt;&lt;p&gt;&lt;b&gt;Current Design Flow&lt;/b&gt; &lt;/p&gt;&lt;p&gt;The current generic design flow that is mainly used for the 45nm and 32nm process nodes is shown in the following &lt;b&gt;Fig 2&lt;/b&gt;. The current design flow represents the collected wisdom of many designers over many development processes. Indeed there is a big advantage of the current design flow because the designer has been familiar with it for a long time.&lt;/p&gt;&lt;p&gt;However, it is also true that the flow has the limitations listed below.&lt;/p&gt;&lt;ul&gt;&lt;li&gt;Each step is connected serially. When some steps have problems, many undesired iterations will be induced.&lt;/li&gt;&lt;li&gt;Automation is not used to its full potential. &lt;/li&gt;&lt;li&gt;Additional and incremental analysis during the design is not easy.&lt;/li&gt;&lt;li&gt;Hidden problems in the design including performance variance affected by LDE can go undetected until a very late phase in the design process.&lt;/li&gt;&lt;/ul&gt;&lt;p&gt;The problems in the advanced nodes listed above all occurred with the previous technology, too. However, the reason that the current (existing) flow that is like the flow shown in &lt;b&gt;Fig 2&lt;/b&gt; is that the effects of those problems in the previous process technologies were very small, and they could be ignored. In the advanced technology required for 20nm or 14nm designs, those problems cannot be ignored. Therefore, the design process cannot be concluded unless designers detect these problems at an early stage of the design, and take necessary actions.&lt;/p&gt;&lt;p&gt;Also, the architectures of double patterning and Interconnect layers have already emerged in the previous technologies. However, these architectures will make a huge impact on performances of designs in advanced node technology. The design process itself needs to be re-evaluated for the advanced node design.&lt;/p&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig2.png" border="0" width="437" height="664" alt="" /&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 2. Current generic design flow&lt;/b&gt;&lt;/p&gt;&lt;p&gt;Therefore, an ideal design environment for advanced node technology is a design flow that allows the user to detect and resolve the non-ignorable problems in advanced node technology without invalidating the usability of the current design flow.&lt;/p&gt;&lt;p&gt;&lt;b&gt;Cadence&amp;#39;s design flow for advanced node technology &lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 3&lt;/b&gt; shows the design flow realized by Cadence Virtuoso Advanced Node design environment.&lt;/p&gt;&lt;p&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig3_reduced.jpg"&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig3_reduced.jpg" border="0" alt="" /&gt;&lt;/a&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;font size="3"&gt;&lt;font face="Calibri"&gt;&lt;/font&gt;&lt;/font&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;b&gt;Fig 3. Cadence Virtuoso Advanced Node design environment for advanced node technology &lt;/b&gt;&lt;p&gt;At first, this flow does not require the user to change his current design flow. It has various enhancements for advanced node technology and inherits properties of the familiar, current design flow.&lt;/p&gt;&lt;p&gt;Several enhancements for advanced node technology are introduced below.&lt;/p&gt;&lt;p&gt;&lt;b&gt;Analog Prototyping Step &lt;/b&gt;&lt;/p&gt;&lt;p&gt;In this step, the user can perform a simulation and consider the LDE before starting the actual layout. This is realized by prototyping the device layout, and simulating the design while considering LDE parameters. With this step, one can dramatically reduce the design modification work caused by performance gaps between the actual design after&amp;nbsp;place and route&amp;nbsp;is completed, and the initial simulation result. &lt;/p&gt;&lt;p&gt;It will work most effectively for considering the WPE (Well Proximity Effect) and performance effects caused by physical stress of the STI (Shallow Trench Isolation). &lt;/p&gt;&lt;p&gt;This step is very powerful because it not only shows LDE effects in a window, but it also allows the user to quickly check and verify characteristic changes due to LDE by running a simulation. &lt;/p&gt;&lt;p&gt;The following figure &lt;b&gt;(Fig 4)&lt;/b&gt; shows this part of the step (Analog Prototyping).&lt;/p&gt;&lt;p&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig4_reduced.jpg"&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig4_reduced.jpg" border="0" alt="" /&gt;&lt;/a&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 4. Analog Prototyping&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Module generation, Device placement Step&lt;/b&gt;&lt;/p&gt;&lt;p&gt;In the real design generation phase, the user can generate modules using Modgen and can place devices using the newly enhanced Pcells.&amp;nbsp; Device placement work in advanced node technology is like pulling teeth.&amp;nbsp; Very complex and rigid design rules need to be satisfied.&amp;nbsp; &lt;b&gt;Fig 5&lt;/b&gt; shows sample complex-design rules related to the device placement.&amp;nbsp; To effectively support those complex design rules, the Pcell abutment function in Cadence Virtuoso Advanced Node design environment was dramatically enhanced.&amp;nbsp; The Pcell abutment function evaluates the relationship between the device to be placed and adjacent devices and realizes the best placements of devices automatically.&lt;/p&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig5b.png" border="0" width="345" height="326" alt="" /&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 5. Example of complex device placement&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Routing step&lt;/b&gt;&lt;/p&gt;&lt;p&gt;Routing work on the Local Interconnect Layer (LI) differs dramatically from the routing on the other routing layers.&amp;nbsp; As the figure (&lt;b&gt;Fig 6&lt;/b&gt;) shows, the LI layers exist between Metal1 and base layers.&amp;nbsp;&amp;nbsp; The layers allow contact-free connection.&amp;nbsp; Also, the length and width of wires on the LI layers are tightly specified.&amp;nbsp; The layers have very rigid constraints.&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig6b_reduced.jpg"&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig6b_reduced.jpg" border="0" alt="" /&gt;&lt;/a&gt;&amp;nbsp;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 6. Local Interconnect Layers&lt;/b&gt;&lt;/p&gt;&lt;p&gt;In Cadence Virtuoso Advanced Node design environment, the user interface has been enhanced as well as the technology file so that the user can smoothly work on routing wires on the local interconnect layers (&lt;b&gt;Fig 7&lt;/b&gt;).&lt;/p&gt;&lt;p style="margin:0in 0in 10pt;" class="MsoNormal"&gt;&lt;span style="color:black;font-size:12pt;"&gt;&lt;/span&gt;&lt;/p&gt;&lt;p style="margin:0in 0in 10pt;" class="MsoNormal"&gt;&lt;span style="color:black;font-size:12pt;"&gt;&lt;/span&gt;&lt;/p&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig7.png" style="width:553px;height:311px;" border="0" width="805" height="495" alt="" /&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 7. Routing Environment for Local Interconnect Layers&lt;/b&gt;&lt;/p&gt;&lt;p&gt;Also, the&amp;nbsp;DPT&amp;nbsp;Assistant (Fig 8) can be used in Cadence Virtuoso Advanced Node design environment so that the routing can easily be done when considering double patterning architecture.&amp;nbsp; The DPT Assistant immediately informs the user where in a design that double patterning conflict occurs.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig8d_reduced.jpg"&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig8d_reduced.jpg" border="0" alt="" /&gt;&lt;/a&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 8.&amp;nbsp; Dynamic Coloring Assistant&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 9 &lt;/b&gt;shows the Odd-Loop Error Detection done by Virtuoso Integrated PVS (IPVS).&amp;nbsp; In Cadence Virtuoso Advanced Node design environment, PVS, a sign-off level Design Rule Checker is fully integrated.&amp;nbsp; It performs &amp;quot;Dynamic Signoff Checking&amp;quot; when a design is updated.&lt;/p&gt;&lt;p&gt;&lt;img src="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig9.png" border="0" width="297" height="176" alt="" /&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Fig 9. Odd-loop error detection&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;&lt;/b&gt;&lt;/p&gt;&lt;p&gt;&lt;b&gt;Conclusion&lt;/b&gt;&lt;/p&gt;&lt;p&gt;This document has been a quick introduction to new features that&amp;nbsp;are available in Cadence&amp;#39;s design development environment for advanced technology.&amp;nbsp; The Cadence Virtuoso Advanced Node design environment is the brand-new design environment that not only supports each new requirement but also integrates new steps into the existing design flow without needlessly disrupting that flow.&lt;/p&gt;&lt;p&gt;Also, the biggest and hidden advantage of this design flow is that software will obviate the possible design problems inherent in advanced node design even if the designer is unaware of these new problems.&amp;nbsp; As the result, the flow can minimize undesired iteration in the design process that was the limitation of the previous design flow.&amp;nbsp; This &amp;quot;Correct-by-Construction&amp;quot; approach realized by Cadence Virtuoso Advanced Node&amp;nbsp;design environment can dramatically reduce the entire design turnaround time.&lt;/p&gt;&lt;p&gt;Hiroshi Ishikawi&lt;a href="http://www.cadence.com/Community/CSSharedFiles/blogs/cic/Hiro%20Ishikawa/Intro_Virtuoso12.1/121_Fig6.png"&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://www.cadence.com/Community/aggbug.aspx?PostID=1311638" width="1" height="1"&gt;&lt;div class="feedflare"&gt;
&lt;a href="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?a=KSqmBEN6a1g:u1Fci1Q1vOE:yIl2AUoC8zA"&gt;&lt;img src="http://feeds.feedburner.com/~ff/cadence/community/blogs/cic?d=yIl2AUoC8zA" border="0"&gt;&lt;/img&gt;&lt;/a&gt;
&lt;/div&gt;&lt;img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/KSqmBEN6a1g" height="1" width="1"/&gt;</description><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Custom+IC+Design/default.aspx">Custom IC Design</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Routing/default.aspx">Routing</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Placement/default.aspx">Placement</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/analog/default.aspx">analog</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/advanced+node/default.aspx">advanced node</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/custom_2F00_analog/default.aspx">custom/analog</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/design+flow/default.aspx">design flow</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/STI/default.aspx">STI</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/module+generation/default.aspx">module generation</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/layout-dependent+effects/default.aspx">layout-dependent effects</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/WPE/default.aspx">WPE</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/dynamic+coloring/default.aspx">dynamic coloring</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/local+interconnect/default.aspx">local interconnect</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/LOD/default.aspx">LOD</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/double+patterning/default.aspx">double patterning</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/well+proximity/default.aspx">well proximity</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/LDE/default.aspx">LDE</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Virtuoso+Advanced+Node/default.aspx">Virtuoso Advanced Node</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/length+of+diffusion/default.aspx">length of diffusion</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/20nm/default.aspx">20nm</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/odd-loop+marker/default.aspx">odd-loop marker</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/Ishikawa/default.aspx">Ishikawa</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/stress/default.aspx">stress</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/interconnect+layers/default.aspx">interconnect layers</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/analog+prototyping/default.aspx">analog prototyping</category><category domain="http://www.cadence.com/Community/blogs/cic/archive/tags/custom/default.aspx">custom</category><media:content url="http://feedproxy.google.com/~r/cadence/community/blogs/cic/~5/jBK8hsKdpVw/1311638.ashx" fileSize="779170" type="image/x-png" /><itunes:subtitle> What can designers do about advanced node technology?&amp;nbsp;This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as&amp;nbsp;a custom/analog&amp;nbsp;design development environment for leading edge-advanced no</itunes:subtitle><itunes:summary> What can designers do about advanced node technology?&amp;nbsp;This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as&amp;nbsp;a custom/analog&amp;nbsp;design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no one could have anticipated from previous design work.&amp;nbsp; New tools in the design flow need not require a completely new design flow. &amp;nbsp;You should maximize the effectiveness of the current design environment.&amp;nbsp; Then, you need to handle new problems appropriately and accordingly. Generally speaking, you will need to pay special attention to the following things with advanced node design.Multiple PatterningLayout Dependent Effects (LDE) o Length Of Diffusion (LOD) / STI Stress o Well Proximity Effect o Interconnect R, C, and inductanceUse of Local Interconnect Layers &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Fig 1 (a) Length Of Diffusion (LOD)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Fig 1 (b) Interconnect layers Fig 1 (c) WPE (Well Proximity Effects) Fig 1(c) shows the WPE (Well Proximity Effect), one of the LDEs. The performance of the devices is different for 26db (~12x) depending on the placement locations of the devices from the edge of the well. For advanced node design, those problems must be evaluated and considered in the design flow. Current Design Flow The current generic design flow that is mainly used for the 45nm and 32nm process nodes is shown in the following Fig 2. The current design flow represents the collected wisdom of many designers over many development processes. Indeed there is a big advantage of the current design flow because the designer has been familiar with it for a long time. However, it is also true that the flow has the limitations listed below.Each step is connected serially. When some steps have problems, many undesired iterations will be induced.Automation is not used to its full potential. Additional and incremental analysis during the design is not easy.Hidden problems in the design including performance variance affected by LDE can go undetected until a very late phase in the design process. The problems in the advanced nodes listed above all occurred with the previous technology, too. However, the reason that the current (existing) flow that is like the flow shown in Fig 2 is that the effects of those problems in the previous process technologies were very small, and they could be ignored. In the advanced technology required for 20nm or 14nm designs, those problems cannot be ignored. Therefore, the design process cannot be concluded unless designers detect these problems at an early stage of the design, and take necessary actions. Also, the architectures of double patterning and Interconnect layers have already emerged in the previous technologies. However, these architectures will make a huge impact on performances of designs in advanced node technology. The design process itself needs to be re-evaluated for the advanced node design. Fig 2. Current generic design flow Therefore, an ideal design environment for advanced node technology is a design flow that allows the user to detect and resolve the non-ignorable problems in advanced node technology without invalidating the usability of the current design flow. Cadence&amp;#39;s design flow for advanced node technology Fig 3 shows the design flow realized by Cadence Virtuoso Advanced Node design environment. Fig 3. Cadence Virtuoso Advanced Node design environment for advanced node technology At first, this flow does not require the user to change his current design flow. It has various enhancements for advanced node technology and inherits properties of the familiar, current design flow. Several enhancements for advanced node technology are introduced below. Analog Prototyping Step In this step, t</itunes:summary><itunes:keywords>Custom IC Design, Routing, Placement, analog, advanced node, custom/analog, design flow, STI, module generation, layout-dependent effects, WPE, dynamic coloring, local interconnect, LOD, double patterning, well proximity, LDE, Virtuoso Advanced Node, length of diffusion, 20nm, odd-loop marker, Ishikawa, stress, interconnect layers, analog prototyping, custom</itunes:keywords><feedburner:origLink>http://www.cadence.com/Community/blogs/cic/archive/2013/01/28/Introduction-to-Cadence-Virtuoso-Advanced-Node-Design-Environment.aspx</feedburner:origLink><enclosure url="http://feedproxy.google.com/~r/cadence/community/blogs/cic/~5/jBK8hsKdpVw/1311638.ashx" length="779170" type="image/x-png" /><feedburner:origEnclosureLink>http://www.cadence.com/Community/blogs/cic/attachment/1311638.ashx</feedburner:origEnclosureLink></item><media:rating>nonadult</media:rating></channel></rss>
