Cadence Custom IC Design Blogshttps://community.cadence.com/cadence_blogs_8/b/cicThe Custom IC Design blog is tailored...en-USZimbra Community 8noThe Custom IC Design blog is tailored...cadence/community/blogs/cichttps://feedburner.google.comSubscribe with My Yahoo!Subscribe with NewsGatorSubscribe with My AOLSubscribe with BloglinesSubscribe with NetvibesSubscribe with GoogleSubscribe with PageflakesThe Art of Analog Design
Part 4: Mismatch Analysishttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/9XjDRT0cG30/the-art-of-analog-design-part-4-mismatch-analysisMon, 16 Oct 2017 00:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:15c90aa4-8780-43b2-a41c-18c50d88ea2cArthur Schaldenbrand0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340493https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/15/the-art-of-analog-design-part-4-mismatch-analysis#comments<p>In <a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/the-art-of-analog-design-part-3-monte-carlo-sampling">Part 3</a>, we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s performance variation? The tool for exploring the relationship process variation and circuit performance variation is mismatch analysis in the tool Virtuoso<sup>®</sup> Variation Option (VVO). </p>
<p>Let’s start by looking at a simple example that shows the sources of offset voltage of a two-pole operational amplifier, see Figure 1.</p>
<p align="center" style="text-align:center;"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/7652.blog-3b-figure-1.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/7652.blog-3b-figure-1.png" style="height:auto;" alt=" " /></a></p>
<p align="center" style="text-align:center;">Figure 1: Two Pole Operational Amplifier</p>
<p style="text-align:center;">Looking at the design, we would expect that mismatch of the p-channel input transistors are the primary source of offset voltage. First, let’s look at the Monte Carlo simulation results for the op-amp, see Figure 2.</p>
<p style="text-align:center;"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/0728.blog-3b-figure-2.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/0728.blog-3b-figure-2.png" style="height:auto;" alt=" " /></a></p>
<p style="text-align:center;">Figure 2: Monte Carlo Analysis Results</p>
<p>The results show that the offset voltage is ~7.3mV. While Monte Carlo analysis tells us how much offset voltage there is, it does not tell us anything about the source of the offset voltage or how much improvement can be achieved. So, what are the sources of the offset voltage? After Monte Carlo analysis, we can plot the relationship between threshold voltage of input p-channel transistors, M17 and PM5, and the n-channel transistors in the first stage load current mirror. The scatter plots in Figure 3 show that there is no correlation between threshold voltage and the offset voltage of the operational amplifier since the correlation between offset voltage and the device threshold voltages is effectively 0.</p>
<p style="text-align:center;"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3443.blog-3b-figure-3.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3443.blog-3b-figure-3.png" style="height:auto;" alt=" " /></a></p>
<p align="center" style="text-align:center;">Figure 3: Scatter Plots, Threshold Voltage versus Offset Voltage</p>
<p>Now let’s try using contribution analysis, see Figure 4.</p>
<p style="text-align:center;"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/5518.blog-3b-figure-4.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/5518.blog-3b-figure-4.png" style="height:auto;" alt=" " /></a></p>
<p align="center" style="text-align:center;">Figure 4: Mismatch Analysis Results</p>
<p>Mismatch analysis shows the relationship between the threshold voltage and the offset voltage. The reasons that the scatter plot showed no correlation was because it looks for linear correlation. Mismatch analysis reports that the dependency is second order, the label shows R^2, The results show that most of the variation, 99.997%, can be explained by the threshold variation of the M17, PM5, NM4, and NM6. The results also show that ~70% of the offset voltage variation is due to the p-channel variation, the contribution from M17 is 34%, and the contribution from PM5 is 34%. The other source of offset voltage variation is the n-channel threshold voltage contribution of 30%.</p>
<p>Let’s use this information and see if we can improve the design. Since the p-channel contributes most of the offset voltage, we will try an experiment. We will increase the p-channel transistor area by 16x, length by 4x and width by 4x, keeping the W/L ratio constant. Increasing the device size should decrease the effect of p-channel mismatch by a factor of four.</p>
<p style="text-align:center;"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/6675.blog-3b-figure-5.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/6675.blog-3b-figure-5.png" style="height:auto;" alt=" " /></a></p>
<p align="center" style="text-align:center;">Figure 5: Monte Carlo Analysis with 16x P-Channel</p>
<p style="text-align:left;">The effect of scaling the p-channel transistors on the offset voltage of the op-amp is to reduce the offset voltage from 7.2mV to 3.7mV. Doing some math, the p-channel offset contribution is ~6.4mV and the n-channel contribution is ~3.3mV. Verifying the offset voltage, the initial offset voltage is (6.4<sup>2</sup>) + (3.3<sup>2</sup>) = 7.2mV. After device sizing, the offset voltage is ((6.4/4)<sup>2</sup>) + (3.3<sup>2</sup>) = 3.7mV.</p>
<p style="text-align:left;">This example shows how mismatch analysis can be used to understand the effect of process variation on circuit performance. While we understand qualitatively that input transistors are the primary contributor to offset voltage, mismatch analysis provides us a tool for qualitative analysis of variation. In the next blog, we will apply mismatch analysis to additional circuits. </p><div style="clear:both;"></div><img src="https://community.cadence.com/aggbug?PostID=1340493&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/9XjDRT0cG30" height="1" width="1" alt=""/>spectre apsAnalog Design EnvironmentVirtuoso Variation Optionmismatch analysisAnalog SimulationMonte CarloCustom IC Designhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/15/the-art-of-analog-design-part-4-mismatch-analysisThe Art of Analog Design
Part 5: Mismatch Analysis IIhttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/m39Ul63KCNE/the-art-of-analog-design-part-5-mismatch-analysis-iiFri, 13 Oct 2017 21:39:27 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:361558c9-e1b2-4833-bd72-22fcbfae5765Arthur Schaldenbrand0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340491https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/13/the-art-of-analog-design-part-5-mismatch-analysis-ii#comments<p>In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology to other types of designs..</p>
<p>The first case we will look at is a circuit without a DC operating point. A dynamic comparator, see Figure 1, doesn’t have a quiescent operating point making it difficult to analyze.</p>
<p><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3036.blog-3c-figure-1.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3036.blog-3c-figure-1.png" style="height:auto;display:block;margin-left:auto;margin-right:auto;" alt=" " /></a>In this case, the offset voltage is measured using transient analysis. A positive and a negative staircase is applied at the input and the input value which results in the output switching being recorded, the average value of input levels is the offset voltage. To increase the resolution of the offset voltage measurement, the step size needs to be small. In this case, the step size of the staircase ramp is 100mV. A Verilog A module was used as the signal source to generate the staircase, see Figure 2. For more details about measuring dynamic comparator offset Voltage, please see the <a href="https://support.cadence.com/COSAgreementPage?artId=a1Od00000066Mn2EAE&id=069d0000003F74eAAC">ADC Verification Workshop Rapid Adoption Kit</a> in Cadence online support.</p>
<p><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/5102.blog-3c-figure-2.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/5102.blog-3c-figure-2.png" style="height:auto;display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p>Looking at the comparator, we would expect that the mismatch of the p-channel input transistors is the primary source of offset voltage. After the Monte Carlo analysis, we will use scatter plots showing the random variable causing mismatch for three transistors: NM2, NM3, and NM4, see Figure 3a. For the devices in the differential pair, NM2 and NM3, we can see that there is correlation between the offset voltage and the input transistors, the correlation coefficient is r about 0.5. For the current source transistor, NM4, there is no correlation, the correlation coefficient r about 0, between the offset voltage and the transistor’s variation. So, the scatter plots are consistent with our expectations about how the devices are impacted and the statistical variation.</p>
<p><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/4544.blog-3c-figure-3.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/4544.blog-3c-figure-3.png" style="height:auto;display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p>Again, we can see the utility and the limitations of the scatter plot. Qualitatively the scatter plot allows us to visualize the relationship between the inputs, statistical variables, and the outputs measured values. However, it is difficult to extract quantitative information from the results. So, while we can use scatter plots to confirm what we already know, they don’t really provide any additional information to designers.</p>
<p>We will use mismatch analysis to analyze the relationship between variations on offset voltage. The mismatch analysis results are shown in Figure 4. Again, we see that offset voltage has a non-linear, second-order relationship with the statistical variables. We can also see that most of the variation, 99.935% is accounted for by the mismatch results. We can see that ~90% of the offset voltage is due to the input transistor variation. Mismatch analysis considers the variation at the statistical variable level: NM2.rn2 contributes 30%, NM3.rn2 contributes 29%, NM2.rn1 contributes 17%, and NM3.rn1 contributes 16%. While our naming convention could be more explicit, you can think about the variables as the individual contributions to variation: gate oxide thickness variation and gate length variation. Another observation is that there is another source of offset voltage variation, the cascode transistors, NM0 and NM1. While not significant, it useful to know that mismatch analysis has enough resolution to identify small contributors.</p>
<p></p>
<p align="center"><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/7268.blog-3c-figure-4.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/7268.blog-3c-figure-4.png" style="height:auto;" alt=" " /></a></p>
<p>Mismatch analysis provides designers a tool to analyze the effect of mismatch qualitatively and quantatively. </p>
<p>To summarize, the mismatch analysis is a useful tool to analyze the results of Monte Carlo analysis. In this case, we analyzed the effect of variation on a dynamic comparator. Traditionally it is difficult to analyze a dynamic comparator because it is not a linear circuit with a DC operating point. Perhaps more than anything else, the ability to analyze circuits that designers have not been able to analyze in the past is the true value of mismatch analysis.</p><div style="clear:both;"></div><img src="https://community.cadence.com/aggbug?PostID=1340491&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/m39Ul63KCNE" height="1" width="1" alt=""/>spectre apsoffset voltagemismatch analysisAnalog SimulationADEMonte Carlo analysisStrong Arm latchdynamic comparatorhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/13/the-art-of-analog-design-part-5-mismatch-analysis-iiVirtuosity: Can I Speed up My Plots?http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/gL77E0SfEhU/quick-plotFri, 13 Oct 2017 14:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:795663a7-ee49-4627-a383-39742a621129AdityaMainkar0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340263https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/13/quick-plot#commentsIf your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® ADE XL setup contains multiple sweeps or corner points, or maybe the transient simulations are time consuming, then plotting waveforms using Plot All may consume significant time and memory.
Here, Quick Plot will help you out. Quick Plot will plot outputs in Virtuoso Visualization and Analysis, faster and with much less memory usage.(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/13/quick-plot">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340263&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/gL77E0SfEhU" height="1" width="1" alt=""/>Analog Design EnvironmentADE GXLADE ExplorerExplorerADE XLanaloglicenseADEMixed-SignalVirtuoso Analog Design EnvironmentVirtuosoADE-GXLAnalog Design EnvironmentViVAADE-XLVirtuositymixed signalCustom IC DesignADE Assemblerhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/13/quick-plotVirtuosity: Power Filtering!http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/W2EYGuMt4Aw/virtuosity-advanced-filteringThu, 05 Oct 2017 16:09:19 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8ae12f58-d615-4e25-bf90-3de6b44fb66eArja Hunkin0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340337https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/05/virtuosity-advanced-filtering#commentsFinally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data View and Setup assistants in Virtuoso ® ADE Explorer and Virtuoso ® ADE Assembler. But, they are not just for finding basic strings like vdd or 1p. They can do so much more; filtering for values within a range, finding strings containing all or any of the words you specify, filtering for prefixes or suffixes, and so on. Let's see what advanced filtering these filters are capable of.(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/05/virtuosity-advanced-filtering">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340337&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/W2EYGuMt4Aw" height="1" width="1" alt=""/>Analog Design EnvironmentADE ExplorerFilteringADEVirtuoso Analog Design EnvironmentAnalog Design EnvironmentADE Assemblerhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/10/05/virtuosity-advanced-filteringThe Art of Analog Design: Part 3, Monte Carlo Samplinghttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/Ur-Pm7C49m8/the-art-of-analog-design-part-3-monte-carlo-samplingSat, 23 Sep 2017 05:25:18 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a6b0ce69-4554-4bf1-91d4-397df7c35903Arthur Schaldenbrand0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340429https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/the-art-of-analog-design-part-3-monte-carlo-sampling#comments<p>In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider what happens once Monte Carlo analysis is complete. Of course, we will need to analyze the results, so let’s look at some of the tools for visualizing what the Monte Carlo analysis is trying to show us about the circuit.</p>
<p>First let’s review the results from the previous blog. The circuit being simulated is a Capacitor D/A Converter, or CAPDAC. The CAPDAC is used in a Successive Approximation ADC to generate the reference levels for comparison. The mismatch of the unit capacitors in the CAPDAC contributes to degradation of the CAPDAC SINAD (Signal-to-Noise and Distortion ratio) and is an important contributor in determining the overall SINAD of the ADC. This CAPDAC is used in a 10 Bit ADC. Based on the error budget for the ADC, if the CAPDAC has a SINAD of 60dB or better we will be able to meet our ADC SINAD target. The CAPDAC SINAD was simulated using Monte Carlo with auto-stop, yield target of 60dB for SINAD, yield of 3s or greater, confidence level of 90%, and Low Discrepancy Sampling, LDS, method. The simulation required 1755 samples to meet the 90% confidence requirement level.</p>
<p>In the last blog append, we looked at the. The effect of process variation on SINAD distribution was plotted, see figure 1. To help understand the how CAPDAC performance compared to the specification,. The specificationthe pass/fail limits have been overlaid on top of the distribution, green is pass and red is fail.</p>
<p><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/2818.blog3a_5F00_figure1_5F00_MonteCarloDistribution.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/2818.blog3a_5F00_figure1_5F00_MonteCarloDistribution.png" style="height:auto;display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p align="center">Figure 1: CAPDAC SINAD distribution</p>
<p>The plot also has bars showing the mean value, s, and the values of standard deviation from -3σto +3σ allowing us to visualize how much margin the CAPDAC has relative to the specification. For the CAPDAC there is almost 2s close margin between the specification and the upper limit of the specification, -3s limit, of the distribution.</p>
<p>One observation from looking at the distribution, is that the distribution appears to have a long tail. In statistics, distributions with long tails means that the distribution has a large number of occurrences far from the central part of the distribution. Looking at the distribution, we can see that on the positive side of the distribution, there is only one point that is > +2s from the mean. While on the negative side of the distribution, there are many data points, < -3s from the mean. Next, let’s apply another tool, quantile-quantile plotting. The purpose is to test our simulated distribution and is a Normal (or Gaussian) distribution. A quantile-quantile plot is a technique to evaluate if two distributions are the same by plotting their quantiles against each other where the quantiles are points taken at regular intervals from the cumulative distribution function (CDF) of a random variable. The 0-quantile of distribution is the median, it is the value where half the samples in the distribution are higher in value than the median and half of the samples in the distribution are lower in value the median. Since the distribution is skewed, the mean value will not be equal to the median value.</p>
<p><a href="https://community.cadence.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3122.blog3a_5F00_figure2_5F00_QuantilePlot.png"><img src="https://community.cadence.com/resized-image/__size/1200x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-15/3122.blog3a_5F00_figure2_5F00_QuantilePlot.png" style="height:auto;display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p align="center">Figure 2: Quantile-quantile plot for CAPDAC SINAD</p>
<p>If the simulated distribution is a straight line when plotted against the reference distribution, the Normal distribution, then the distributions match and the simulated distribution is Gaussian. As expected, the simulated distribution is not a straight line when plotted against the Normal distribution (see Figure 2). The distribution is only Normal in the region from -1s to +1s of standard deviation. Another way to look at the effect of the long tail is to consider how the CAPDAC yield compares to the expected yield of a Normal distribution. For the CAPDAC, there is 1 failure for 1755 samples. The worst-case value of CAPDAC SINAD is 59.85dB, -5.2s from the mean value. Using the Normal distribution, the expected failure probability for 5s deviation from the mean value is 1 failure per 3.5 million attempts. The effect of the long tail, non-Normal nature of the distribution, is a significant reduction in the yield compared to the yield when the distribution is a Normal distribution. Using quantile-quantile plots provides a powerful tool for visualizing whether the simulated distribution is a Normal distribution or not.</p>
<p>Next, let’s look at another measurement that is useful for designers. First, let’s determine the process capability index or Cpk value. The Cpk is a statistical measure of process capability which is the ability of a process to produce output within specification limits. For the CAPDAC, the Cpk is one of the outputs in the Virtuoso ADE Assembler results window (see Figure 3). The Cpk can only be output if a specification has been defined.</p>
<p>The Cpk is defined as the ratio of the distance from the mean value to the specification in standard deviations over the distance from the mean value to the actual distribution limit in standard deviation. For the CAPDAC, the numerator is 4.6s, the distance from the mean value of 61.15dB to 60dB in sigma, see sigma to target. The target yield was 3s so the denominator is 3s. </p>
<p>The less precise way to think about Cpk, is to think of it as a measure of design margin. It tells us how much margin we have between the actual limit of the process and the user’s expectation for the process.</p>
<p>To summarize we have looked at two tools for visualizing the results of Monte Carlo analysis and using the tools to identify problems. Plotting distributions allows us to understand how well centered a design is. Quantile plots allow us to look at the distribution and identify if it has a long tail since a long tail can translate into poor yield. And by using Cpk we can quantify how much design margin we have. In the next blog post, we will start to look at what we can do to identify and correct issues. </p><div style="clear:both;"></div><img src="https://community.cadence.com/aggbug?PostID=1340429&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/Ur-Pm7C49m8" height="1" width="1" alt=""/>Analog Design EnvironmentAPSADE ExplorerAnalog SimulationanalogADEMonte CarloAnalog Design EnvironmentViVAADE AssemblerCusstom IC Design In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider what happens once Monte Carlo analysis is complete. Of course, we will need to analyze the results, so let’s look at some of the tools for visualizing what the Monte In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider what happens once Monte Carlo analysis is complete. Of course, we will need to analyze the results, so let’s look at some of the tools for visualizing what the Monte Carlo analysis is trying to show us about the circuit. First let’s review the results from the previous blog. The circuit being simulated is a Capacitor D/A Converter, or CAPDAC. The CAPDAC is used in a Successive Approximation ADC to generate the reference levels for comparison. The mismatch of the unit capacitors in the CAPDAC contributes to degradation of the CAPDAC SINAD (Signal-to-Noise and Distortion ratio) and is an important contributor in determining the overall SINAD of the ADC. This CAPDAC is used in a 10 Bit ADC. Based on the error budget for the ADC, if the CAPDAC has a SINAD of 60dB or better we will be able to meet our ADC SINAD target. The CAPDAC SINAD was simulated using Monte Carlo with auto-stop, yield target of 60dB for SINAD, yield of 3s or greater, confidence level of 90%, and Low Discrepancy Sampling, LDS, method. The simulation required 1755 samples to meet the 90% confidence requirement level. In the last blog append, we looked at the. The effect of process variation on SINAD distribution was plotted, see figure 1. To help understand the how CAPDAC performance compared to the specification,. The specificationthe pass/fail limits have been overlaid on top of the distribution, green is pass and red is fail. Figure 1: CAPDAC SINAD distribution The plot also has bars showing the mean value, s, and the values of standard deviation from -3σto +3σ allowing us to visualize how much margin the CAPDAC has relative to the specification. For the CAPDAC there is almost 2s close margin between the specification and the upper limit of the specification, -3s limit, of the distribution. One observation from looking at the distribution, is that the distribution appears to have a long tail. In statistics, distributions with long tails means that the distribution has a large number of occurrences far from the central part of the distribution. Looking at the distribution, we can see that on the positive side of the distribution, there is only one point that is > +2s from the mean. While on the negative side of the distribution, there are many data points, < -3s from the mean. Next, let’s apply another tool, quantile-quantile plotting. The purpose is to test our simulated distribution and is a Normal (or Gaussian) distribution. A quantile-quantile plot is a technique to evaluate if two distributions are the same by plotting their quantiles against each other where the quantiles are points taken at regular intervals from the cumulative distribution function (CDF) of a random variable. The 0-quantile of distribution is the median, it is the value where half the samples in the distribution are higher in value than the median and half of the samples in the distribution are lower in value the median. Since the distribution is skewed, the mean value will not be equal to the median value. Figure 2: Quantile-quantile plot for CAPDAC SINAD If the simulated distribution is a straight line when plotted against the reference distribution, the Normal distribution, then the distributions match and the simulated distribution is Gaussian. As expected, the simulated distribution is not a straight line when plotted against the Normal distribution (see Figure 2). The distribution is only Normal in the region from -1s to +1s of standard deviation. Another way to look at the effect of the long tail is to consider how the CAPDAC yield compares to the expected yield of a Normal distribution. For the CAPDAC, there is 1 failure for 1755 samples. The worst-case value of CAPDAC SINAD is 59.85dB, -5.2s from the mean value. Using the Normal distribution, the expected failure probability for 5s deviation from the mean value is 1 failure per 3.5 million aAnalog Design Environment, APS, ADE Explorer, Analog Simulation, analog, ADE, Monte Carlo, Analog Design Environment, ViVA, ADE Assembler, Cusstom IC Designhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/the-art-of-analog-design-part-3-monte-carlo-samplinghttps://community.cadence.com/cfs-file/__key/telligent-evolution-components-attachments/01-15-00-00-01-34-04-29/Why-should-I-care-about-this-stuff-anyway-Part-3a-v3.docxVirtuosity: Sweeping Multiple DSPF Views in ADEhttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/vUfTbgooXkU/virtuosity-sweeping-multiple-dspf-files-in-adeFri, 22 Sep 2017 13:47:37 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e5df3df5-6797-460f-bcee-7edd41fbfdb4Arja Hunkin0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340187https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/virtuosity-sweeping-multiple-dspf-files-in-ade#commentsWouldn't it be great if you could have a view for your DSPF files and sweep them in an ADE session without having to add them as simulation files? Well now you can!
You can create a DSPF view just like any other view, schematic, layout, extracted - and this can be easily included in any ADE simulation. You can also combine this with the config sweep feature to enable you to sweep several DSPF views at once. Just make note that the top-level test bench must be a config. Let's see how to do this...(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/virtuosity-sweeping-multiple-dspf-files-in-ade">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340187&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/vUfTbgooXkU" height="1" width="1" alt=""/>Analog Design EnvironmentViVa-XLcustom/analogADE ExplorerAnalog SimulationDSPFADEBlock-level simulationVirtuoso Analog Design EnvironmentAnalog Design EnvironmentSchematic EditorViVAVirtuosityCircuit DesignCustom IC DesignSchematicADE Assemblerhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/22/virtuosity-sweeping-multiple-dspf-files-in-adeVirtuosity: Sweeping Multiple Config Viewshttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/tZ9VLz4TP4s/sweeping-multiple-config-viewsMon, 18 Sep 2017 13:41:36 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3a6ce84a-1e03-426f-a552-027c530987bbArja Hunkin2https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340188https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/18/sweeping-multiple-config-views#commentsBefore IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in your design. What if you have more than one block that has multiple views that you want to sweep? Well from ISR10 onwards, you can do that. Here's how.(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/18/sweeping-multiple-config-views">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340188&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/tZ9VLz4TP4s" height="1" width="1" alt=""/>Analog Design EnvironmentADE ExplorerExplorerAnalog SimulationADEVirtuoso Analog Design EnvironmentAnalog Design EnvironmentSchematic EditorVirtuosityCircuit DesignCustom IC DesignSchematicADE Assemblerhttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/18/sweeping-multiple-config-viewsVirtuosity: What Color is Your Virtuoso Wearing Today?http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/k3m2PNgnwDk/virtuosity-what-color-is-your-virtuoso-wearing-todayFri, 15 Sep 2017 14:11:26 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e71e39c4-b648-4150-8241-0941ea436715Rishu Misri Jaggi0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340415https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/15/virtuosity-what-color-is-your-virtuoso-wearing-today#commentsLike you, Virtuoso can dress in a different color too every day. Interested to know, how? Read on to find out ....(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/15/virtuosity-what-color-is-your-virtuoso-wearing-today">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340415&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/k3m2PNgnwDk" height="1" width="1" alt=""/>Customize VirtuosoVirtuoso Editorcolorcolor-aware designVirtuosityCustom IChttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/15/virtuosity-what-color-is-your-virtuoso-wearing-todayVirtuosity: Driving Along a Longer Route May Take You Home Sooner!http://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/CFOeFHOV-kk/virtuosity-driving-a-longer-route-may-help-reach-home-soonerTue, 12 Sep 2017 13:16:13 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:75ccf712-e555-48e3-8ad2-45e651b1a68bRishu Misri Jaggi0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340271https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/12/virtuosity-driving-a-longer-route-may-help-reach-home-sooner#commentsOn my way back home every day, I need to make a decision — should I drive less, or more? Because, there are two different routes that I can take to home. The shorter route is usually busier at peak traffic times. The other route, is long.
When I reach the cross road, I almost get swayed in to take the shorter, seemingly straight path. The days I give in to that temptation, I usually reach home late.
It can be the same when using software — what may seem to be a harmless shortcut could cost you a lot of troubleshooting time. Here's how a customer recently experienced this when copying a library in Virtuoso.(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/12/virtuosity-driving-a-longer-route-may-help-reach-home-sooner">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340271&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/CFOeFHOV-kk" height="1" width="1" alt=""/>library managerVirtuosoVirtuosityphysConfigCPHcopy libraryCustom IChttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/12/virtuosity-driving-a-longer-route-may-help-reach-home-soonerVirtuosity: Saving, Loading and Sharing ADE Annotation Settingshttp://feedproxy.google.com/~r/cadence/community/blogs/cic/~3/Gnvt0e96dPI/virtuosity-sharing-and-automatically-loading-ade-annotation-settingsThu, 07 Sep 2017 09:17:51 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2528fb72-ada1-44bc-a085-5cb4f099d34eArja Hunkin0https://community.cadence.com/cadence_blogs_8/b/cic/rsscomments?WeblogPostID=1340321https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/07/virtuosity-sharing-and-automatically-loading-ade-annotation-settings#commentsThe whole ADE annotation flow was overhauled way back in IC6.1.6 but at that time there was no way to share the annotation settings between designs, or to automatically load them. Well, in IC6.1.7 ISR13 we have added the ability to do both!
(<a href="https://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/07/virtuosity-sharing-and-automatically-loading-ade-annotation-settings">read more</a>)<img src="https://community.cadence.com/aggbug?PostID=1340321&AppID=15&AppType=Weblog&ContentType=0" width="1" height="1"><div class="feedflare">
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</div><img src="http://feeds.feedburner.com/~r/cadence/community/blogs/cic/~4/Gnvt0e96dPI" height="1" width="1" alt=""/>ADE ExplorerAnnotation SettingsADE AnnotationsADEAnalog Design EnvironmentSchematic EditorVirtuositySchematicADE Assemblerannotation setuphttps://community.cadence.com/cadence_blogs_8/b/cic/archive/2017/09/07/virtuosity-sharing-and-automatically-loading-ade-annotation-settingsnonadult