Cadence Digital Implementation Blogs

Using A Dual Flop Methodology for Dynamic Power Savings

Design4Life — Fri, 10 Jul 2009 13:00:00 GMT

Imagine this scenario: Your chip is a low power design. You’ve used everything in the book – clock gating, multiple threshold optimization, power shutoff, multiple supply voltages etc. What else can you do to reduce power in your design?

Or, maybe you can’t do power shutoff – the entire device is always on. Maybe you can’t use multiple supply voltages (face it – if you’re already running at 0.8V, how much lower can you go?) But you know you have plenty of random logic, and you know you have to reduce power in your design.

A dual flop methodology could help to furter reduce power in your design. What is a dual flop? It’s basically two flops physically merged into one. Kind of like a multi-bit flop, but in parallel instead of in series. The merged flop will share the same clock pin, but besides that, it’ll have two separate inputs and outputs.

This setup saves dynamic power in two ways: first of all, there is some savings from efficiency by using a common clock pin. In the worst case scenario, the new clock pin will have double the amount of capacitance, resulting in no significant savings, but usually there is some amount of efficiency and the resulting capacitance of the clock pin will not be double the original capacitance of the individual clock pins, but some amount less than that. Therefore some amount of dynamic power will be saved there.

The second way this setup saves dynamic power is in the clock network distribution. For every two flops, instead of the clock network having to route to two individual places, the clock network now only has to reach one location. Therefore, dual flops are more tighly clustered than individual flops, which results in savings on clock distribution net length, and more importantly, the buffers needed to drive the clock distribution network.

So, how much power does dual flop save? It really depends on what kind of design you’re dealing with. For designs with a large portion of random logic, and especially designs where clock power is a significant contributor to total power (e.g. designs with large clock networks or low signal-to-clock switching ratio), using a dual flop methodology will yield better results. Used in the right design category, a dual flops methodology has the potential of saving roughly 10%-20% of total power in the design.

What do you think?

Wei Lii Tan

Flow? What Flow?

Design4Life — Thu, 02 Jul 2009 21:30:00 GMT

For EDA software, it seems that it takes just as much effort to develop a methodology to use the software, as writing the tool itself. Ask any CAD group or design group that has to develop their own methodology and you can quickly gauge the many challenges in building a flow for your favorite EDA tool.

Why is it so hard to build and maintain a working flow? There are many reasons. First of all, EDA tools change. Updates, revisions, bug fixes etc - all these change the way the tool is used, sometimes incrementally, or sometimes in a drastic way. Secondly, every design is unique in at least a couple of ways. Design requirements (whether it's a low power design, or a 32nm design that needs advanced node capabilities, or both) dictate the necessity of steps needed in the design flow.

EDA companies have all tried to create flow wrappers that cater for every design (similar to a makefile system), but there are challenges in that too - with unique design requirements in each design, as well as ever-changing use models, creating an all-encompassing design methodology system is difficult.

One thing that EDI System has done is not to focus on creating a comprehensive flow wrapper, but a set of "Foundation Flows" that act as a baseline for user-customizable flow scripts. These Foundation Flows are based on a specific need, e.g. a Timing Closure Foundation Flow, or Low Power Foundation Flow, and contain a set of commands that are usually used by designers, in the order they are usually done. Foundation flows are available starting EDI System 8.1.

In your design environment today, how is the issue of flows handled? Is there a central group that handles flow-related issues for design groups? Do you use a makefile system? Or do design teams build their own custom flow for each project? Most importantly, do you think flow management should be provided by the tool? Sound off in the comments section!

Wei Lii Tan
Cadence Design Systems

Cadence: Committed to DFM

mchacko — Sat, 20 Jun 2009 01:19:00 GMT

On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions. A few of the published items do not accurately describe the actions that were taken, and we’d like to set the record straight.

Manufacturing-side DFM involves post-tapeout processing that transitions a finished layout into the factory (i.e. for manufacturing). Cadence has successful offerings in this area and will continue to appropriately invest. But in select areas such as mask proximity correction our investment will decrease as we emphasize design-side DFM.

Design-side DFM means seamless incorporation of manufacturing process effects within the design environment – like the Cadence Encounter® Digital Implementation System and Cadence Virtuoso® custom design environment – so designers can implement manufacturing-friendly designs that achieve higher yield and performance while meeting tight design schedules.

Our design-side DFM tools, including Cadence Litho Physical Analyzer (LPA), Cadence Litho Electrical Analyzer (LEA), Cadence Chemical-Mechanical Polishing (CCP) Predictor, and Cadence Pattern Analyzer (CPA), are production proven at multiple technology nodes. The Cadence LPA, for example, was the first tool qualified by TSMC from 90nm through the advanced nodes. The Cadence LEA is the first of its kind in the EDA industry. And the Cadence CCP is the established CMP predictor tool used by most leading foundries and IC manufacturers.

Today most of the top 20 semiconductor companies use Cadence design-side DFM tools. Leading semiconductor companies like TI, Freescale, AMD, Broadcom, Qualcomm, TSMC, Chartered, UMC, NXP, NEC and others have publicly described the successes they have had with our tools and technology in published papers. Cadence continues to develop and integrate DFM technology to address next-generation manufacturing requirements, such as double patterning. We hope this perspective clears up any confusion generated by speculative blogs. Cadence is committed to DFM.

Manoj Chacko

Technical Webinars Hosted by the Experts - Don't Miss Them!

soheilm1 — Thu, 18 Jun 2009 17:33:00 GMT

Starting June 23, 2009, Cadence technical experts will host a series of technical webinars on myriad of topics. During this free webinar series, you’ll discover possible solutions and best practices to overcome the challenges you may be facing today or ones you’ll soon be facing. Learn new applications and methodologies, ask questions, and follow up with our technical experts after the event to continue the discussion. These webinars are slated to be technical and interactive. Choose the topic that interest you most, or attend all 7 webinars. Our objective is to assist you in overcoming your design challenges, to hear your feedback, and to hear about your design experiences. You don’t have to travel for this; you can listen to these presentations from the comfort of your home or office.

Webinar #1: Design Planning: Plan for the Inevitable - June 23

Webinar #2: Transitioning from Flat to Hierarchical: How Scary is That? - June 24

Webinar #3: Block Timing Closure: Get the Most out of Your Timing Closure Engine - June 25

Webinar #4: Low-Power Design: Making Advanced Low-Power Techniques a Physical Implementation Reality - July 14

Webinar #5: Advanced 45/32nm Design: Don't Sit on the Fence, Take the Jump! - July 16

Webinar #6: Understanding Impact of Implementation Choices, Linking Back to Original IC Design Goals - July 21

Webinar #7: Don't be Late for Your Date: How to Actually Tapeout and Schedule with Better Powr and Timing Convergence - July 23

Attend one webinar or all 7 webinars, listen to experts, ask questions, and follow up via additional blog discussions, live discussions, or hands-on workshops. I encourage you to come back to this blog and post your questions and/or comments after every webinar. Our experts would like to hear from you.

Visit http://www.secure-register.net/cadence/encounter_webinars for more details and to register.

Soheil Modirzadeh

MarCom 2009 - New, Exciting, Educational

soheilm1 — Fri, 29 May 2009 12:00:00 GMT

As a Marketing Communications professional, I am always looking for creative ways to communicate with our current and potential customers. Over the last 13 years that I have been in this profession, I have seen many methods and vehicles used by Cadence and various other companies to reach out to external and internal audiences. I must say that some of the things I have seen have been pretty creative and unique. Last year we got together and came up with a unique way of our own to communicate with our current and potential customers. You see, we were about to launch a very unique product and wanted to make things more exciting for visitors to learn and get educated.

We launched Encounter Digital Implementation (EDI) system last December. We had all the basic materials developed and ready for distribution - web, printed collateral, internal content, PR activities, etc. However, we needed an extra kick to better communicate with our audience. We came up with what you see on the site now. Interactive presentations and reference materials are available for each of the topics in EDI System; after each material is reviewed, visitors take a quiz and beomce certified in a specific topic. Visitors don't have to stop there; they can get up to 5 certificates and enter to win cool prizes. Since its launch 1000s of folks have visited and participtaed in the web-based training and communication program. We have had 5 monthly winners and 1 grand prize winner. I was able to ask some of the winners about their expereinces going through the program and here is what they had to say:

"This campaign is really good and helpful to understand the Cadence Encounter Digital Implementation System. I like the way of representation of the tool capabilities in the form of quizzes supported by the very informative video lectures and PDF reference materials. So many different aspects are integrated in a single platform is really very helpful for the designers. I like the whole campaign very much and very informative. I am thankful to you for taking such innovative steps and wish you all success."

Thanx and Regards,
Jai Prakash Sharma
(January winner)

"I thought the training process was great, and very convenient. Some modules I did at home sipping a beer and some from work (not sipping beer). I could start and stop as I took various interrupts and rewind the module as necessary.

The reference guides were useful when taking the quiz and reinforcing some ideas that were presented that I was unclear about. I don’t think the presentations were the cause of my unclarity but rather me taking interrupts during the presentation and the quantity of information presented. I will refer to the documents again when I need to since now that I know where they are and what they are about.

I will point my piers and managers to this website. And as time goes on, hopefully, everyone will understand the effort required to produce a low-power, mixed-signal, small-geometry device and that there is a methodology that can cover the new design hurdles."

Rich Harwood
(February winner)

There is still time to participate and learn about EDI System - and win prizes! I encourage you to give this a try and let me know your thoughts. You never know, you may win a prize or two at the same time. Looking forward to hearing from you,

Soheil Modirzadeh
Sr. MarCom Manager
Digital IC Design, Logic Design, Low Power

Getting Started with dbSet

Kari — Mon, 18 May 2009 13:00:00 GMT

A while back, I posted a blog called Getting Started with dbGet. It was a brief introduction to this database access mechanism. Well, dbGet is only half the story - there is also a command called dbSet, which can give you even more power in your scripting or manipulating of the design database.

It works in much the same way as dbGet. As a quick review, let's say we wanted to find out the placement status of the instances in our design. If we didn't remember the exact syntax, we would start with:

> dbGet top.?

The ? will list all the things we can look at regarding "top", the top cell of our design.

> topCell: fPlan hInst insts name nets numBidirs numInputs numInsts numNets numPhysInsts numPhysNets numTerms objType pgTerms physInsts physNets props statusClockSynthesized statusGRouted statusIoPlaced statusPlaced statusPowerAnalyzed statusRCExtracted statusRouted statusScanOpted terms

What we want is insts, or all the instances in the design:

>dbGet top.insts.?
>inst: box cell instTerms isDontTouch isHaloBlock isJtagElem isPhysOnly isSpareGate name objType orient pStatus pgCellTerms pgTermNets pt

And finally, pStatus (placement status):

>dbGet top.insts.pStatus
>fixed placed placed placed placed... (etc.)

So now that we have the attribute we want, let's change it! Suppose we want all the instances to be fixed and not just placed. Well, dbSet makes this very easy:

>dbSet top.insts.pStatus fixed

If you reissue the dbGet command, you'll see that all the instances are now fixed.

Here's a more realistic example. I had a design where I wanted to fix the placement of all of my adder cells. They were large cells, and allowing them to be moved around after their initial placement would cause them to be placed far away from their original location. So, first I had to grab pointers to all of the adder cells:

>dbGet -p2 top.insts.cell.name ADD*

The -p2 means to grab the database pointers of the instances gathered by this command, which means all instances whose master cell names start with ADD. (For some more explanation of how the -p function works with dbGet, see the post A dbGet Code Example).

Now that I have those pointers, I can examine the placement status of these instances:

>dbGet [dbGet -p2 top.insts.cell.name ADD*].pStatus

But what I really want to do is set the placement status to fixed, so the final line would look like this:

>dbSet [dbGet -p2 top.insts.cell.name ADD*].pStatus fixed

For a list of attributes that are editable with dbSet, you can check out Appendix B of the Encounter Text Command Reference. Scroll down the tables and look at the "Editable" column. Most of the editable attributes fall under the "inst" database object.

I hope this short introduction to dbSet has inspired you to check it out and use it in your scripts. Let me know in the comments how you're using dbSet. I'm always interested to see clever one-line dbGet/dbSet commands. In fact, I'm collecting them for a future post. (Don't worry, I'll give you credit!)

Kari Summers

EDA Industry Stays Ahead of Technology Curve

Nora — Tue, 05 May 2009 12:00:00 GMT

The EDA Industry is the unsung hero behind for modern era electronic revolution since early 80s and gets the spotlight it deserves in the recent DAC newsletter.

I would like to applaud the author Geoffrey James, for crediting the EDA industry in rising to the challenges associated with each and every technology process node, in particular advancing the use of multi-core architectures. The EDA industry continues to help the semiconductor sector by solving some of their core business issues, such as chip performance, reliability, power consumption, manufacturability and productivity.

The demand for higher clock frequency and less power/heat dissipation is the main driving force for multi-core configuration. As an enabler, the EDA industry must stay ahead of the curve. We must invigorate parallelism, multi-tasking capability within applications while delivering an array of automation tools for design implementation, analysis and validation. We must also continuously focus on ease-of-use to enable better and faster design of multi-core systems, and enable time-to-market saving for our users. “The EDA industry has always depended upon the most-recent generation of chips to provide the power needed to crunch the data required to build the next generation” noted by Tom Spyrou, Cadence Distinguished Engineer and Encounter Platform RnD Manager, who is featured in this interview.

This challenge is immersive, and the Encounter Digital Implementation System is a great example. One of the obvious challenges is transforming enormous number of lines of code, that were not written to be parallel, to be multi-threaded, distributed or both. The solution must also be optimized for scalable performance and adhere to our customers’ unique computing environments and needs. Another challenge, which is equally important, is to speed up any serial computation steps left in the flow, else the performance gains from multi-threading in a RTL to Signoff flow could be significantly limited, according to Amdahl’s law.

With its unified client-server multi-cpu backplane, the Encounter platform has supported multi-processing since 1999, and has been continuously optimized for performance over time. Encounter’s focus is on overall flow performance from end-to-end, and we often achieve an average 2X- 4X runtime/memory footprint improvement per each major release. The latest release of the Encounter platform, called the Encounter Digital Implementation System is multi-cpu enabled by default.

In addition, to enable efficiency throughout the complete design flow, adjacent products such as sign-off analysis, DFM validation, the Virtuoso platform, functional verification and simulation are all multi-cpu enabled. It is Cadence’s goal to stay at the forefront in this, offering fully integrated and comprehensive parallel processing throughout back-end implementation. No matter what new challenges may come down the road, the EDA industry must continue to help the semiconductor industry overcome obstacles and deliver new, innovative products despite the economic slow down.

To learn more about the state of the art in multi-process Encounter applications, join us at the Parallelism tutorial at the 46th Design Automation Conference – DAC this summer, featuring the Distinguished Engineer Tom Syprou of Cadence, together with Professor Kurt Keutzer of UC Berkeley, Tim Matsson and Michael Wrinn of Intel.

Nora Chu

Interview with SiRF's Nigel Foley on Low-Power Design

soheilm1 — Mon, 04 May 2009 13:00:00 GMT

Over the last three years, customers have been able to leverage the Cadence Low-Power Solution to tapeout their most complex designs. SiRF is no exception. However, in the case of SiRF, another secret weapon was used that made things even easier and cut design time significantly – SiRF leveraged the expertise of the Cadence VCAD Services team. “I believe we could not have met our aggressive schedule or power targets without the VCAD Services team help in ensuring our fast ramp up on low power tools and methodology,” said Nigel Foley, Director of Development Technology. We were able to chat briefly with Nigel about their project and their experiences using Cadence methodology and VCAD Services. Here is what Nigel had to say.

Soheil: What is your job function at SiRF?

Nigel Foley, Director of Development Technology: My role is to enable a state-of-the-art EDA design flow which allows our design teams to produce world leading products in a short time.

Soheil: Tell us about SiRF and its product line

Nigel: SiRF develops and markets multifunction location platforms based on semiconductor and software products that are designed to enable location-awareness utilizing GPS and other location technologies, enhanced by wireless connectivity and multimedia capabilities, for high-volume mobile consumer devices and commercial applications. SiRF's technology has been integrated into a wide range of mobile consumer devices such as automobile navigation and telematics systems, portable navigation devices (PNDs), mobile phones, mobile computers, mobile internet devices, handheld and wearable GPS recreational devices, digital cameras and camcorders, mobile gaming devices, child and pet trackers, and GPS-based peripherals, as well as into commercial applications such as logistics management systems, enterprise and carrier LBS servers, asset tracking devices, and fleet management systems.

Soheil: What challenges did you face in your design?

Nigel: Our designs are composed of a sizable mix of memory, digital and analog circuits and being a mobile product, performance and power is critical for us. I would say that maximizing our performance while minimizing our power use is the most critical challenge we face during design. Striking the right balance which gives all the performance and flexibility required to our customers while dramatically reducing the power footprint is key.

Soheil: How did Cadence technologies help you overcome such challenges?

Nigel: The Cadence Low-Power Solution has enabled us to properly control and balance our low power/performance needs. Having a single CPF reference file throughout the process has lowered the barrier of entry to true low power design throughout the design process. The tools take an optional CPF file and everything is handled internally in the tool. This is key in particular for equivalence checking to ensure that functionality of your design is still sound even after low power constructs are implanted, and also for DFT implementations. Having CPF integrated into each step simplified low power design for us and we did not have any major issues with achieving equivalence correctness after each step.

Soheil: How did you leverage Cadence Services in achieving your goals?

Nigel: The Cadence VCAD Services team was critical to our ramp up on CPF low power design. Although all of the design work was done in house in SiRF, the Cadence services team were with us at every step, helping us learn how to properly harness and use the power of the Cadence Low-Power Solution. They were an excellent expert reference, advisor and problem solver resource and helped us overcome any issues we encountered quickly.

Soheil: Please describe the engagement process with Cadence Services?

Nigel: We started with a static project, one which was already complete but suitable as a test case. We asked the services team to go through that IC and convert it to a CPF low power flow. This gave us the basic building blocks and scripts, introduced us to CPF and pipe-cleaned the flow on a real project. When we started on a new project intending to use CPF, the services team was in lock step with us, with regular meetings to review progress and work from both sides. Often we would be addressing a particular design step and the services team would be working on the following step or another step in parallel. At all times we could see what was being done thanks to the collaboration chamber setup. All learning was effectively transferred into SiRF enabling us to be self sufficient going forward.

Soheil: What is your overall impression of Cadence products and services?

Nigel: The integration of CPF into all digital tool steps has been a positive experience for us. That coupled with the expert ramp up via the services team has made us much more confident using a true low power strategy going forward. But the biggest indicator of our success is the end result, our IC was first time functional with all low power modes working as expected. I believe we could not have met our aggressive schedule or power targets without the VCAD Services team help in ensuring our fast ramp up on low power tools and methodology.

Soheil: What suggestions do you have for Cadence R&D and technologists to enhance its current products and services?

Nigel: Continue to simplify and integrate low power into all tools, it's becoming a necessity for so many designs going forward. Ensure that the low power workshop is kept up to date and highlights the latest enhancements in the tools. And finally continue to work closely with all the foundries to make sure that the necessary support infrastructure is in place to enable the tool flow.

Soheil Modirzadeh

VoltageStorm Is Alive and Kicking!

PeteMc — Mon, 27 Apr 2009 12:03:00 GMT

If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is “a lot”.

If you have read my bio, I came to Cadence from Simplex and so power integrity analysis is close to my heart, and at the time of the acquisition, VoltageStorm PE was the recognized standard for static power integrity analysis, and Apache had taken the lead in the dynamic power rail analysis space (and I definitely wasn’t a happy camper because of this).

The whole VoltageStorm team determined that there needed to be a very focused effort to develop a dynamic VoltageStorm solution, which resulted in the launch of the VoltageStorm Dynamic Gate Option (VoltageStorm DG) in mid-2005. The new dynamic functionality enabled VoltageStorm to regain market share in the dynamic analysis segment, and with a very solid reputation and a large installed base, VoltageStorm became, and continues to remain, the #1 selling analysis product in the Cadence portfolio.

But we didn’t stop there. As an ex-design engineer, I fully understood the value of power and power rail analysis within the design implementation flow, where analysis results could help create more robust designs prior to signoff analysis, and so we integrated some of the VoltageStorm functionality into the Encounter platform. Today, instead of being used solely for signoff analysis, it is great to see that functionality from VoltageStorm is a critical component within our digital implementation solution.

Encounter Power System … The Next Generation of Power Integrity Analysis
I’m not sure if you caught the announcement, but we recently launched the new Encounter Power System (EPS) at the end of 2008. EPS continues to build on the VoltageStorm engines, but is tightly integrated with the Encounter Timing System (ETS) … the EPS/ETS combination enables an easy-to-use, comprehensive timing-SI-power signoff analysis solution required for advanced designs.

So, plagiarizing the immortal words of Mark Twain, I am very pleased to report that any rumors of VoltageStorm’s death have been greatly exaggerated. On the contrary, VoltageStorm’s functionality is stronger than ever and lives on within the new Encounter Power System products.

By the way, if you haven’t yet learned about ETS and EPS, I encourage you to follow this link to get more information … set your mouse on the “Signoff analysis” tab on the left.

I am very proud of the fact that not only has VoltageStorm survived against tough competition, but the VoltageStorm functionality lives on as an integral part of the Encounter Digital Implementation System and as a next generation signoff analysis product.

I plan to start off some more threads on power and power integrity analysis, so if you have comments or questions around power integrity analysis, watch this space. If there is something specific you would like to know, let me know and I will get you the answers.

Pete McCrorie

WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication's Latest Innovation on WiMAX Devices

Design4Life — Mon, 27 Apr 2009 12:00:00 GMT

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was unthought of just 10 years ago: people working on laptops, accessing wireless internet at broadband speeds. I don't know about you, but to me, that is simply amazing. Imagine, 10 years ago we would have been content with surfing the internet at 56k dialup speeds. Now, we've come to expect consistently fast broadband speeds. If a website takes more than 5 seconds to load, immediately we think something's wrong with the connection.

So are we in wireless utopia? Apparently the answer is not yet. The ideal situation would be where you could access high-quality broadband anytime, anywhere. This requires a wireless data protocol that has greater range. The WiMAX standard is a step in that direction. With a 50km/30miles max range, it promises to take broadband wireless data a step beyond what's capable today. Of course, the closer you are to the 30 mile max range, the worse your reception and speed is going to be. But the potential is there. That is why manufacturers are recognizing WiMAX to be a step in the right direction.

Sequans is one of the innovators in the WiMAX field. Recently they introduced their SQN1210 WiMAX chip at the Mobile World Congress in Barcelona in March. Some specifications: Baseband and triple RF on a single die; 350W @ 600MHz with fully loaded MIMO traffic, and less than 0.5W in sleep mode. It also has it's own built-in SDRAM, eliminating the need for external memory banks. These specifications are actually pretty impressive, as they offer not only savings in system/die area ($$), but also the high performance needed for mobile applications going forward, and of course the ability to stick withint he system's power budget to operate for a long period of time on batteries.

The question is: what technological feats did Sequans have to pull off, in order to achieve the above? One of the things Sequans designers did for this design, was to employ power shutoff (PSO) in their design. Another was to utilize multiple supply voltages (or MSV for short). The combination of these two advanced low power techniques meant that Sequans had to work with the multiple power domains throughout their entire design flow. The Cadence Low Power Solution was used for this task, including Encounter Digital Implementation System for the physical implementation for the design. You can read more about Sequans' tapeout at this link: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=022509_sequans

Regarding the actual design flow of low power chips: the ability to simulate power switches in your design from the start, even without having them in your RTL, is very handy. RTL today usually doesn't have power switches, in order to retain the re-usability of the RTL, but we still need a way to simulate RTL with the knowledge that eventually, power switches will enter the netlist. During the physical implementation stage, more automation is always better. Physical designers already have too many items to worry about (dont' we all). Having the tool handle all the intricacies of power domains automatically so that designers can focus on design issues has always been appealing. In addition, before the chip tapes out, there has to be a systematic way of checking out and signing off everything related to the low power techniques in use: power switches placed in the correct locations, sleep signals corrected correctly, power nets connected correctly... the list goes on. As you can see, the tasks Sequans designers overcame, were pretty significant.

So, if everything goes well for Sequans and the WiMAX industry in general, maybe our days of putting "I am on vacation and will be out of e-mail contact" in our out-of-office messages are numbered... but on the bright side, we would also be able to run remote sessions of Encounter while sitting at the beach... how about that!

Wei Lii Tan
Cadence Design Systems

Noise Induced Double Clocking Explained

mikeNaustin — Tue, 14 Apr 2009 12:30:00 GMT

In my previous blog on noise analysis accuracy, I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise analysis expert Trisha Kristof, who’s been working on our SI analysis since the CadMOS CeltIC days, to guest blog on this topic.

A note from Trisha Kristof on “Double Clocking”:

Double clocking happens when signals adjacent to the clock net switch in the opposite direction as the clock’s transition. If this causes a bump during the clocks transition, then double clocking can occur. Encounter Timing System actually looks at the worst opposite slope on clock nets when checking for double clocking. If this causes a clocking event on the receiving flop, we flag this as a double-clocking violation.

This is something we implemented back in in 2002 a customer who came to us to see if we could detect this situation which we subsequently implemented for them. Since creating this double clocking check, several customers using other solutions have come to us with silicon failures that were not detected. Running Encounter Timing System, they were able to find the failure right away.

Double clocking is just one of the advanced techniques we have evolved over the years since CeltIC was first announced in 2000 to ensure that your designs will not fail in silicon due to noise problems. We also employ advanced pessimism reduction algorithms to make sure that you don’t get overwhelmed with false noise violations during signoff.

Trisha Kristof
Staff Product Engineer
Cadence Design Systems

Constraint Construction: What's Its Function? Part 4 of 4

Thom Moore — Thu, 09 Apr 2009 16:25:00 GMT

This is the last in the series of Constraint Construction blogs! Today we're going to go over DESIGN RULES and MODES OF OPERATION.

DESIGN RULES: Follow them, or else...

Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce noise issues. Or maybe you want to give yourself some margin of safety with minimum capacitance. Let's go over the main design rules to live by.

Max Fanout
- How many cells should each instance drive?
- Does the timing library set this at all or is it necessary for any specific library cells or instances in the design?

Min/Max Transition
- What is the maximum slew that each pin in the system should have? Should you have max transitions on any input or output ports?

"So I cranked the max transition down to 100ps, and all my noise problems went away. Of course the design doesn't meet timing and is packed with buffers. But focusing on the good,... I got rid of the noise!"

Min/Max Capacitance
- Should there be a limit to the load on each driving pin?
- Perhaps even on an input port or internal net?

Design Environment
- What timing library should we use?
- Which timing corners (PVT)?
- Will you be setting the operating conditions in the constraints?

"So you're saying there is a Best Case environment? Why would I care about that if it's so good?"

MODES OF OPERATION: There's more than one way to peel an apple.

Functional Mode(s)

Is there more than one functional mode?
- Will one set of constraints handle all the modes?
- If multiple modes will be used, are all the files correctly defining each mode correctly with the use of constants?

Test Mode(s)
- Are there test modes that differ significantly from the functional operation (JTAG Boundary Scan, BIST/MBIST, Shift, and Capture)?
- Have these been defined correctly as well?

Well, I hope this has been informative for everyone! The goal here is, whenever you get some constraints from someone, and you are not sure how well they are 'constructed', reference back to this and ask these simple questions and you just might catch problems early enough!

To read up some more on this topic, check out this section in the Encounter docs (please note, to access the doc requires and account and password): Setting Constraints and Performing Timing Analysis in Encounter RTL Compiler

Thomas Moore

Encounter Digital Implementation System 8.1 San Jose Live Blog

BobD — Tue, 07 Apr 2009 15:45:00 GMT

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar that focuses on the 8.1 release of the Encounter Digital Implementation System, and we'll be focusing on the following areas:

Design Closure
Mixed Signal
Low Power
Advanced Node
Analysis & Signoff

A live blogging application should appear below:

&amp;amp;amp;amp;amp;amp;lt;a href=&amp;amp;amp;amp;amp;amp;quot;http://www.coveritlive.com/mobile.php?option=com_mobile&amp;amp;amp;amp;amp;amp;amp;task=viewaltcast&amp;amp;amp;amp;amp;amp;amp;altcast_code=a25c902fe9&amp;amp;amp;amp;amp;amp;quot; mce_href=&amp;amp;amp;amp;amp;amp;quot;http://www.coveritlive.com/mobile.php?option=com_mobile&amp;amp;amp;amp;amp;amp;amp;task=viewaltcast&amp;amp;amp;amp;amp;amp;amp;altcast_code=a25c902fe9&amp;amp;amp;amp;amp;amp;quot; &amp;amp;amp;amp;amp;amp;gt;Cadence Encounter Digital Implementation System 8.1 Seminar&amp;amp;amp;amp;amp;amp;lt;/a&amp;amp;amp;amp;amp;amp;gt;

Bob Dwyer

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"

mikeNaustin — Fri, 27 Mar 2009 16:52:00 GMT

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen & Krishna, having "perfect correlation" for timing from RTL to Signoff can dramatically improve design closure and cycle time which is always a good thing.

I enjoyed this article because it not only talks about the benefits of making sure you have correlation but goes into great detail on exactly how to ensure it. Check it out on EDN's web page here:

Establishing Timing Correlation Between Tools

One of the keys to is also starting with the right tools. If your flow can leverage common timing and SI engines it makes your job much easier. Learn more about the common timing and SI anaylsis infrastructure in Cadence's Encounter Timing System and Encounter Digital Implementation System.

Mike Jacobs

Get on Board With Bus Guides

Kari — Thu, 26 Mar 2009 13:59:00 GMT

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you out there have probably looked at the results of a routing job and thought, "Why didn't it route this bus all together? It's all over the place!" Well, with bus guides, you can get your busses routed exactly the way you want. Here's how to do it:

First, you need to create a net group.

   createNetGroup myNetGroup -net {DTMF_INST/rom_data*}

Encounter will report back something like:

   Added [16] net(s) in the net-group [myNetGroup]

Next, you create the bus guide for that net group. You can use the createBusGuide command, but the GUI is much more fun here.

Click the Bus Guide icon:



Then hit F3 to bring up the Bus Guide form:



In the form, you can select the net group you created earlier and pick the horizontal and vertical layers for the guide. Click the "Calculate Width" button for both vertical and horizontal, and then you can close the form.

Now we get to draw the guide! It's very similar to a hand-route. Click where you want the guide to start, click to change direction, and double-click to end the guide. If I was to make a guide between two modules (which will become partitions), it would look something like this:



Now, when you go on to create your partitions and assign partition pins, the pins associated with the bus guide you just created will be placed where you put the guide and in the layers that you specified on the Bus Guide form. And the best part is that when you route, the routes will follow the guide you just made. No more messy bus wires all over the place!

Here's another cool thing you can do: let's say you have a whole bunch of bus guides. It could be hard to tell from a glance which one is which. It can be very helpful to make each bus guide a different color. This is done with the command:

   setBusGuideMultiColors

Here's an example, but with only two bus guides:



(If you want to get rid of the colors, no problem. Just use the command resetBusGuideMultiColors.)

Finally, here's a little bonus: if you are the logic designer, then you are probably very familiar with which nets or busses go between each module. But if someone else designed the netlist and you are doing the physical work, then it may not be obvious. So, how can you quickly find what the nets between two modules are? Here is one way:

set mod1nets [dbget -u -p2 top.nets.allTerms.name top/mod1/* ]
set commonNets [dbget -u -p2 $mod1nets.allTerms.name top/mod2/* ]
dbGet $commonNets.name

Have you used bus guides yet? Do you think you will use them on your next design? Let me know in the comments.