Cadence Functional Verification Blogs

AOP Discussion on LinkedIn

teamspecman — Fri, 10 Jul 2009 13:00:00 GMT

Hello All,

Last week over in the LinkedIn Design Verification Professionals group, a thread came up in the discussion area regarding support for AOP in VERA. The discussion quickly changed to the benefits of AOP for Verification. Unfortunately, for the user who kicked off the thread, most of the other respondents seemed to only have experience with VERA's limited AOP capabilities and not with the more complete implementation of AOP in e. In case this question comes up at your company (and in case you not already a LinkedIn subscriber), allow me to repeat my reply on the value of AOP in e/Specman below.

Also I forgot to mention this in the original LinkedIn post but added it later. I personally think a great reference on this topic of AOP and e, is the book: Aspect Oriented Programming with the e Verification Language by David Robinson

Enjoy! Brett Lammers

************************ Post to LinkedIn discussion *************************

Hello All,

I just could not resist putting my 2 cents in on this discussion. Not being a Vera user myself, I cannot comment on AOP support in Vera, but I am getting the feeling from the other posts that there may be some limitations especially if it can only be used to layer testcases on top of an existing tesbench.

I would agree with Dean and Igor that a very powerful usage of AOP is to manage testcases layered over an existing testbench. However, at least when using e, I would argue that AOP plays an important role in testbench design also.

As a reminder, (you all probably already know this): AOP (at least as implemented in e) goes beyond OOP in providing the user more flexibility to organize their code modules not only by objects, but also by cross-cutting-concerns (functionality that touches multiple objects in the code set). In verification, these cross cutting concerns can include DUT related functionality such as operation modes as well as verification related functionality like coverage collection or checking. Of course, as Dean and Igor already mentioned, the test itself is a cross-cutting-concern as it configures and constrains many objects within the testbench. However, using AOP in designing the testbench is extremely useful encapsulating object functionality, safely maintaining existing code, and reusing existing code.

In the context of encapsulating object functionality, just like in OOP, it is good practice to go through some planning to organize both objects and their associated concerns into the appropriate modules. This will prevent code that is difficult to read and maintain. In fact, it may even make it easier to read and maintain since there will be additional modularity and encapsulation. If we think about it modularity and encapsulation are really the motivation behind OOP in the first place. AOP just gives you yet another dimension in which to manage your code.

As Igor mentioned, since AOP gives you more freedom to split object functionality across multiple modules it is possible for you to create some incredibly messy code. However, back in the day (over 7 years ago), the Specman team understood this risk, and in partnership with lighthouse customers created what was called the e Reuse Methodology ("eRM"). Today the same eRM concepts for building reusable testbenches in a methodical and organized manner can be found under the OVM umbrella as OVM e. The success of eRM (it's been adopted by 98% of e/Specman customers), and the ongoing growth of Specman usage itself, shows that "structured AOP" is effective for block, chip, and system level verification challenges.

Brief digression: For additional information on OVM and how it applies to Specman/e check out this article and the related discussions:

www.cadence.com/Community/blogs/fv/archive/2008/07/12/why-is-ovm-important-for-specman-e-customers.aspx

What about code maintenance and reusing existing code? Here again, AOP is almost indispensable. By using AOP extensions, users can methodically update an existing environment with concerns that were missed in the initial planning, or are the result of changes that occur later on in the project. This sort of "after-the-fact" manipulation can be difficult in a standard OOP environment and/or if you only hold yourself to strict OOP practices. In the context of reusing existing Verification IP, AOP allows you to configure, control and add functionality to the existing VIP without touching the base code set - hence the reference to "safety" above since you don't have to muck with proven code. This can become critical when sharing IP across multiple projects or groups.

I would also invite you all to check out additional discussions on this subject as well as other related topics here: www.cadence.com/community/posts/teamspecman.aspx

Cheers, Brett

********************************** End Post **************************************

Another New Blog on e/Specman

teamspecman — Fri, 03 Jul 2009 13:00:00 GMT

Specmaniacs rejoice: there is a new blog centered around verification with e/Specman by Sandeep Gor:

http://digitalverification.blogspot.com/

Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are some other e/Specman-oriented sites we know of, and by all means please send us links to any sites that are missing from this list so we can promote them:

* The venerable Specman Yahoo group
http://tech.groups.yahoo.com/group/specman/

* The IEEE 1647 Working Group
http://ieee1647.org

* The Cadence Functional Verification forums
http://www.cadence.com/community/forums/30.aspx

* Avidan Efody's "Specman Verification" site
http://www.specman-verification.com/index.php

* Yaron Ilani's "Think Verification" blog
http://www.thinkverification.com

* e verification by Shivayogi
http://e-verification.blogspot.com/

* OVM World Forums (for OVM e discussions)
http://ovmworld.org/forums/

* JL Gray's "Cool Verification" blog
http://www.coolverification.com

Happy coding!

Team Specman

Inside Cadence: Food for Charity & Freedom

jvh3 — Thu, 02 Jul 2009 21:48:00 GMT

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle from the regular "Stars & Strikes" charity event series, where this time the focus was on food with a hot dog eating contest to benefit for Second Harvest Food Bank’s "Share Your Lunch Drive".

For more images from the event, click here for an annotated gallery

This event might seem like it's coming out of the blue, but hot dog eating contests are actually a 4th of July holiday tradition. The first such contest was held on July 4, 1916 in Coney Island, New York by Nathan's Famous hotdogs; and this particular contest continues to this day.

Our Cadence contestants didn't threaten the world record of 66 hot dogs eaten in one sitting (OMG!) set in 2007 by Joey "Jaws" Chestnut, since the goal of the contest was speed -- how many hotdogs you can eat in 5 min -- versus quantity. Despite some chicanery by a tricky Viking, our winner managed to down 9 hot dogs and remain vertical. Even better, $525 was raised for a good cause. Many thank yous are due to the ticket buyers, the hearty contestants, as well as the donation of time & materials from our catering provider Guckenheimer.

The winner!

Indeed there is a *delicious* irony here: a benefit to fight hunger that's based on competitive gluttony. (Sorry, some puns are impossible to resist.) I also can't resist tying this event to 4th of July itself: whenever "hunger" appears as an issue, I always recall the famous Norman Rockwell "Freedom From Want" illustration of a traditional Thanksgiving dinner that was inspired by President Franklin D. Roosevelt's "Four Freedoms" speech.

In real sense, this charity event was small step toward providing this particular freedom in advance of a day that's primarily about celebrating freedom in all its forms.

Happy 4th of July!

Joe Hupcey III

Reference links:
Second Harvest Food Bank
http://www.2ndharvest.net/

Second Harvest is conducting a three month campaign called Share Your Lunch. The goal for this campaign is to raise the resources to feed 66,000 children each month this summer. For less than the price of a lunch out, you can feed 20 children. Find out more at ShareYourLunch.net.

Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator

hilker — Wed, 01 Jul 2009 01:45:00 GMT

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer. So much of my time was spent on design and verification, there was little time to explore all the capabilities of the software.

With that in mind, I'd like to share a demo of a new signal comparison utility, SimCompare. You can do interactive comparisons within SimVision, as well as scripted and batch comparisons using Tcl.

The embedded video is best viewed full screen, which you can do by clicking the lower right-hand icon with the arrows.

If you have problems with the embedded player click here.

Be on the lookout for future videos and tips on using the Incisive Enterprise Simulator!

Bob Hilker

Create a Sine Wave Generator Using SystemVerilog

tpylant — Tue, 30 Jun 2009 13:00:00 GMT

Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI.

Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions to your simulation. Here is an example of a package I created to contain the math functions:

package math_pkg;

//import dpi task C Name = SV function name

import "DPI" pure function real cos (input real rTheta);

import "DPI" pure function real sin (input real rTheta);

import "DPI" pure function real log (input real rVal);

import "DPI" pure function real log10 (input real rVal);

endpackage : math_pkg

The import"DPI" construct defines a new function that you can use in your code that refers to a C function. In the case of the math functions listed above, they already exist in the libmath.so library built into Linux and so there is no additional code required. Now that I have my math functions, I can create my module.

module sine_wave(output real sine_out);

import math_pkg::*;

parameter sampling_time = 5;

const real pi = 3.1416;

real time_us, time_s ;

bit sampling_clock;

real freq = 20;

real offset = 2.5;

real ampl = 2.5;

always sampling_clock = #(sampling_time) ~sampling_clock;

always @(sampling_clock) begin

time_us = $time/1000;

time_s = time_us/1000000;

end

assign sine_out = offset + (ampl * sin(2*pi*freq*time_s));

endmodule

Here I have used import in a different context. In this case import is used to make the code in my package available to the scope in which I import it. Now when I call the sinn function, it will use the DPI code from math_pkg to execute the function.

The sine_wave module also shows the use of passing a real value through a port. The output sine_out is of type real and is computed using the sin function.

SystemVerilog allows a real variable to be used as a port. The limitation is that a real variable can only be driven by a single driver. If that is a problem, you can make the module a Verilog AMS module and define the real variable as a wreal (real wire). By using wreal, you can have multiple drivers and use a variety of resolution types to solve any conflicts.

Tim Pylant

Yikes - Synopsys is Following Me!

jvh3 — Mon, 29 Jun 2009 13:01:00 GMT

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following me:

Before discoursing on this unusually public display of affection, allow me to take a step back and announce that I've started to tweet on Twitter. While initially put off by the apparent solipsism embedded in Twitter's "What are you doing now" conversation starter, I've come to appreciate two benefits of Twitter: it's effectively a huge public focus group where I can glean specific feedback and general trends regarding my products and corresponding methodologies, and it's a font of unfiltered world news from primary sources.

That said, like Friendster or CB Radio, Twitter might eventually fall by the wayside and/or devolve to serve some niche purpose. Regardless, as with blogging in general, I've discovered that sending tweets stimulates the same part of the brain that produces guilty, narcissistic pleasure produced by self-expression to an audience. Rephrasing, what Marketer doesn't love public speaking -- with Twitter you get to satisfy this urge 24/7! Whooo-hoo!

Now back to Synopsys, and their "following":
The first question that sprang to mind when I saw the "Synopsys is following you" notice is whether this whole entity in its entirety is following me (for all I know they have some sort of automatic logger/wiki of competitive info)? Or is there some wizard behind the curtain hanging on my every tweet? Could it even be that Synopsys' CEO Aart DeGeus himself is discretely glancing down at his Blackberry every time I fire off a tweet?!? (Don't laugh -- it's possible -- really -- ok, maybe more like "improbable but possible".)

More likely suspects are people who I used to work with who are working there now. Larry: if you are the actual Synopsys follower, I believe you still owe me $10 for lunch for that time you forgot your wallet. However, all is forgiven since I got to keep the Palladium logo clock that you left in your cube.

Taking a more competitive view:
Of course following me/Cadence activity on Twitter is a logical extension of Synopsys' devoted following of the innovations that myself and my many colleagues have introduced in verification technology and methodology over the years. It started back at the turn of the century, when Synopsys attempted to push VERA as a credible alternative to the then new paradigm of coverage driven verification pioneered by e/Specman. In the present day, they are now including e language support natively in VCS, as well as supporting OVM in VCS (where OVM itself has many roots in the e Reuse Methodology).

I could go on, but the point is that Synopsys has been in the rear view mirror for years, and thus my fleeting surprise at this "following" has been quickly replaced by my regular, Andy Grove-style "Only the Paranoid Survive" alert level reserved for any competitor. So "Synopsys", whoever you are, I welcome your continued following -- both of me personally, and the products & methodologies I drive here at Cadence. Borrowing a line from Charles Osgood, "See you on the radio!"

Joe Hupcey III

Using Constraints to Pass Configuration Options in the Unit Hierarchy (Top-Down approach)

teamspecman — Fri, 26 Jun 2009 13:01:00 GMT

To allow for increased solvability, some constraints that were previously uni-directional with the old “Pgen” generator are now treated by IntelliGen in a bi-directional manner by default. This behavior dramatically improves solvability and gives you a lot more freedom in writing and layering very complex constraints.

However, if you are coding with a Pgen frame of mind there is one case where the results might not be what you expected. Specifically, the behavior of IntelliGen can differ from Pgen for the case where you want to constrain a child struct’s fields from within the parent (for example, when you want to pass configuration options down the unit hierarchy). Fortunately, the code needed to address this situation is very simple to apply. Consider the following general example:

type size_t: [SMALL, MEDIUM, LARGE];

struct config_s {

sz: size_t;

valid: bool;

}; // struct config_s...

unit agent_u {

cfg: config_s;

bfm: bfm_u is instance;

keep bfm.cfg == cfg; // constraint [1]

}; // unit agent_u

unit bfm_u {

cfg: config_s;

keep soft cfg == NULL; // constraint [2]

}; // unit bfm_u

unit env_u {

agent: agent_u is instance;

}; // unit env_u

Specman users familiar with Pgen will know that Pgen will treat constraint [1] as unidirectional (from agent_u.cfg to agent_u.bfm.cfg), allowing agent_u.cfg to be randomly generated, and then pushing that struct down to agent_u.bfm.cfg. Additionally, constraint [2] will not be enforced given that it is a soft constraint (and of course with Pgen the user would have to make constraint [2] a hard constraint in order for it to be enforced.) If we run the above code we would find that agent_u.cfg and agent_u.bfm.cfg both point to the same config_s instance. Here is the potential gotcha: since constraint [1] is unidirectional, (soft) constraint [2] will be ignored, which might not be the intended behavior – in this example it’s not clear if the user truly desired the cfg struct of the bfm_u to be NULL

Now consider the behavior of this code with IntelliGen: IntelliGen will treat constraint [1] as bi-directional by default. As a result, constraint [2] will be applied in addition to constraint [1], Users will find that both agent_u.cfg and agent_u.bfm.cfg both point to the same instance of cfg_s which, in this case would be a NULL struct. IntelliGen will apply all constraints in the above example, which is generally more intuitive and showcases the additional solving capabilities of IntelliGen.

But what if the intention was to pass the value of parent fields down into child structs in a purely top-to-bottom, unidirectional way? The correct way to implement this in IntelliGen would be to wrap the right hand side of the constraint in a read_only() to enforce top-down unidirectionality (because wrapping constraint variables in read_only() causes them to be generated first), as shown in the following example:

type size_t: [SMALL, MEDIUM, LARGE];

struct config_s {

sz: size_t;

valid: bool;

}; // struct config_s...

unit agent_u {

cfg: config_s;

bfm: bfm_u is instance;

keep bfm.cfg == read_only(cfg); // constraint [1]

}; // unit agent_u

unit bfm_u {

cfg: config_s;

keep soft cfg == NULL; // constraint [2]

}; // unit bfm_u

unit env_u {

agent: agent_u is instance;

}; // unit env_u

In the above example, constraint [2] would not be enforced as sys.agent.bfm.cfg would point to the same cfg struct as its parent due to constraint [1]. Without the read_only(), constraint [1] would be bidirectional and IntelliGen would also consider constraint [2], hence the NULL cfg struct in bfm_u would be propagated upwards through the hierarchy resulting in sys.agent.cfg == NULL.

Bottom line:
IntelliGen has improved solvability over the previous generation engine (Pgen) given more constraints are now treated as bi-directional by default. Thus if you would like to push parent fields down into lower level child structs, you will need to wrap the parent field value in a read_only() call.

Corey Goss

Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Adam Sherilog — Wed, 24 Jun 2009 13:45:00 GMT

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009). In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 -- are growing fast. That is exactly the type of design we've targeted with the Incisive Enterprise Verification solution and the OVM.

Cadence and Xilinx are working to simplify the development of these complex SoCs by applying the Incisive solution to the newly announced Xilinx Targeted Design Platforms. There are two significant parts of the announcement -- collaboration around new, high-performance, standards-based simulation libraries and application of the OVM for SoC FPGAs.

The first point represents significant engineering work to move away from the proprietary packaging that Xilinx used to the new IEEE standard encryption championed by Cadence. The new encryption standard was originally donated by Cadence and is now part of the SystemVerilog (1800), Verilog (1364), and VHDL (1076) standards. Cadence chairs this standards effort and was able to help Xilinx adopt the technology and prove it in common customers. The result is an average 2X speed-up for simulation, with some users experiencing still higher performance. Watch this blog for a team genIES explanation of this compelling new standard.

The second, and possibly more significant, point is the recognition that the OVM is an ideal choice for SoC FPGAs. These FPGAs typically depend on standard protocols -- on-chip bus and interface protocols -- and reuse of both vendor-supplied and user-created VIP. Furthermore, these FPGAs are scaling to the point where users need to break with the traditional "burn-and-churn" FPGA methodology and adopt the more comprehensive, metric-driven methodology applied to ASICs of the same size and complexity.

For all of you who have been looking for more FPGA verification content from Cadence, look at this announcement as just the first with more to come. If you have any requests in the FPGA space, please feel free to comment here or contact me at asherer@cadence.com.

=Adam Sheriblog

Send Us Suggestions for Updating the e/Specman Quick Reference Card

teamspecman — Fri, 19 Jun 2009 17:31:00 GMT

Team Specman is about to start a project to refresh the e/Specman Quick Reference card included with every Specman/IES release. (While the basics of the current card are OK, we concede some of its content is getting a little long in the tooth). Hence, please let us know your preferences about what we should edit, add, or subtract from the next version of the card in the comments below, or contact us directly offline.

For those of you who didn't know there was such a thing, you can access the card in two ways:

* Open up [Cadence Help] -> [Specman] -> [Specman e Language Reference Manual]

* Or grab a ready-to-print PDF: $SPECMAN_HOME/../../doc/sn_eref/sn_eref.pdf

Happy coding!

Team Specman

VCS Runs OVM -- 2 Years Late, But Welcome None the Less

Adam Sherilog — Thu, 18 Jun 2009 16:00:00 GMT

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is buzzing this week about the OVM running on VCS. We first saw a post on the LinkedIn "OVM Professionals Network"on Monday June 15. Today we saw a more detailed posting at IntelligentDV specifically stating a released version of VCS that will run the OVM.

For nearly two years we have talked to many VCS users who wanted to access the reuse and scalability only found in the OVM. While these user reports do look legitimate, VCS users will have to run their own tests to confirm. It would be great to see an official statement of support from Synopsys, but this blogger can only wonder if that will come before or after a similar statement about e support in VCS. Or for that matter, PSL support in VCS.

Cadence and Mentor have worked hard, with the help of the nearly 8000 users on the OVMWorld, to assure that one library can run unmodified on both simulators. We welcome input on any issues VCS users see with the OVM code and recommend posting them to http://www.ovmworld.org/forums/ .

It looks like the OVM has unified the simulator world!

=Adam Sherilog

New Video on "Metric Driven Verification 101", With Yours Truly Giving the Intro

jvh3 — Thu, 18 Jun 2009 13:15:00 GMT

Recently I had the honor of delivering the introductory section of a detailed demo on "Metric Driven Verification 101" given by my colleague Nick Heaton, an Architect in our Verification Solutions organization.

Specifically, after a few introductory slides by yours truly set the stage, in the video Nick shows in detail the methodology behind metric driven verification ("MDV"), and how it improves upon the classic coverage driven verification ("CDV") approach. All of this will be familiar to the alumni of our recent "Deep Dive" Workshops on this topic, but for the uninitiated, here is the Cliff Notes summary:

The familiar CDV approach is about using automated testbench and formal means to explore the verification space of the DUT using code and functional coverage as metrics. MDV is the next logical extension for planning, managing, and tracking massive parallel execution of these CDV environments to dramatically scale verification throughput for today's complex projects. To start with, not only do you use code & functional coverage as metrics, but you also track the behavior of checkers, assertions, and testcase status -- even arbitrary metrics like firmware coverage, man hours, compute cycles. In short, whatever you the end user, project manager, or executive management see fit to track and report over the life of the project, it's tracked and reported by the MDV process we describe in the demo.

Note for the marketers out there:
I have to complement the Demos on Demand people for their easy-to-use, professional setup. Granted, the Demos' studio, equipment, post-production editing & graphic overlays, etc. could all be replicated if you put your mind to it. However, they have everything dialed in such that the process was very smooth from start to finish. Unless your company needs to do a lot of demos and also has access to the equivalent pre- and post-production facilities, it would be a challenge to match their economy of scale & production quality. Bravo, Demos team!

Finally, on a personal note, of all the videos and presentations I've given over the years, I'll never forget this particular video since it was shot the day before my daughter was born!

Joe Hupcey III

Tip for Linking AMIQ’s DVT to the Specman Docs

teamspecman — Wed, 17 Jun 2009 22:00:00 GMT

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development environment (IDE), AMIQ has seen a spike in interest in the tool (yeah!) Given the particular interest being shown by Specmaniacs, AMIQ has forward us the the following tech tip about how you can point to Specman’s HTML docs, AND how you can search through the docs from inside DVT itself. (Recall that DVT is free to try – go to AMIQ’s site for details.)

If you have stand-alone Specman installed, all you have to do is configure the path to the documentation from the DVT menu [Window] > [Preferences] > [Help] > CDN eLRM:

Besides browsing the Specman documentation in the Eclipse integrated help:

you can directly select code in the editor and press <Ctrl>+<Shift>+<H> to find matching topics in the documentation:

Of course, you can type anything in the search text-box and locate your relevant topics.

BONUS:
You can also use DVT to scan the Specman/IES-XL output and automatically create hyperlinks to source code from errors, warnings, etc. From the main DVT menu, execute [Run] > [Run Configurations], create a new Generic launch configuration, give it a name, then specify the launch command and work directory:

Next, while still in the Run Configurations dialog box, click on the [Filters] tab and turn on the Specman and other relevant filters as shown in the following example:

When finished selecting filters, click the [Run] button in the lower right hand side. As shown below, output is then dumped to the console and patterns matching the filters (customizable BTW) are turned into hyperlinks to source code (both for compilation errors and run-time dut errors, assertions etc.)

Note that once you have configured a run, you can easily access it from the main window’s [Run] drop-down menu.

There’s more:
If you just want to load some code in Specman to detect some semantic errors, there is a quicker way: right click on a file (top/test file typically) and chose [Run As] > [Load in Specman] as shown below:

Happy Coding!

Team Specman and AMIQ

Enabling OVM Transaction Debug in SimVision Without Code Changes

Team genIES — Thu, 11 Jun 2009 13:05:00 GMT

Are you tired of putting print statements in your code to do debug? Do you work with designers who just want to use waveforms to debug testbench and design problems?

There is a cool feature in the OVM library and Incisive Enterprise Simulator that comes to the rescue. It is the built-in OVM transaction recording.

Modern metric driven testbenches generate a lot of dynamic data on the fly during a simulation run. The test and testbench combination is usually simulated with multiple random seeds to produce different sequences of transactions to maximize stimulus variation to the design. When the checker catches an error, there is always the question. Is it the design or the testbench? The answer usually is, let's look at the waveforms to figure out if the testbench is doing the right thing.

Here you need a way to visualize and interact with the transaction stream without modifying your verification environment. We want to get away from doing vector decodes to figure out that this packet is going to port 5 or this transaction is a read request over a serial interface.

Using OVM with the Incisive Enterprise Simulator gives you a built-in way to visualize sequences and transactions generated by OVM sequencer without writing any code!

Consider the following class called xbus_transfer representing a CPU transaction. The steps in the illustration highlight how transaction recording is automated via base class functionality and macros that implement virtual functions.

This xbus_transfer class is used to create sequences of transaction in a verification environment using ovm_sequencer base class. Typical environments have a handful of random sequences that the user defines to capture interesting scenarios using constraints on transactions. The user can use ovm_random_sequence to perform random selection of user defined sequences or specify their own weighting or specific sequence selection for a test. The following example shows how transactions are automatically recorded during the simulation and their visualization by using SimVision waveform window; these transactions are from the bus master and use the ovm_random_sequence.

From the above graphic, let's figure out what happened.

On the left you see the sequence hierarchy. It shows that the top most sequence, also called the default_sequence is set as ovm_random_sequence for this test. Upon expanding this stream (clicking on the plus sign in the left frame next to ovm_random_sequence), you can see what the ovm_random_sequence did during the simulation run.

In debug, it's helpful to correlate the sequence tree that ultimately creates the transaction so you can review the sequence code and adjust constraints if required. For example, to see how the first random write occur, I can put the cursor in SimVision anywhere on the transaction and immediately understand that the WRITE of size 1 to address ‘hE539 was caused by the following sequence chain:

ovm_random_sequence

--> incr_read_write_seq

--> write0

--> write_byte_seq0

--> request WRITE, size=1, addr='hE539

Using the GUI, you can easily correlate the abstract transaction chain with transaction details, all by leveraging automation in the Incisive Enterprise Simulator and the OVM library.

How To Control Transaction Dumping in a Simulation

Transaction recording is controlled by setting "recording_detail" variable at the component level using the standard OVM configuration API. You can control transaction dumping for any ovm_component or the derived class, through SystemVerilog test or IES TCL command. Remember the ovm_sequencer is a child of ovm_component.

Controlling recording_detail from IES TCL Command

The two above examples show different ways to enable the transaction recording:

The first one turns on transaction recording for the specific component hierarchy "ovm_test_top.xbus_demo_tb0.xbus0.masters[0].*"

This includes all subcomponents under masters[0] instance.

The second command uses the wildcard "*" to enable transaction recording for ALL components in the testbench. Wildcarding is very convenient to affect large portions of the design with a single command. However, care should be taken when using it in a large verification environment because it may create a lot of waveform data affecting simulation performance.

To turn transaction recording off using TCL, use OVM_NONE in place of OVM_FULL as value of recording_detail.

This command can also be used during the run to capture transactions in a time-window desirable for bug analysis.

Controlling recording_detail from SystemVerilog Test

You can use standard OVM configuration mechanism from your test's build method to control transaction recording dumping as follows:

Once transaction recording is enabled in a simulation, transactions can be viewed by loading the waves.shm database in SimVision interactively or in post-processing mode by selecting the appropriate component from the testbench hierarchy and sending it to the waveform viewer as shown below.

Some Practical Considerations

Incisive Enterprise Simulator and the OVM library ensure that changing "recording_detail" of a component doesn't affect random values. This way a failing random simulation from a regression run can be rerun with the same random seed value with transaction recording, signal probes and high message verbosity to speed up failure analysis.
TCL api provides a better alternate to control transaction recording vs. the SystemVerilog build() function because:
- TCL doesn't require recompilation, any change to SystemVerilog test does.
- TCL can be used to enable recording in a time window to speed up debug simulations
You need to use the OVM library distributed with Incisive Enterprise Simulator to take advantage of automatic transaction recording and TCL API.
Simply use "-ovm" switch with the irun script to pick up the OVM library with transaction recording hooks into SimVision and OVM TCLcommands.
Transaction recording can be used in more applications such as displaying transactions collected by monitor, showing cause and effect by linking transactions traversing the design, and more.

For more information, see:

xbus example distributed with the OVM library
OVM Class Reference Manual, Component Hierarchy, Transaction Recording under <IUS install>/doc/ovm_ref
OVM User Guide, XBUS OVC example under <KITSOCV install>/doc/ovm_guide
OVM User Guide, OVM TCL Commands under <KITSOCV install>/doc/ovm_guide

NOTE: You can download KITSOCV and IES tools from downloads.cadence.com

If you have any questions, feel free to post a comment or email genIES@cadence.com.

=Team genIES

Team genIES Bloggers Create Simulation Magic

Team genIES — Thu, 11 Jun 2009 13:00:00 GMT

Simulation is a huge topic. Performance, debug, mixed-signal, low-power, assertions, coverage, IEEE languages, lint checking, interfaces, and much more. Many of us started using simulation when it was gates and waveforms while others joined in the era of complex, multi-language, testbench-driven simulation. Regardless, the pace of design and verification is accellerating for all of us. So how can we get those pearls of simulator wisdom that let us work our verification magic?

Team genIES is the answer. We have assembled the greatest set of simulation minds in EDA ready to provide technical tips, insights, suggestions, and recommendations that you can use to work your verification magic. Our first topic -- Enabling OVM Transaction Debug in SimVision without Code Changes -- is now up in this blog. We have a long list of additional topics throughout the simulation space.

So what's on you mind? How can I show a new test matches a golden test at the transaction level? How do I know my simulation is running as fast as it can? Under what conditions should I use DPI, VPI, PLI, VHPI, etc.? Just email us at genIES@cadence.com and we'll provide the tricks that will make you the magician!

=Team genIES

Tips on Using “vhdlsync” With e+Mixed HDL Simulation

teamspecman — Thu, 11 Jun 2009 13:00:00 GMT

[Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch]

As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined. Even worse: there is no standard that specifies the order of execution of always blocks and VHDL processes, which can lead to simulation results in differing from an equivalent pure VHDL or pure Verilog simulation. Specifically, there are two very common problem scenarios, both of which can get trickier when Specman comes into the picture. Consider:

Scenario 1 - VHDL entities that drive Verilog regs and nets
In this scenario, Specman might sample Verilog signal values that are premature

Scenario 2 - Verilog entities drives VHDL signals
In this case, Specman might not sense a change on VHDL signals.

In order to better understand why these scenarios happen, let's look at a "normal" Specman-simulation cycle:

First all signal updates are performed.
Next, VHDL “processes” and Verilog “always” blocks are executed
If executing these “process” and “always” blocks trigger more signal updates, then it loops, until all signal updates and process are executed. (You often hear this referred to as “the active region”.)
Specman then synchronizes (i.e. samples values) just after that, and before the execution of non-blocking assignments (“NBAs”) list.
Once all this is evaluated (the active region+Specman), then Verilog NBAs are executed.
Since the VHDL language signal assignment statement always performs the signal value update in the next delta cycle (there is no blocking/non-blocking or any similar concept in VHDL), then at a given simulation time, for mixed language designs, Specman synchronizes after all VHDL signal updates have been done.

When you tie this sequence of activity to Scenario 1 above, Specman will sample the Verilog signal after it is already changed to the next value (instead of seeing the value before the change).

In reference to Scenario 2 above, Specman might miss the change on the VHDL signal since it is updated after the synchronization sample is taken.

To avoid both of these problems, the switch 'vhdlsync' has been added to irun/ncelab. In short, this switch separates VHDL process and Verilog always block execution lists. Thus, if you want to consider VHDL signal assignments to be treated as NBAs, and want Specman to sample the VHDL values just before they are updated, then 'vhdlsync' should be used. In such a case Specman starts synchronizing after the execution of VHDL process list and before it loops for more signal updates in the same simulation time (VHDL delta cycle increments), i.e. order of execution will be Verilog followed by VHDL and Specman gives consistent results irrespective of if it samples a signal in Verilog or VHDL.

Conversely, if this switch is not used, the order of evaluation is arbitrary, (as mentioned, there is no standard that specifies the order). Nevertheless, there might be many designs that count on that order (or should I say, “disorder”), and using 'vhdlsync' might change the behavior of their simulation. For example, consider the case where there are messages coming from different blocks at the same simulation time which may come in a different order. In this case the switch is not default, and both behaviors (with and without the switch) are supported, and "correct".

There are more details and examples where this switch can be required in Specman's Integrator's Guide, Chapter 13.4.6, "Mixed HDL Synchronization Issues”

Happy coding!

Avi Farjoun
Principal Support Application Engineer
Incisive & Specman Technology