Cadence Functional Verification Blogs

Ten Things I've Learned About Formal

tomacadence — Fri, 06 Nov 2009 14:00:00 GMT

2009 is the tenth year that I've spent at least a portion of my time responsible for formal analysis products. As per my profile, my two most recent employers before Cadence were 0-In (now part of Mentor) and Synopsys. Between these jobs I consulted for eight other EDA companies, four of which offered formal products.

You would think that I've learned a few things during the past decade, and I believe that I have. Here are ten lessons I learned along the way, one for each year:

Formal should be applied early – any formal tool that requires an advanced simulation testbench as a starting point can only be run late in the project when there are few bugs left

Formal is about proofs as well as bugs – proving at least some assertions correct instills additional confidence in the design once bugs are no longer being found

Designers should be directly involved in formal analysis – many of the best assertions arise from designers capturing the assumptions in their heads

Automatic assertions can be interesting – while no tool can divine from RTL the intent in the designer's head, customers see real value in many types of automatic checks

You can't neglect the basics – R&D should not focus on exotic features at the expense of language support, robustness, and core engine performance

Assertion-based VIP should be a product, not a freebie – creating quality VIP is hard work that requires a serious resource commitment, so you should get paid for it

Coverage is a good way to link simulation and formal – customers understand coverage in simulation, so anything that formal can do to contribute metrics is a motivation for use

A good marketing story is not enough – licensing a generic formal engine from an external research lab and tacking it onto a “lint” front end does not yield a true solution

Moving users from “lint” to automatic assertions to full formal is not easy – it's better to demonstrate the value of user-specified assertions and formal right up front

It is possible to create a mainstream formal solution – Incisive Formal Verifier (IFV) is a successful product being used by logic designers as well as verification specialists

I learned the first nine things from my direct experience with customers and clients prior to arriving at Cadence three years ago. IFV was already a well established product at that point, so I realized when I joined that Cadence had also learned these important lessons even if some of its competitors had not.

Of course, IFV has continued to evolve since then, and I'm proud to have been a part of its ever-growing success. Now we've introduced Incisive Enterprise Verifier (IEV), offering novel links between simulation and formal analysis. We also have automatic assertions, high-quality assertion VIP products, coverage links, and the methodology and support for wide deployment.

The other day I sat in a Sales review at which I heard that just one Cadence customer, at just one of its sites, is actively using more than 200 IFV and IEV licenses. I could only dream of this sort of deployment in my past involvement with formal. I guess that we’ve all learned a few things in the past ten years!

Tom A.

The truth is out there...sometimes it's in a blog.

"ClubT" Herzelia Israel Verification Seminar Invitation 17 November

teamspecman — Fri, 06 Nov 2009 14:00:00 GMT

Specmaniacs Based In Israel,

Please join us for a day of in-depth presentations and demonstrations of the latest methodologies and technologies for advanced verification this 17 November at the Dan Accadia Hotel in Herzelia.

Specman users and Cadence R&D experts will deliver presentations and demos, as per the following agenda:

08:30-09:00 Registration

09:00-09:15 Welcome and Introduction

09:15-10:30 MDV flow & solutions
--> includes updates to Enterprise Planner, Enterprise Manager, OVM e & OVM Multi-Language, IES-XL siimulation, VIP and the Compliance Management System

10:30-11:00 How to build your own Compliance Management System

11:00-11:15 << Break >>

11:15-12:00 User Presentation: "Choosing verification language and methodology: a first hand testmonial", Wilocity

Technology deep dives:

12:00-12:45 OVM e and OVM Multi-language

12:45-13:45 << Lunch >>

13:45-14:30 Panel discussion: "The Debug Challenge"

14:30-15:45 IES-XL 9.2 technology updates and Specman 9.2 Core deep dives

15:45-16:00 << Break >>

16:00-17:00 Round table discussions with R&D:
- IntelliGen + Gen Debug
- Closure automation
- Verification IP
- Enterprise Manager & Planner
- IES-XL + SimVision
- OVM e / SystemVerilog / Multi-language　

To register, please contact Etty Alon: etty at cadence dot com

Hope to see you there!

Team Specman

OVM Innovation Means Business

Adam Sherilog — Tue, 03 Nov 2009 20:01:00 GMT

Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished our image as the verification leader and created new business opportunities.

To understand the impact, we need to step back to 2007. SystemVerilog implementations were just coming together and VMM was a mix of SystemVerilog and Vera. e and eRM, on the other hand, were well established with years of success at this point. So why OVM? To unify the ecosystem. OVM was the first open, multi-vendor, scalable methodology architected for multi-language. Looking back, this statement seemed simple enough, but the simplicity is the innovation.

Open. It doesn't get more simple than that, but it was a rallying point in the marketing and development that changed everything. The OVM started as both Apache licensed and multi-vendor and, in fact, remains the only verification methodology embodying both. With a community now 8000+ strong as measured on the OVM World website, the marketing and development simplicity certainly resonated.

Scalable. The OVM introduced to the SystemVerilog community the agent-architecture used by the e community for years. The concept itself is simple -- a consistent way to describe verification components for reuse -- but is backed by a sophisticated implementation. The innovation here is all technical -- place the burden of complexity on the methodology/library developer and provide the consumer with ease of use.

Creative: Building on past success was important, but new solutions were needed to win the hearts and minds of the nascent SystemVerilog community. The development team built an advanced factory mechanism, field automation, test classes and test selection mechanism, and more many of which have found their way into competing libraries due to that bold move to be open. As the next point will show, the team has never looked back. The creative stream is still flowing with callbacks, configuration mechanism, OVM multi-language capabilities, and much more.

Passionate. Did that one surprise you? If you have talked to anyone from the extended OVM team -- and there are hundreds of us -- that is our simple connection. I've been with Cadence for 18+ years and working with the OVM rekindled the start-up in us. We argued. We fought. We united and we delivered. And we are still doing that today. The simplicity of that emotive drive assures that you get the best out of us all the time, every time. Maybe that was latent in the team for a while, but we are certainly bringing it now. And for those on the internal team, you know we were doing that even today. :-)

I know this blog was a "pat on the back" for the OVM team, but we all need to step back from time to time and assess ourselves. We're proud of the innovation we have brought to verification and even more proud to say we ain't done yet!

=Adam Sherilog on behalf of the whole OVM team

Today's Innovation Awards and The "Trailblazer" Marathon

jvh3 — Tue, 03 Nov 2009 19:00:00 GMT

Today myself and the whole Trailblazer team are proud to celebrate the success of my colleagues' winning awards on Cadence's "Innovation Day". In specific reference to the verification segment winners, over the past year I've had a front row seat to their struggles. They will be too modest to admit this, but let me tell you there were times when it was really dark for them.

Boston Marathon: Hearbreak Hill

But despite temptations to settle for less ambitious solutions, guided by their years of industry experience, deep technical expertise, collegial teamwork, as well as the strength derived from their hobbies (like running marathons -- no kidding, see above), they persevered to deliver on their innovative roadmap.

Fast forward to the present:

The Trailblazers are currently in mile 20 of a product development marathon to automate verification in ways no one has dared attempt before. In Boston Marathon terms, it feels like we are ascending Heartbreak Hill; so to say the least it's encouraging to have our award-winning colleagues cheer us forward as we count down the remaining miles!

Joe Hupcey III

P.S. Fellow blogger and Cadence Innovation Day award winner Adam Sherer is a real live marathon runner, who has requalified and committed to running his 8th consecutive Boston Marathon for the benefit of Children's Hospital. Beating the Patriot's Day rush by sponsoring Adam now will no doubt inspire him during his 5AM winter training sessions!

OVM Tricks and Treats

Team genIES — Fri, 30 Oct 2009 20:30:00 GMT

Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets!

Callback Mechanism

From day 1 the OVM has employed a factory mechanism for both simple reuse and multi-language consistancy. While factories are the generally accepted practice for object oriented languages, users migrating to the OVM from other methodologies may be more comfortable with extending procedural and structural elements using callbacks. This donation adds callbacks to the OVM SV (SystemVerilog) library.

Compliance Checklist

With it's roots in eRM, users of the OVM can access to the collective experience of 5000+ tapeouts over nearly a decade using the contributed OVC (OVM Verification Component) Compliance Checklist. Since each donation is open, it is easy for the ecosystem to take them and create value-added products. Amiq has done this by automating the checklist in an OVM DVE. A demo of the OVM e version was recently blogged and one demoing the OVM SV (SystemVerilog) version will be up shortly.

Objection Mechanism

When everything works perfectly, life is just so easy. Unfortunately (or fortunately for those of us who need the work!!), it rarely works that way. The Objection Mechanism package adds a number of capabilities to help coordinate and manage complex testbenches. It includes hierarchical status coordination, objection handling, simplified end-of-test coordination, heartbeat detection of malfunctioning objects, and more.

Fourth in alphabetical order, this most downloaded contribution on the entire OVM World website with 1500+ at the time this blog was written. In its second release now, this register package contains significant improvements recommended by our customers and the OVM Advisory Group (OAG). Among these include greatly improved capacity/performance, multi-bus system-level control, alignment with IP_XACT 1.5, and much more. We do recommend upgrading from our 1.1 version and there is documentation on how to do so. The most-often asked question is "when will there be a joint package" and we are continuing to work with Mentor on that so say stuned to the OVM World and this blog!

Regression Speed-Up

OVM messages are critical to understanding both nominal and error conditions in your testbench. However, when you scale up the environment those innocent string manipulations can become very expensive regardless of the verbosity settings. This contribution show you how to optimize your messaging to improve OVM testbench performance. Like all of our contributions, this should improve your life regardless of the simulator you choose. Of course, this blogger would prefer y'all use Incisive Enterprise Simulator!!

Christmas / Hanukkah / Kwanzaa is coming next. Will there be more treats?

Yes! The genIES are hard at work conjuring up more magical treats for you so visit the OVM World contributions area and this blog frequently or sign-up for the RSS feed.

=Team genIES

Why Verification Engineers Are Like Football Players

Adam Sherilog — Fri, 30 Oct 2009 19:01:00 GMT

Is it their raw power? Is it the cheerleaders? Why are verification engineers like football players? It's because they know how to squeeze the maximum performance out of their resources to win the verification game. Charlie Dawson, Senior Engineering Manager at Cadence, has been leading teams that build performance into our products for years and has taken some time to put the whole game in perspective. Read more about it in his article published in EDA Design Line.

The article follows a similar thought to the paper Charlie delivered at CDNLive! San Jose last month. That paper should be post shortly with the rest of the CDNLive! content.

If you have any questions or want to follow-up on any of the points in the article, feel free to post you comment here or send them to genIES@cadence.com.

=Adam Sheriperf (just extending the "Sherilog" brand to verification performance. :-) )

4 Minute Demo: OVM e Compliance Checks Added to AMIQ's DVT

teamspecman — Wed, 28 Oct 2009 15:00:00 GMT

Specmaniacs rejoice: long time Verification Alliance partner AMIQ has just added OVM e compliance checking to their "DVT" integrated development environment (IDE). Here is a 4 minute video demo with the highlights of this new capability:

If the fails to launch click here.

To get the full scope of the DVT tool and AMIQ as a company, recall the 5 minute general demo of the tool in an earlier post, and this interview with AMIQ's leadership. Alternatively, you can cut to the chase and email etools@amiq.ro to ask AMIQ for an evaluation license. There is additional information at www.dvteclipse.com, including the complete set of DVT manuals.

Happy coding!
Team Specman

P.S. Do you have an e language or Specman-related product, utility, plug-in, or shareware that you would like to promote? If so, please contact Team Specman offline and we’ll work with you to introduce and discuss it via this blog.

Where’s The “You” In The OVM?

Adam Sherilog — Tue, 27 Oct 2009 15:00:00 GMT

Cadence and Mentor have dedicated teams to the development and support of the OVM and you, our user community, have literally tens of thousands of developers dedicated to developing reusable VIP with it. But where do “you” and the OVM meet?

Sometimes the “you” is obvious – the OVM World Forum. With 1100+ unique threads and 4500+ posts, the OVM Forum is by far the most active testbench and reuse site. Every day users interact with the Cadence/Mentor development and support teams, as well as others in the OVM ecosystem, in an open community. Topics range from beginner questions, to enhancement and bug requests, to OVM contributions support, and beyond. Combined with trade-show presentations and webinars, the forums are by far the most public, open face of a testbench methodology.

Speaking of OVM contributions, this is another area on OVM World that is about “you” in a big way. If you have ideas for extensions to the OVM, contribute them! They will be given full consideration for inclusion in future releases. In the meantime, “you” can all share each other’s great ideas.

And sometimes the “you” is less obvious, but may be even more mission-critical. Because your OVM experience depends in part on the methodology/library and in part on the tool suite, some enhancements and bug requests are reported directly to the EDA vendors supporting and developing the OVM solutions. In the case of Mentor and Cadence, we use these reports to fix bugs in the OVM source code. Since these are often accompanied by customer-proprietary examples the bug reports themselves are retained by each EDA provider, but we do exchange simplified examples so that we can jointly produce OVM updates. This effort results in two benefits for OVM users – responses within contractual support timelines to assure the success of their critical projects and bug-fix updates to the OVM downloads. Cadence and Mentor produced two updates to the OVM 2.0 release using this process and a third one – OVM 2.0.3 – is coming in November.

And we can’t forget the OAG – the OVM Advisory Group. This organization of OVM users provides direct guidance for the OVM, and the member companies are publicly identified. The OVM roadmap, presented on the floor of DAC in July and available on OVM World, is a direct result of the OAG. This group will expand over time so that more of “you” can participate directly.

So where is the “you” in the OVM? It’s everywhere – in the public face of OVM World and in the private relationship users have with their EDA partners.

=Adam Sherilog

Specman/IES-XL 9.2 Is Posted - Come And Get It!

teamspecman — Thu, 22 Oct 2009 20:46:00 GMT

We interrupt the Specman 9.2 preview series and ClubT news to announce that 9.2 is now posted on downloads.cadence.com, under the "INCISIV92" umbrella!

Hence, for those of you who couldn't get to a recent ClubT, CDNLive, or Incisive Seminar, our "9.2 preview series" is changing into the "9.2 highlights series", covering the major new features announced back at DAC.

Happy Verifying!

Team Specman

Why OVM? John Aynsley of Doulos Has 10 Reasons

Adam Sherilog — Thu, 22 Oct 2009 13:00:00 GMT

Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM.

If video fails to play please click here.

Question? You can post them here or send them directly to John at john.aynsley@doulos.com.

=Adam Sheriblog

Demo: New Signal Tracing Capability in Incisive Enterprise Simulator

hilker — Wed, 21 Oct 2009 13:00:00 GMT

One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release. The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal tracing function in SimVision.

I thought you might like to see a preview demonstrating the new capabilities for tracing signals directly within the source browser, as well as updates to the Trace Signal Sidebar.

The embedded video is best viewed full screen, which you can do by clicking the lower right-hand icon with the arrows.

If you have problems with the embedded player, click here.

Feel free to post any questions or comments!

Bob Hilker

Extending Multiple When-Subtypes Simultaneously

teamspecman — Tue, 20 Oct 2009 13:00:00 GMT

[For those of you that didn't / can't make it to a ClubT last week/this week, here is a meaty technical article from guest bloggers Matan Vax (R&D Architect), Yuri Tsoglin (R&D), and Dean D'Mello (CoreComp Architect)]

When subtypes let you add properties and behavior to a struct or a unit when one or more enumerated/boolean fields take on specific values. The fields that define when subtypes are called determinants.

Consider the following data type:

      type size_t: [TINY, SMALL, BIG, HUGE];
      struct packet {
        size: size_t;
           // etc.
       };

If the behavior of a corrupt packet applies only to huge packets, you can define it thus:

      extend HUGE packet {
             corrupt: bool;
             keep corrupt => ...; // mess up data if corrupt flag is TRUE
      };

This is, of course, elementary e. But imagine that similar functionality applies to both tiny and huge packets. Can you extend both at once? Is there a tiny-or-huge packet type?

This request is often raised by e users, as there is no built-in language construct for doing so. Fortunately, e is an extensible language, so users can introduce their own constructs with macros to address specific needs.

Here is one way to define the syntax of the required construct:

      extend [TINY, HUGE] packet {
             // ... definitions that apply to both TINY & HUGE packets
      };

We need to come up with a macro that expands such code into a separate 'extend' statement for each of the specified determinant values. Since the number of values may vary, we need to expand the code iteratively. So we need a computed macro, which will return a string of code to be parsed when code with calls to the macro is loaded/compiled.

The definition of the macro is rather straightforward:

define <multi_when' statement> "extend \[<detr'name>,,...\] <base'type>
(<MEMBERS>{<struct_member>;...})" as computed {

            for each in do {
                   result =
   appendf("%sextend %s %s %s;",result,it,<base'type>,<MEMBERS>);
           };
      };

The "trick" to this is the use of a repetition operator in the match expression - [<detr'name>,...]. It reads: one or more comma separated determinant names (identifiers), enclosed in square brackets. With that in the match expression, the variable <detr'name> holding the respective list of matched strings is available inside the macro body. For convenience we also use the submatch label <MEMBERS> for the struct-member block.

The macro capabilities of Specman were greatly enhanced over the past few years, including debug tools: you can see the expansion of loaded macros and use the step-debugger with macro code too! The e reference manual has a more information on computed macros, explaining the structure of match expressions and their operators. It also has some interesting application examples, and info on debugging capabilities.

An important thing note to about this "multi-when" pattern: It syntactically duplicates the required definitions in the scope of each subtype. It does not provide a way to abstract over the added functionality. So in the above example one cannot declare a field or variable of type '[TINY, HUGE] packet', and so cannot get access to field corrupt other than by having a variable of the specific subtype - either 'TINY packet' or 'HUGE packet'. There is simply a different 'corrupt' field for each subtype. When implementing a macro solution it is important for the macro writer to understand the needs of those who will use it as well as the capabilities and limitations of the generated code.

If the "disjoint" property is something that is worth abstracting over (and this is often the case), there is a simple way to introduce the commonality in real semantic terms. Instead of the macro example above, we need to:

1. Introduce a new boolean attribute
2. Put the relevant definitions under it
3. Determine the relation to existing properties through constraints

Here is how it would be done for our example:

     extend packet {
            corruptible: bool;
            keep corruptible == (size in [TINY, HUGE]);
          when corruptible packet {
                 corrupt: bool;
                 keep corrupt => ...; // mess up data if corrupt flag is TRUE
       };
     };

Note that the new subtype 'corruptible packet' lets you access the functionality without having to know the packet's size. The condition on the corruptible property is as flexible as could be. One can declare that, for example, corruptible packets are all but small packets, or dependent on ranges of other scalar attributes.

This pattern too can be captured in a simple macro and made into a single construct with native look & feel. We leave its definition to the reader...

Happy macro writing!

Matan Vax, Yuri Tsoglin, Dean D'Mello

(Plus a shout-out to AE Nils Luetke-Steinhorst who inspired this post based on recent work with a customer on this issue.)

Team Specman

Incisive Enterprise Verifier for Everyone!

tomacadence — Wed, 14 Oct 2009 13:00:00 GMT

Last week Cadence announced a new product called Incisive Enterprise Verifier (IEV) that combines simulation and formal technologies in unique and interesting ways. I am very excited about IEV for two good reasons. The first is simply that it's the product I've been most involved with during my time at Cadence, so I have a personal stake in its success. The bigger reason is my vision that IEV will be the primary tool on the desktop of every design and verification engineer in your company.

That's a bold statement, even coming from a Marketing guy. But I absolutely think that IEV has this potential. Why? Well, IEV has all industry-leading features found in our very successful Incisive Formal Verifier, so you can run formal analysis on fresh RTL code to find bugs, check your design against your assertions, and even hit assertion coverage points to see how well you're exercising your design. But as every formal user knows, on large or complex blocks pure formal analysis may not always give 100% results.

That's where the unique technology blends of IEV come into play. You can take the exact same assertions used with formal and automatically generate simulation stimulus to exercise large designs beyond the range of pure formal. You can pick interesting points in this simulation and perform additional formal runs to find more bugs and hit more covers, "ping-ponging" between simulation and formal if you so desire. You can even use formal to hit an interesting point, such as a cover, and kick off simulation from there.

You can do all this very early in the design process, before any testbench is available. When your testbench is ready, whether it's a simple directed-test setup or a complete constrained-random, metric-driven OVM environment, you can run it with IEV. Yes, IEV also has all the industry-leading features found in our very successful Incisive Enterprise Simulator. If you're mostly a simulation user, you can start with a testbench, and then add in some formal runs using the same assertions you've been simulating to exercise your design more thoroughly.

So what else do you need on your desktop? IEV includes RTL linting, intuituve debug features, verification planning, regression management, tracking of unified verification metrics, example designs and verification environments, testbench simulation, formal analysis, and unique combinations of these technologies. Give every design and verification engineer a copy of IEV, and if you run both simulation and formal on your server farms put IEV there as well. Add VIP Portfolio licenses for your standard protocols, buy Incisive Enterprise Manager for your project leads, and go verify your chip!

Tom A.

The truth is out there...sometimes it's in a blog

The Scoop on the New Incisive Enterprise Verifier

Sarah Lynne — Tue, 13 Oct 2009 21:00:00 GMT

Last week we announced Incisive Enterprise Verifier (IEV). What is cool about IEV is that it integrates formal analysis and simulation engines in unique ways that provide users with more power. One of the great things about IEV is that it is easy to use and get value quickly. It is all about helping to reduce the overall verification time.

Take a look at the press release, and read Richard Goering's blog Combining Formal Analysis and Simulation Provides New Capabilities.

Here is my 3 minute scoop video:

If video fails to launch click here.

Sarah Lynne Lundell

Spanning the Globe to Bring You the Constant Variety of Verification

jvh3 — Tue, 13 Oct 2009 02:29:00 GMT

Any sports fan living in the US during the 70's and 80's will remember the dramatic introduction to ABC television's "Wide World of Sports":

"Spanning the globe to bring you the constant variety of sport… the thrill of victory… and the agony of defeat… the human drama of athletic competition… This is ABC's Wide World of Sports!"

I'll leave it to the reader make your own analogy between the image of the skier crashing that ran during the "agony of defeat" line, and the agony of bug escapes. The point of this post is to highlight upcoming events in verification that I've been involved with preparing to some degree that literally span the globe (hence, my decrease in blogging here, and only minimal micro blogging on Twitter):

CDNLive San Jose 2009
Building on the momentum started in last week's CDNLive San Jose program, the Verification track continues tomorrow with deep dives on OVM with ABV presented by Cadence Architect Sharon Rosenberg, followed by another techtorial on OVM Advanced Applications by Team Specman's own Brett Lammers. In short, in 1 day you can learn everything you need to know about OVM from two of the actual contributors to the OVM itself! (Specmaniacs: be advised that OVM e is a significant part of Brett's presentation; and do NOT miss Specman Architect Matan Vax's presentation on how "OOP Falls Short Of Verification Needs" this Thursday. Consult Team Specman's "CDNLive San Jose guide for the Specmaniac" for more details.)

2009 "ClubT" Series
The ClubT R&D-user group "interlock sessions" are going on in cities across Europe this week and next in the EU (more info posted by Team Specman here) As the founder of the ClubT series, I'm particularly proud of how these events have gotten R&D together with power users to share roadmaps and brainstorm solutions to literally *the* hardest problems in verification. (Here is a report and some snapshots from last year to give you an idea what ClubT's are about.)

Incisive Verification Seminars
This year the Incisive Verification Seminar series kicks off in Yokohama, Japan on October 21 (in 2 weeks)! This event series takes a step back and gives current and future users a bird-eye view of the Incisive Verification platform, in the context of solutions to common flows ("traditional" RTL functional verification, HW/SW, AMS, low power, OVM scalability, etc., etc.), and our roadmap(s) to address the changes these flows will encounter in the next few years (like how to deal with the growing number of billion logic gate chips that continue to appear on drawing boards.)

One final note:
Preparing for these events (especially the ClubT's, which have been "my baby") prompted me to recall one of my original blog posts on "Experiences on Marketing a Verification Library"; inspired by a challenge issued by EDA blogger JL Gray. Re-reading the text, one struggle that still remains with creating the content for any event is answering the audience's selfish-but-totally-fair question of, "what's in it for me?" in a "balanced" way. Here the term "balanced" is applied to the task of giving enough meaty technical content to the expected attendees (in the ClubT case, typically end-users and front line management) that they can go back and try on their workstations immediately, yet also provide enough of the "big picture" to put these capabilities in a proper context.

Unfortunately, the "big picture" is often derided as marketing fluff by EDA industry pundits. However, the truth is that all levels of the R&D ladder share the same big picture hopes & dreams for the benefits that EDA could bestow on their efforts. Paraphrasing, "I want tools and methodologies that can help me make the product I'm working on incredibly valuable to our current customers, and so visibly valuable that new customers will flock to it too; all delivered before our competition has a clue."

This is why you'll see in the ClubTs and other events we take care to show you the big picture right up front, before deep diving into the topic of the day. Ideally this big picture is aligned with yours. If it's not, I encourage you stop the speaker right there, and to trust us enough to share your vision and ideas about what's amiss, and how we might align our respective views.

Joe Hupcey III