Cadence Logic Design Blogs

Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Kenneth Chang — Tue, 27 Nov 2012 17:45:00 GMT

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via...(read more)

Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

SumeetAggarwal — Tue, 07 Aug 2012 15:00:00 GMT

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true...(read more)

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

SumeetAggarwal — Tue, 24 Jul 2012 14:36:00 GMT

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis,...(read more)

8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

David Stratman — Mon, 20 Jun 2011 13:00:00 GMT

It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design...(read more)

Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

Kenneth Chang — Mon, 07 Feb 2011 18:00:00 GMT

Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments...(read more)

New Era Of SoC Design – Still Enabled By Logic Designers

Jack Erickson — Thu, 08 Jul 2010 13:00:00 GMT

If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked...(read more)

Now Available: Encounter RTL Compiler 10.1

Jack Erickson — Mon, 28 Jun 2010 18:50:00 GMT

The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical...(read more)

TSMC Reference Flow Adds TLM Support -- Here's Why

Jack Erickson — Fri, 11 Jun 2010 16:25:00 GMT

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting...(read more)

EDA360: Enlightenment for Silicon Test

Ed JM — Fri, 21 May 2010 21:00:00 GMT

At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies...(read more)

Friday Fun: InCyte Chip Estimator infomercial

Jack Erickson — Fri, 14 May 2010 13:00:00 GMT

This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's...(read more)