Cadence Manufacturability Signoff Blogs

DAC DFM Coalition - Do You Work On Sunday Afternoons?

wilbur — Wed, 14 Jul 2010 17:15:00 GMT

It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010. On...(read more)

Tidbits From TSMC Q209 Earnings Call - 40nm Yield

wilbur — Fri, 07 Aug 2009 13:00:00 GMT

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...(read more)

Moore no More

ChrisClee — Fri, 10 Apr 2009 11:00:00 GMT

"The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months". This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com. This has, of course, surfaced because of the recent release of the Watchmen movie. OK so I admit that I haven't read the book or even seen the movie - and based on my recent experiences of superhero movies (with the exception of the Hellboy movies, starring the very wonderful Ron Perlman) I may not bother.

But when it comes to the "real" Moore's law - Gordon Moore, that is - I think we have all read the book, seen the movie and got the tattoo. So I hereby pledge that I will never again begin another datasheet, article or white paper with words such as, "With design features getting smaller and smaller...". With all respect to Dr. Moore, there are plenty of other interesting and less-explored angles on the manifold complexities of electronic design.

Although we can't take Moore's law for granted, I think we can take it as read.

Chris Clee

Assura Foundry Support

ChrisClee — Mon, 23 Mar 2009 13:00:00 GMT

I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks.

Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give you an answer if you are considering using a new process or foundry, and you want to know whether Assura is supported. Your friendly local Cadence physical verification AE has access to this information and should be able to answer your questions about rule deck support.

Our Assura R&D team is constantly working with the foundries to help update existing rule decks and create new ones. But with all due respect to our foundry partners, their field support teams are not always aware of the latest efforts on rule deck creation and support.

Of course, it's important to check the status of Assura support with your foundry. This has the added benefit to Cadence that it lets them know that you're using Assura. But please also double-check with your Cadence AE, who can ping me to make sure that you're getting the latest information.

Assura On Steroids

ChrisClee — Tue, 17 Mar 2009 15:00:00 GMT

In a recent post, I hinted at a significant performance improvement in Assura.

Our R&D team focused on performance improvements in the 3.2 release, which was shipped last August. Based on our suite of performance benchmarks, we achieved an overall 10x performance boost. This comes from two fundamental improvements: an overall 3.5x boost in single processor performance, and an overall 2.8x performance boost from using four CPUs in a multiprocessor configuration.

Your mileage may vary, of course. Our test suite includes a variety of designs and processes - LVS testcases as well as DRC. We typically noticed the most significant performance improvement on large designs that previously ran for many hours.

This is a maintenance upgrade from the previous release, so there's no risk if you want to download the latest version just to kick the tires. It will probably save you some time.

ERC in Assura II

ChrisClee — Tue, 10 Mar 2009 13:00:00 GMT

In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura.

"But", I hear you ask, "is it programmable?"

One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design platform is that it shares the platform's programming language, SKILL. So yes, it's programmable - in the very same language that your Pcells are written in.

The Buzz Around New Business Models

wilbur — Fri, 06 Mar 2009 11:00:00 GMT

The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model? I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

ERC in Assura

ChrisClee — Thu, 05 Mar 2009 23:08:00 GMT

A few customers have recently asked whether we can provide schematic-based ERC checks. This is no doubt spurred by a recent product announcement by one of our competitors. No - I'm not going to say who, and I'm not going to provide a link to their product page.

We have had layout-based ERC checks as part of our Assura physical verification product since release 3.2 became available last August. A quick check with our field AEs revealed that it's also possible to use Assura for ERC checks based on netlists and schematics, as well as layouts. One of our AEs has put some instructions together, and it actually looks pretty easy. Ask your friendly Cadence physical verification expert for a copy of the document, and tell them to send out an email on the Cadence internal Assura AE email alias if they can't find it right away. While you're at it, ask about the 10x performance improvement that we made in Assura 3.2.

It's interesting that our competitor has made a separate product from this when we give it away for free with Assura. Marketing, I guess.

Big Bang

ChrisClee — Mon, 02 Mar 2009 14:00:00 GMT

When something big and expensive fails, we usually hear about it in the headlines. Recent examples include the launch failure of the Orbiting Carbon Observatory and the setback at CERN, apparently caused by a dry solder joint, that resulted in a 12-month delay in their search for the Higgs particle.

When something small and cheap fails, it rarely makes the headlines. Unless, of course, it causes something big and expensive to fail - like a particle accelerator, a satellite or perhaps a semiconductor company.

In the semiconductor industry, we have built up a system of safeguards and checks to minimize the risk of failure. We apply these checks throughout the design process, and as a series of sign off steps that precede manufacture.

I would be interested to understand whether other industries - e.g. avionics or automotive - have built up a similar infrastructure of pre-manufacturing sign off checks. Do they rely on modeling during design, pre-manufacturing sign off or a combination of both? Is there anything that we can learn from other industries? Is there anything that they can learn from us?

All For One

ChrisClee — Mon, 23 Feb 2009 14:00:00 GMT

Finally, sanity. Concerned about the level of electronic waste created by discarded phone chargers, the European Commission has told mobile phone manufacturers that they must adopt a standard. This will hopefully have the additional advantage of reducing blood pressures if we no longer need to rummage in our desk drawers frantically searching for the right charger.

I wonder whether manufacturers would have voluntarily adopted a standard without external influence. The choice of how to wire our "wireless" appliances seems to offer so little differentiation, and standards are so freely available that I am surprised that this hasn't happened sooner.

Unfortunately, there are few parallels in the EDA/manufacturability world. EDA products derive a significant part of their differentiation from the range and types of data that they can connect to, particularly in the case of enabling information such as library and technology files.

The good news is that technology file standards are becoming available that could replace what were once proprietary formats, and there is motivation to adopt the standards because our foundry partners (as well as our customers) evidently recognize the value of common formats. Whether the foundries can agree among themselves on common formats remains to be seen.