Cadence Manufacturability Signoff Blogs

Moore no More

ChrisClee — Fri, 10 Apr 2009 11:00:00 GMT

"The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months". This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com. This has, of course, surfaced because of the recent release of the Watchmen movie. OK so I admit that I haven't read the book or even seen the movie - and based on my recent experiences of superhero movies (with the exception of the Hellboy movies, starring the very wonderful Ron Perlman) I may not bother.

But when it comes to the "real" Moore's law - Gordon Moore, that is - I think we have all read the book, seen the movie and got the tattoo. So I hereby pledge that I will never again begin another datasheet, article or white paper with words such as, "With design features getting smaller and smaller...". With all respect to Dr. Moore, there are plenty of other interesting and less-explored angles on the manifold complexities of electronic design.

Although we can't take Moore's law for granted, I think we can take it as read.

Chris Clee

Assura Foundry Support

ChrisClee — Mon, 23 Mar 2009 13:00:00 GMT

I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks.

Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give you an answer if you are considering using a new process or foundry, and you want to know whether Assura is supported. Your friendly local Cadence physical verification AE has access to this information and should be able to answer your questions about rule deck support.

Our Assura R&D team is constantly working with the foundries to help update existing rule decks and create new ones. But with all due respect to our foundry partners, their field support teams are not always aware of the latest efforts on rule deck creation and support.

Of course, it's important to check the status of Assura support with your foundry. This has the added benefit to Cadence that it lets them know that you're using Assura. But please also double-check with your Cadence AE, who can ping me to make sure that you're getting the latest information.

Assura On Steroids

ChrisClee — Tue, 17 Mar 2009 15:00:00 GMT

In a recent post, I hinted at a significant performance improvement in Assura.

Our R&D team focused on performance improvements in the 3.2 release, which was shipped last August. Based on our suite of performance benchmarks, we achieved an overall 10x performance boost. This comes from two fundamental improvements: an overall 3.5x boost in single processor performance, and an overall 2.8x performance boost from using four CPUs in a multiprocessor configuration.

Your mileage may vary, of course. Our test suite includes a variety of designs and processes - LVS testcases as well as DRC. We typically noticed the most significant performance improvement on large designs that previously ran for many hours.

This is a maintenance upgrade from the previous release, so there's no risk if you want to download the latest version just to kick the tires. It will probably save you some time.

ERC in Assura II

ChrisClee — Tue, 10 Mar 2009 13:00:00 GMT

In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura.

"But", I hear you ask, "is it programmable?"

One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design platform is that it shares the platform's programming language, SKILL. So yes, it's programmable - in the very same language that your Pcells are written in.

The Buzz Around New Business Models

wilbur — Fri, 06 Mar 2009 11:00:00 GMT

The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model? I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

ERC in Assura

ChrisClee — Thu, 05 Mar 2009 23:08:00 GMT

A few customers have recently asked whether we can provide schematic-based ERC checks. This is no doubt spurred by a recent product announcement by one of our competitors. No - I'm not going to say who, and I'm not going to provide a link to their product page.

We have had layout-based ERC checks as part of our Assura physical verification product since release 3.2 became available last August. A quick check with our field AEs revealed that it's also possible to use Assura for ERC checks based on netlists and schematics, as well as layouts. One of our AEs has put some instructions together, and it actually looks pretty easy. Ask your friendly Cadence physical verification expert for a copy of the document, and tell them to send out an email on the Cadence internal Assura AE email alias if they can't find it right away. While you're at it, ask about the 10x performance improvement that we made in Assura 3.2.

It's interesting that our competitor has made a separate product from this when we give it away for free with Assura. Marketing, I guess.

Big Bang

ChrisClee — Mon, 02 Mar 2009 14:00:00 GMT

When something big and expensive fails, we usually hear about it in the headlines. Recent examples include the launch failure of the Orbiting Carbon Observatory and the setback at CERN, apparently caused by a dry solder joint, that resulted in a 12-month delay in their search for the Higgs particle.

When something small and cheap fails, it rarely makes the headlines. Unless, of course, it causes something big and expensive to fail - like a particle accelerator, a satellite or perhaps a semiconductor company.

In the semiconductor industry, we have built up a system of safeguards and checks to minimize the risk of failure. We apply these checks throughout the design process, and as a series of sign off steps that precede manufacture.

I would be interested to understand whether other industries - e.g. avionics or automotive - have built up a similar infrastructure of pre-manufacturing sign off checks. Do they rely on modeling during design, pre-manufacturing sign off or a combination of both? Is there anything that we can learn from other industries? Is there anything that they can learn from us?

All For One

ChrisClee — Mon, 23 Feb 2009 14:00:00 GMT

Finally, sanity. Concerned about the level of electronic waste created by discarded phone chargers, the European Commission has told mobile phone manufacturers that they must adopt a standard. This will hopefully have the additional advantage of reducing blood pressures if we no longer need to rummage in our desk drawers frantically searching for the right charger.

I wonder whether manufacturers would have voluntarily adopted a standard without external influence. The choice of how to wire our "wireless" appliances seems to offer so little differentiation, and standards are so freely available that I am surprised that this hasn't happened sooner.

Unfortunately, there are few parallels in the EDA/manufacturability world. EDA products derive a significant part of their differentiation from the range and types of data that they can connect to, particularly in the case of enabling information such as library and technology files.

The good news is that technology file standards are becoming available that could replace what were once proprietary formats, and there is motivation to adopt the standards because our foundry partners (as well as our customers) evidently recognize the value of common formats. Whether the foundries can agree among themselves on common formats remains to be seen.

Coffee, Anyone?

ChrisClee — Tue, 13 Jan 2009 11:00:00 GMT

How little the world changes. Back in the days of 68000-based workstations, we would open up a design and retreat to the break room for a coffee while it loaded. Now, in the gigabyte / multicore era, we open up a design and retreat to the break room for a coffee. Moore's law clichés aside, semiconductor design is sometimes reminiscent of lifting oneself by the bootlaces. We produce faster and more powerful designs so we can... produce faster and more powerful designs!

But the philosophy of the one laptop per child initiative (which spurred the current netbook trend) contrasts with the processor/software arms race. It is a lightweight solution focused on solving a specific problem.

To draw a parallel in the EDA world, consider our QuickView product. This is a nimble layout and mask data viewer that quickly opens and pans/zooms around data files across multiple formats in the gigabyte-terabyte range. It's not for general purpose layout editing, but it's great for when you just want to take a quick peek.

Coffee, anyone? Better make than an espresso...

Getting Good Silicon With More Accurate Timing

wilbur — Fri, 09 Jan 2009 17:43:00 GMT

In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window.

To that end, there appears to be a heightened interest in variation-aware methodologies to more accurately predict the electrical characteristics due to manufacturing/process variation. CMP, Litho, and stress effects all play a role in changing the transistor and interconnect characteristics at 90nm, 65nm, and below.

Are you concerned? How much variation would start being a concern for you? 5% in the critical path? 10%? I'd like to hear the risk tradeoff people make.

Diagnosis of Compressed Test Patterns: Several Things to Consider

Tom J — Tue, 21 Oct 2008 18:45:00 GMT

Today, it is essential to put into place a strong methodology to identify sources of yield loss during manufacturing. One widely accepted method involves diagnosing a representative sample of device failures during manufacturing test. The failing results are aggregated, analyzed and a Pareto is created showing the highest frequency of failures from one or more of: cell, instance, net, test pattern, metal layer and layout topology. i.e. nets on M4 with more than five vias

This methodology is called volume diagnostics and basic information about it can be found at:www.cadence.com/newsletters/new_pdf/article3_diag.pdf

There are many considerations when you deploy diagnostics including:

On or offline diagnosis - do you diagnose failures in real-time or do you sample failures and diagnose them outside of production
Number of failures in sample - how many lots and wafers do you use to collect a sample, how many failing die are in the sample
Diagnose scan test vectors or compressed test vectors - in the case of the former, you diagnose directly from the failing scan registers and in the case of the later, you diagnose failures from output (signature) of the compactor logic

In considering item three, the growing use of embedded compression techniques that are often used to lower both the volume of test data and subsequently testing time complicates both the diagnosis of scan chain failures as well as failures in the logic clouds between scan registers. Compression involves hardware placed on-chip that is used by ATPG tools to provide compressed test patterns. In simple terms, compression involves a decompressor that fans out compressed scan data to all scan chains and a compactor that combines the outputs of all scan chains into a compressed signature. In these two elements, there can be combinational and or sequential logic depending on the compression architecture. In the case of Cadence's tools, we have support for XOR (combinational) and OPMISR (sequential) compression architectures.

With sequential logic being used in on-chip compression, this infers temporal data must be used by the diagnostic tool. When a failure is observed in the signature of the compactor the diagnostic tool needs to 'unrolled' the failing bit(s). It analyzes the data back wards in time to find the offending input pattern. This task can involve examining hundreds or thousands of clock cycles to get the actual scan bits that detected the failure. This issue can be even further complicated when multiple failures exist in the scan chains and or in the logic clouds between scan chains.

In the case of a pure combinational compression architecture, the 'unrolling' of time task is taken away as a diagnostic challenge but there are still added diagnostics complexities especially when there are a very large compression ratio. i.e. small number of inputs fanning out to many scan chains and then being compacted down to a small number of bits. In this case, failure aliasing is very likely.

What can one do to assure the best diagnostics results?

The optimal solution for combinational compression is to run diagnostics in a single pass. However, when a OPMISR is used or when results are less than optimal, it is desirable to have some number of scan vectors available to run on ATE. This vector set can be small in size as long as it provides effective test coverage on the order of 80% plus. When performing on line diagnosis, this augmented test set can be quickly applied to a failing device to improve diagnostic results. The cost of doing a reload can be minimized by many factors such as ATE architecture and the use of multi-site testing. The small set of scan vectors can be quickly loaded on early failures during the testing of passing devices. Likewise, if the device is of an AMS type, then scan tests can be easily loaded onto failing devices during the long analog test sequences.In summary, it is important to plan your diagnostics methodology and be prepared with scan test for all situations when sequential compression os used or diagnostic results are less than satisfactory.

Video interviews from the floor of CDNLive!

Dieds — Wed, 10 Sep 2008 20:08:00 GMT

With hundreds of attendees buzzing about, our video crew has been busy with their “man-on-the-street” style interviews from the floor of “CDNLive! Silicon Valley 2008” here at the San Jose Convention Center.

The “CDN” in the name stands for “Cadence Designer Network.” This week’s conference is part of a worldwide series of meetings where Cadence power-users can network with their peers as well as industry experts and Cadence technologists. This annual event provides a unique forum for participants to exchange ideas and best practices.

The vision for this year’s conference is to help designers overcome challenges stemming from the increased “consumerization” and macro-economic pressures affecting the global electronics market.

I’ll be adding more videos as they come in. Meantime, take a look at some of the coverage below. (Double-click each video to see a larger version)

What works best?

Tom J — Thu, 14 Aug 2008 16:35:00 GMT

Today's conventional wisdom tells us EDA folks the majority of yield loss at semiconductor companies is due to systematic issues, that's what my customers say to me. When I speak with new prospective users of my yield ramp solution, I normally see concurring facial expressions when I mention this as the most pressing problem facing product engineers.

Given this apparent reality, the majority of manufacturing failures are being caused by defects due to a specific layout being implemented using narrow process windows. For example, lithography windows have shrunk significantly, the usable depth of focus can be ~200nm or less. If this is the case, and we see misprints that impact a device's implementation how can we best find the topologies that are being effected the most often?

I am very curious if readers believe that traditional inspection and or metrology methods are sufficient or do we need to use diagnostic tools to correlate ATE failures to likely offending pattern in the layout?

Please allow me to ...

Tom J — Wed, 06 Aug 2008 20:29:00 GMT

In the words of the Rolling Stones…. Please Allow Me to Introduce Myself ,,,,, I took a different slat than Chris on my intro but I am a Product Marketing Director for Cadence's Diagnostics and silicon analysis products. I also have over 20 years of EDA experience and began my career as a test engineer working on hardware accelerators. I have held various positions in field applications and product marketing in the areas of design for test, formal verification, diagnostics and yield management. I work out of my home office in beautiful Merrimack, New Hampshire.

Anyone involved in managing OPC or DFM may want to read this

Tom J — Wed, 06 Aug 2008 19:21:00 GMT

There is a good article in the August edition of Microlithography World that anyone involved in managing OPC or DFM may want to read. I may be a bit biased (I was one of the authors) but it is good......

Here's a link to the article.

Fujitsu, Applied Materials and Cadence collaborated for this article to discuss the process we used to help Fujitsu create CD-SEM recipes. It was a great experience and our collaboration helps determine the effectiveness of OPC on their silicon. Our results showed using the Cadence technology reduces the time spent on the CD-SEM recipe creation process by a factor of 6× (1,200 minutes to 213 minutes).

I would be very interested in what people think about the article and how they create CD-SEM recipes. Feel free to comment below.