Cadence PCB Design Blogs

What's Good About Innovation at Cadence? – It’s alive and well and increasing!

Jerry GenPart — Tue, 03 Nov 2009 14:00:00 GMT

I'm switching gears this week from my regular SPB technical product posts to focus on an annual Cadence event - Cadence Innovation Day.

Today Cadence will honor the 2008 recipients of the Excellence in Innovation Awards. This year, 35 winners will be celebrated amongst their peers from all geographies and organizations - 13 of this year's recipients are from locations outside San Jose.

Adam Sherer is one of this year's recipients and a fellow blogger - so send him
congratulations on his Blog.

Cadence has been a consistent leader in innovation since its foundation 21 years ago. One measure of innovation is the number of patents issued. With more than 800 U.S. patents issued (an additional 150 international), Cadence holds far more patents than any other EDA company in the world.

"The Excellence in Innovation Awards program recognizes our best inventors and most significant inventions," said Interim Chief Technology Officer Charlie Huang, "These annual awards are a reminder of just how innovative Cadence is. We want to recognize our company's great spirit and tradition of innovation with a day of celebration and appreciation."

"The Excellence in Innovation Awards program was established to encourage, promote, and recognize the wealth of innovative, internally developed technology," said Mike Williams, Vice President and Associate General Counsel, and program manager.

Our customers rely on Cadence for innovation leadership. "Leadership in innovation is fundamental for customers to choose Cadence as their trusted design partner," said Tom Cooley, Sr. Vice President, Worldwide Field Operations. "Innovation is and must always be part of the Cadence brand."

Bringing innovation a bit closer to my own organization - the Global Field & Customer Support (GFCS) team - we've initiated a web based idea submission and management approval system (called iInnovate) for GFCS employees late last year. This Wiki based site contains all the details for everyone to review and measure - submissions, ideas approved and implemented/referred, awards presented, process info, etc. It's a very easy and comprehensive innovation enabler!

The goal that Dan Rourke, VP Customer Support established was to cultivate a sustainable innovation engine among all GFCS employees to empower us to submit ideas and increase the value-add we provide to both our external and internal customers. A team within GFCS was formed to look at innovation best-practices among companies and deliver a web-based approach to streamline all aspects of delivering innovation across the GFCS team. There are several categories available on the web site to help focus innovators in key areas - among them being Customer, Process, and Technology. Everyone in GFCS can view ideas submitted, check on the status of the ideas, and see how the iInnovate review team and GFCS management has dispositioned each submission. There are inspirational quotes updated periodically, and the GFCS management team updates the site with new directions they'd like to see employees focus for a period of time (usually 3-6 months). This allows everyone to think within the current strategic focus and provide new ideas to support these efforts. More than 40 new ideas have been submitted through the iInnovate site since we began with more than 15 ideas implemented or referred to other teams for implementation.

Some of the GFCS's ideas that have been implemented are:

Enhanced videos/screen casts on Cadence Online Support
Cadence Online Support product release schedule updated
Added an “All Products” choice in the Cadence Online Support search selection

It's great to work for Cadence where innovation is recognized at the corporate level and employees are energized within my own group to continue to explore new innovative methods to improve how we work with our customers.

As always, I welcome your suggestions and discussion on this topic.

Jerry "GenPart" Grzenia

What's Good About Net Color Override in Allegro? Check Out The SPB16.2 Release and See!

Jerry GenPart — Thu, 29 Oct 2009 16:00:00 GMT

Color assignment in Allegro PCB Editor has been accomplished with either a class/subclass color assignment or a color assignment done with the highlight command. With designs becoming more complex, it's desirable to be able to assign colors, including custom colors to independent objects.

Database elements may be displayed using either the class/subclass color or a single color assigned to an element, also known as a custom color. To assign a custom color to an entire net or to its pins, vias, clines, shapes, or rats, you use the Nets grid. Assigning a custom color automatically enables the custom color state for that element as well, meaning that the custom color displays in the design canvas.

You can also define how the custom color displays the element using a combination of states — none, highlight or custom color state, or highlight plus custom color state — all of which may be set independently. Highlighting or custom colors are set or unset by right clicking and choosing Set Highlight State or Clear Highlight State, respectively in the color chip. If an object is highlighted the text for that object type will be in bold.

To prevent a custom color from displaying in both the Nets tree and the design, right click and choose Clear Custom Color. A color box without a color assigned to it has no custom color state. These custom color and highlighting states affect the display of the element as follows:

Custom Color	Highlight State	Custom Color State	Display Using
Yes	No	No	Class/subclass color
Yes	Yes	No	Highlighted color
Yes	Yes	Yes	Highlighted color
Yes	Yes	No	Custom color. No highlighting
No	Yes	No	Highlight with temporary highlight color
No	No	Yes	Custom color with tempororary highlight color
No	No	No	Class/subclass color

As always - I welcome your question & suggestions.
Jerry "GenPart" Grzenia

What's Good About Package Power Integrity? You'll Need SPB16.2 To See!

Jerry GenPart — Wed, 21 Oct 2009 18:25:00 GMT

As clock and data frequencies increase and high-speed systems become ever more densely populated, the distribution of power becomes a major challenge for package power/ground design. To ensure that high-speed systems continue to deliver the required performance at these new signal frequencies, power distribution impedance has to be controlled over a wider range of frequencies. This can be accomplished through careful consideration of the design of the switching power supply, bulk capacitance, ceramic capacitance and power/ground over the frequencies of interest. Having the ability to accurately simulate a power distribution system and synthesize the necessary quantities and values of decoupling capacitors is now crucial, as the power distribution system has become a critical element of system design in high-speed systems.

This feature provides a flow to analyze the power delivery for power nets in APSI and SiP SI. This flow uses Apache's PakSi-E 3-D field solver to model the power and ground nets of the package. You set the target impedance for given power net, then assign port types, group and excitation for die and package pins, and place various appropriate decoupling capacitors in the design. Then the equivalent circuit for simulation can be extracted.

Requirements

The Package Power Integrity feature is available in the Allegro Package Designer SI L and the SiP Digital SI products.

Package PI also requires a third- party product, the Apache Paksi-E field solver. The PakSi-E solver is not licensed or provided by Cadence.

Tips and Workarounds

When the Paksi-E extractions fails, save the design, delete the paksi.run directory and restart the tool.

Package Power Delivery Analysis

In the Package PI solution, when you have board and on-die information, a complete analysis can be accomplished by using a subcircuit model for the PCB board as well as for the die. The equivalent circuit of the die and board can be extracted by either EDA tools or measurement. Both spice-like circuit and S-parameter models can be accepted. The PCB circuit model and VRM (Voltage Regulator Model ) do not need to be present for the tool to determine the "Z" as seen from the die. A more accurate impedance Z can be determined with more of the overall system modeled.

The PCB model which is now a 2 terminal subcircuit model and does not have to be present for analysis.

Use Model

Step 1 — Preliminary Configuration

The following parameters are common for design and are out of the scope of the package PI flow, and should be configured correctly before analysis. In most cases, you should have set up these parameters correctly in package design editors, like the wirebond profile, bump and ball pins, and so on.

   1. Identify power and ground nets' voltages and assign voltage property
   2. Set up ball & bump parameters.
   3. Set up bondwire profiles.
   4. Set Paksi-E field solver parameters.

The Enable Multiport is typically YES and Frequency is the center frequency of the extracted model.

Step 2 — Power/Ground Net Information

   1. Select a power net from the drop-down list.
   2. Select ground nets for later decoupling capacitors' placement.
   3. Set target impedance (voltage, tolerance, max ramp current and so on).
   4. Select VRM model and board power supplier subcircuit. [Optional].

The Power Supply button brings up a form where the VRM model can be selected and edited. The form also allows you to select a subcircuit model for the PCB board if one is available. That PCB model is expected to come from measurement of a board, or some 3rd party extraction tool. A subcircuit model could be made with some assistance and effort by hand editing some files from an Allegro PCB PI board level simulation, but we do not currently have an automatic flow to use an Allegro board database.

VRM Model

The VRM model an equivalent circuit model consisting of an ideal voltage source and four passive elements. Many of the components are common to both a nonlinear and linear VRM. R0 is the value of the resistor between the VRM sense point and the actual load, and is usually only a few milli-Ohms. A VRM is not capable of regulating the voltage at the actual load.

L_out represents the output inductance of the VRM. It may be the inductance of cables that connect the VRM to a system board or it may be the inductance of pins that connect a VRM to a micro-processor module (about 200 nH and 4 nH, respectively). The maximum effective frequency for the VRM is determined by L_out.

R_flat represents the ESR of the VRM at frequencies beyond the response time of the loop. The ideal voltage source has the value of the power supply voltage. L_slew is the only element in the linear model that is not traceable back to an element in the nonlinear VRM model. The value of L_slew is chosen so that current will be ramped up in the linear model in about the same time as it is ramped up in the real VRM. It is calculated from the equation V=L(di/dt).

V is the amount of voltage droop or spike that can be accepted in the PDS (for example 5% of 1.8V). The maximum transient current is used for di. The total amount of time for the VRM to ramp this transient current either up or down is used for dt. The graphic shows a sample calculation for L_slew for a VRM that can ramp down 20 amps in 15 microseconds.

The VRM model can be text edited and so the internal subcircuit can be changed. PI will check the model to find out that this specified VRM model has only two terminal ports. If this model has only two ports, Package PI will view this model as a valid VRM model. It should be pointed out that you should be responsible for your own defined VRM model because a bad model for a VRM can cause a simulation failure that may not be easy to detect.

Step 3 — Port setup

There is a Port Information tab on the main Power Integrity form where die pads and BGA pins are setup and grouped together. The die current profile and circuit model are also set here.

All die and package components connected to the power net will be listed automatically and you should then configure the on-die information and port information.

   1. Set die current profile [Optional].
   2. Set on-die series capacitance and resistance, or subcircuit [Optional].
   3. Set port group information for die and package components.
   4. Set port sink/source type and sink excitation for die and package pins.

All package pins are forced to be SOURCE and you cannot change them. All die pins are considered to be SINK type by default. But you can change the die pins into OPEN or SOURCE type, because in some SiP cases, some die pins can act as sources.

Note: The actual difference between OPEN, SOURCE and SINK pins is that the current flowing through the SINK pins are pre-determined and fixed, while the current flowing through the SOURCE pins are variable and to be calculated, and no current flows through the OPEN pin. Tthe Paksi-E extracted subckt will not have ports for pins with an OPEN port type.

A whole column can be changed at once by using the RMB on a column header such as Port Type or Excitation. The port assignments can also be imported and exported to a file.

Port Grouping

The ports are grouped into basic categories to use the multiport capability on the field solver. This makes a model of the package power and ground nets that have a connection for each port rather than the much larger connection for each BGA and DIE pin.

Consult the Paksi-E documentation for more information on port groups and multiport.

Step 4 — Decoupling Capacitor Selection and Placement

This is a repeating step for Power Integrity analysis until you get satisfactory simulation results.

1. Select an appropriate dml model for the decap. You can browse for the model from the design or import one from an Allegro part library, for example the power_integrity.dml or vendor supplied models. You can also edit the parameters on the models when necessary.

2. Place virtual decaps into the design.

Virtual decaps can be placed into the design with from the RMB menu on a Decoupling Capacitor. Place or move the pins on power and ground nets for best location to reduce the impedance profile. When they are verified as correct, you can replace them with instant decap, then finish fanout and routing for final analysis in APD or SiP.

Use the Visibility and Options to show each power and ground shape when placing the selected pin showing on the Options section.

The above figure shows pin 2 of a virtual capacitor on the GND layer on a shape associated with the VSS net with pin 1 already placed.

3. Add probe port in design for output [Optional].

Using the RMB out on the design canvas, you can add a probe port or VPort in the canvas to output the voltage ripple and impedance value on a specific point for testing purposes during the analysis. A probe port is a specific one-pin component that acts as an output port during circuit extraction.

Note: Both virtual decaps and probe ports are removed once Package PI exits and are restored when it is next invoked.

There are other virtual decap and Vport operations that can be done from this menu.

Step 5 — Extraction and Analysis

You can now perform the voltage ripple analysis in the time domain or target impedance analysis in frequency domain and check the result in SigWave. When the results doesn't meet the target, repeats steps 2, 3, and 4.

1. Select analysis type and options.

You can select the analysis type among voltage ripple analysis in the time domain, target impedance analysis in the frequency domain, or equivalent circuit extraction only. There is also an option to reuse pre-stored equivalent circuit extracted by the field solver in a previous analysis.

Paksi-E will automatically extract equivalent circuits for the selected power net and coupled ground nets, including bondwire, ball and bumping, vias, fanout of decoupling capacitors and so on, and store this in the Package PI working directory for later simulation. Paksi-E will extract the narrowband model by default, but you can change the parameter to extract another other type. Package PI uses the extracted model, builds the circuit with the extracted dml model, other dml models in virtual and instant decaps, VRMs, board and die power supply circuits, sink excitations and so on, and then pass it to TLSim for simulation. The netlist used for TLSim simulation is stored in Package PI working directory pdnAnalysis.run.

2. Check analysis results in SigWave.

After voltage ripple or impedance value analysis, Package PI displays the analysis results in SigWave. You can check the result with a preset target. Those points on the package where the impedance value or the voltage ripple exceeds the target at any frequency or time domain will receive particular attention and you can repeat step 4 to place the decoupling capacitors to achieve the target impedance.

SigWave displays the impedance at the different ports of the model. It also shows an Estimated Target Impedance which is calculated from the Voltage, Max Delta Current and Ripple Tolerance from the Power Integrity general form. There is also a display of the Calculated Target Impedance which is determined from the Excitation Sources on the current Sink ports.

Step 6 — Report & Export

You can view the detailed report for decoupling capacitors used in design for power integrity and export the decoupling capacitors used in design for the selected or all power nets. Use this report to guide the actual placement of capacitors on the package with APD or APSI

As always, please keep your suggestions and questions coming!

Jerry "GenPart" Grzenia

What's Good About PDV Symbol Property Templates? The Secret's in the SPB16.2 Release!

Jerry GenPart — Wed, 07 Oct 2009 16:50:00 GMT

Allegro PCB Librarian / Part Developer (PDV) Symbol Property Templates have been a very beneficial feature in the SPB16.2 release.

IEEE standards define a certain set of properties and their attributes for a symbol. Adding these properties individually to each symbol and setting the attributes according to the defined standards is a time-consuming and error-prone task for librarians. The Part Developer SPB16.2 release provides easy-to-use functionality for creating symbol property templates and applying them not just at the setup level, but also at a symbol level. This support for symbol property templates makes symbol creation a quick and efficient process for librarians who need to create symbols according to specific standards.

Enhancements added to support Symbol Property Templates include:

Defining text height for properties
How the property will be displayed (i.e. visibility, color, rotation, location, and alignment)
Extracting a template from an existing symbol

Part Developer provides you the ability to define part construction rules and property settings through the use of templates. Using templates, you can quickly create parts that follow your company standards, yet have the flexibility to add properties and behaviors specific to the parts. You can also apply the templates to existing parts.

Typically, a symbol-level template needs to be modularized so that you can create reusable libraries for different symbol elements such as properties and graphics

Displaying Components of Symbol Property Templates

Symbol Property Templates contain a set of symbol level properties and their attributes which are added to a symbol when the template is applied. The application of a symbol property template on a symbol will enable users to quickly add these properties on the component that they are building. The template can be applied on the existing as well as new components.

Symbol Property Templates contain the following data:

Default property height (system units)
List of symbol level properties, where each property contains the following attributes
- Name
- Value
- Visibility
  (Note: the typical options apply - Both, Invisible, Name, Value
Display attributes
- Color
- Rotation
- Height
- Location
- Alignment

Symbol Property Templates basics

Selecting Templates> New, will present the symbol property creation dialogue box:

The template type will be saved in a file with an extension of .sptpl

In order to view, edit, or apply an existing template, select Templates> Open.

In order to extract a template from an existing symbol, Right-Mouse-Button (RMB) click on the symbol in the left side tree view and select Extract Property Template:

As always, I welcome your discussions on this new SPB16.2 PDV feature.

Jerry "GenPart" Grzenia

What's Good About APD's Design Integrity Check? - It's in SPB16.2!

Jerry GenPart — Wed, 30 Sep 2009 18:01:00 GMT

The Cadence IC Packaging tools are complex, flexible tools that allow a designer freedom to create a package substrate layout in a myriad of ways. As a result, it becomes possible to run a particular feature at a time when the database is ill-configured to handle the request. Or, a given command could have a bug which results in the corruption of a specific database object in a manner that is not illegal to the database structural integrity but will not be processed correctly by other commands.

While programs built on top of Cadence Allegro database technology have a built-in check for the integrity of the database itself, they lack any similar checking capability for validating that the database is configured in the manner expected for a given application.

It is with this in mind that we aim to implement not a database integrity check, but instead a design integrity checking tool. The goal of these checks, then, is to ensure that the database adheres to the implied requirements of the tool modifying it.

A simple example involves interfacing with the Optimal Paksi-E Field solver. The solver may return incorrect results if the database is not properly configured, but it can run for hours, even days, before returning these bad results. If the customer can run checks to reasonably ensure the database is correctly configured, it can save precious time in the competitive world of package substrate design and layout.

In this way, the user can diagnose some of their own problems and can work to self-correct their flows to account for the expectations of the tool. This can save time and aggravation.

The intention here is to allow a proactive, instead of reactive approach to assisting customers working through common problems.

If the customer is having problems getting a specific command to act appropriately, they are advised to run any checks from this command which deal with the problem area. In addition, the customer should run the Tools->Database Doctor command.

Use Model

This command should be run prior to performing certain milestone events, such as doing a full 3D SI model extraction on your database and before calling Cadence technical support. The tool will make every attempt to help you overcome problems in your design by correcting them on your behalf or advising you how to correct them.

To run the command, launch it from the menu / toolbar icon and select the checks which you want to run. Press apply, once the appropriate checks are selected and the reporting options are configured to your desire.

If any errors are found in the database which cannot be automatically corrected, we advise you to correct those errors and re-run this command prior to continuing with your design flow to ensure that you do not encounter further problems or compound the difficulties later on.

Menu and Command Line Access

This command is available near the existing Database Doctor tool. It will exist under the tools menu as:

Tools > Design Integrity Check…

From the command line, it may be run by typing: package integrity

Graphical User Interface

The user interface for the design integrity checker is shown below. The fields operate as follows.

NOTE: Rules listed in the Check Categories are for illustration purposes ONLY.

All On: Toggle all defined integrity checks in all categories to on (checked) state.
All Off: Toggle all defined integrity checks in all categories to off (unchecked) state.
Check Category Tree: This tree defines all the categories and checks which are currently registered for the active running product. The user may toggle either a full category or individual rules on/off through this interface. Selecting the name of a rule or category instead of the checkbox will display its documentation in the right panel but will not change its active state. All rules default to de-selected. Any rule which can be automatically fixed by the tool will be suffixed with “(F)” to indicate this and, when selected, will display “(Fixable)” in the display window. Rules which cannot be fixed automatically will provide the user as much detail instructionally as to how to best fix the problem and why the resulting database structure is better.
Log File: Whether or not to write a log file of problems found to disk. This defaults to on.

Log File Name: Name of the log file to write, defaults to package_design_check.log. This file will be written to the location pointed to by the ADS_SDLOG user preferences variable.
Fix errors automatically (where possible): If enabled, this will cause rule checks to fix errors where possible in your design. The ability to self-correct the errors will vary for each rule being checked. Defaults to on.
External DRC markers: If enabled, the tool will generated external DRC markers at the locations where violations appear. These markers will use the name of the defined rule as their description element, therefore making them easier to location. This defaults to off.
Clear DRCs: Press this button to remove any DRC violations found by this command during this or previous runs of the tool.
Descriptive Bitmap: Provides an illustration regarding what this check / category is designed to look for. This is optional for user-defined rules.
Descriptive Text: Provides a (detailed) text description of the check / category, including such information as what the problem is, how it manifests, what problems it will cause and how it can be corrected or avoided in future design flows.
OK: Close the form and run the selected checks.
Close: Close the form without running any checks.
Apply: Perform the selected checks, but leave the command active and form displayed.
Help: Raise context-sensitive help for this command.

As always, I look forward to your feddback on using this new capability in the SPB16.2 APD release.

Jerry "GenPart" Grzenia

What's Good About Allegro's Component Placement Changes? - More Features in SPB16.2!

Jerry GenPart — Wed, 23 Sep 2009 16:35:00 GMT

In the SPB16.2 release of Allegro PCB Editor, there are two (2) new very helpful features (among the many others) that assist PCB designers with component placement - Component Alignment and Placement Replication.

Component Alignment

You can now specify a Vertical or Horizontal alignment of symbols based on their body center.
- There are no associated options.

The feature automatically attempts to determine the axis to align.
- You'll be prompted for a direction (Vertical or Horizontal) in ambiguous situations.
The use model requires the pre-selection of all symbols to be aligned.
- You can hover over an anchor symbol then right mouse button (RMB) – Align Component.
This is a single-sided application.

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;}

Now the parts are aligned -

Placement Replication

This is an application designed to replicate common blocks of circuitry.
- Based on common device and connectivity model.
- No Front End dependencies other than net list.
The process begins by establishing an initial “seed” circuit.
The Place Replicate Create function is then used to create a .CRF file with origin point.
- The CRF (Circuit Replicate File) can be stored in the board DB or on disk for re-use on other boards.
The PCB Designer then applies a .CRF to selected group of symbols.
The Place Replicate algorithm generates common circuits if matches are found.
- Available on cursor for placement.
Placement Blocks are represented as a Group Object in the Allegro database.

As always, I look forward to hearing how you're using these new features and any recommendations you may have.

Normal 0 false false false EN-US X-NONE X-NONE

Jerry "GenPart" Grzenia

What's Good About Eye Masks in PCB SI? You'll Need SPB16.2 to See!

Jerry GenPart — Wed, 09 Sep 2009 17:00:00 GMT

Eye masks let you specify the acceptable parameters for what an eye should look like in order to extract clock transmissions and high-speed data to buffer models. The current method of creating and saving eye masks is tedious. SigWave has been enhanced to allow you to create eye masks that you can save in .sim files and view/edit when you display the waveform in Eye Diagram mode.

One current use model for creating eye masks is to recreate an eye mask by redrawing it in an open waveform file. This is very repetitive and prone to errors, and it defeats the purpose of saving a .sww file.

Another use model is to import a waveform into an existing .sww file which contains a mask. This requires saving the waveform, exiting the current file, opening the mask file and importing the saved waveforms. This is both tedious and counterintuitive and requires many steps.

To support easier use of new or existing eye masks, the following features have been added:

Ability to import existing eye masks into open waveform files
A new GUI to facilitate eye mask creation and modification

Using Eye Masks

Eye masks that you create in a simulation file reside at the root of the waveform library. These “root-level” eye masks are linked to the waveforms they are attached to.

You can attach the same root-level eye mask to multiple waveforms. If you delete linked eye masks from a waveform, the root-level eye mask remains; however, if you delete the root-level eye mask, all iterations of the linked eye masks will also be deleted.

You can attach only a single eye mask to a waveform; if you attempt to attach a second eye mask to a waveform, the second eye mask replaces the first.

Creating and/or Loading an Eye Mask

You create a new eye mask or load an existing one into SigWave by way of the Eye Mask toolbar icon , or by selecting a waveform and clicking the right mouse button to display the context pop-up menu.

When you launch the Load/Create Eye Mask dialog box from the toolbar icon, the mask you create attaches itself to the waveform library of your .sim file, not to an individual waveform. You can attach an eye mask residing in the waveform library to an individual waveform by highlighting a waveform and selecting the Attach Eye Mask option from the right-button popup menu. You can then choose an eye mask from a list of the eye masks in the .sim file.

Eye mask configurations can be either hexagonal or octagonal. You select the appropriate configuration from the Load/Create Eye Mask dialog box.

The Create button allows you to save the eye mask. When this button is selected you will be prompted to enter an eye mask name.

When you load an existing eye mask from the eye mask library, you can edit all the parameter settings except the hexagon/octagon eye mask type. The control fields in the dialog box let you specify the eye mask point values in the vertical (time) and horizontal (voltage) dimensions. You can also offset the eye mask by specifying time and voltage values. Time measurement units are selectable in picoseconds (ps), nanoseconds, (ns) and unit intervals (UI). Voltage measurement units are selectable in volts (v) and millivolts (mv).

Note: The parameter settings in the dialog box are dynamic; that is, if you move the eye mask with your cursor to another point in the waveform, the settings in the dialog box will have changed to reflect the new position when you reopen it.

Editing an Eye Mask

You can edit an existing eye mask through the use of the Edit Eye Mask toolbar icon or by right-clicking on a selected eye mask to display the context sensitive pop-up menu.

Either operation opens the Edit Eye Mask dialog box.

You can change the display of the eye mask through the right-button pop-up menu. The options on the pop-up menu let you:

Change the color of the eye mask outline
Display/hide the eye mask
Re-name the eye mask
Export the eye mask data to a .sim file or a DML file
Delete the eye mask

As always, I welcome your suggestions and experience in using this new SPB16.2 feature!

Jerry "GenPart" Grzenia

What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!

Jerry GenPart — Thu, 03 Sep 2009 13:00:00 GMT

This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. The PSpice engine can identify different sections of a split part and simulate them as a single component by intelligently combining the sections into one single part. At present, the Split Part support is available only in the AMS-DEHDL flow.

Details

The Split Part feature has been provided to allow users the ability to simulate large parts that cannot fit onto a single schematic sheet or the user wants to split the part for easier generation of the schematic (cosmetic preferences). Prior to the SPB16.2 release, the AMS Simulator (PSpice) netlister did not recognize the split part and would give warnings during the PSpice net listing process. The simulation results were also not as expected because of this. With this feature, the PSpice netlister will gather connectivity information for all instances of split parts and merge them into a
single instance.

AMS Simulator uses the two properties - SPLIT_INST and LOCATION - to identify split part sections and combine them. Alternatively, the SPLIT_INST_NAME property can be used to identify sections of a split part.

Considerations while working with split parts in AMS-DEHDL flow:

All instances of split parts should be instantiated on the same level of hierarchy.
SPLIT_INST and LOCATION properties must be present on the part.
A complete PSPICE_TEMPLATE property must be present on all the parts of the split part.
Incomplete instantiation of a split part is not supported.

As always, I welcome your feedaback and suggestions about how to use this new capability.

Jerry "GenPart" Grzenia

What's Good About Blogging? - The People: Readers, Posters, Cadence!

Jerry GenPart — Wed, 19 Aug 2009 12:34:00 GMT

I'm taking a break this week from the technical type posts to say THANK YOU to the people who make blogging a success.

Of course, Blogging and Blogs are only successful if they are read and people post their thoughts and questions to continue a discussion. The PCB Design Community members - customers, Cadence, and industry folks - have been a terrific team in posting both in the Blog and Forums. Truly, it is the readers and posters that make a Blog successful!

Thank you for your continued interest and please continue to write-in about topics you'd like to discuss: anything from design techniques, to new flow methodologies, to product suggestions and questions. It's great when we all learn from each other. We've already seen a few frequent posters (Evan and Charlie to name a few) that provide their keen technical expertise to discussions.

The Cadence team is instrumental in the continued success of our Blogs. There is a good amount of "behind the scenes" work that our Social Media team at Cadence performs on a daily basis. David Stokes keeps the "fire in the belly" of the Bloggers. He keeps us on track with interesting new subjects to blog about, upcoming events, and suggestions about blogging styles. David keeps our Blogging engine running smooth. Jim Price manages the entire Cadence corporate Blogging effort - from strategy, to infrastructure, to success measurements. This strong Cadence Social Media team of which David and Jim are a part, insures the success of the individual Bloggers.

A special thanks to Rik, Sue, Jeff, and Neha. While my focus area is Front-end PCB Design/FPGA-PCB co-design/Library and design data management (you can read more about each product area - PCB Design and IC Packaging and SiP Design), from time to time, I do get deep technical questions in areas I'm not familiar with in the PCB design flow. That's where Rik (Layout and routing), Sue (Signal and power integrity), Jeff (Allegro Package Designer), and Neha (AMS simulation) provide a wealth of knowledge. As a customer, you've no doubt worked with Rik/Sue/Jeff/Neha.

I recently received the Q1 Blogger of the Quarter award - presented by Jim Price during a quarterly Cadence marketing meeting.

I consider this achievement a success by the entire team - the community readers/posters (that's YOU), and the Cadence team. Our PCB Community Blog is one of the highest readership Blogs in the Cadence community - again a testament to your involvement. It was an unexpected honor to receive this award. I'm now in the company of the previous award winners - Robert Dwyer and Joseph Hupcey III who've been terrific examples of innovative blogging - videos, web chats, man-on-the-street, etc.

As always, I look forward to your continued reading, suggesting, and discussion on the Blogs!

Jerry "GenPart" Grzenia

What's Good About DEHDL Usability Improvements? The Secret's in the SPB16.2 Release!

Jerry GenPart — Wed, 12 Aug 2009 20:00:00 GMT

The Design Entry HDL (DEHDL) usability improvements are many and significant in the SPB16.2 release!

The DEHDL product moves even closer to other Windows based applications, such as Capture CIS, Adobe Reader and Microsoft Office applications, in terms of the general usability standards. These changes provide support for common Windows commands and operations making Design Entry HDL more user-friendly and easy to use.

The usability changes are available under the Windows mode, which is a new UI mode introduced in Design Entry HDL.

I'll cover some of the more frequently used capabilities below.

Windows Mode

The usability changes are available under the Windows mode, which is a new UI mode introduced in Design Entry HDL. To use the available changes, you need to enable the Windows mode.

Follow the steps below to enable the Windows mode:

1. Choose Tools> Options.

2. In the General page of the Design Entry HDL dialog box, select the Enable Windows Mode checkbox in the Preferences section.

3. Click OK.

Reorganized Menus

In the SPB16.2 release of DEHDL, the most prominent change you will notice is the reorganization of menus.

The menus are organized in such a way that they now fit into 12 menus in the Windows mode as compared to the 14 menus in the normal mode. You'll notice that some of the main menu names have changed, some menu commands are accessible from the same locations with little or no change in the sequence, while some others have either moved to a new menu or are now nested inside a new or existing submenu for increased granularity.

Some of the sub-menu items have been moved while some others have been reorganized/added to maintain a synchrony with Capture CIS and other windows based applications.

Note: If you are unable to see the reorganized menu bar select Tools> Customize> Menus and click on the 'Reset' button.

Design Entry HDL Options Dialog Box

The Design Entry HDL Options dialog box has been changed to maintain a similar look to the Preferences dialog box of Adobe Acrobat Reader. Instead of the tabbed pages, the page names appear in a neatly organized tree structure on the left panel. Rest of the functionality remains the same.

Bounding Box on Components

A bounding box with anchor points or handles around a component appears when you click a component on a schematic in the Windows mode. This acts as a selection indicator. The mouse pointer changes to a move pointer when you hover the mouse over the handles. This indicates that you can move the component around. When you move a component, all the wires connected to it also move with it.

You can also rotate a component by clicking the mouse pointer on the handles at the edges. As you move the mouse pointer to one of the four edges of a bounding box, it changes to a rotate pointer. You can click at this point and the component is rotated in the direction of the rotation arrow.

Support for Keyboard Operations

Another important change done to bring Design Entry HDL closer to a standard Windows application is the support for keyboard functions, such as CTRL+C for copy and CTRL+V for paste. You can now copy objects from the Windows clipboard on to a schematic using the keyboard shortcuts. The other keyboard operations supported are listed in the following table:

Key Combination	Operation
Ctrl + C	Copy
Ctrl + V	Paste
Ctrl + A	Select All
Ctrl + X	Cut
Del	Delete
Home	Go to the first sheet within a module
End	Go to the last sheet within a module
Shift + Up Arrow	Move component up to the next grid point
Shift + Down Arrow	Move component down to the next grid point
Shift + Left Arrow	Move component left to the next grid point
Shift + Right Arrow	Move component right to the next grid point
Arrow Keys	Moves objects in small increments
Page Up	Moves one page up
Page Down	Moves one page down

New-Look Attributes form rechristened as the Properties Window

The Attributes form appears as the Properties window in the Windows mode. It is a dockable window. As soon as you select an object on the schematic, the Properties window is populated with the properties information of the object, be it a component or a net. The window has icons to add, delete, and save properties and to load and save a property (.attr) file. The dockable attributes window saves time as you do not need to redisplay the form when you reenter attributes form.

Showing Unconnected Pins on Components

Design Entry HDL now provides a method to quickly identify all the components which have unconnected pins. This option is made available through the following console command:

Set SHOW_UNCONNECTED_PIN ON

Notice that all the unconnected pins are marked with pink dots. Also, you can see the unconnected pins by selecting Component> Unconnected Pins from the main menu.

Changes in Global Navigate Window

The Global Navigate window now consists of three icons: Next, Previous, and Zoom by points. If the Zoom by points button is depressed, it zooms to selected region in the schematic as you navigate back and forth across the nets using the Previous and Next icons.

As always, I welcome your feedback and discussion on how you're using these new features and any suggestions you may have on how to improve the DEHDL interface.

Jerry "GenPart" Grzenia

Power Issues? Manage Your IR Drop The "Advanced" Way

Maxwell86 — Tue, 11 Aug 2009 13:00:00 GMT

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions. In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature stability. As Chris mentions, the challenge of managing power paths is complicated by the need to carve up power planes into swiss cheese like structres around high pin count BGA devices. We're pleased to hear of the successes Chris and his team have found navigating these challenges using Allegro PCB SI, and specifcally using the IR Drop feature available in all 16.x releases of the tool.

You can find this whitepaper as well as many other resources for Signal / Power integrity in our Resource Library (click here).

Please let us know if you've had similar experiences.

Brad Griffin

What's Good About Cavity Support in APD? You'll see for yourself using the SPB16.2 Release!

Jerry GenPart — Wed, 29 Jul 2009 18:46:00 GMT

No - we're not talking teeth, candy, and cavities here ...

Many customers have been asking us to support cavities inside of the Cadence IC Packaging tools for a number of years now. These are most frequently requests from companies trying to design leadframe packages (a technology that Cadence does not support within either the APD or SiP toolsets), though some have come from customers wanting to embed a die within a regular BGA package substrate as well.

To implement a complete solution for cavity support would likely require significant engineering resources across multiple releases. There are many challenges to be faced and many commands to be updated. From making manual and auto routing understanding cavities to the complexities of modeling the cavity in signal integrity analysis and any fill material inside the cavity, the challenge can be daunting.

The aim of this feature is to provide a small first step in introducing cavity support, by allowing users to "push" a die stack into the surface of the substrate and down a specified distance or number of layers. For leadframe designs, where there is no package routing, this allows the user to get accurate analysis and 3D views of the design.

It is the intention to use this to open discussions for what is additionally needed to complete cavity support, but doing so in a manner that will allow for the logical extension into the complete solution without unnecessary changes to the use model or underlying data model inside the database.

I'll limit the details to defining the user interface and use model for cavity depth specification for die stacks. I'll not attempt to deal with problems such as preventing the auto-router or manual routing from trespassing inside the boundaries of the cavity on a given layer.

When setting up your die stacks after adding die components, spacers, and interposers to your design, you should ensure that the offset of the stack from the top/bottom of the substrate is accurately set. This will maximize the up-front accuracy of your database and any measurements, such as 3D bond wire lengths.

Use Model

In order to mount a die stack within a cavity on the substrate, the user must launch the die stack editor command. On the main die stacks tab of the die stack editor form, select the appropriate die stack from the list. Then, select the layer atop which the stack should sit inside the substrate.

To view the impact of these changes on the design, launch the 3D Viewer tool. This will update to show the die sitting below the surface of the package substrate layers. Note that the edges of the cavity itself are not drawn in the 3D Viewer, as this tool only draws positive conductor objects, not negative region boundaries.

Graphical User Interface

The user interface for the die stack editor tool in SiP Layout and Architect has been modified to add new fields for specification of the depth of the stack relative to the surface it exists on. The new fields are defined below, and all exist on the "Die Stacks" tab of the form:

Sits on Layer: The user may select the layer on top of which the bottom of the die stack sits. For a surface-mounted stack, this is the outermost conductor layer of the design. All layers are listed in the pull-down, ordered relative to the stack’s substrate surface. Default value when changing to this method is the exposed substrate surface layer name.

If you have an applicable .sip file, we'll walk through an example. Open the design in 3D.

Notice that the bottom DIE is on the same layer as the power rings, the Surface Layer.

Open the Diestack Editor

You will NOT see the feature.

Close the Diestack Editor

In the command line type: set diestack_cavity_beta

Then open the Diestack editor once again and the feature will now be active.

Select Inner_1 for the Die to "Sit On".

Open the design once more in 3D.

The bottom DIE is now shown BELOW the surface layer.

Pan around to view this.

As always, I welcome your discussions on this new feature!

Jerry "GenPart" Grzenia

What's Good About Allegro's Placement Application Mode? - Look to SPB16.2 and See!

Jerry GenPart — Wed, 22 Jul 2009 15:57:00 GMT

In prior releases, Allegro PCB Editor does not provide the user the ability to place or make placement changes easily. New functionality to provide greater usability for component placement, alignment, replication of circuitry would greatly impact the time to get a design to fabrication.

The SPB16.2 Allegro PCB Editor introduces the 4th application mode; General, Etch Edit, IFP and now Placement available to Allegro PCB Editor products. Allegro will continue to support the legacy command driven editing model commonly referred to as ‘verb-noun’ however application modes, based on context sensitive editing (noun-verb) offer a more intuitive approach to common design tasks such as etch edit, placement and querying.

Placement Application Mode

"Placement Application Mode" is a tuned, high performance editing environment designed to increase efficiency during component placement sessions. Find filter settings are limited to those elements typically involved in placement such as symbols, pins and rat tees. This reduces unnecessary cycling of unwanted elements that do not contribute towards placement activity. In this mode, it is still possible to perform non-placement functions like add connect or slide however context sensitive and auto executed commands are biased towards component placement functions.

The Placement Application Mode can be enabled a number of ways:

Setup — Application Mode — Placement Edit
RMB click in Canvas area followed by Application Mode — Placement Edit
ToolBar Icon

Placement GUI

The list of unplaced components is conveniently located in the Options Panel while in Placement Application Mode. The form is an abbreviated version of the main Place Manual User Interface and supports:

Selection of one or more components from the tree view form.
Refresh of form as components are placed.
"Place by refdes" function to place specific components by reference designator names; wildcards (* and ?) are supported.
Mirror" option automatically changes component selection set from Top to Bottom side."More Options", when selected launches the main Place Manual form providing access to filtering functions.

Context Sensitive Editing

The RMB is context sensitive where commands and parameter options associated with component placement are available based on the selection set of elements. A context sensitive environment is designed to reduce the extra steps involved in traveling to the toolbar, menus or option panel while maintaining focus on the area of work in the canvas. Additionally, certain commands can be automatically enabled by a single pick or drag on the element.

An example of context sensitive menus is shown in the figures below. The menus are a result of either hovering over or selecting with the LMB a symbol or pin followed by a RMB pick.

As with other application modes, the TAB key can be used to cycle through parent elements. For example, when hovering over a Pin, use the Tab key to change the selection state to Symbol (Symbol is the Parent of a pin).
In General Edit Mode, using the TAB key while hovering over a Pin cycles to both Symbol and Net.

Placement Application Mode - Automatic Execution of Commands

Certain commands associated with component placement can be automatically executed using the LMB pick or drag functions. Simply click on a symbol, group, text or rat tee to Move it. Spin or Copy commands require the combination of either the Shift or Control key while in a drag operation with the LMB.

Element Type	Drag	Shift-Drag	Control-Drag	Single Click

Group	Move	Spin	Copy	Move
Symbol	Move	Spin	Copy	Place Manual
Text	Move	Spin	Copy	Move
Rat T	Move			Move

Align Components

The Align Components command is available while in Placement Application mode and only operates on a pre-selected group of symbols.

The use model for aligning components is designed to be straight forward and involves:

Set Application Mode to Placement Edit
Select with the LMB all components that are to be aligned. The selection set is limited to the same side of board.
Hover over the reference component which should be part of the original selection set and pick Align Components from the RMB popup menu.
Components in the selection set will be aligned to the reference component by body center.

There are no options available with this command.

Row versus column alignment will be decided by checking to see any movement of the components into a row or a column will cause the component placebounds to overlap. If an overlap in one direction occurs, then the opposite direction will be chosen. If this rectangle is "close" to a square, the user will be prompted for row or column alignment. If there is etch routed to the pins of components that are being moved, the first cline segment that is not marked as fanout will be deleted.

Placement Replication

A new suite of commands is introduced in SPB16.2 designed to replicate circuits within the PCB Editor tool. Circuit replication in the Cadence flow has traditionally been accomplished with the Design Re-Use Module application which requires both Front and Back End participation and is limited to Cadence supported schematic systems.

A less restrictive, intuitive use model is desired that limits the dependency of front end requirements to just the traditional netlist. The placement of a "seed" circuit followed by a selection of randomly placed components generates the replicated circuits based on common device types, symbols and connectivity. Circuits that often get replicated are memory modules, IO channels and the capacitor scheme associated with BGAs or other active components.

The steps involved in placement replication are as follows:

Set Application Mode to Placement Edit; Place Replication is only available in this mode.
Layout initial (seed) circuit.
Create .CRF (Circuit Replicate File).
- With the LMB, select all components associated with the seed circuit then use RMB — Place Replicate Create command.
- Enter a name for the replication file. There is an option to save the file to disk for use on other boards
Apply .CRF (Circuit Replicate File)
- Window select components of the targeted replication groups. Selection can include components that do not factor into the replicated circuits however limiting the selection to relevant members reduces processing time.
- Once selected, use RMB — Place Replicate Apply command then select the .CRF file in the RMB menu or browse to the file on disk.
- If a solution is found, the resultant circuits appear on your cursor, one instance at a time.
- Each circuit is stored in the database as a group object. The naming convention used is _PR_CRF#. In the above example, the group names would be _PR_DIMM_1, _PR_DIMM_2, etc.
- Routes are not captured as part of the .CRF file. Use the copy command to copy routes from the seed circuit to each replicated one.
- Currently if changes are made, for example the need to add components to each circuit, a new .CRF must be generated and re-applied. This will result in the re-placing of each circuit.

Please reply with how useful you find this new feature.

Jerry "GenPart" Grzenia

What's Good About ABIML in PCB SI? It's in SPB16.2!

Jerry GenPart — Wed, 15 Jul 2009 19:01:00 GMT

First - ABIML is an acronym for Algorithm-Based Interconnect Model Library.

Currently, the model in the interconnect model library (IML) can only be reused by matching model name, model type, or exact "TraceGeometryData", which includes key information such as shield layer, dielectric layer, trace layer and the exact trace physical geometry. If any of the model geometry data is mismatched, the field solver is called to create a new model. In addition, for dynamic analysis, the frequency spectrum must also be matched. This "exact" model matching procedure provides designers the most accurate electrical parameters as our tool can and will still be active in the future.

Interconnect modeling, which relies heavily on electromagnetic computation and optimization, is essential and critical in high-speed electronic circuit design. The more complex interconnect structures require the use of the new EMS2D full wave field solver, where computation is extremely CPU intensive and not practical in interactive design.

The new methodology is to shift the time needed in model generation by building the algorithm-based models off-line through rigorous full-wave EM simulation. These verified models are then reused to generate new required models efficiently without calling the field solver again.

In the algorithm-based interconnect model library (ABIML), interconnect models are all parameterized and validated for their application range with pre-specified accuracy control. When a specific model is requested from this library, the library will try to provide the model by checking if the needed model is within the algorithm range of the existing same kind of models in the library. Otherwise this library calls the field solver to acquire the model.

Algorithm-based interconnect models are designed to greatly enhance simulation times when interconnect models that match simulation criteria cannot be found in existing traditional models. Algorithmic model generation lets you create accurate interconnect models off-line that exactly match not only shield, dielectric, trace and physical geometry layer information but also entire frequency spectrums. These models are then integrated into libraries for reuse in multiple simulations. There is currently no capability for users to create their own ABIML models.

Algorithm-based modeling is optional. You can enable/disable it from the InterconnectModels tab of the Analysis Preferences dialog box in Allegro PCB SI or the Simulation Parameters tab in SigXplorer.

If you turn off algorithm modeling, the PCB SI tools will not search for algorithm-based models. Instead, it will directly engage the selected field solver to create the required model. This process is illustrated in the flow chart below.

I'm curious how many have been using this feature in the SPB16.2 release?

The ABIML libraries are stored in <install_dir>/share/pcb/signal. The syntax of the model contains two sections:

Model information such as parameter range, interpolation type, and sweep step type
Multiple RLGC data used in model generation

The following is a simple example of the file format.

[Model] abiml_test
[Model Info]
  [Field_Solver_Used] ems2d
  [ABIML_Version] 1.0
  [Model_Type] singletrace
  [Num_of_Port] 2
  [Num_of_DielectricLayer] 1
  [Num_of_ShieldLayer] 1

  [Parameter Info]
    [LayerStack]
      [Layer] 1
        * min max step step_type interp_type ID
        [Thickness] 1.0 1.0
        [Constant] 1.0 1.0
        [Losstangent] 0.0 0.0
        [IsShield] YES

      [Layer] 2
        * min max step step_type interp_type ID
        [Thickness] 1.0 2.0 5 linear linear 1
        [Constant] 4.4 4.6 3 log 2_order_poly 2
        [Losstangent] 0.0 0.0
        [IsShield] NO
    [End LayerStack]
    [CrossSection]
      [conductor] 1
        * min max step step_type interp_type ID
        [Thickness] 1.0 1.5 5 linear linear 3
        [Width] 1.0 10.0 20 linear 2_order_poly 4
        [Losstangent] 0.0 0.0
        [end CrossSection]
[End Model Info]
[Model Data]
    [Data] 1
      [R] 1.459500e+01
      [L] 6.088700e-07
      [G] 0.000000e+00
      [C] 5.162900e-11
      [Data Condition]
      *       ID          value
              1            1.0
              2            4.4
              3            1.0
              4            1.0
      .....
    [Data] 4725
      [R] 3.630000e+00
      [L] 4.567500e-07
      [G] 0.000000e+00
      [C] 7.440100e-11
      [Data Condition]
      *       ID          value
              1            2.0
              2            4.6
              3            1.5
              4           10.0
[End Model Data]
[End Model]

As always, I welcome your feedback!

Jerry "GenPart" Grzenia

What's Good About USB 3.0? You Tell Me

Jerry GenPart — Wed, 01 Jul 2009 16:06:00 GMT

I read a recent article (June 11, 2009) in EDN magazine - "USB 3.0: A simple Idea Full of Challenges" by Ron Wilson.

In a nutshell, Ron says "Super-speed USB (Universal Serial Bus) 3.0 sounds like a great idea. Just start with widely used, fast, and bulletproof USB 2.0 and graft in the PHY (physical-layer) interface from another common and reliable standard, PCIe (peripheral-component-interconnect express) Generation 2. Put two differential pairs into the USB connector to carry the high-speed serial signals from the Generation 2 PHY, and you have a rugged, flexible, inexpensive interface that can operate at 5 Gbps over consumer-priced cables and connectors with interfaces cheap enough to drop into a flash drive."

"The idea promises to unleash new ways of using PCs with mobile devices and with storage. With application-level throughput approaching 400 Mbytes/sec and the ability to simply plug anything from a flash drive to 3m of USB cable into a host, usrs could link PCs and netbooks, quickly dump the contents of huge flash drives, or easily transfer HD (high-definition) video between devices. They could even create their own external storage networks (Figure 1). This promise of speed and flexibility, however, carries the seeds of a difficult challenge for chip, board, and system designers."

Some of the challenges encountered are:

PCB material used and real estate needed on the PCB for connector pairs and routes.
With speeds of 5 Gbps, cabling certification becomes an important consideration (and increases the manufacturing costs).
The PHY (physical-layer) is quite variable due to the types of devices (e.g. thumb drive, cable, etc.) that are plugged into the port.
The interface must be low enough in power to allow cable-powered operation. "The USB 3.0 standard will allow a device to draw as much as 900 mA during operation, but it must draw no more than 150 mA before configuration. That limitation itself demands a well-studied power-management strategy at the chip level."

As for the timeframe to market "USB 3.0 will start out expensive, but, by 2011, it will probably be standard in netbook computers and handheld consumer products, such as cameras, media players, and flash drives."

"One of the greatest differences between PCIe Gen 2 PHYs and USB 3.0 PHYs will be in the receiver-equalization circuit. Many designers expect the quality of this block to be a major differentiator in the market, for PHY-IP (intellectual-property), chips, and the systems that use them. The equalizer must be both powerful in its action and adaptive. Otherwise, a PHY would be unable to handle the range of channel conditions that USB can throw at it. As an adaptive equalizer, this circuit will require a training sequence to lock onto. Yet, the equalizer must be low in power and compact to meet the needs of consumer-product applications. Those challenges are formidable."

"If a design team has really understood PCIe Gen 2, then they can adapt about 90% of their work to USB 3.0, says Scott Kim, manager of business development at Texas Instruments. Yes, the equalizer will need beefing up, but much of the circuitry will remain the same. For example, getting 5-Gbps performance from the PHY requires a careful trade-off between deep pipelining to meet throughput requirements and limited latency to meet bus timing."

I'm curious about any experience you have with designing around the USB 3.0 protocol and what Cadence products/flows you're using to get past the design challenges.

Jerry "GenPart" Grzenia