Cadence PCB Design Blogs

What's Good About USB 3.0? You Tell Me

Jerry GenPart — Wed, 01 Jul 2009 16:06:00 GMT

I read a recent article (June 11, 2009) in EDN magazine - "USB 3.0: A simple Idea Full of Challenges" by Ron Wilson.

In a nutshell, Ron says "Super-speed USB (Universal Serial Bus) 3.0 sounds like a great idea. Just start with widely used, fast, and bulletproof USB 2.0 and graft in the PHY (physical-layer) interface from another common and reliable standard, PCIe (peripheral-component-interconnect express) Generation 2. Put two differential pairs into the USB connector to carry the high-speed serial signals from the Generation 2 PHY, and you have a rugged, flexible, inexpensive interface that can operate at 5 Gbps over consumer-priced cables and connectors with interfaces cheap enough to drop into a flash drive."

"The idea promises to unleash new ways of using PCs with mobile devices and with storage. With application-level throughput approaching 400 Mbytes/sec and the ability to simply plug anything from a flash drive to 3m of USB cable into a host, usrs could link PCs and netbooks, quickly dump the contents of huge flash drives, or easily transfer HD (high-definition) video between devices. They could even create their own external storage networks (Figure 1). This promise of speed and flexibility, however, carries the seeds of a difficult challenge for chip, board, and system designers."

Some of the challenges encountered are:

PCB material used and real estate needed on the PCB for connector pairs and routes.
With speeds of 5 Gbps, cabling certification becomes an important consideration (and increases the manufacturing costs).
The PHY (physical-layer) is quite variable due to the types of devices (e.g. thumb drive, cable, etc.) that are plugged into the port.
The interface must be low enough in power to allow cable-powered operation. "The USB 3.0 standard will allow a device to draw as much as 900 mA during operation, but it must draw no more than 150 mA before configuration. That limitation itself demands a well-studied power-management strategy at the chip level."

As for the timeframe to market "USB 3.0 will start out expensive, but, by 2011, it will probably be standard in netbook computers and handheld consumer products, such as cameras, media players, and flash drives."

"One of the greatest differences between PCIe Gen 2 PHYs and USB 3.0 PHYs will be in the receiver-equalization circuit. Many designers expect the quality of this block to be a major differentiator in the market, for PHY-IP (intellectual-property), chips, and the systems that use them. The equalizer must be both powerful in its action and adaptive. Otherwise, a PHY would be unable to handle the range of channel conditions that USB can throw at it. As an adaptive equalizer, this circuit will require a training sequence to lock onto. Yet, the equalizer must be low in power and compact to meet the needs of consumer-product applications. Those challenges are formidable."

"If a design team has really understood PCIe Gen 2, then they can adapt about 90% of their work to USB 3.0, says Scott Kim, manager of business development at Texas Instruments. Yes, the equalizer will need beefing up, but much of the circuitry will remain the same. For example, getting 5-Gbps performance from the PHY requires a careful trade-off between deep pipelining to meet throughput requirements and limited latency to meet bus timing."

I'm curious about any experience you have with designing around the USB 3.0 protocol and what Cadence products/flows you're using to get past the design challenges.

Jerry "GenPart" Grzenia

What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers

Jerry GenPart — Wed, 24 Jun 2009 13:00:00 GMT

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting the new FPGA System Planner (FSP) product from the Cadence Silicon Package Board (SPB) division at the recent CDNLive! EMEA event.

You can watch Hemant from the event:

If your the video fails to launch please click here.

Available in two forms - Allegro FPGA System Planner and OrCAD FPGA System Planner - this new technology works in the respective Allegro/OrCAD front-to-back flows.

Some of the differentiators of the new FPGA System Planner compared to what's available on the market today are:

FPGA System Planner (FSP) automates the pin assignments. For large pin count FPGAs (300, 500, 1000 pins or more), this is a very laborious process which is greatly streamlined with FSP.
FPGA System Planner considers the PCB routing architecture when assigning and thus optimizing the pin selections.
High level (system level) component connectivity is considered for multiple FPGAs and other components when synthesizing the optimal pin assignments.

One of the customers using this technology had 4 FPGAs on the PCB and were able to reduce their design cycle by 4-6 weeks.

Another customer used FPGAs to do ASIC prototyping. They constructed a design containing 48 FPGAs on 5 separate PCBs using FSP. This took only HALF the time compared to a design with 19 FPGAs on a single PCB with a manual approach - which amounts to about an 80% - 90% design cycle reduction.

Even with just a single FPGA on a single PCB, working with FSP in the OrCAD front-to-back flow, customers can realize benefits due to eliminating the manual approaches (wrong pins on the clock, wrong voltage pins assigned, etc.) which lead to errors caught in the lab after the PCB is prototyped.

As always, I welcome your comments and suggestions about the new FPGA System Planner product.

Jerry "GenPart" Grzenia

What's Good About the new FPGA System Planner? - Ask Hemant Shah!

Jerry GenPart — Wed, 17 Jun 2009 20:36:00 GMT

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the FSP product in his Blog post - Innovative Approach to Optimized FPGA Pin Assignment

For an interesting interview about the new FPGA System Planner (FSP) product, please read the details here.

Here are some "take-aways" from Hemant's interview that I found noteworthy:

Our customers are leveraging the power, design flexibility, and cost savings of using FPGAs in designs in an ever increasing volume over the past few years. At the same time, to provide the increased complexity of designs, the pin count on FPGA devices is increasing - thus adding new design challenges for both the Electrical, and PCB Designers.
Pin assignments of the FPGA (to determine functionality) is usually a manual process and for large pin-count devices, this is cumbersome. Also, determining the optimal pin assignments to provide the best integration of the part on the PCB involves quite a bit of back-and-forth changes between the PCB Designer and FPGA Designer (and often without an automated method).
Some of the unique capabilities of FSP -
- A relative placement of the FPGAs on the board can be controlled by the FPGA/Electrical Designer before sending the netlist to the PCB Designer. By optimizing this placement in advance, the routing solution is optimized.
- Pin assignments are automated using assignment rules during synthesis.
- The FPGA Designer can do so much more pre-board planning, placement, and synthesis in advance of the schematic netlist driving the PCB. To quote Hemant in a nutshell - "The FPGA designer can do the placement, do the pin assignment, and take the results of the automated pin assignment to the FPGA vendor tools to make sure there are no issues with internal timing of the FPGAs. Once the FPGA designer is satisfied with the pin assignment and the internal timing of the device, that pin assignment can be sent over to the schematic process by exporting synthesized schematics that have the FPGA symbols and the connectivity that's associated with it. The hardware designer can then take that FPGA subsystem, integrate it with the rest of the PCB system, and pass it on to the PCB layout system."
- Because of the pin assignment rules built into the FPGA part libraries, the designers can catch incorrect pin assignments (wrong power voltages assigned on a multi-voltage design) using FSP. This is typically a manual process to "flag" these situations, but not with FSP.

As always, I welcome your comments and suggestions about the new FPGA System Planner product.

Jerry "GenPart" Grzenia

Innovative Approach to Optimized FPGA Pin Assignment

hemant — Tue, 19 May 2009 01:30:00 GMT

Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design.

The FPGA-PCB co-design solution includes proven technology from Taray Inc for optimized, correct-by-construction FPGA I/O pin assignment synthesis that takes into account the placement and routing of the FPGAs.

What is unique about this technology is:

It provides automated FPGA I/O pin assignment that is accurate per FPGA vendors' pin assignment guidelines
It enables architecural exploration to do cost/performance trade-offs that is not practical with manual pin assignment methods.

To learn more about this exciting new approach, read more:

Cadence Introduces Innovative FPGA-PCB Co-Design Solution - Cadence Article
Allegro FPGA System Planner - Product information / Datasheet
Cadence OrCaD FPGA System Planner - Product information / Datasheet
Successfully designing FPGA-Based Systems - white paper
Cadence Introduces Innovative FPGA-PCB Co-Design Solutions -press release

I would love to hear your comments, feedback on this new introduction from Cadence.

Hemant Shah

What's Good About New Smoke Analysis Devices? Check out the SPB16.2 Release and See!

Jerry GenPart — Wed, 13 May 2009 17:58:00 GMT

The AMS Simulator Smoke Analysis has been enhanced in the SPB16.2 release to support a few new devices. Also, the Model Editor now supports the addition of smoke parameters to devices like LEDs, Zener Diodes, Varistors, etc.

The following new devices are now supported by Smoke Analysis:

Electrolytic Capacitor
Inductor for DC Current
VSWITCH
Transformer (Single and Double Winding)

In addition, smoke parameters can be added to the following new devices in the Model Editor:

LED
Zener Diode
Varistor
Diode Bridge
GaAs MESFET
Thyristor
Voltage - Controlled Switch
4 Pin Optocoupler
NPN - PNP
NMOS - PMOS
Dual BJT
Dual MOS
Transformer

Smoke Analysis parameter details:

Capacitor

New model params ESR, RTH, and POWER have been added to CAP devices. This corresponds to smoke checking for power loss and temperature rise of capacitors.

Smoke Test Name        Symbol param Name        Symbol parameter Value
“PDML”                              “ESR” & “POWER”           "ESR" & "CPMAX"
“TJL”                                  “RTH”                                     "RTH"
"CV"                                "VOLTAGE"                          “CMAX”
"CI"                                   "CURRENT"                          “CIMAX”
"SLP"                                "SLOPE"                              “CSMAX”
"TBRK"                             "KNEE"                               “CBMAX”
"TMAX"                             "MAX_TEMP"                      “CTMAX”

In addition two more params CVN (Max -ve voltage) & CVP (Max +ve voltage) have been added to the electrolytic capacitor analog\C_elect.

Resistor

New model param RV (maximum voltage) has been added to RES devices. This is a smoke check for the voltage rating of resistors.

Inductor

New model param CURRENT (maximum DC current) has been added to IND devices. This is a smoke check for saturation of inductors due to DC current.

Voltage Switch

New model params CURRENT, VOLTAGE, and POWER have been added to the Voltage Switch. This corresponds to smoke checking for max current through contact, max voltage difference between nodes NODE_SW_1 & NODE_SW_2, and power deration of the switch respectively.

Smoke Test Name        Symbol param Name        Symbol parameter Value

"SV"                                    "VOLTAGE"                                    “?”
"SI"                                      "CURRENT"                             “?”
"PDSW"                               "POWER"                                    "?"

Symbol parameter values need to be added on symbol in schematic

Transformer

New model params have been added to transformer (single winding):

Smoke Test Name        Symbol param Name        Symbol parameter Value

"Primary_Current"               "P_CURRENT"                   “?”
"Secondary_Current"          "S_CURRENT"                    “?”
"Isolation_Voltage"             "ISOLATION"                      “?”

Symbol parameter values need to be added on symbol in schematic

Addition of Smoke Parameters in Model Editor:

In order to add smoke parameters to a device from the Model Editor, go to Model> Add Smoke and chose the appropriate device type.

As always, I welcome your feedback!

Jerry "GenPart" Grzenia

What's Good About Relational Table Support in Capture-CIS? You'll Need SPB16.2 to See!

Jerry GenPart — Wed, 29 Apr 2009 16:32:00 GMT

With SPB16.2 release, Capture-CIS allows you to create and use relational tables in the parts database. These tables have a one-to-many relationship with part information (primary) tables. For example, the database may contain a Vendor table with multiple vendor / manufacture part numbers for one company part number in your Resistor table. This structure allows you to query for data across the primary and relational tables.

What is Relational table support and how it works

Short for relational database management system, RDBMS and pronounced as separate letters, is a type of database management system (DBMS) that stores data in the form of related tables. Relational tables are powerful because they require few assumptions about how data is related or how it will be extracted from the database. As a result, the same database can be viewed in many different ways. An important feature of relational systems is that a single database can be spread across several tables.

How it works in Capture-CIS

Capture-CIS allows you to create and use relational tables. You can define the primary - foreign key relationship between the parts (primary) tables and related tables in the database. In the Relational Database tab, you define the relationship between the part (primary) and relational tables in the database.

Relationship through Part Number between Capacitor table and Vendor table

Note: Capture CIS supports a one-to-many database relationship between the part information tables and related tables.

The Set Relational Data grid contains the following fields:

Primary Table Name: Use this list to define the part (primary) tables in your relational database. This is the only read-only field in the grid.
Primary Key: Use this list to define the primary key that you want to use to form the relationship with the relational table.
Relational Table: Use this list to specify a relational table that has a primary - foreign key relationship with the selected primary table.
View Name: Use this text field to define a friendly name for the view that will display when a designer selects the primary table to create a relational query. In this case I have defined it as CapVen.

To define the relational data:

First, ensure you are in the Relational Database tab of the Configure Database dialog. Go to a row that contains a primary table.

Select the Primary Key field drop down list. This list displays all the fields in the primary key table. Note: If the specified ODBC driver provides support for retrieving the primary key, this will be displayed by default in this field for the corresponding primary table.
Select the field to use in your relation.
Select the Relational Table field drop-down list. This displays the list of tables in the database that have a primary - foreign key relationship with the corresponding primary table.
Select the table to form the relationship with the primary table.
In the View Name field, define a friendly name for the view that will display when a user selects the primary table to create a relational query. Repeat above steps for every table in Primary table list that is to be defined as a primary table in CIS and you want to create a relationship with a relational table.
Click OK.

How will the you see the relationship in CIS?

In Capture-CIS the relation table can be viewed using the View Name, for example : CapVen
The Capacitor table and Vendor table can be viewed using Part Number.

As always, I look forward to your feedback on how you employ this new capability in Capture-CIS.

Jerry "GenPart" Grzenia

What's Good About Social Networking? Boomer Adoption up, Gen Y Flat

Jerry GenPart — Wed, 22 Apr 2009 21:23:00 GMT

I decided to switch gears a bit and write about an interesting article I read in Electronic Engineering Times (April 6, 2009) - "Social networking: Boomer adoption Up, Gen Y Flat" by Junko Yoshida.

What I found fascinating is that us "old time" Baby Boomers are increasing the volume of blogs we read, social networking, and podcasts we listen to by 67%. Our counterpart Gen Y'ers (while having a larger percentage of participation) have been flat during the same time period. The management consulting firm, Accenture, conducted the poll of 3000 consumers. A senior executive with Accenture's consumer technology practice, Kumu Puri, stated - "Baby boomers are more hip with technologies than we usually give them credit for". The pickup in boomer's adoption of the Internet-enabled applications and services over the past year might indicate a brewing social imperative.

The number of baby boomers connecting on social networking sites jumped by 59% over last year's tally. The article goes on to say that the Gen Y'ers are turning more toward "on the go" services (e.g. mobile phone access) compared to the internet.

So, while you're "hip" and plugged into Blogs (since you're reading this), I'm curious how many of your fellow designers where you work have jumped on the Blog-wagon?

I look forward to your input.

Jerry "GenPart" Grzenia

What's Good About TCL, P&S, STUFF in ASA? The Secret's in the SPB16.2 Release!

Jerry GenPart — Wed, 15 Apr 2009 15:17:00 GMT

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent anything other than ... more stuff).

We're back to exploring the new SPB16.2 features in Allegro System Architect (ASA)/System Connectivity Manager (SCM).

TCL
For those who may not know - "Tcl (Tool Command Language) is a very powerful but easy to learn dynamic programming language, suitable for a very wide range of uses, including web and desktop applications, networking, administration, testing and many more. Open source and business-friendly, Tcl is a mature yet evolving language that is truly cross platform, easily deployed and highly extensible." The source for all things TCL - "Tcl Developer Xchange". A good site that I've used to obtain TCL and Perl development tools is ActiveTcl. You can review ASA TCL commands from the System Connectivity Manager TCL Commands Reference located at /doc/comm/comm.pdf.

While TCL capabilities within ASA have been available for the past couple years, the SPB16.2 release has been enhanced to support the SCM user interface commands.

Designers and corporate rules require guidelines or methodology for most of the design content. These guidelines or methodology could contain naming conventions for the power and ground signals used in the design or the libraries which need to be used. To perform these repetitive tasks and minimize the manual effort required, designers and CAD groups can create TCL scripts to automate the design process.

You can start the TCL shell from SCM View menu - Open TCL Shell.

Beginning with the SPB16.01 release, all tasks performed in one session of SCM get recorded in the projectTCL.tcl file. This file captures the commands specified in the tcl shell, as well as the actions performed using the SCM user interface. Any messages displayed by SCM during the design process are also captured in the projectTCL.tcl file. This file is saved in the temp directory, under the project directory.

Physical and Spacing Constraints
Now in the SPB16.2 release, you can use Constraint Manager connected to the System Connectivity Manager to create, view, edit, and assign physical and spacing constraints to groups of nets or directly to nets in addition to electrical constraints.

Global Find and Modify for Associated components
Enhancements have been made to the Global Find and Replace functions. You can now search for Associated components, highlight the parent component and modify the associated component by selecting another PTF row from the same component.

Block Packaging options
This will allow changing block packaging options on the fly. Now you can change block packaging options for a hierarchical block instance from any previous option used to package that block. New prefix / suffix values will be applied to the reference designators of the block.

Pin Swaps and Net Swaps in front-to-back flow
Pin Swaps that are performed on the board are now reported as either Pin Swaps or Net Swaps in the Visual Design Differences window. The algorithm has been modified to check for the type of component - for components where the Pin name is the same as Pin number - Pin Swaps are reported as Net Swaps. You can override this default behavior by attaching the property ALLOW_CONN_SWAP to the component.

BOMHDL support for the SCM design
The SCM report generation utility does not support mechanical parts. To generate the BOM report with the mechanical parts, the DEHDL BOMHDL utility has been enhanced to support the SCM design. To generate the BOM report with mechanical parts, follow these steps:

Set the following environment variable: setenv DS_PRESERVE_PSTFILE 1
Define the PPT directive in the Global section of the project .cpm file for the ppt file path of the cell associated with mechanical parts. This is because the canonical names in SCM generated pst* files do not have the primitive binding in their canonical names for bom to get the cell level ptfs
Run "bomhdl" from the command line as: bomhdl -proj -mode scm

Please post your experiences with using these new SPB16.2 features.

Jerry "GenPart" Grzenia

What's Good About DEHDL-CM Physical and Spacing Constraints? You'll need SPB16.2 to see!

Jerry GenPart — Wed, 08 Apr 2009 18:10:00 GMT

That's right - the SPB16.2 release now includes support for Physical and Spacing (P&S) Constraints from within the Design Entry HDL Constraint Manager.

Prior to this release, you could only set electrical constraints in Design Entry HDL Constraint Manager (CM). Beginning with the SPB16.2 release, in addition to electrical constraints, you can use Constraint Manager connected to Design Entry HDL to create, view, edit, and assign physical and spacing (P&S) constraints to a net or group of nets. You also have the option to switch between read-only and edit modes for P&S constraints.

Physical and spacing constraints impact the physical layout of a PCB board or of a SiP, and are therefore usually captured and modified during the layout design stage by the layout engineer. However, stack-up information and some physical and spacing constraints are usually finalized during the design capture stage itself. For example, physical constraints, such as minimum line width and maximum line width, which have an impact on the manufacturing as well as the functioning of the design, are available. Such constraints can be entered during the design stage, and later on modified in physical layout. Similarly, information such as layers to be used by signal groups, and also trace proximity - these are often decided at an early stage of the development. In the SPB16.2 release, the layer stackup and P&S constraints can be imported via a technology file into the front-end Constraint Manager, or fed back from the board via Import Physical.

So now in the SPB16.2 release, the following operations are possible in DEHDL Constraint Manager:

Ability to enter, view and/or modify Physical and Spacing constraints
Ability to apply Constraint Sets on the objects of Physical and Spacing worksheets
Ability to override (directly set) values to constraint objects, aligning with the back-end
Ability to apply Physical & Spacing Constraints at all hierarchy levels
- Note: It is recommended that the layer stackup of lower-level blocks is the same as the layer stackup for the root design. The layer stackup defined at the top level is the winning stackup, and if none is found at the top level, the stackup coming from lower level blocks is ignored.
Ability to modify Physical and Spacing Constraint Sets defined in the back-end
Technology file import/export. (note layer stackup can be defined in the back-end only, but it can be viewed in the front-end)

Because of potential issues in a mixed release environment (e.g. a 16.2 Front End with a 16.01 Back End), be advised that the Constraint Manager Enabled flow requires the same release across the Front-End/Back-End flow.

Also note that any front-end design that utilizes the CM-enabled flow and which has been migrated to 16.2 is not backwards compatible with 16.01 or earlier releases.

As always, I look forward to any suggestions or questions you may have on this topic.

Jerry "GenPart" Grzenia

What's Good About Schematic Drawing Standards?

Jerry GenPart — Wed, 01 Apr 2009 19:06:00 GMT

This past week, there has been a very interesting discussion on the "icu-pcb-forum" Email alias. Most of the people have migrated to our Cadence Support forums, but there are still a few that use the "icu-pcb-forum" Email alias.

The topic - Schematic drafting practices.

There are some "veteran" designers (several with more than 25 years of experience) posting their perspective and company practices employed for how to interact with schematic design content. Some very good guidelines/standards are contained in the posts. I'd ask these folks to feel free and chime in here as well - and take credit for some key points below!

Here are some of the discussion highlights:

Where can I obtain web URL links or other sources for good schematic drafting practices?
It's tough to keep an up-to-date drawing standard. o Including "layout-pertinent information on the schematic" is important.
"Remember to hide unnecessary pin numbers, like for resistors and other two pinned components."
Tables, Tables, Tables! A Table of Contents, power/ground pins, test points.
There was an "intense" discussion about power/ground pins being included on the symbols or embedded in the part (in the chips.prt file). There are advantages/disadvantages to each method. I'm curious - which method do you consider a "Best Practice" and why?
I just have to include this one - it's amusing (IMHO)

"I had an engineer that insisted upon placing all like components on the same page.
- Page 1 thru 4 showed all the IC's
- Pg.5 transistors Pg.6 resistors
- Pg.7 capacitors And so on....
- He couldn't figure out why I was arguing with him. Go figure."

Grids are important to control object locations and proximities.
Here's a gem - "Print it out a 11 x 17 paper. Is it still legible? If not fix it."

Based on these discussions, I'd like to open this topic up to the greater PCB audience and dialog about the following:

How do you maintain and communicate your drawing standards to engineers? All details need to be considered - schematic "flow", part placement (orientation), text font/height/location, naming conventions, etc.
How much PCB/simulation properties do you add on the schematic? Are most kept in the Physical Part Table (PTF) files? Do you use symbol place-holder properties? This is in addition to the Constraint Manager properties that are commonly used.
How much "table data" (e.g. table of contents, block diagram, spares list, mechanical information, power/ground data, etc.) do you include on pages before the schematic electrical content?
How many companies consider schematic "style"/flow important? How many engineers use the Allegro System Architect/System Connectivity Manager table based approach? In other words, is the schematic content not nearly as important as the netlist derived from it?
How many designers use the ANSI/IEEE style of graphical symbols? For examples, you can visit any of the "a" series libraries (those prefaced with the letter "a" in the library name - like a54lsttl, a74fast, etc.)? Are these required for just a small subset of designs you produce? How do the various groups (PCB Design, Manufacturing, Testing, etc.) react to the symbols?

As always, I look forward to our continued communication on this topic!

Jerry Grzenia

What's Good About Cline Change Width in APD? It's in SPB16.2!

Jerry GenPart — Wed, 25 Mar 2009 16:21:00 GMT

In IC package design, it is becoming increasingly necessary to change a cline’s width in a given region, whether for signal integrity reasons or to allow all necessary traces to pass through a particularly dense region. This can be done to a limited extent through the use of constraint areas, glossing, and the change command.

However, depending on the nature of the desired width change, this can be difficult to achieve. Constraint areas can be time consuming to construct, and if a cline serpentines around itself for delay reasons, the region can be difficult to accurately specify. The change command can only be used to modify an entire segment, and cannot add new vertices.

This command will overcome the above limitations and allow the user to more efficiently update key sections of their design, such as the fanout area beneath a flip-chip.

Use Model

Upon launching the tool, you should select either the two-pick or window mode. In two-pick mode, you pick the first point on the cline, then the second point. The length of the clines between these two points (following the cline path) will be changed. In window mode, you make two picks to mark the two corners of the box. Two separate picks are still used, so that you are able to “oops” the first pick if it is not in the desired location, same as with the single trace mode.

Next, set the desired new line width.

Finally, make your selections in the main drawing canvas.

The picture below shows two copies of a cline, with the lower one resulting from a cline change width operation to lessen the line width between the two user picks.

Menu and Command-Line Access

Menu Pick: Edit > Cline Change Width… (near edit vertex)

Command Line: cline change width

Graphical User Interface

The interface for this tool exists within the mini status options panel. It is shown in its default configuration in the figure below. The fields are defined as follows:

· Two-pick single trace mode: Select this option (the default) to pick two locations on a single cline and change the width along the cline between those two points.

· Window pick multi trace mode: Select to draw a selection window in the main canvas and change all the clines inside that region to the new width.

· New width: The new width for the modified pieces of the cline(s). This defaults to the minimum line width on the top conductor layer in the design.

Once again, I'm always interested in your perspective on the new SPB16.2 features!

Jerry GenPart

What's Good About Dynamic Fillets in Allegro PCB Editor? Check out the SPB16.2 Release!

Jerry GenPart — Wed, 18 Mar 2009 18:20:00 GMT

The existing Fillet application, a function of the Gloss routine, has been enhanced to support the dynamic updating of fillets on pins, vias or T-junctions. The application continues to support the interactive or Batch mode options as well as the parameters in place. The new dynamic option offers the convenience of filleting during interactive etch editing with no additional procedural steps.

Shape based fill

The fill associated with Fillets has transitioned from line to shape based. For DRCs purposes, the fillet is considered an extension of the pad or via. Prior to the SPB16.2 release, line base fillets contributed to unwanted DRCs.

Shape-based fillets -

Line-based fillets -

Parameter form update

New parameters, located in the Pad and T Connection Fillet form, associated with the Fillet application include

Allow DRCs
Dynamic Fillets
Curved Lines

Fillet Algorithm

The algorithm first tries to create the fillet at the desired angle, tangent to the pad. If the fillet cannot be created, the angle is incremented up to the Max Angle. If the fillet length, pad tip to vertex of fillet, is greater than the Max Offset, the vertex is adjusted by an amount to satisfy the Max Offset requirement. The end points of the fillet are adjusted by the same amount to maintain the angle.

Reporting

A new report called Missing Fillets Report lists junctions with missing or partial fillets. This report can be found in Tools> Reports or Tools> Quick Reports.

Downrev

Boards with fillets will uprev with no conversion to shape based fillets. The SPB16.2 release will support the combination of line and shape based fillets, however new fillets added will be shape based.

Uprev

Shape based fillets will be removed on downrev to the SPB16.01 release.

As always, I look forward to your comments about this new Allegro PCB Editor capability.

Jerry GenPart

It’s All In The Metrics

MattB — Wed, 18 Mar 2009 16:00:00 GMT

You could be forgiven for thinking that this was going to be a discussion of the benefits of imperial versus metric units, but its not. The metrics I’m talking about are those business metrics that constrain a design. These business metrics may be anything from cost, to part quality to RoHS compliance. What I’d like to discuss is how important these metrics are to you, how do you handle this information today and where does it come from. As business constraints become more important in the design of products, this is an increasingly important topic. The Allegro Design Workbench team is focusing some energy on building broader support for metrics and design analysis and this is an opportunity to provide feedback that will help us shape future product development.

Let's look at each of these areas is turn:

How important are metrics to you?
Historically the electronics design area focused primarily on function. Libraries and part selection were based on functional parameters. The design process was executed in somewhat of a black-box, with one of the outputs being a bill of materials. This BOM would at some point be analyzed and then feedback provided, however this may be after the design has already been completed. Fast forward to the present day, where design cycle times and market windows are shrinking and business constraints are growing.

How are you bringing this type of analysis earlier in the design cycle?
How important is this information to you as a design engineer?
What business metrics do you collect and how automated is their collection?

How do you handle this data today?
So lets suppose you do have access to all the business information you need to generated metrics about the design. What is the typical metric report that you need and when do you need it? Is it sufficient to have statically generated reports that indicate parts out of compliance, for example run a report that shows all the parts in the design that are not RoHS complaint? Or do you really need a dashboard of metrics where you can see multiple metrics and how they change in real time as the design progresses? For collaboration with others would it be beneficial to have graphical rollup summaries to quickly show the overall health of a design.

What type of reports do you need to generate?
How important is it to run analytics in addition to reports (for example make suggestions for optimizing a BOM based on certain criteria)
Do you look at metrics across multiple BOMs simultaneously?

Where does this information come from?
Much of the business information, especially around part data is owned by other business functions. It’s not reasonable to expect CAD librarians to maintain much of this in a CAD library. Can you imagine having to update cost information for 20,000 each month? However there are business systems that do contain this data: either a corporate part database or PLM system is the most likely source. Integrating this data into the engineering desktop is one challenge, but necessary to make it available at component selection time. Some folks do export data from enterprise systems directly into the CAD tools (for example into CIS or by auto updating PTF data). There is also a plethora of potential data available: do you just need to know whether a part is RoHS compliant or do you really need to know the percentage of hexavalent chromium in it?

Can you see all the data you want at component selection time?
Do you use more than one system for component selection (one to research the part and the other to select it for the CAD tools)?
How do you handle access to all the part business data?

We've only scratched the surface of metrics, but I’ll leave it there for now. In later posts I’ll talk about the importance of process metrics in addition to design business metrics. And just to keep you salivating with anticipation other future topics will include design data management, design reuse, ECAD and the enterprise and other juicy topics!

As always - I look forward to your feedback and continued discussion on this topic.

What's Good About Allegro® Design Entry HDL – User Customizations? You Tell Me!

Jerry GenPart — Wed, 11 Mar 2009 14:00:00 GMT

Well ... if you like tweaking and tuning an environment to suit your needs, Allegro Design Entry HDL (DEHDL or previously known as ConceptHDL) has plenty to offer.

I began in the Blog-sphere-posting-world of Cadence with one of my first posts titled - "How many DEHDL (Concept) designers customize their DEHDL environment?" You can read the details here

Although I asked about this almost a year ago, the relevance still applies today:

How many designers customize the DEHDL environment to suit their taste?
Do you add just a few hotkeys (softkeys), or strokes?
Do you adjust the toolbars?
Do you customize the menus and add your own commands?

All this has been possible for years, and novices to DEHDL can really take advantage of this to make the environment more efficient to the tools they've used in the past.

I wrote a paper about this for last year's CDNLive! 2008 event in San Jose. The presentation can be found here -
(look under the "VII. PCB Design" section). You'll see that several of the customizations I employed in the SPB16.01 release were included as part of the new SPB16.2 Windows mode in DEHDL. But, there are still several areas of customization that can be explored.

The intent was to show the myriad methods available to customize the environment and in some scenarios, make it simpler for the new designer to adopt using the product. All the details and reasons can be found in my paper. Efficiency, productivity, and enablers to get the job done are key to customizing DEHDL.

As always - I look forward to our discussion on this topic and sharing/exploring new ways to customize DEHDL!

Jerry GenPart

What's Good About Coplanar Waveguide Support in PCB SI? It's now in SPB16.2!

Jerry GenPart — Thu, 05 Mar 2009 20:22:00 GMT

Coplaner waveguides (CPW) are widely used in packaging, high speed designs and on silicon. These structures are now supported in Allegro PCB SI.

The figure below shows a typical coplaner waveguide. The important distinction for a segment to be a coplaner waveguide is a segment "W" surrounded by two large shapes. In order to detect coplaner waveguide segments while traversing a net, there needs to be a Shape window. The existing Geometry Window is used as the shape window. For a given segment, if two shapes adjacent to the segment exist within the Geometry Window, that segment will be analyzed as a CPW structure.

CPW Detection Flow

Enable CPW for the entire design using the Preferences form
Disable any individual nets that you do not want to be handled as a coplaner structure. This is done by attaching the CPW_DISABLED property to these nets.
Set the Geometry Window
Only traces surrounded by shapes that are assigned a DC voltage will be modeled as CPW
The EMS2D field solver is used to generate the model.

Global Setting to enable CPW

The InterconnectModels tab of the Signal Analysis Preferences form has been enhanced to add an option to enable/disable CPW.

One or both of the fields Enable CPW Extraction and EMS2D can be selected at a time. The effects on the field solver are as follows:

Only Enable CPW Extraction enabled:

With only this option enabled, the extraction code goes through a flow different from the regular (old) flow and tries to detect coplanar waveguides. The model generated is then passed to EMS2D to get a solution. Except for CPW, all other models are generated with BEM2D.

Only Field Solver EMS2D enabled:

With EMS2D enabled, the extraction code follows the normal (old) flow. The only difference is that instead of calling BEM2D to get the field solutions, the EMS2D field solver is called.

Both Enable CPW Extraction and EMS2D enabled:

With both options enabled, the extraction code uses the new flow, which tries to detect CPWs. All models are solved with the EMS2D field solver instead of BEM2D.

EMS2D Preferences

The Preferences button is only active when the EMS2D solver is selected. By default, EMS2D uses default frequencies (same as BEM2D).

Frequency Settings Default Frequencies is used to create values in the same manner and with similar settings as BEM2D with respect to frequency data. If no cutoff frequency is set in the main Preferences dialog, both BEM2D and EMS2D will generate a DC and INF value. If a cutoff frequency is set, both will use a range of frequencies based on the cutoff value (usually DC to 50 GHz).

The other two radio buttons allow you to specify the exact Frequency range and/or Frequency Points.

Frequency Point File Option to provide a frequency point file.

Example of a frequency points file:

0.0001
0.0002
0.001
0.002
1
2
10
20

Mesh OrderA Mesh Order setting of 1 will speed up the performance of the field solution without significantly sacrificing accuracy. A setting of 3 will provide the highest accuracy. EMS2D generates a mesh based on the wavelength of the highest frequency point. This setting impacts the order of the polynomials used to analyze each of these cells.

Fast Frequency Sweep This setting should only be used when a large number of frequency points are being solved. Rather than generating a full solution for each point, this option allows for the solver to find acceptable ranges where values can be interpolated. This does not mean a degradation in accuracy, however, as the solver compares fully solved values to points where interpolation will be used and does so with a very tight tolerance.

Output S-parameter Waveform Enables EMS2D to produce S-parameter touchstone file (.snp). The output file is named <modelname>.snp is written to the run directory. This is only enabled when the Frequency Settings are set to either specific Frequency Parameters.

Coplanar Waveguide Characterization

The following CPW structures are supported:

Single stripline CPW
Coupled stripline CPW
Single microstrip CPW
Coupled microstrip CPW
Single CPW
Coupled CPW

Library Enhancements

To support CPW structures, two new IML model types have been added to the SI library. These model types are:

Single CPW - This describes a single trace with ground shapes on both sides
Diff Pair CPW - This describes two diff pair traces with ground shapes on both sides

The following enhancements have been made to support these new model types:

Coplanar Waveguide models are stored in the IML library in a section with a header of CPW. Each of these models is stored as a subsection within this section of the library.
The IML model browser shows CPW models with the following model type keywords:
- SingleCPW
- DiffPairCPW
The following new options have been added to the Model Type Filter on the IML model browser:
- Single CPW - shows only CPW Single models
- Diff Pair CPW - shows only CPW Diff Pair models
- Any CPW - shows all CPW models
The Add Model button on the IML Model Browser includes an option for adding each of the new CPW models.
The CloneSelection option on the Add Model button in the IML model browser handles cloning both types of CPW models
When Edit or TextEdit are selected for a CPW model in the IML model browser, the model is displayed in a text editor

A CPW model can only be created if running from a product that supports the new EMS field solver. However, if you have an existing IML library that contains CPW models, you will still be able to see these models in the IML model browser regardless of the product that you are running. You must be running a product that supports EMS before one of these existing CPW models will be used for a simulation.

Disabling CPW extraction on individual nets

A new property, CPW_DISABLED, has been added to disable CPW extraction on individual nets. Attach this property to any nets that you want to be handled during analysis as non-CPW nets. If you have selected only the Ems2d Field Solver option (without Enable CPW Extraction), non-CPW nets will be generated with Bem2d.

As always, I'm interested in hearing how you employ these new features.

Jerry GenPart