Cadence System Design and Verification Blogs

Industry Standard SystemC is What Designers Want

SteveSvoboda — Fri, 03 Jul 2009 08:00:00 GMT

This past Monday saw not one HLS related announcement but two...this space is really heating-up! Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new...(read more)

DAC Virtual Platform Workshop

jasona — Tue, 30 Jun 2009 15:00:00 GMT

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC 2009 . Well, now it is too late to start thinking about it, and it is time to start acting by making plans to get to San Francisco. One of the events I will attend is the...(read more)

The Golden Age of Electronics

jasona — Fri, 26 Jun 2009 14:07:00 GMT

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota. We wanted to visit the museum for some time, but never made quite it. We even went there once last year only to find out it is closed every Monday. The history of the museum...(read more)

Speeding up SystemC compilation with Incisive SystemC

georgef — Fri, 19 Jun 2009 13:00:00 GMT

If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking down a nasty bug, nothing can bum your trip more than having to wait around for a long recompile. Compile time is a bottleneck for SystemC development...(read more)

OVM Metric Driven Verification With an FPGA-based Design

TeamESL — Wed, 17 Jun 2009 19:30:00 GMT

During the last 2 years I have enjoyed the opportunity to work with the Incisive Software Extensions (ISX) with many customers. I learned a lot about software/hardware co-verification and we reached the point were we started to see beyond one’s...(read more)

The DWARF Debugging File Format

jasona — Fri, 12 Jun 2009 18:00:00 GMT

The Chronicles of Narnia has always been one my favorite series of books. Today, I'm not going to talk about dwarfs such as Trumpkin , the dwarf that appeared in Prince Caspian ( check out the latest movie ), but instead something called the DWARF...(read more)

Synthesis Really DOES Need to Change

SteveSvoboda — Tue, 02 Jun 2009 13:00:00 GMT

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful...(read more)

Where's the Bridge to Cross the Great Divide?

jasona — Thu, 28 May 2009 13:00:00 GMT

At this year's Embedded System Conference in San Jose there was a panel with the title Who's Taking over Whom - Is EDA Moving into Embedded or Embedded into EDA? One of the analogies Mike McNamara from Cadence used was hardware and software engineers...(read more)

Way Worse Than The Real Thing

TeamESL — Tue, 19 May 2009 04:05:00 GMT

This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual...(read more)

ESL Verification News From CDNLive! EMEA

Steve Brown — Tue, 19 May 2009 01:00:00 GMT

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time again for one of the most popular CDNLive! tour stops here in EMEA. The location is the beautiful European city of Munich , at the Park Hilton Hotel . The hotel overlooks...(read more)

System D&V at CDNLive! EMEA

Ran Avinun — Mon, 18 May 2009 23:17:00 GMT

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were...(read more)

SystemC Debug: A Summary of Summary Probes

TeamESL — Fri, 15 May 2009 13:00:00 GMT

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in...(read more)

ISX Presentations at CDNLive! Munich

jasona — Wed, 13 May 2009 15:45:00 GMT

As we head into next weeks CDNLive! event in Munich it's great to see today's post in the Industry Insights area by Richard Goering on the Embedded Software Challenge . It provides concrete data on the rising costs of embedded software design...(read more)

Modeling Interfaces with C-to-Silicon Compiler

TeamESL — Thu, 07 May 2009 13:15:00 GMT

Users of ESL tools are curious about the procedure for handling the interface to a bus or other communicaton protocol in a High Level Synthesis environment. This is usually formulated in the following question: “How do we take into account the interface...(read more)

Tracing TLM 2.0 Activity in an ESL Design – Part 3

georgef — Thu, 07 May 2009 13:00:00 GMT

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM 2.0 transaction data ( http://www.systemc.org ). In this post, we’ll explore the data in the Simvision Waveform Viewer, the Transaction Explorer, and with TxE...(read more)