Cadence System Design and Verification Forum

Smoke Analysis on subcircuit

tt543 — Tue, 11 Jun 2013 07:45:04 GMT

Hello,

I've been trying to run smoke analysis on my design for a while. I've managed to run it on active devices (FETs and diodes), but it refuses to run on passive components - subcircuit based .lib files. For example I have an inductor with the following model:

.subckt ind_reg0 1 2

L1 1 3 10e-6

R1 3 2 0.3

.ENDS

I also added the following definition to device property file:

("IND_REG0"

(Creator "XXXXX")

("device_info"

( SYMBOL_NAME "inductor" )

( MODEL_TYPE 2 )

( PORT_ORDER

("1")

("2") )

)

("device_max_ops"

(LI "0.11")

)

When I run smoke analysis (after transient) I get the "non-fatal error: Current data not found for Smoke test LI" I've verified that I check "All" in data collection options. I also tried updating node names in pre-smoke section of template property file. But nothing helped.

Does anyone have an idea how to run smoke analysis on subcircuit based passives?

Thanks in advance for you help!

How to change SPECTRE command line path ?

bojankoce — Fri, 07 Jun 2013 09:41:48 GMT

Hi guys,

I have a litlle technical problem here... Namely, I want to move to 32-bit version of MMSIM12.1 tool.

I thing that I'm currently using the 64-bit version because when I enter "spectre" commant I can see in my .log file that my command line is "/tools/Cadence/MMSIM121/tools.lnx86/spectre/bin/64bit/spectre".

My question is how I could change the path of command line to be "/tools/Cadence/MMSIM121/tools.lnx86/spectre/bin/32bit/spectre" ?

I suppose that this information is "embedded" somewhere during the Cadence installation.

Thank you in advance for your time and effort.

Best regards,

Bojan

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Regarding: reference designator

cad2314 — Mon, 13 May 2013 15:00:31 GMT

Is LOCATION a default properrty in CONCEPT HDL for reference designator or can the property be disabled or renamed with another name. Because even if the property LOCATION is not defined the it shows up automatically when packaging. Is it a tool constraint?

Regarding: symbol property 'has_fixed_size'

cad2314 — Mon, 13 May 2013 13:10:34 GMT

Hi,

I am using CONCEPT HDL version 16.5. When i define the property 'has_fixed_size' in the symbol property, an error message is displayed suggesting that 'has_fixed_size' is a reserved property and cannot be user defined. And when i enter the property in the part table key properties and specify a value for it the following error is displayed while saving "cannot find a ppt part that matches the instance properties"
So is there any way to define a user defined value for the property 'has_fixed_size'

Thanks in advance.

Regarding symbol attributes display

kis51437568 — Mon, 13 May 2013 12:22:31 GMT

Hi,

In the schematics the symbol attributes have value field "<<null>>" when we have not provided any value for the particular header in the part table. Is there a way to make the value field "blank" (i.e in schematics) when we have not provided any value in the part table?

Thanks in advance.

Regards,

M.Kishore Kumar

Read Orcad Data?

gainfocus — Sat, 11 May 2013 06:31:56 GMT

I have been tasked with integrating Orcad with an ERP database. The ERP database is a SQL Server database and I have no problems writing to it. However I am clueless on where to go to read Orcad data. What type of database is Orcad stored in? Where is it stored? Is the data open source or would I need special licensing to read the data?

Any insights appreciated.

Modeling languages and rad hardened cell libraries for ARM processors

Baldur — Wed, 24 Apr 2013 18:13:43 GMT

Dear Sirs,

My company is considering ARM processors, in particular the A15 or even AXM5512-B or AXM5516-B, for a certain project that we are evaluating.

Key Project Requirements
1. General Processing Capabilities
* At least 24 32-bit processor cores.
* Min. of 24 GOPS and 10 GFLOPS performance (concurrent) at 7 W or less.
* Radiation hard to at least 1 Mrad TID.
2. Simulation Model of the Processor Architecture
The simulation model should be capable of providing high confidence estimates of power utilization, throughput and other performance metrics.
3. Board Level Computer Reference Design
The reference design will include all necessary components for a single board computer, including memory, external interrupting routing, I/O, boot ROM and clock.

Questions
1. What sort of languages for behavioral modeling does Cadence offer, for this purpose?
- Imagars' personnel is proficient in Verilog in addition to C/C++.
2. Does Cadence offer rad hardened cell libraries for ARM processors, in particular the A15?

Any helpful pointers and/or comments would be most appreciated.

Best regards,
Baldur

leakage power

Saranya22 — Tue, 23 Apr 2013 10:07:55 GMT

How to find Leakage Power in cadence analog design environment?

Fixed step size

TLIG — Sat, 20 Apr 2013 09:45:18 GMT

Good day evryone

can you told me how to simulate with a fixed the step size ?

in my simulation i use the MOSFET commutation and with maximum step size ORCAD variate the step size in commutation. But i need fixed step size.

thank'you

tlig