Cadence PCB Skill Forum

From Signal Integrity to EMC: Join Daniel Beeker for a Two-Day Science-Based PCB Design Seminar in Derby, United Kingdom in October 2026

Azitech Aps — Mon, 20 Jul 2026 15:53:59 GMT

Introduction: PCB Design Has Entered a New Era

Electronic systems continue to evolve at an extraordinary pace. Faster edge rates, higher switching frequencies, compact multilayer stack-ups, dense BGAs, mixed-signal architectures and increasing reliability expectations have fundamentally changed the way printed circuit boards must be designed. In many applications, including aerospace, defence, industrial automation and medical electronics, PCB layout is no longer simply an interconnection exercise; it is a critical part of overall system performance.

Engineers are now expected to achieve first-pass success while meeting demanding signal integrity, EMC and reliability requirements. Every additional prototype, compliance failure or late-stage design modification increases cost and delays product delivery. As a result, organisations are placing greater emphasis on understanding the engineering principles that govern PCB behaviour rather than relying solely on historical design rules.

Many traditional layout practices were developed when switching speeds were considerably slower. Today, however, rise time is often more significant than clock frequency. A design that appears electrically correct in the schematic can still fail because of poor return current paths, discontinuous reference planes, excessive loop area, uncontrolled impedance or inadequate power distribution.

Why Physics Matters More Than Rules of Thumb

Rules and design guidelines remain valuable, but they are most effective when engineers understand why they exist. Science-based PCB design focuses on electromagnetic behaviour rather than memorising isolated layout recommendations. It asks questions such as: Where does the return current flow? How do electric and magnetic fields interact with the PCB structure? What effect will a split reference plane have on a high-speed signal? Why does a seemingly minor layout change create unexpected EMI?

Core Principles of Science-Based PCB Design

Maintain continuous return current paths for every high-speed signal.

Treat reference planes as part of the signal path rather than as passive copper.

Plan PCB stack-ups early to support impedance control and EMC performance.

Reduce loop area to minimise radiated emissions and susceptibility.

Design the power distribution network with low inductance and effective decoupling.

Understand the relationship between placement, routing and electromagnetic field behaviour.

Return Current Paths: Often Overlooked, Always Important

One of the most common causes of EMC and signal integrity problems is an interrupted return current path. High-speed return currents naturally follow the path of least inductance, remaining close to the signal trace on the adjacent reference plane. When that reference is interrupted by plane splits, voids or poorly managed layer transitions, the return current must detour around the discontinuity. The result can be increased loop inductance, higher emissions, greater susceptibility and degraded signal quality.

Signal Integrity, Grounding and Stack-Up Planning

Signal integrity cannot be considered independently from PCB stack-up, grounding strategy and power delivery. Controlled impedance, consistent reference planes and carefully planned layer assignments all contribute to predictable electrical behaviour. Likewise, effective decoupling is not simply about capacitor values; placement, mounting inductance and current loops determine whether transient current demands are met.

From Theory to Practical Engineering

The objective of science-based PCB design is not to make PCB development more theoretical. Quite the opposite. By understanding the underlying physics, engineers can make faster, better-informed design decisions. Rather than following a checklist blindly, they can evaluate trade-offs confidently and identify potential issues before fabrication, reducing PCB re-spins and improving first-pass success.

Daniel Beeker's Engineering Approach

Many engineers know Daniel Beeker through his presentations, design reviews and international technical seminars. With more than 44 years of experience in electronic system design and electromagnetic compatibility, Daniel has developed a teaching style that bridges engineering theory and practical product development. Instead of presenting design rules in isolation, he explains the physical mechanisms behind them, enabling engineers to apply the same reasoning to new technologies and future designs.

His sessions combine real-world PCB examples, practical demonstrations and engineering experience gained from decades of solving challenging EMC and signal integrity problems. This practical approach has made his seminars valuable for PCB designers, hardware engineers, SI engineers, EMC specialists and engineering managers alike.

Benefits for Engineering Teams

Improve first-pass PCB success and reduce costly redesigns.

Strengthen signal integrity and EMC performance.

Understand grounding, return currents and stack-up decisions with greater confidence.

Reduce compliance risk before laboratory testing.

Develop engineering judgement that extends beyond individual design guidelines.

Technical Seminar Hosted by Azitech ApS

To support the engineering community, Azitech ApS, Denmark, will host the Science-Based PCB Design Seminar led by Daniel Beeker on 27–28 October 2026 at Delta Hotels Breadsall Priory Country Club, Derby, England, United Kingdom.

The seminar is intended for experienced PCB designers, hardware engineers, EMC specialists, signal integrity engineers and engineering managers seeking a deeper understanding of the engineering principles that lead to robust, reliable PCB designs. Topics include return current behaviour, grounding, EMI reduction, signal integrity, PCB stack-up planning and practical high-speed design techniques.

An Invitation to the Cadence Community

The Cadence Community has long been a place where engineers share experience, discuss design challenges and exchange practical solutions. We hope this article contributes to that conversation. If the topics discussed here align with the challenges you face in your own designs, we would be delighted to continue the discussion.

As external links may be filtered within the Cadence Community, please feel free to leave a comment or send us a direct message if you would like additional information about the seminar, agenda or registration process. We look forward to engaging with fellow engineers and learning from the wider Cadence community.

Attachment: Seminar Invitation Poster

Can we highlight multiple vias by using xy cordinates at a time in allegro

BC202603263145 — Fri, 17 Jul 2026 11:07:10 GMT

I have a list of vias with its XY locations. I need to highlight all these vias at once. How would I do that in Allegro?

From Challenges to Solution: Interactive 3DX Canvas Session - Join us on July 22nd

Renu Vibha — Thu, 16 Jul 2026 11:22:00 GMT

Curious about how users are leveraging 3DX Canvas to accelerate PCB design and overcome complex design challenges?

Join us here, for an interactive live session with Cadence experts and get real-time answers to your most pressing PCB design questions.

Date: July 22, 2026
Time: 3:30 PM – 4:30 PM IST

What’s on the Agenda?

Model Mapper
3D DRCs

Why Attend?

Get expert answers to your PCB design questions in real time
Discover practical, real-world use cases and best practices
Network with peers and exchange valuable insights and experiences

Bring your design challenges, explore innovative solutions, and leave with actionable insights you can apply immediately.

Board Outline and Cutouts Not Showing Up for PCB Manufacturer

SB202607126042 — Sun, 12 Jul 2026 19:25:11 GMT

Hi everyone,

I'm facing a problem after exporting my Gerber files. My PCB outline and cutouts are not showing up for the manufacturer.

I'm using JLCPCB, and when I use their DFM tool to perform the final verification, everything appears correctly except the board outline and cutouts.

The board outline was created in Board Geometry > Design_Outline, and the cutouts were created in Board Geometry > Cutout. Both layers are included in my artwork and are being exported to the Gerber files that I send to the manufacturer.

Am I missing something? This is my first project using Cadence PCB software.

SPB 16.6 BASE RELEASE NOT FOUND

KB202607102640 — Sat, 11 Jul 2026 04:40:19 GMT

Hello everyone,

I have a legitimate Cadence OrCAD/SPB 16.6 standalone perpetual license purchased directly from Cadence.

However, the installation DVD I have contains only:

HotFix_SPB16.60.010_wint_1of1.exe (ISR10)
My license (.lic) file
The installation guide (PDF)

There is no SPB/OrCAD 16.6 Base Release installer (setup.exe, Disk1, Disk2, etc.).

When I run the HotFix installer, I receive the following error:

SPB 16.6 Base Release Not Found

I understand that the HotFix requires the Base Release to already be installed, but I do not have the Base Release installation media.

My questions are:

Is the SPB/OrCAD 16.6 Base Release still available for customers with a standalone perpetual license?
Can it still be downloaded from the Cadence Support Portal?
If not, what is the recommended way to obtain the Base Release installer?
Has anyone else encountered this situation where only the ISR DVD was provided?

I would appreciate any guidance from Cadence staff or users who have dealt with this issue.

Thank you.

Board Geometry / DESIGN_OUTLINE vs. OUTLINE And What Are the Real-World Implications?

Electro Node — Wed, 08 Jul 2026 15:01:34 GMT

Hi everyone,

I've always been a bit confused about the difference between Board Geometry / DESIGN_OUTLINE and the legacy Board Geometry / OUTLINE subclasses in Allegro X PCB Editor.

If the board boundary is defined using Board Geometry / OUTLINE instead of DESIGN_OUTLINE, could that cause any issues during manufacturing, fabrication outputs, MCAD exchange, or other downstream processes? Or is it still generally acceptable in production designs?

I'd love to hear how others are handling this in their workflows. Have you encountered any problems, benefits, or best practices related to using one versus the other? Looking forward to learning from your experiences!

Best Regards,

How important is symmetry or trace consistency in your designs?

John T — Wed, 08 Jul 2026 09:50:01 GMT

Recently, I had an extremely interesting design-chat with a high-speed designer working for a globally recognised electronics firm. (Cannot name names, but you’re allowed to guess…)

They raised a very interesting point: They found designs in review that would fail or were performing poorly due to critical traces and vias being drawn “by hand”; trace by trace. As a result, there were layout variations in certain key areas such as pad-trace exits, distances from signal via to pin or return, dynamic shape patterns… Once corrected the design performance improved.

We would be very interested to hear from experienced engineers to know how important you feel symmetry or consistency is in pcb design?

Do you see any specific design aspects where symmetry or consistent patterns of shapes, traces or other objects become important?

How do you overcome these challenges / with what methods?

Add Collision Detection and ability to XY snap to faces to 3Dx

JM20241029170 — Tue, 07 Jul 2026 16:18:59 GMT

A critical feature missing from 3Dx is collision detection. The new 3D drc is good for internal designs, but I can't determine if mechanical imported models collide with the design. This is how I check multi-board assemblies, by exporting each board to a STEP then importing them into one canvas to assemble and check for collisions. Also, 3Dx doesn't allow me to select faces on component bodies (like a connector) to snap with XY like on the old 3D canvas...this makes assembly impossible besides doing it by hand!

I can't use the old 3D canvas since it has recently become unstable when importing 3D models, so forced to use new 3Dx that is missing core features.

Don't miss our Live, Interactive upcoming OrCAD X Session on July 8th, Wednesday

Renu Vibha — Thu, 02 Jul 2026 14:36:25 GMT

Curious about what other users are trying in latest release of OrCAD X—or looking to solve design challenges faster?

Join our live, interactive session with Cadence experts and get real-time answers to your toughest PCB design questions.

Date : July 8, 2026 at 7:30 – 8:30 PM IST

Location : here

What’s on the agenda:

Cloud Features: Work in shared cloud workspaces, create and manage components, track revisions, control versions of design and collaborate seamlessly.
Variants: Create BOM Variants, manage alternate and substitute parts, and export variant.lst file for downstream manufacturing processes.

Why you should attend:

Get instant answers to your questions
See real-world use cases in action
Connect and exchange insights with peers

Bring your challenges, explore new possibilities, and walk away with actionable insights.

Save your spot now and be part of the conversation, register now!

Join us for a Lunch & Learn session on Allegro X System Capture on July 9th at Cadence Bangalore

Renu Vibha — Tue, 30 Jun 2026 09:25:45 GMT

You are cordially invited to an exclusive Lunch & Learn session on Allegro X System Capture – the next-generation schematic technology built to accelerate your design productivity.

Discover how System Capture helps your team design faster, smarter, and right-first-time through powerful automation and built-in intelligence.

Session Agenda:

One-Stop Library Cockpit – Unified Search & Part Manager for instant component access
Core Capabilities – Version Control, Variant Editor, and 120+ built-in Audit Checks
Productivity Boosters – Decap Wizard and TCL Script Automation for rapid design cycles
Integrated Layout Experience – Cross-probe, floorplan edits, and full-fledged Constraint Manager

Join us at the Cadence Bengaluru Office for an interactive session and networking with our experts — over lunch.

Session Speakers:

Shikhar Dwivedi - Principal Application Engineer

Bhargava Hegde - Senior Application Engineer

Event Details

Date: Thursday, 9 July 2026
Time: 10:00 AM – 2:00 PM IST
Venue: Agamya Training Room, 1st Floor, Campus 4A & 4B, RMZ Ecoworld, ORR Road, Bengaluru

Seats are limited. Please confirm your participation ASAP by writing to hbhargav@cadence.com or dshikhar@cadence.com

We look forward to hosting you!

Fanout of Outer-Layer GND smd Pins to Via-in-Pad in Allegro

BC202603263145 — Tue, 30 Jun 2026 05:28:53 GMT

I am looking for a solution to select all GND smd pins on the outer layers (TOP/BOTTOM) and fan them out directly to a custom via-in-pad (user-defined padstack) using a fully automated, batch-driven flow.

Is there any set of steps that I could try?

How can i install 16.6-era Allegro Free Physical Viewer?

CF20260629245 — Mon, 29 Jun 2026 14:18:14 GMT

Hi there,

I'm looking to install an older version of the Allegro Free viewer to see an older pcb. How can i do this?

Feature Suggestion: Impedance Workflow Green Color setpoint

JM20241029170 — Wed, 24 Jun 2026 20:53:00 GMT

I'd like to suggest that the impedance workflow vision allow users to set the goal impedance. This way, the green color is the desired impedance. I often have a small heart attack every time I see wild coloring on the board just to notice the impedance range is in milliohms.

How do I cut only a cline segment ?

BC202603263145 — Wed, 24 Jun 2026 07:17:53 GMT

Hello,

While working on routing, I often need to adjust or remove just a specific section of a trace. However, the tool seems to treat the entire trace as a single entity or trace segments forcing me to rework the whole trace even when changes are required only on specific length.

Is there a method to isolate and cut only a portion of cline segments?

OrCAD X PCB Professional Copper Wire passing through Mechanical Hole but no DRC Error

BaldEngineer — Wed, 17 Jun 2026 09:28:20 GMT

I just came across this problem where a Copper Line is passing through a 3mm Mechanical hole on Layer4 of my design.

And i don't see any DRC Error reported. I can confirm that this is not something that has gone through Waive DRC Window.

As seen in picture below, thin green lines was the original location of this 3-pin connector. And i moved it a bit to the right.

So, now pin 3 mechanical hole(No net) is crashing with the copper line(Net 5309092) and i am getting no error about this.

How do you route multiple nets (like buses) efficiently in Allegro PCB Editor?

Electro Node — Mon, 15 Jun 2026 16:57:55 GMT

Hi everyone,

I’m working on a DDR design with multiple data buses, and routing nets individually feels quite time-consuming.
Is there a way in Allegro to route multiple nets together while maintaining consistent spacing?

I need to route multiple nets in one go. Would love to hear your approach!

Thanks!

Join us on Wednesday June 17, 2026 for a live “Ask Me Anything” Dedicated Expert Session: Constraint Manager

Renu Vibha — Thu, 11 Jun 2026 05:43:52 GMT

Got Questions on Constraint Manager?

Want clarity on new features and solving everyday design challenges?

Ask a Cadence expert— LIVE

Join Us Here

June 17, 2026 | 7:30–8:30 PM IST

Topics:

Electrical Constraints
Physical & Spacing Constraints

Let’s make this an engaging, insightful, and impactful session together!

Bring your questions. Share your experiences. Be part of the energy

Make smarter design decisions with in-design analysis : Leverage the upcoming Allegro X Webinar

Renu Vibha — Thu, 11 Jun 2026 05:29:55 GMT

Struggling with SI/PI Challenges in PCB Design?

Are you looking for clear answers on:

How to configure a PCB for in-design analysis using Sigrity X Aurora within the Allegro X environment?
How to choose the right layer stack-up for power and ground to minimize PDN inductance?
How to validate your routing topology against industry specifications?
How to catch and resolve SI/PI issues early—before they become costly problems?

If these sound familiar, you’re not alone—these are some of the most pressing challenges faced by PCB designers today.

Get the Answers You Need

We’ve already covered these exact topics and more in a practical, insight-packed webinar designed for engineers like you.

Register Now

Why this webinar matters:

Step-by-step guidance on real workflows
Industry-aligned best practices
Actionable techniques you can apply immediately

Tip: Visualizing spacing net classes using Class Color

Gowtham P — Mon, 08 Jun 2026 16:14:19 GMT

For designs with multiple spacing rules (especially HV or compliance-driven designs), visually distinguishing net classes can simplify design review and documentation.

Using Display > Class Color in Allegro X PCB Editor, you can assign unique colors to spacing net classes and generate a legend directly in the canvas.

Typical flow:

1. Navigate to Display > Class Color. This command opens a form, which lists all the spacing net classes from the current design.

2. Assign colors to spacing net classes.

3. Apply changes and optionally Generate/Update legend

3. Save settings for reuse across designs

This can be particularly useful for:

Reviewing high-voltage or constraint-critical nets
Improving design readability during checks
Creating documentation-ready visuals

How are you handling net class visualization in your designs today?
Any feedback on usability or behavior across different releases?
Would be great to hear if this is part of your regular workflow or if you rely on alternate approaches.

Note: This capability exists in Allegro X Productivity Toolbox Option

Add layers menu is grayed out in Cross Section

BC202603263145 — Mon, 08 Jun 2026 15:42:29 GMT

Hi,

I am trying to add a conductor layer in the stackup, but the Add Layers option in the Cross Section is grayed out.

This issue occurs only in a specific design.

Any suggestions on what might be causing this or how to enable it?

How to use skill to select Domain for each film in Allegro X

MZ20250602835 — Wed, 03 Jun 2026 05:49:14 GMT

Dear All,

may i ask how could i select Domains such as Artwork, IPC2581, PDF or Visibility for each Film using skill? Many thanks.

Many thanks and Best Regards

ERROR(SPMHOD-I): Design has been corrupted, saving as 'AUTOSAVE.SAV'.

kevcon — Tue, 02 Jun 2026 14:04:40 GMT

Hi everyone,

A few weeks ago, I started receiving this message and I'm trying to track down the cause.

Some days I get none and some days I get as many as ten.

I have checked the files with DB Doctor, but no errors are found.

I am using Version 25.1. of OrCAD

Any ideas?

Kevin

Sneak circuit analysis

Shashank — Mon, 01 Jun 2026 07:20:28 GMT

Can we perform sneak circuit analysis or do we have something similar to this in cadence.

How are you creating your testpoints?

John T — Wed, 27 May 2026 11:32:29 GMT

In theory we should have a testpoint for every net. How are you achieving this or coming close? There are multiple different testpoint approaches.

Let us know if you are designing by any of the following:

Testpoints created in the schematic; become single pin surface components on the PCB.
Assigning testpoints manually to specific component pins.
Vias as testpoints with open soldermask.
Other…?

Let us know if you have any problems or advice about how to approach this important part of design using the Allegro/OrCad PCB Editors. We can help the community with any questions on this.

IPC2581 import issue: traces shown as lines. How to convert it to Clines?

BC202603263145 — Tue, 19 May 2026 09:07:31 GMT

Hi,

I imported trace geometry from HFSS to Allegro using IPC2581. After import, when I move the differential pair traces to the Top etch layer, the traces do not get any net name even when placed over pins.

When I query the geometry, the traces are showing as Line objects. But in my other designs, traces are Cline objects.

How can I convert these Line objects into Cline objects?

I would prefer not to manually reroute the traces, as it takes more time and effort.