Cadence Digital Implementation Forum

How to get the resistance per micron of metal layers?

qijianfei — Fri, 24 May 2013 16:24:54 GMT

Dear All,

I need to get the resistance per micron of a certain metal layers. What commands can I use?

I find two commands.

One is "dbLayerRes". There is no manaul for the command. What is the unit of its returned value?

The other one is "getPGNetResis". It mentioned in its manual that the effective resistance between two pins can be returned by the option -psp <x1 y1 layer1 x2 y2 layer2>. How should I use this commond to get the effective R btween two pins? What does x1 or y1 mean?

Best,

qijianfei

Power Stripe - Power Via Generation in Encounter

bsparkma — Wed, 22 May 2013 22:05:36 GMT

I am trying to use a power ring, special routing, and power stripes for my power routing. I can set up the ring, special routing, and stripes correctly as far as location is concerned. However, I am having spacing violations in Encounter (and after exporting to Cadence using oaout) where it places power vias from the top metal down to the special routing during the power stripe insertion. My power rails are max-sized in the cells based on our cell template, but it adds extra metal around the vias, causing these spacing issues.

It seems to be generating the power vias without checking information in the tech LEF. It seems to be disregarding my VIARULE GENERATE DEFAULT statements.

Is there a specific location I can set the power via rules so that the enclosure of metal 1 is smaller?

Thanks,

Brett Sparkman

How to get the loading capacitance of a certain instance by encounter?

qijianfei — Wed, 22 May 2013 20:09:51 GMT

Dear All,

If I know the instant name and its output pin's name. How can I use encounter to get the loading capacitance of that pin? Which command should I use?

Thanks

qijianfei

Getting instance orientation

victory2vicky — Wed, 22 May 2013 11:55:51 GMT

Hi All ,

Is there any command to get the orientation of a instance other than dbGetInstOrient ?

Thanks in advance.

antenna diodes in LEC

kienu — Tue, 21 May 2013 06:41:57 GMT

I am presently seeing antenna diodes in the umapped points(unreachable points) of the revised netllist. How can i do away with these?

thanks

kiran

IC5141 CDL in skipping passive devices

lcaley — Mon, 20 May 2013 20:19:15 GMT

Hello everyone,

I'm trying to import a CDL netlist that contains IO pads and logic into IC5141. The issue I am having is that it skips all of the passive devices within the cell. This particular cell has 3 active MOS devices, 3 diodes, and a resistor. CDL in appears to run correctly, but upon checking the schematic, only the 3 transistors are present. Below is the appropriate snippet of the CDL file, my Device Map file, and my ni.log file. I cannot see any reason for the import process to be skipping the passive devices. Please let me know if any additional information or details are needed.

Thank you!

P.S. I couldn't find a way to enclose the text in a code box, so please excuse the wall of text.

-----------------CDL FILE----------------------

.SUBCKT IDDBREAK VDD VSS VSSIO

*.PININFO VDD:B VSS:B VSSIO:B

RR0 VSS net40 169.876K $SUB=VDD $[RNPPO_SP] $W=500n $L=204.91u

MNM4 VDD net40 net49 VSS NA W=40e-6 L=120n M=4

MNM0 VSS VSS VDD net49 NA W=40e-6 L=120n M=12

DD2 VSSIO VSS DP 2e-11 4.2e-05 M=5

DD0 VSS VSSIO DP 2e-11 4.2e-05 M=5

DD1 VSS VDD DP 2e-11 4.2e-05 M=5

MPM0 VDD net40 VDD VDD PR W=3e-6 L=4u M=12

.ENDS

-------------------DEVICE MAP FILE-------------------------------

devMap := nfet N_11_SPHVT

propMatch := subtype NH

devMap := pfet P_11_SPHVT

propMatch := subtype PH

devMap := nfet N_25_SP

propMatch := subtype NR

devMap := pfet P_25_SP

propMatch := subtype PR

devMap := nfet N_11_SPRVT

propMatch := subtype NA

devMap := pfet P_11_SPRVT

propMatch := subtype PA

devMap := diode DIOP_SP

propMatch := subtype DP

devMap := diode DION_SP

propMatch := subtype DN

-----------------ni.log--------------------------

==========================

Subckt: IDDBREAK

==========================

Created the CV IDDBREAK->netlist_tmp.

#####################################

MOS Instance: MPM0

#####################################

...Searching for a valid mapping in the dev-map file...

...Bingo! Cell mapped to P_25_SP->symbol.

Now, searching for the cellview P_25_SP->symbol in ref libs...

...in umc65sp: Bingo! Found the master cellview: P_25_SP->symbol.

instName->'MPM0' is created.

propName->'subtype'; propVal->'PR' is created.

propName->'w'; propVal->'3E-06' is created.

propName->'l'; propVal->'4E-06' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MPM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM0

#####################################

...Searching for a valid mapping in the dev-map file...

...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM0' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MNM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'net49' of instance 'MNM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM4

#####################################

...Searching for a valid mapping in the dev-map file...

...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM4' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'4' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MNM4' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MNM4' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'net49' of instance 'MNM4' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VSS' of instance 'MNM4' has been connected to the terminal 'B'.

INFO (CDLIN-54): CDL In successfully created the schematic view IO_lib_SP_2_5V_Inline_Reg_VT.IDDBREAK::netlist. Read the log file

'conn2sch_IDDBREAK.log' for more information.

Rail analysis

kasyab — Fri, 17 May 2013 10:28:16 GMT

Hi,

I am trying to set up rail analysis under different conditions (min,max, different levels of activity etc.). In order to be able to analyze results at a later time I would like to utilize a separate state directory each time I run RA. I could not find any switch to go with the set_rail_analysis_mode command to enable this. I see a -work_directory_name switch but I assume this chooses the name for the working directory for each run ('work' in the default 'FE2VSEarlyRA/' directory).

Is there a way to specify an entirely different state directory rather than the default FE2VSEarlyRA?

Kasyab

bottomup flow,how to make submodule ring and stripe can been see in top module

verysmart — Tue, 29 Sep 2009 06:21:32 GMT

in a bottomup design flow , there is a submodule,it has its own power ring and stripe,

when load the submodule to top level, how to make toplevel know the submodule's ring and stripe, so when do Sroute, top level row and stripe will hook up the subblock ring and stripe correctly.

the submodule designed by FLAT Encounter flow with a speical digital library, it has IO row, POWR ring/stripe and core row.

right now I use lef2oa and oa2lef, I can see VDD and VSS pin,but I cannot see the RING and Stripe definition.

can somebody show me how to do this

rc extraction in encounter

berbagci — Tue, 14 May 2013 14:30:33 GMT

Hi,

I'm using encounter for a tape-out. I want to use QRC for higher accuracy. However, I think I need to tell the tool where the executable for QRC is. How do I do that? Modifying PATH variable didn't help. Is there a command to do that?

In addition, I know for static timing analysis, coupling capacitances are not extracted seperately with setExtractRCMode -coupled false command. However, when I do timeDesign with -si option, I see some negative slack. Since the block I'm working on is a timing critical one, I need to make sure timing is accurate. You think I should take signal integrity into account for timing analysis and optimization?

Thanks!

IO filler cell violations power routing

amythpai — Tue, 14 May 2013 08:14:15 GMT

Hello,

I am trying to do the power routing of the IO pads in my design. I connected all the power and ground pins using global net connect command.

globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {}

globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {}

globalNetConnect vdd -type pgpin -pin {VDD} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A0SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A1SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A2SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A3SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A4SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A5SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {A6SRC} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {TRIGGER} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {BOOST} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {REFIO} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {gnd} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {gnds} -inst * -module {}

globalNetConnect gnd -type pgpin -pin {GND} -inst * -module {}

and then executed the Sroute command:

sroute -connect { padPin } -layerChangeRange { M1 M7 } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -checkAlignedSecondaryPin 1 -allowJogging 1 -crossoverViaBottomLayer M1 -allowLayerChange 1 -targetViaTopLayer M7 -crossoverViaTopLayer M7 -targetViaBottomLayer M1 -viaConnectToShape { padring ring }

But I got a lot of open violations on the IO filler cells that I have used in the design. please have a look at the image attached. Can anyone please tell me where I am going wrong

Thank you