Cadence Digital Implementation Forum

Issue while performing signoffTimeDesign in Innovus

VLSI lab IITB — Tue, 13 Jan 2026 11:23:54 GMT

Hello everyone,

I am facing an Issue while executing signoffTimeDesign in Innovus . Once I invoke innovus tool, and run the below commands it works fine.

But , after I source my design and then do signoffTimeDesign , I am getting the following error -

innovus 2> signoffTimeDesign

*info: Tempus executable from /vlsi/cad/cadence/SSV231/tools/bin

**ERROR: (IMPESO-521): Tempus executable '/vlsi/cad/cadence/SSV231/tools/bin/tempus' has the following issue 'did not start', so tool won't be able to run signoff timing analysis.

It will be really helpful if you can please help me in resolving the error.

innovus create offgrid viacuts

Alessadnro — Fri, 19 Dec 2025 10:39:50 GMT

when using innovus, it sometimes create viacuts that are offgrid

the vias themselves are on-grid but the metal around the vias is sometimes offgrid (e.g. it has 0.001um offgrid placements, while the vendor requires things be on 0.005um)

on a small design, they can be fixed by hand, but on a large design the number of issues explode easily in the thousands.

on a large design the set_verify_drc_mode innovus command is not an option, since it is much slower than other DRC checkers (and it often get stuck).

So I would like to do all that it is possible, to have innvous not making the offgrid errors in the first place

1) I think innovus is aware of the grid being 0.005um, as most of the shapes generated are on a 0.005um grid. But I am not 100% sure
Is there a command to set (or get) the grid spacing in innovus?

innovus seems to have a grid command, but I cannot find the usage in the manual nor in the various Cadence training
even the -help option is not helpful
(so I am not sure if it is indeed defining the grid)

innovus 5> grid -help
wrong # args: should be "grid option arg ?arg ...?"

2) alternatively, is there a an innovus command to "extend" (e.g. overlapping an additional piece of metal) the offgridshapes, so that they snap on grid?

thank you

Power and Net Area Discrepancies in Joules When Analyzing PR Netlists Across Different Tool Versions

QJ202512045614 — Thu, 04 Dec 2025 11:46:55 GMT

Dear Cadence Community,

Recently, our company upgraded Joules from version 22.17 to 23.14. While performing power analysis on the final place-and-route (PR) netlist of a project, I noticed a significant difference in the area and power reports between these two versions.

In Joules 22.17, the area report includes a non-zero Net Area value, and the report clearly states:

Interconnect mode: global.

However, in Joules 23.14, that line no longer appears. Instead, the report shows:

Wireload mode: enclosed,

and—more critically—the Net Area is consistently reported as zero.

This change directly impacts power estimation: the total power reported by Joules 23.14 is noticeably lower than that from 22.17. Based on silicon measurements from the actual chip, the power estimate from Joules 22.17 aligns much more closely with real-world behavior.

Therefore, I would greatly appreciate your guidance:

Are there specific TCL commands or startup options in Joules 23.14 that can restore the net-area calculation behavior (e.g., re-enable global interconnect mode) to match that of version 22.17?

Our goal is to obtain a more accurate power estimate consistent with prior results and silicon validation.

Thank you very much for your time and support!

Best regards

Procedure in Innovus common UI to generate scripts for placement

nrk1 — Fri, 31 Oct 2025 04:33:30 GMT

In an older Innovus version (152), the following lines were executed before placement. pnrflow/ was generated in innovus using "writeFlowTemplate -directory pnrflow"

./pnrflow/SCRIPTS/gen_flow.tcl all
make init

In the new common UI, "writeFlowTemplate" is replaced by "write_flow_template" according to the manual (foundation flows guide). When I run "write_flow_template -directory scripts" it generates the folder scripts/ and scripts/flow with the following content. How do I proceed? Web search points to a script "scripts/run_flow.tcl" as the equivalent of gen_flow.tcl, but no such script is generated in my case. Basically I need to equivalent of "gen_flow.tcl" and "make init" mentioned above.

scripts> 291: ls
design_config.template eco_config.template flow.yaml_template innovus_config.template setup.yaml_template
dist.py* flow/ flow_config.template metric_config.yaml
scripts> 292: ls flow
common_flows.tcl common_steps.tcl innovus_steps.tcl

=====

Innovus version info:

Version: v21.18-s099_1, built Tue Jul 18 13:03:50 PDT 2023
Options: -stylus

=====

Thanks

Nagendra

"Undefined scan chain" error during Innovus `place`

GS202507021424 — Thu, 16 Oct 2025 15:58:29 GMT

I'm trying to run a RocketChip (rv64gc) design through the Genus/Innovus synth+place&route flow (with gpdk045 as the underlying technology), and running into a "scan chain" related issue during Innovus place (and subsequently cts). During place, I get this error:

    [check_scan_connected]: number of scan connected with
        missing definition = 5267, number of scan = 18274,
        number of sequential = 27937, percentage of missing
        scan cell = 18.85% (5267 / 27937)
    **ERROR: (IMPSP-9099): Scan chains exist in this design
        but are not defined for 18.85% flops. Placement and
        timing QoR can be severely impacted in this case!
    It is highly recommend to define scan chains either through
        input scan def (preferred) or specifyScanChain.

If I ignore this and continue by running cts, I then get this error:

    **ERROR: (IMPCCOPT-1349): Clock tree clock connects to 5 module(s)
        without definitions in the netlist.
    ...
    **ERROR: (IMPCCOPT-2196): Cannot run ccopt_design because
        the command prerequisites were not met. Review the previous
        error messages for more details about the failure.

Synthesis (with Genus) completes error-free, for whatever that's worth...

I suspect that this is somehow related to the RocketChip's debug interface, which has its own independent debug_clock and a few additional *reset signals:

    module ExampleRocketSystem(
      input         clock,
      input         reset,
      input         resetctrl_hartIsInReset_0,

      // debug interface:
      input         debug_clock,
      input         debug_reset,
      output        debug_clockeddmi_dmi_req_ready,
      input         debug_clockeddmi_dmi_req_valid,
      input  [6:0]  debug_clockeddmi_dmi_req_bits_addr,
      input  [31:0] debug_clockeddmi_dmi_req_bits_data,
      input  [1:0]  debug_clockeddmi_dmi_req_bits_op,
      input         debug_clockeddmi_dmi_resp_ready,
      output        debug_clockeddmi_dmi_resp_valid,
      output [31:0] debug_clockeddmi_dmi_resp_bits_data,
      output [1:0]  debug_clockeddmi_dmi_resp_bits_resp,
      input         debug_clockeddmi_dmiClock,
      input         debug_clockeddmi_dmiReset,
      output        debug_ndreset,
      output        debug_dmactive,
      input         debug_dmactiveAck,

      // mem_axi4_0 64-bit data width AXI (master) port;

      // mmio_axi4_0 64-bit data width AXI (master) port;

      // l2_frontend_bus_axi4_0_axi4_0 64-bit data width AXI (slave) port;

      input  [7:0]  interrupts
    );
      ...
    endmodule

In the .sdc file for Genus (synthesis), I have designated clock as the clock signal (using create clock -name "clock" -period ...), but I'm unsure of whether (and how) to deal with the debug_clock signal, or if that's even the way to address the subsequent "scan chain" errors I get during place...

Any clues, tips, or pointers much appreciated!

Skewing of sink pins at post route

PN202510149547 — Tue, 14 Oct 2025 14:26:18 GMT

Hi ,

In my design, the clock tree looks good up to the routing stage, and I want the tool to preserve it as-is. However, during the post-route optimization phase using:

opt_design -post_route -report_dir reports -report_prefix postroute -setup -hold

I noticed that the tool inserts a significant number of USKC cells, which disrupts the clock path and introduces considerable skew, leading to numerous hold violations. My intention is to prevent the tool from modifying the clock tree or altering the skew at sink pins.

I attempted to preserve the clock tree after CTS by applying the following constraint:

set_db skew_group:<skew_group_name> .cts_skew_group_constrains all

Unfortunately, this approach didn’t work, and the post-route stage still modified the existing clock tree.

".tch" file for QRC extraction of RC corners in MMMC.VIEW file.

GS202509267745 — Fri, 26 Sep 2025 11:43:09 GMT

Greetings of the day !

I have designed an SPI ( Serial Peripheral Interface) Module using TSMC65nm technology in Cadence Innovus. At last during the Sign-Off stage I am checking for Slack values (WNS/TNS) by clicking on the timing report. After the execution of this I'm getting an error saying "Extraction failed because *Quantus QRC* is not specified for all RC corners in MMMC file, this is mandatory for medium or high or signoff effortLevel postRoute extraction. If all files are unavailable, set 'setExtractRCMode -effortLevel low'. Ideally specify the technology file for each RC corner using the -qx_tech_file option of the create_rc_corner or update_rc_corner commands."

This error actually is due to the missing referencing to the ".tch" file in *MMMC.VIEW* " file, which is being loaded during design import in Innovus. I have searched for this .tch file everywhere in the TSMC 65nm technology bundle, but could not find it. However, for gpdks this .tch file is clearly available.

Kindly help me in knowing where this .tch file is accessed from for tsmc65nm technology or is it specified with some other name in the technology folder.

Thanks & regards,

Dr. Garima Shukla.

ecoChangeCell

MA202509235119 — Tue, 23 Sep 2025 11:06:13 GMT

Hi, I’m new to using Innovus and I’m trying to rename a submodule called “abc” to a new submodule "abc2" with the same ports in a netlist. The structure looks like this: top/u_abc. I need to change the module name of “u_abc” from “abc” to “abc2”. I’m trying to use ecoChangeCell with “top” set as the top_cell, but I can’t proceed because “top/u_abc” isn’t identified as an instance (it’s in hinsts). Can anyone help me with this?

Hi, How virtual clock latency is getting updated after Clock tree synthesis stage and what parameters does it consider to update that latency?

MS202509109551 — Thu, 11 Sep 2025 02:28:46 GMT

How to create tech file (.tch) and captable file (.capTl) if we have .ict files from foundry

Keththura — Tue, 09 Sep 2025 20:25:16 GMT

I am trying to learn the implementation of a Digital design. I am following Cadence-RLT-to-GDSII course. But I am using my own pdk which is TSMC 65nm.
I am unable to file the Tech files and Captable files. I found in this forum that we can generate tech file from .ict files using Techgen.
But unfortunately, I don't know how to generate it. Can someone help me on this.

I really appreciate your help on this matter.

Thanks & regards,
Keththura

Timing Differences seen between Innovus & Tempus

AD20250812946 — Mon, 08 Sep 2025 03:27:28 GMT

Hi Experts ,

I see the following timing differences between Tempus & Innovus .

The path which is matching in Innovus but failing in Tempus .

Pasting the headers of both the reports :

Tempus : Failing

Path 1: VIOLATED (-0.0222 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D

View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0_rcmax

Group: jtag_tck

Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK

Clock: (R) jtag_tck

Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D

Clock: (R) jtag_tck

N-Sigma: 4.5000

Capture Launch

Clock Edge:+ 0.0000 0.0000

Src Latency:+ 0.0196 ( 0.0196, 0.000) 0.0079 (0.0079, 0.000)

Net Latency:+ 0.3363 ( 0.3298, 0.001) (P) 0.2755 (0.2813, 0.001) (P)

Arrival:= 0.3559 ( 0.3494, 0.001) 0.2834 (0.2892, 0.001)

Hold:+ 0.0284 ( 0.0201, 0.002)

Uncertainty:+ 0.1400

Cppr Adjust:- 0.0392 ( 0.0323, 0.002)

Required Time:= 0.4852 ( 0.4773, 0.002)

Launch Clock:= 0.2834 ( 0.2892, 0.001)

Data Path:+ 0.1685 ( 0.1856, 0.004)

Slack:= -0.0222 (-0.0025, 0.004)

Path 1: VIOLATED (-0.0222 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D
View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0_rcmax
Group: jtag_tck
Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK
Clock: (R) jtag_tck
Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D
Clock: (R) jtag_tck
N-Sigma: 4.5000

Capture Launch
Clock Edge:+ 0.0000 0.0000
Src Latency:+ 0.0196 ( 0.0196, 0.000) 0.0079 (0.0079, 0.000)
Net Latency:+ 0.3363 ( 0.3298, 0.001) (P) 0.2755 (0.2813, 0.001) (P)
Arrival:= 0.3559 ( 0.3494, 0.001) 0.2834 (0.2892, 0.001)

Hold:+ 0.0284 ( 0.0201, 0.002)
Uncertainty:+ 0.1400
Cppr Adjust:- 0.0392 ( 0.0323, 0.002)
Required Time:= 0.4852 ( 0.4773, 0.002)
Launch Clock:= 0.2834 ( 0.2892, 0.001)
Data Path:+ 0.1685 ( 0.1856, 0.004)
Slack:= -0.0222 (-0.0025, 0.004)

Innovus : Meeting

Path 1: MET (0.027 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D
View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0
Group: REG2REG
Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK
Clock: (R) jtag_tck
Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D
Clock: (R) jtag_tck
N-Sigma: 4.500

Capture Launch
Clock Edge:+ 0.000 0.000
Src Latency:+ 0.187 (0.187, 0.000) 0.187 (0.187, 0.000)
Net Latency:+ 0.382 (0.373, 0.002) (P) 0.339 (0.346, 0.001) (P)
Arrival:= 0.569 (0.560, 0.002) 0.526 (0.533, 0.001)

Hold:+ 0.029 (0.019, 0.002)
Uncertainty:+ 0.140
Cppr Adjust:- 0.025 (0.016, 0.002)
Required Time:= 0.714 (0.704, 0.002)
Launch Clock:= 0.526 (0.533, 0.001)
Data Path:+ 0.201 (0.223, 0.005)
Slack:= 0.027 (0.052, 0.006)

I see a huge difference between clock latencies in both the reports.

Any comment/ Suggestions .

My timing is badly failing in Tempus .

Thanks

addRing creating rings outside design boundary

TA202503121730 — Sat, 30 Aug 2025 03:41:26 GMT

It seems that there is a glitch involved with creating the power ring.I set the floorplan with floorPlan -d $TOP_macro_sizex $TOP_macro_sizey 0.612 0.612 0.612 0.612 -noSnapToGridThis sets the core and IO boundary properly and I can see the accurate measurements in the GUI.However, when I create the power ring using addRing -nets {VDD VSS} -type core_rings -follow core \
-center 0 -layer {top M8 bottom M8 right M9 left M9} -width 0.04 -spacing 0.04I receive this error,**WARN: (IMPPP-220): The power planner does not create core rings outside the design boundary. Check the design boundary, or specify valid offsets.
**WARN: (IMPPP-4051): Failed to add rings, because the IO cells might contain gaps. Run the 'addIoFiller' command to fill gaps between the cells and try again.When I change the -follow flag to io , Innovus creates a ring that is 1.0um away from the core boundary on all sides.

gsclib045 data sheet available?

FG202508072745 — Mon, 18 Aug 2025 14:37:26 GMT

While we were able to obtain all the required implementation views and reference manual for the gsclib045 example stdcell library, I was unable to find a data sheet that explains the individual cells. Specifically, I'd like to know about the syntax of the various flip flop types - e.g., a SDFFRHQX1 is probably a Scannable D-FF with Reset, but what does the (H)Q suffix mean? I could not find an explanation of this anywhere.

Any help is greatly appreciated.

Issue about using SkyWater130 and Genus

SR202412023415 — Fri, 08 Aug 2025 22:07:39 GMT

Hey all,

I am trying to synthesize a design using Cadence Genus with SkyWater 130. Although the synthesis does not report any issue, when I try to simulate the gate-level netlist using XCELIUM, it gives me all X's for all the signals.

I appreciate your help in advance for any insights.

Best regards

Residual power in whole design vs summed gate groups in Joules, even with full instance coverage

SR202412023415 — Wed, 06 Aug 2025 21:08:10 GMT

Hi everyone,

I'm running power analysis in Joules (Version v21.19) using simulation-based activity from a VCD file for a purely combinational design (ISCAS-85 c432). To understand the power contribution of different parts of the circuit, I split the gate-level netlist into two groups: odd and even gates, Based on their gate IDs (i.e., simply splitting them). Every single cell instance in the netlist is assigned to exactly one of these two groups; there is no gate left unaccounted for.

I then use Joules to compute:

Power of the entire design
Power of just the odd gate group
Power of just the even gate group

At key simulation times (e.g., 21 ns, when input vectors change), I observe a significant difference between:

Total power reported by Joules vs. Sum of power of `odd` and `even` gate groups

For example, at 21 ns:

Whole design power = 0.000438382069755 W
Odd group power = 0.000196574924795 W
Even group power = 0.000208780383976 W
Residual = ~33 µW

Despite confirming that:

All cell instances in the design are included across both groups
There are no flops, clock trees, or unlisted primitives
The switching activity is fully captured from gate-level simulation
There is no sequential logic or memory macro in this design

I still observe this non-zero residual power.

My questions:
1) Where is the extra power coming from in the "whole" design that is not reflected in the sum of gate groups?
2) Is Joules attributing interconnect (net-level) switching power or glitching activity separately from gate instance power?

I also observed these results even in other designs.

I appreciate your help in advance.

Best regards,
Saeid

You can find the commands that I am calculating the power:

read_stimulus -file [getenv VCD] -dut_instance /c432_tb/dut -frame_count [getenv FRAME_COUNT]

power_map

compute_power

set vcd_filename [file tail [getenv VCD]]

set trace_basename [file rootname $vcd_filename]

# Generate the power report and PNG with unique filenames

report_power -out "${trace_basename}.data"

compute_power -mode time_based

plot_power_profile -format png -unit W -out "${trace_basename}.png"

DRC Violations due to Macro Placement and Power Straps in Innovus Stylus Flow

XL202501136611 — Thu, 31 Jul 2025 16:17:23 GMT

I have a working Genus + Innovus Stylus 21.1 for a design. But now, instead of flattening everything, I need to turn one of the modules into a macro and place it in my top level.

I limit macro's top layer to be M5, with a pair of horizontal on M4 and a pair of veritcal straps on M3, all with pg pins.

In the original top-level flow, there are power straps on M2, M3, and M4 layers, and I didn't change it.

I placed the macros using:

set_db $inst .location [list $x $y]

set_db $inst .orient R0

set_db $inst .place_status fixed

The problem is that there are many SHORT and SPACING DRC violations at the power straps of top level.

This is the placement view diagram.

This is the DRC report.

What could be causing the problem and how should I resolve it?

Here are the several directions I was thinking about:

1. Adjust power strap layers of either macro or top-level (my attempts caused some errors)

2. Add blockages around macros (not sure which command to use in the stylus flow, I used setobjfplanbox in a non-stylus flow which didn't have any problem, but it doesn't exist in stylus)

2. Aligning power strap in macros with top-level power straps, or increasing spacing between top-level power straps to leave room for macros (but it is unpractical if I need to place more macros.

Could any please point me to the right direction? And some classic example scripts or flow or implementation would be perfect. Thank you

How to manage block-level and top-level SDC constraints?

MichR — Wed, 30 Jul 2025 10:52:50 GMT

I am currently facing some issues trying perform a hierarchical implementation of a chip with Cadence tools, particularly on how to manage timing constraints.
The chip includes a few digital blocks which are independently synthesized with block-level constraints (with multiple modes defined), while their size and position in the chip is defined by the top-level partitioning, which also pushes down top-level constraints.

Let me detail the steps I follow in my flow.

Block synthesis script (for the synthesis of each digital block) in Genus:
1. Synthesize the block design with block-level constraints (having multiple modes defined)
2. Output the netlist, and the updated constraints with write_mmmc command

Top level script (for partitioning) in Innovus:
1. Import digital block netlists from previous Genus script.
2. Create the top level floorplan, place the macros and define the digital partition area, run power routing (rings and stripes)
3. Push down top level constraints to the digital partitions with deriveTimingBudget and saveTimingBudget commands. Then, commit the partitions.
4. Route the partition signals to each others and to the macros, then save the design.

After this, I would like to implement (PnR) the block in Innovus by loading the generated partition, the pushed-down constraints and the block-level constraints. However, I don't understand how should I merge the top-level constraints (generated by saveTimingBudget) with the block-level constraints (generated by genus starting from my original hand-written sdc). In particular, at this step, I find myself with:
- top-level constraints which are automatically loaded when I load the partition in Innovus, defining two modes: one for setup and one for hold (despite the fact that I defined only one in my top-chip level script for both setup and hold!)
- block-level constraints generated by genus, which are associated with different modes

Is this flow the correct one for hierarchical implementation? The Innovus User Guide is not very clear about how to perform synthesis and how to manage the constraints.

For managing the constraints, should I promote them to top-chip level and run an Innovus partitioning again or should I instead merge the block-level ones in the Innovus partition during PnR?

I patiently wait for help. Thank you

Min Pulse Width Violation

SG20250716916 — Thu, 17 Jul 2025 05:22:50 GMT

How do we address if there is a Minimum Pulse Width violation in the design?

Congestion at Routing Stage

SG20250716916 — Thu, 17 Jul 2025 05:10:47 GMT

I'm seeing congestion at the routing stage. I'd truly appreciate it if someone could guide me on what my approach should be and which things I should take care of to address this congestion issue at the routing stage.

Thanks.

Foundation flow stylus

VK20250620161 — Tue, 15 Jul 2025 05:47:01 GMT

Hi Guys,

I am new to entire cadenced tool set,working for a project where i have to primarily use foundation flow scripts to construct basic flow for rtl to gds.I have explored on write_flow_template,assuming stylus will only be used,it appears to be .yaml based,not make flow !! how to start with what files to be edited and cosntruct basic flow.Highly in need of sugegstions.

INNOVUS: connect internal power nets between hard macros

PK202501238151 — Sun, 13 Jul 2025 20:08:35 GMT

I have a design with two hard macros, where one of the macros creates internal supply voltages for the other. In the synthesized netlist, the respective pins (e.g. VQQ) are connected to common nets. In the place&route script I initialize the nets as power nets:

set_db init_power_nets "w_VQQ"

During floorplanning, I add stripes on various layers and nets and run route_special:

add_stripes \
    -direction horizontal \
    -width 2.5 \
    -spacing 1 \
    -nets {w_VQQ} \
    -set_to_set_distance 5

route_special \
    -nets {w_VQQ} \
    -connect { blockPin } \
    -block_pin all \
    -block_pin_target {stripe block_pin } \
    -allow_layer_change 1

I can see that they correctly connect to the global power nets in the macros. However, the local/internal nets are not being touched. I get the following warning:

**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of the w_VQQ net were not found in the design. Check netlist or change the parameter value to include block pins in the design.

I don't understand this warning. I checked the netlist, the net is definitely there with that name. However, the name of the pins is different, it is simply VQQ (without w_).
Additionally, I'm unsure what the second part of the message means. Which parameter value needs changing and why are the block pins not included in the design?

I'm using Innovus (Common UI) 21.17, any help is appreciated.

Kind regards,
Patrick

Tracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus

SR202412023415 — Fri, 27 Jun 2025 19:39:11 GMT

Hi Cadence Community,

I'm using Genus 21 to synthesize a design and need help with two goals:

Tracing gates to RTL lines: I've set set_attribute hdl_track_filename_row_col true, which enables RTL source tracking in report_gate -source. This attribute set works, but I want get the information about each gate that they came from which line of my RTL code.
Preserving module info in gate names: After flattening with ungroup -flatten -all, I want gate names to reflect their originating modules. I tried set_attribute hdl_flatten_naming_style module_path, but got an error: "Invalid attribute name [TUI-40]". Is this attribute unsupported in my version, or is there an alternative to embed module names in a flattened netlist?

My script includes write_hdl -source > ${design}_RTL_track/netlist_final/${design}_syn.v for writing netlist. Thanks!

Synthesizing Specific Gates in Cadence Genus

SR202412023415 — Mon, 16 Jun 2025 21:33:30 GMT

Hello Cadence Community,

I'm working on a flattened netlist in Cadence Genus for a design and would like to apply targeted synthesis optimizations to a specific list of gates (e.g., g1234, g5678) while keeping the rest of the design unchanged. Is it possible to synthesize or optimize only these gates, and if so, how can I achieve this?

My current synthesis script uses commands like syn_generic, syn_map, and syn_opt, but these seem to reprocess the entire design, which I want to avoid. I'm using the NangateOpenCellLibrary_slow_ccs.lib library and have a list of gate names. Ideally, I'd like to apply optimizations such as using different cell types or adjusting attributes only for these gates.

Any guidance on commands (e.g., set_attr, incremental synthesis) or script modifications would be greatly appreciated. Thank you!

Best regards

Cadence Genus: Submodule synthesis and reuse and integrate it in top module

XH202505277146 — Sun, 08 Jun 2025 16:29:20 GMT

I'm currently working on a large RTL design using Cadence Genus, and I'm running into some issues with hieratical synthesis and submodule resue.

My goal is to synthesize submodules independently, save its results and later reuse it during top-level synthesis to save runtime and memory resources. Here is what I tried, I firstly used "create_derived_design" to promote the submodule instance to a top-level design, ran synthesis and save result using write_db. Then, read the .db file in my top-level flow.

read_db submodule.db
read_hdl top_module.v
elaborate top_module

However, in some attempts, Genus treated the submodule as a black box. I checked the documentation, but it doesn't clearly explain whether write_db/read_db is fully supported for partial module reuse like this. Did I miss any steps? If write/read db is not supported for partial module resue is there any other method that I can use alternatively?

in VSVN netlist getting error , i am using mlcv swicth

SM20250402327 — Wed, 28 May 2025 12:15:53 GMT

Hi,

I am running mlcv switch in VSVN netlist, Ia m doing in batch mode, for single lib,cell,view i am not getting error, for mlcv only i am getting this , this is a new feature from cadence

the error is *Error* deleteDir: directory not empty - "my own rundir path "

am i need to use extra SKILL code for this

Thanks

Shaik Sharif