Cadence Functional Verification Forum

how to reduce explored

BharathECE — Wed, 22 May 2013 05:36:08 GMT

Hi,

Iam using IFV for formal property checking and i have some of the assertions/Property explored.How to make them either pass/fail.

Thanks

Bharath

IFV Dead code check fail

BharathECE — Mon, 20 May 2013 07:38:58 GMT

In Formal properyty checking deadcode assertions and property getting failed.What is the meaning of these getting failed.How we can pass them.

How to debug this

ncelab ncutilities E,BUILDF

lucacenzato — Fri, 17 May 2013 15:06:24 GMT

Hi all,

Switching from release 10 to 12.2, I've found some problem with testbench which uses nc utilities.

ncelab (version 12.2) with option "-update" exit with :

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

Updating: package NCUTILS.NCUTILITIES (AST)

/cadence/IS12.2/tools/inca/files/NCUTILS.src/ncutilities.vhd:

ncvhdl_p: *E,DLPAKW: Attempt to write package ncutils.ncutilities (AST)

into a read-only library.

errors: 1, warnings: 0

ncupdate: *E,BUILDF: Rebuild of unit package NCUTILS.NCUTILITIES (AST) failed.

entity worklib.tb_ncutil (AST) is already up to date.

ncelab: *F,DLUPFL: Update failed for entity WORKLIB.TB_NCUTIL (AST)

(unable to update).

---------------------------------------------------------------------------------------------------------------------------------------------------------------------

I didn't find clues on the web or in the docs,

Thanks,

Luca

specman clock

hellohi — Sat, 04 May 2013 11:26:57 GMT

i need to use specman clock for the simulation in standalone mode instead of DUT clock. I read about si_util_time_mgr in a cadence newsletter.

http://www.cadence.com/newsletters/incisiveplatform/incisive_q406.pdf?CMP=NLC-TD5628415825

But it is not working. Is it possible to get a specman clock to handle the timing in the verification environment? Please help on this

FSM coverage (RTL from CtoS)

GiuseppeDG — Fri, 10 May 2013 21:43:31 GMT

I am trying to measuring FSM coverage of RTL code that tis generated with CtoS and co-simulated with its original TLM testbench (CtoS generates some wrappers for doing that).

I am passing -COVFILE covfile.ccf as an argument of ncsc_run. The covfile contains:

select_coverage -all -instance sc_main.channeldownsampleCb.tlm_instance.m_dut_vlog

at the end of the simulation I can visualize toggle and block coverage (iccr) but not FSM coverage.

During simulation I get the warning:

ncsim: *W,COVUSC: Unsupported SystemC module (worklib.sc_main) specified for coverage

What is my error?

Cadence lint HAL tool

LINT — Fri, 10 May 2013 09:22:15 GMT

CG cell is not detected as gated clock, can u help me?

i hv tried with below setting, but it didn't work....

params GTDCLK {identify_clock_gating_cell="no"}

ATPG for RTL

GiuseppeDG — Wed, 08 May 2013 16:29:43 GMT

Does Cadence provide any ATPG for RTL descriptions? The goal should be to maximize some coverage metrics (e.g., toggle, block).

Warning in Toggle coverage exclusion

nenu09 — Tue, 07 May 2013 09:24:08 GMT

Hi ,

I am getting the following warning when trying to exclude toggle coverage.

ncelab: *W,PSEFDM: The pattern "sig_1" specified on line 7 of file "toggle_exclude.cf" did not result in exclusion of any signal(s).

I am loading the exclude file by set_toggle_excludefile -bitexclude toggle_exclude.cf

There is no recursive exclusion of same signal . Also deselect_coverage option is not used . Still I am getting the warninig . But in the report the bit is excluded . Please help .. Thanks in advance ..

UniPro eVC integration

PeterSVerif — Thu, 02 May 2013 08:53:17 GMT

Hi,

I'd like to integrate the CDN UniPro eVC to a verification component, that will be reused multiple times. I noticed that each layer in the UniPro stack communicates upwards and downward via method ports. My idea is to reuse the upward method-ports of the transaction layer to communicate with the UniPro eVC (drive, monitor the UniPro operation from a higher layer). To do so , I need to know the definition of the method-type of each port, but I could not find it in the documetation of the eVC.

Is there a way to get information about those method ports?

Can you suggest better way to integrate the UniPro eVC?

Best Regards,

Peter

ncsim -out directive

affaqq — Tue, 30 Apr 2013 16:40:21 GMT

Hi,

I created a sub-directory inside the main directory where I am invoking Incisive to dump all the files generated using "-out" argument. In my design, I need to pick values from a certain file from the main directory. Now the ncsim looks for that file into the sub-directory I have created and obviously its not there. Is there any way to specify such argument in the Makefile attached alongwith?