Cadence Logic Design Forum

finding average,dynamic, static power

PSASWALE — Wed, 22 May 2013 10:19:24 GMT

I have design the full adder with different style in virtuoso(cadence). I want to find the power consumption of the same. I have downloaded some manual in which different methods are given to find the power. but I am getting different values for each method.

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I am using following method:

virtuos Analog Design environment window select OUTPUT ..> saveall.

In save all options enable all options.

Run simulation.

In waveform window select Browser..> results...> open results , then Select Waveform Data base window will open ,here select psf file. In left side of waveform window we can observe a browser. In browser doble click on tran option

Here we can have current , voltage and power signals at various parts of the design.

Double click on pwr option. Then we can observe wave of power signal in waveform window.

select pwr signal and do as follows to get avg power

In Waveform window goto TOOL option open calculator.

In calculator go for Functional panel select average function and then clik on evaluate button.

The obtained value is the average value.

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But If we measure the power using formula then I am getting different values.

Please guide me on this topic.

I am a student.

cell_leakage_power

msanyal — Fri, 17 May 2013 16:20:34 GMT

Does Encounter use default "cell_leakage_power" in the library cell for calculating leakage, or does it use the state-dependent leakage power provided in .lib?

Scan mode and scan chain control from internal registers

Sinjeetp — Sat, 27 Apr 2013 01:25:43 GMT

Hi,

I have unique requirement that scan mode be set by internal register which would control output at PO. By default PI/PO which drives scan are set for something else. Before scan starts, I need to set register to a proper value so PI and PO controls inserted scan chain. I do know that there exist a way to have tester drive the Register interface to drive PI to set registers to desired value. What I do not now how to generate such pattern that tester understands and how to include them in initialization sequence.

Thanks,

Sinjeet

How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler

lvcargnini — Tue, 14 May 2013 15:23:59 GMT

Hello all,

Please I would like to use my Encounter RTL Compiler, later the EDI, to place the parallel synthesis into a HPC cluster. I understand that for this purpose I must use Super-Thread, and that I must configure it using:

set_attribute super_thread_servers {machine_names} /

In this stage I already have some issues, shouldn't I use only the keyword batch instead of the node machines ?

Second, I don't have and won't have rsh access to the nodes, and they use Tivoli workload to control the access and jobs launching into the HPC.

If I understand well, I should use:

rc:/> set_attribute super_thread_batch_command {llsubmit .....} /

rc:/> set_attribute super_thread_kill_command {llkill ....} /

So how do I properly configure it for Tivoli queue commands.

Last how to set the number of CPUs ? using set_attribute ? command line there is something like -lsf_cpus 4, into tho attributes how to do that, instead of placing X times the machine or bactch into super_thread_servers variable.

Best Regards,

Vitorio.

Exclude Paramter name/value during module generation in LEC

Rafeeq2129 — Fri, 10 May 2013 10:05:16 GMT

Hi,

I'm using Conformal LEC to match RTL vs Netlist (synopsys's DC generated).

Our requirement is just to use Uniquification numbers for same modules, and do not require tool to append parameter names/values for the generated modules. The generated netlist has been generated as expected.

But , Is there a way in Conformal LEC to exclude Paramters(name&value) while generating module name ?

regards,

rafeeq

Two warnings(external_delay and CSA rejected)

20050710212 — Wed, 08 May 2013 12:47:14 GMT

There are two kind of warnings always happened during synthesis. I checked them in the user manual but I do not know how to solve them.

1. The following primary outputs have no clocked external delays. As a result the timing paths leading to the ports have no timing constraints derived from clock aveforms. The'external_delay' command is used to create new external delays.
/designs/FIFO/ports_out/dataout[0]
/designs/FIFO/ports_out/dataout[10]
/designs/FIFO/ports_out/dataout[11]......

2.There is 1 CSA group in module 'FIFO_csa_cluster_33'... Rejected. Somtimes it is accepted. sometimes it is rejectd. What is CSA group?

Could you please give me some advieces to fix these problems?

Thank you very much.

How do I delete clock groups (created via set_clock_groups)

moogydmaxim — Fri, 03 May 2013 19:14:42 GMT

Hi,

I have been using set_false_paths between clocks, and found out that it is better to use clock groups using set_clock_groups. Therefore, I updated my SDC files, but I now have a slight issue.

I use RTL compiler to do some sanity checks of SDC prior to handoff. In pseudo code

read netlsit

for sdc in func1.sdc func2.sdc scan.sdc loop

reset_design

read_sdc

timing lint, timing reports etc

write_sdc -strict

endloop

Previously, this has worked well, but it seems that clock_groups cannot be deleted. In the above, reset_design leaves the clock groups untouched, therefore my exported SDC files have clock groups for clocks that may not exist.

As an experiment, I also rm /design/my_design and reloaded - the clock groups were still not deleted !

Any ideas?

Thanks,

Steven

module naming with hexadecimal values

Rafeeq2129 — Wed, 24 Apr 2013 07:19:39 GMT

Can anyone help me with the command for LEC-XL to generate modules with Hexadecimal values (instead of Decimal) of inputs signals ?

Example :

1.) add #( x(23) , y (1'h0) , z(1)) (.clk (clk) .reset(rst))

LEC output : add_x23_y0_Z1

2). applied renaming rule : set naming rule -parameter "_"

LEC ouput : add_23_0_Z1

3). Desired output : add_23_000000_Z1

Command required to generate module name as above .

regards

rafeeq

Command to Store, Restore a RTL Compiler session

beginer — Sat, 02 Mar 2013 04:48:34 GMT

Are there commands similar to synopsys's save_session and load_session in RTL Compiler.

RTL Compiler: VCD Annotation and CPF

moogydmaxim — Tue, 23 Apr 2013 08:20:26 GMT

Hi,

In RTL compiler, I have successfully used the following flow

- Read Verilog Netlist

- Read VCD Annotation Data between times t0 and t1 (Chip "Active")

- Report Power for "Active"

- Reset Design

- Read VCD Annaotation Data between times t2 and t3 (Chip "Standby")

- Report Power for "Standby"

This has worked succesfully and reported "Active" and "Standby" power is as excpected

I am now trying to improve the flow by reading the CPF file, which defines the power modes. So, now I attempting to report power for each power mode, whilst also including the VCD annotation data.

Unfortunately, this does not seem to work. As far as I can tell, the VCD annotation data is not being used in the power calculation such that the power is the same in both "Active" and "Standby".

Has anyone used this flow? Should it work?

Thanks,

Steven