Cadence IC Packaging and SiP Design Forum

Electrical Net Classes Import Using technology file (.dcfx, .tcfx)

AnanthVedalaLM — Tue, 24 Feb 2026 20:57:17 GMT

I'm trying to import The net classes in APD from a technology file with extension (.dcfx and also tried with .tcfx) The spacing and Physical Netclasses are being imported but not Electrical Net Classes, is there any default setting that we need to change in the APD Constraints Manager or is there any other issue

FAQ about Net resistance in APD+ and Allegro

JuanCR — Mon, 26 Jan 2026 19:01:49 GMT

Here are some frequently asked questions regarding Net Resistance in Allegro PCB Editor and Advanced Package Designer:

What does the net resistance include?

Net resistance includes traces, shapes, and ratsnest only. For the complete net with vias and other objects, you need to use SIGRITY tools for elaborate power analysis.

What thickness is used to calculate traces, ratsnest, and shapes?

The thickness of the layer where they are routed will be used for traces and shapes. For ratsnest, parameters defined in "Unrouted Interconnect Models" will be used.

What trace width is used in the calculation? Does this come from the cross section or from the width that is actually in the design?

The actual width of the trace will be used.

What is the conductivity or resistivity that is used? Is it the conductivity of the material for a given layer?

Yes, it is the material's conductivity for a given layer in the cross-section.

What other questions do you have about this topic? Leave them in the comments below.

While opening *.mcm file in APD 2023

AM202601203416 — Wed, 21 Jan 2026 09:33:14 GMT

While opening files in APD, getting error SPMHOD-29.. which read unable to open design. design compatibility log says "This design was last saved with: apd 24.1 P001 - 9/4/2024".. How fixed this issues.

How to create soldermask at pins in APD+ and set up soldermask-to-soldermask spacing DRC

SaiPavanl — Fri, 16 Jan 2026 17:17:52 GMT

When I try to create a soldermask for pins of BGA or DIE pad using the Create Bond Finger Soldermask command, I cannot choose the Pins object in Find Filter. I can choose only Finger and Vias.

How can I create soldermask at pins in APD, and how can I set the DRC for the soldermask-to-soldermask spacing for the pin?

Follow the steps given below to create soldermask at pins in APD:

1. Open Allegro Package Designer+ and go to Setup > User Preferences

2.Enable the icp_soldermask_allow_pins variable by going to Ic_packaging > Early_adopter.

3.To create soldermask for pins, go to Manufacture > Create Bond Finger Soldermask.

4. Choose Pins in the Find Filter window.

5.Select the pins to create soldermask. To have an option for checking soldermask spacing, change Class/Subclass in the Options pane from Substrate Geometry – Soldermask_Top/Bottom to Component Geometry – Soldermask_Top/Bottom.

Follow the steps given below to set up Soldermask-to-Soldermask spacing:

1. Go to Setup > Constraints > Modes

2. In the Design tab under the Soldermask section, set the Soldermask to soldermask DRC value and enable the DRC.

3.Check the SOLDERMASK_SPACING DRC created in the layout.

Display Bump Pin Numbers APD 2023

SB202512083449 — Wed, 24 Dec 2025 14:35:23 GMT

Hi,

I would like to display the bump pin number,

Below is an example with and without the pin number showing on the same file:

I've tried a lot to things but nothing seems to work.

Thanks,

Shai

P.S. the one who sent me the photo with the pin numbers don't know why it works for him.

Exploring Advanced Packaging: 2.5D vs. 3D

Master Shifu — Wed, 24 Dec 2025 13:41:23 GMT

Exploring Advanced Packaging: 2.5D vs. 3D

The semiconductor industry is undergoing a transformation with 2.5D and 3D packaging technologies—but what sets them apart, and why should engineers care? Dive into this insightful breakdown:

🔹 2.5D Packaging

Intermediate solution between traditional 2D packaging and full 3D architectures
Employs a silicon interposer with Through‑Silicon Vias (TSVs) to host multiple dies side by side
Advantages:
- Enhanced performance via shorter interconnects → better signal integrity & latency
- Reduced footprint—ideal for compact applications
- More power-efficient designs, especially useful in battery-powered systems [resources....adence.com]

🔸 3D Packaging

Involves vertically stacking multiple semiconductor dies
Enables ultra-dense integration with minimal inter-die routing
Advantages:
- Highest level of integration in tight form factors
- Improved heat management—stacked dies help dissipate power more effectively
- Shortest interconnects (~70% of 2D paths), cutting wiring capacitance and power draw by ~30% [resources....adence.com]

🔸 2.5D vs. 3D: A Comparative Snapshot

Feature	2.5D Packaging	3D Packaging
Integration Level	Side‑by‑side dies on interposer	Vertical stacking of dies
Footprint Reduction	Smaller than 2D	Most compact formats
Power & Signal	Reduced interconnects, good latency	Shortest interconnects, lowest power cap.
Thermal Management	Better than 2D	Excellent heat dissipation
Complexity & Cost	Moderate	Higher—it demands more intricate design & testing

🔸 Key Takeaway

2.5D acts as a stepping stone: balances performance gains with manageable complexity
3D is the go-to for extreme integration needs—especially in AI accelerators, advanced memory (HBM), high-performance CPUs, and IoT edge devices [resources....adence.com]

These aren’t competing approaches—they’re complementary tools in the semiconductor engineer’s toolkit!

🔸 Read more about how these technologies are reshaping the future of chip design and how Cadence’s Allegro X Advanced Package Designer supports the transition ➡️ Explore the full Cadence blog

How to export the updated die pin information during die text-out

SaiPavanl — Fri, 05 Dec 2025 16:42:53 GMT

I used group edit to replace a few padstacks (NEW_DIE_PAD) of the die pin with the NEW_DIE_PAD_1 padstack. However, all die padstacks exported during die text-out remain NEW_DIE_PAD, even though die padstacks have already been replaced by NEW_DIE_PAD_1, as shown below. Also, the die pin rotation information cannot be exported during die-text out.

You can select Instance data during die text-out and the updated information of all die pins will be exported, as shown below:

Export as STEP

bdc66a938f164d — Sun, 09 Nov 2025 11:33:06 GMT

I am using Allegro X APD 24.1. I want to export the design as a STEP file, including all layers, dielectrics and vias. I found that should be possible but I don't see the option:

IC Packagers: Optimizing the connectivity between die escape routing and BGA balls made easy in Integrity System Planner

JFLepere — Wed, 05 Nov 2025 08:57:21 GMT

Package designers need to add escape routes to a die to facilitate further package routing: these routes provide essential pathways for signals to exit the die and reach other parts of the package or PCB. Without well-planned escape routing, signal traces can become congested or blocked, especially in high-density designs, leading to increased complexity, longer trace lengths, and potential signal integrity issues. Escape routes help optimize the layout by ensuring that each I/O pad has a clear and efficient path to its destination, improving electrical performance and manufacturability.
Integrity System Planner enables system and package engineers to aggregate data from IC, package, and PCB design teams, allowing them to perform key system planning tasks such as component placement and the definition and optimization of interconnectivity between components. Its connection optimization feature relies on selecting a subset of a component’s pins, with one side fixed and the other side free, allowing net assignments to be updated dynamically. Escape routes, on the other hand, are part of the physical implementation within the package design tool and are typically not recognized as pins when imported into Integrity System Planner.
However, it is important to consider the fanout pattern from the die escape routing during the optimization process. Once escape routes are created, optimizing connectivity from die pins to BGA balls may no longer yield optimal results, potentially leading to tangled or inefficient connections.
The post aims at guiding you through the process of creating a new component based on an existing die escape routing in Allegro X Advanced Package Designer. This new component will have pins located at the end of the breakout routing and can be imported into Integrity System Planner for further connection optimization.

Overview

The following figure shows the overview of the new component creation in Allegro X Advanced Package Designer and its transfer to Integrity System Planner where the connection optimization can be performed.

Step #1: Generate the die escape routing in Allegro X Advanced Package Designer

You can generate die escape routes using Route > Flip Chip Die Escape Generator.

Although the connections were optimized prior to die escape generation, rastnets are observed crossing on the northeast side of the breakout routing, indicating potential inefficiencies in the layout.

Step #2: Creating a new component in Allegro X Advanced Package Designer

After loading a Skill context file containing custom code, a new command becomes available: brk comp create.

Upon executing the command, you are prompted to select two points to draw a rectangle around the end of the escape routes and to enter a reference designator name for the new component.

The component is then created with pins representing the endpoints of the escape routes, making it ready for import into Integrity System Planner for further connection optimization.

Step #3: Importing the Allegro X Advanced Package Designer database in Integrity System Planner

Thanks to the interoperability of our tools, you can import the Allegro X Advanced Package Designer database into Integrity System Planner in the blink of an eye using the Tools > Merge Updated Allegro command.

The newly created BRK component, along with its associated connectivity, is seamlessly imported into Integrity System Planner, ready for further optimization.

Step #4: Optimizing the connectivity between the escape routing and the BGA balls

In Integrity System Planner, you can optimize connectivity between two sets of pins: one set is fixed, meaning no changes are applied, while the other set remains flexible and can be updated.

By clicking Optimize, the connections are efficiently refined between the endpoints of the escape routes—represented by the BRK component’s pins—and the BGA balls.

Over to You

Do you want to try out this method? Delve deeper into the details of each step? Well, you can try out all the steps right away with a sample design using the Optimizing from die escape routing to package balls in Integrity System Planner Application Note available at Cadence ASK if you are a Cadence customer with a valid login ID.

Do You Have Access to Cadence ASK?

You will need an account to access the links below; if you don´t have an account, go to Registration Help and complete the requested information.

You might also be interested in our free online training Allegro X Advanced Package Designer and/or in the following Training Byte Channel.

Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offerings, visit the Cadence Training website.

Cannot see NPTs in my PCB

bdc66a938f164d — Wed, 15 Oct 2025 09:16:41 GMT

How do I enable showing NPTs?

I have enabled in "Color dialog" both `Ncdrill_Figure` and `Ncdrill_Legend`, holes still invisible.

`.psm` files missing for placement

bdc66a938f164d — Wed, 08 Oct 2025 14:32:43 GMT

I am using Cadence Allegro X APD. In my computer I have the two files

- `/path/to/somewhere/component.psm`
- `/path/to/somewhere/deleteme.psm`

When I go to "Place manual" and select "Advanced settings/List construction/Database" unchecked and "Advanced settings/List construction/Library" checked, only `deleteme` is available. `deleteme.psm` was crated by copy-pasting `component.psm` and changing its name. Last week I used `component.psm` in my design. Why today it fails?

Component imports mirrored

bdc66a938f164d — Thu, 02 Oct 2025 09:36:20 GMT

I made a component in `component.dra` and imported it into `package.mcm`. For some reason, it imports mirrored. This is the information about the component:

```
LISTING: 1 element(s)

< SYMBOL >

RefDes: J1
Symbol name: component
origin-xy: (-71120.00 0.00)
rotation: 90.000 degrees
mirrored_geometry

pin layer: TOP
size: 30804 UM (w) x 21105 UM (l)
thickness: 2008 UM

Attached text:
class = REF DES
subclass = ASSEMBLY_TOP
value = J1

Attached text:
class = REF DES
subclass = SILKSCREEN_TOP
value = J1

Properties attached to symbol
LOCKED
MAX_LINE_EXIT_ANGLE = 45

Properties attached to symbol definition
LIBRARY_PATH = path/to/component.psm
PKGDEF_STEP_TRANSFORMATION = MICRONS, 0.000733, 0.000000, 400.220
703, 90.000, -0.000, -90.000
PKGDEF_STEP_FILE = component.step, 0, 0, -1, 0.
000000, 0.000000, 0.000000, 0
MAX_LINE_EXIT_ANGLE = 45

-------Component Instance J1-------

Component Class: IO
Device Type: DEVICE_1

Function(s):
Designator: TF-2
Type: __TMPDEV__
Pin(s): A01, A02, A03, A04, A05...

Properties attached to component instance
COMP_SUBTYPE = DIE

Pin IO Information:
Pin Type SigNoise Model Net
--- ---- -------------- ---
A01 UNSPEC GND
A02 UNSPEC J1_A02
A03 UNSPEC GND
A04 UNSPEC GND
A05 UNSPEC GND
A06 UNSPEC J1_A06
A07 UNSPEC GND
A08 UNSPEC GND
A09 UNSPEC GND
A10 UNSPEC J1_A10
```

I see it has a `mirrored_geometry` flag, but I don't know where it comes from and how to remove it.

Automatic net assignment between one symbol and multiple symbols

bdc66a938f164d — Wed, 01 Oct 2025 16:34:49 GMT

In `project.mcm` I have one symbol that has >300 pins, and I have >300 symbols with 1 pin each. I want to use the automatic net assignment tool to map them. Is this possible?

When I open the tool, it asks me to select the source, and I click on the symbol with many pins. So far everything works fine. Then it asks to select the destination. Here, however, I cannot select the other symbols, not even one of them. When I tyr to select, Allegro says `(SPMHIS-246): No pins matching specified component class in selection set. Select pins again.`. I believe that this is due to the fact that the symbol with multiple pins (which was given to me) is defined such that it has

```
Component Class: IC
Device Type: DEVICE_1
Die Type: FLIP-CHIP
```

and the symbols with 1 pin are defined such that

```
Component Class: DISCRETE
Device Type: DEVICE_2
```

I don't know if this is actually the issue, and how to change the definition of the discrete component into an IC component to fix it.

Change "Component Class: DISCRETE" to "IC"

bdc66a938f164d — Wed, 01 Oct 2025 13:54:37 GMT

I have `my_component.dra` which is included in my `project.mcm`. It is comming in as "Component Class: DISCRETE" and I want it to be "IC". How do I change this in `my_component.dra`?

Map pins to nets using CSV

bdc66a938f164d — Wed, 01 Oct 2025 08:55:38 GMT

I have a symbol with >300 pins and I want to assign them to nets using a CSV file that was externally generated. The CSV file has this format:

```
PINNAME,NET
A1,gnd
A2,net1
A3,netB
A4,netwhatever
...
A435,netfinal
```

I go to `File/Import/Symbol spreadsheet...` and Allegro prompts me to select a component. I click the component and the "Symbol Update from Spreadsheet" window pops up. I configure the fields of this window like this:

- File name: /path/to/the/file/with/mappings.csv
- File type: CSV
- Worksheet: Not applicable
- The box below "Worksheet", I have a list with "Pin Name" and "Net Name".
- Delimiter: ,
- Spreadsheet cells have data labels: Uncheck
- Spreadsheet has row and column headers: Check
- Add/Delete pins based on cell contents: Uncheck
- Create new nets defined in spreadsheet: Check
- Allow deassignment of pins: Check
- Assign cell colors to nets: Uncheck
- Rows and columns defined by: Component pin pitch

Next I click "Update" and the window closes, no error is shown, but the pins are still connected to the original nets.

refdes, device and package are required to add a part

bdc66a938f164d — Wed, 01 Oct 2025 07:07:41 GMT

I have a symbol that I draw and I want add it to my APD. I go to `Logic/Edit Parts List...` and this opens up a "Parts List" window with some options. I have chosen my symbol in the "Package" field and manually entered "Refdes" to some value. I am still missing "Device", which I don't know what it means. Where can I read about this? Are there tutorials available?

Pin is not part of a components. No net changes may be made.

bdc66a938f164d — Tue, 30 Sep 2025 15:13:34 GMT

In my `project.mcm` file I did "Place/Manually..." and inserted a symbol from a library. Now I go to "Logic/Create net...", type in the name of the new net, click "Ok" and Allegro says "Enter selection point" which I interpret as "select a pin to be assigned to the new net" (from what I see in tutorials). When I click any pin, Allegro says "(SPMHIS-229): Pin A5 is not part of a component. No net changes may be made.".

What am I missing?

What(SPMHIS-229): Pin H35 is not part of a component. No net changes may be made.(SPMHIS-229): Pin H35 is not part of a component. No net changes may be made.

Update symbol from library not working

bdc66a938f164d — Sun, 28 Sep 2025 17:36:06 GMT

I have a symbol drawn in `/path/to/symbol.dra` and the corresponding `/path/to/symbol.psm` file. This symbol was included in my `/path/to/main.mcm` design earlier. Now I modified `symbol.dra` and also the corresponding `symbol.psm`. I want this change to be updated in all instances of this symbol in `main.mcm`. I went to `Place/Update symbols` but it does not work.

If I do `Place/Manually/Advanced settings/List construction` and uncheck `database` and check `library`, Allegro finds `symbol` but with the old design. If I copy-paste `/path/to/symbol.psm` into `/path/to/symbol_deleteme.psm`, now this new symbol is found by Allegro and it has the modifications. Why does it fail if I don't change the name?

Documentation about default classes and subclasses

bdc66a938f164d — Sat, 27 Sep 2025 09:27:06 GMT

I am new to Cadence Allegro. I find tens of default classes and subclasses. Are they documented somewhere? Some are self explanatory by the name, but others not. I am looking for detailed information.

My current issue: I want to draw some reference lines just to guide my design in some class/subclass that is completely ignored afterwards, like a comment in a code file. Is "Substrate geometry/outline" the appropriate for this? Or "Drawing format/Outline"? Other?

Delete outline

bdc66a938f164d — Sat, 27 Sep 2025 08:37:04 GMT

I want to delete the following object (sorry, cannot upload screenshot because "An error occurred, please try again or contact your administrator."):

```

LISTING: 1 element(s)

< SHAPE(auto-generated) >

class CAVITY

subclass BOTTOM

Shape is solid filled in Smooth mode

Area: 6.350 (sq cm)

Exterior boundary:

segment:xy (-13200.00 12000.00) xy (12200.00 12000.00) width (0.00)

segment:xy (12200.00 12000.00) xy (12200.00 -13000.00) width (0.00)

segment:xy (12200.00 -13000.00) xy (-13200.00 -13000.00) width (0.00)

segment:xy (-13200.00 -13000.00) xy (-13200.00 12000.00) width (0.00)

*** Part of the Dynamic Shape ***

class BOUNDARY

subclass BOTTOM

Shape priority: 0

Number of etch shapes: 1

Dynamic fill style: SMOOTH

Area: 6.350 (sq cm)

Original boundary:

segment:xy (-13200.00 -13000.00) xy (12200.00 -13000.00) width (0.00)

segment:xy (12200.00 -13000.00) xy (12200.00 12000.00) width (0.00)

segment:xy (12200.00 12000.00) xy (-13200.00 12000.00) width (0.00)

segment:xy (-13200.00 12000.00) xy (-13200.00 -13000.00) width (0.00)

```

When I select this object and click on "delete", the software says:

```
Selected item not valid for current operation, ignored: Shape(auto-generated) "Not On A Net, Cavity/Bottom"

No valid items selected for the current operation, exiting.

```

How can I delete this?

Add footprint

bdc66a938f164d — Fri, 26 Sep 2025 13:50:46 GMT

I have a footprint for a component defined in `/path/to/footprint.dra`. How can I include it as an element of my `package.mcm`? I am trying to do [this]( BoardSurfers: Training Insights: Manually Placing Components in Allegro PCB Editor) but I see no way of browsing for `/path/to/footprint.dra`.

Mouse wheel pan weird acceleration

bdc66a938f164d — Mon, 22 Sep 2025 10:18:42 GMT

I am using Allegro X APD 24.1 on Windows 11. I have set the `/UI/Input/designhdl_pan` setting to `enabled` to get a more natural panning experience when clicking the mouse wheel. However, there is still a weird acceleration or scaling factor between the mouse movement and the panning distance move, something like `distance_the_viewport_moves_in_allegro = a*distance_mouse_moves_in_the_screen` with a>1. Is it possible to set a=1?

How to check and fix redundant vias in Allegro X APD?

mahimag — Mon, 08 Sep 2025 14:33:41 GMT

There is an easy check to identify and fix your duplicate vias that are the same XY location.

You can utilize Package Design Integrity Checks in Packaging tools. If you have not looked into the below post yet, please have a look:

Package Design Integrity Checks

In order to perform the checking, you have to specify a tolerance value for the “packinteg_redundant_via_tol” environment variable from Setup > User Preferences in the Ic_packaging/Package_integrity folder. For example, a tolerance value of 1um is set in the following image:

Once this is set, enable "Redundant Padstacks" checking from Tools > Package Design Integrity in the Manufacturing folder and click Apply.

You will get the violation coordinate as well as it adds external DRC.

A small tip, If you want to remove the duplicate via when running the Package Design Integrity Checks, then enable the option 'Fix errors automatically (where possible)

why is display options in setup greyed out for some of the items

am4590 — Fri, 22 Aug 2025 06:09:57 GMT

How to convert a shape to a bondfinger and add a wirebond?

SaiPavanl — Tue, 12 Aug 2025 12:01:38 GMT

In some scenarios we have a polygon shape and would like to convert it to a bondfinger and add a wirebond to it.

Below steps will guide you through converting a shape to a bondfinger and add a wirebond?

Convert a shape to a padstack

To convert a shape to a bondfinger, you need to first convert it to a padstack. To convert a shape to a padstack, perform the following steps:

Select Tools > Convert > Shape to Padstack.
Enable the following checks in the Options tab:

Create via and remove shape

Add padstack to via list

In the "Padstack name:" field, type a padstack name, like PWR_FINGER.

4. The padstack loads into your design. You can use the padstack as a bondfinger, if you desire.

B. Using the padstack as a bondfinger

To add a wirebond, using the padstack created earlier, as a bondfinger, perform the steps that follow:

Select Setup > Application Mode > Wire Bond Edit.
RMB on a die pad and select Add Wire Bond from the popup menu.
Add the padstack in the Options tab, under the Finger section. It will act as a bondfinger.

4. You can now draw a wirebond with the padstack as a bondfinger.