Cadence RF Design Forum

Spectre netlist defining voltage gain and saving the results to view in the psf file

GM202510215619 — Thu, 22 Jan 2026 16:41:51 GMT

Hello, I have a simple circuit with Vout as the output node of the amplifier and Vin as the input node of the amplifier.

I want to save the dB voltage gain results and plot it in ViVA from the raw file.

Is there a way to do it through using a few lines of code in my spectre testbench netlist?

Any help would be appreciated. Thank you

-GGM

P+ diffusion resistor with salicide (3 terminal)

SamanMKD — Tue, 09 Dec 2025 12:16:42 GMT

Hello everybody,

In order to use "P+ diffusion resistor with salicide (3 terminal)" in my design, how can I connect the Bulk (N-Well) to VDD (metal 8)?

Best,

Clarity menu in Virtuoso

ArbLouis — Tue, 18 Nov 2025 15:06:59 GMT

Hi everyone,

I have installed Clarity 2024 (SIGRITY 2024.1) and I am using Virtuoso IC23.1 on RHEL9.

I can successfully run Clarity as a standalone application (Layout Workbench), so the installation path and license seem correct. However, I cannot see any Clarity/Sigrity menu inside Virtuoso Layout, even when switching to the "Electromagnetic" workspace.

Here is the configuration I added to my .cshrc file:

# 1. Fundamental Root Variable
setenv SIGRITY_EDA_DIR /home/EDA/cadence/IC_23/SIGRITY20241
# 2. Compatibility Variable
setenv CNI_ROOT $SIGRITY_EDA_DIR
# 3. Update PATH (Note: tools.lnx86 is essential here)
set path = ( $SIGRITY_EDA_DIR/tools.lnx86/bin $SIGRITY_EDA_DIR/tools/bin $path )

Is there a specific SKILL script I need to load manually in my .cdsinit for the 2024 version, or is there an installation script in the bin folder I missed?

Thanks in advance for your help.

I've used this guide: Virtuoso RF Solution Package Electromagnetic Simulation Rapid Adoption Kit (RAK) Product Version: IC23.1 July 2023

LoapPull Analysis For Differential Power Amplifier

RM202501276525 — Mon, 10 Nov 2025 08:34:09 GMT

Is using a VCVS to convert the differential output to single-ended the correct way to perform a load pull on a differential power amplifier?

---- Cannot upload pictures onto the website.

cross coupled oscillator design problem

CC202509218347 — Sun, 21 Sep 2025 18:27:30 GMT

Hello everyone,

I'm currently working on the design of a cross-coupled oscillator, based on the circuit architecture shown in the attached figure (from a referenced paper). The resonator has a center frequency of 2.49 GHz, with C0 = 0.98 pF.

One of the key challenges I’m facing is ringing, which appears to be caused by the negative capacitance effects introduced by Csp and CHPF. In order to suppress this ringing, I attempted to ensure that the loop gain is less than 1 at the ringing frequency. However, this makes it difficult to simultaneously satisfy both of the following conditions:

Loop gain > 1 at 2.49 GHz
Loop gain < 1 at the ringing frequency

Simulation Setup:

For loop gain analysis, I used the STB (stability) analysis with an iprobe placed at the gate of M2.
For analyzing negative impedance and capacitance, I ran AC simulations by placing a current source across the output nodes and calculating the real and imaginary parts of the resulting impedance.

I would appreciate any suggestions or insights on simulation techniques and design strategies that could help with this issue.

source : B. Bahr, D. Griffith, A. Kiaei, T. Tsai, R. Smith and B. Haroun, "Class-C BAW Oscillator Achieving a Close-in FOM of 206.5dB at 1kHz with Optimal Tuning for Narrowband Wireless Systems," 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 311-314, doi: 10.1109/RFIC54546.2022.9863092. keywords: {Wireless communication;Phase noise;Performance evaluation;Micromechanical devices;Radiofrequency integrated circuits;Oscillators;Tuning;BAW;MEMS;Oscillator;resonators},

Re: How to get all data from srrWave？

EA202509149412 — Mon, 15 Sep 2025 07:21:08 GMT

Hello! I designed a PA and performed load pull on it. In the obtained constant power contour plot, I want to extract the data of the constant power lines on the Smith chart. I can normally extract the required data (X, YRe, YReImag) using 'send to export'. I wish to extract this data through code.

I use the code

line = leafValue( cPwrContour(i("/I1/out" ?result "hb_fd" ) v("/net7" ?result "hb_fd") '1 ?refImp 50.0 ?numCont 11 ?modifier "dBm") "p" 9.4631312)

and get the reply from CIW that :

srrWave: 0x5d9b5de0

I want get data from this srrWave, I use the code

ocnPrint(line)

but I get the result data (X, |Y|). Obviously, I could't get the phase from this data which I need. The output data type of the waveform should be Impedance, but it actually outputs Rectangular type. How can I get the data I need from this srrWave?

Pcell inductor EMX simulation

SamanMKD — Fri, 12 Sep 2025 02:22:01 GMT

Hello everyone,

I am designing a VCO, and for the on-chip inductor, I will use a center-tapped inductor. For first-pass design, I want to simulate the "spiral_sym_ct_mu_z_a28_dm" from PDK. There is some ambiguity for me as follows:

1- At a specific frequency, why do the inductor and quality factor values in the Pcell parameter differ from what the EMX simulates?
2- Which result should be considered as the correct value for the design procedure?
3- Are my frequency and pins' setup correct? (I used depth=1 to use the default PCell labels for ports.)

Best regards,

* I can not upload the image 😞
Please see the image using links below:
https://ibb.co/8nK5smkW
https://ibb.co/6JYqsJpJ
https://ibb.co/Rk33RwWN

Integrating the EMPro/ADC in cadence virtuoso environment

Tarique mohd — Thu, 11 Sep 2025 14:32:20 GMT

I would like to run EMPro and want to import EM results into Cadence for S-parameter and other analysis.

Is it possible to integrate High Frequency tools( like ADS, EMpro) in cadence virtuoso environment?

BR,

Tarique

Discussion on Poly-Endcap in CMOS Layout

yogeshjaiswalCAD — Thu, 21 Aug 2025 06:36:48 GMT

Greetings,

I hope we are all learning and growing together. I would like to share some thoughts on the concept and concerns related to the Poly-Endcap in CMOS layouts ( Option A) when both sides are considered under ideal conditions.

Option A (ideal conditions) & Option B ( Non ideal conditions)

Now, let's examine the situation when the Poly-Endcap is not the same in a CMOS layout ( Option B) under non-ideal conditions on both sides.

Could you please share your insights on the implications if the Poly-Endcap differs in high-speed or RF layouts?

Specifically, I’m interested in the potential impacts on performance and fabrication at lower technology nodes. I have attached the CMOS layout in this email (ideal & non-Ideal condition).

Thank you!

BeSt regards,

Yogesh Jaiswal

Licence Issue

EB202503094911 — Mon, 26 May 2025 22:57:05 GMT

Hello, I am using a single-user license however when i try to download my PREPARED license got that error. I do not know what to do. Can you help please ?

Failure getting SUL

Current offline license is up to date, license request is ignored. (1995)

Turning off non-linearity contribution of cells

FPMKh — Fri, 14 Mar 2025 16:37:32 GMT

Hi,
Spectre version: 23.1.0.594.isr12

I was wondering if we can turn off non linearity contribution of a certain blocks in the design. Something similar to what is possible for noise analysis where you can turn ON/OFF certain blocks in the noise simulation.
I run linearity simulation using large signal transient.

Thank you.

doing an em simulation with emx but with a parameter sweep

BARID — Mon, 03 Mar 2025 17:10:20 GMT

hello everyone,

I have a transmission line that I want to extract hundreds of s2p files for hundreds of length values. Is there anyway to do an em simulation but with a sweep for the length ?
I know that with hfss you can have a python script that will do it for you but I have emx directly from cadence so I was wondering if it can do the same

How do you optimize using Microwave Office?

DS202502112843 — Tue, 25 Feb 2025 07:30:08 GMT

I am trying to use this software to optimize my L and C values. I saw my professor teaching it but he is using the 17 version. I have AWR Design Environment (24.1) and I'm at a total loss with why this software doesn't change my L and C values. Its asks me to do it constrained so I select that option but my instructor's old version doesn't have it.

I then click optimize and I get this window but nothing works after I click start.

Using deepprobe to see internal extracted nets

FPMKh — Mon, 03 Feb 2025 18:17:16 GMT

Hi,
My Spectre version is 21.1.0.854.isr22.
I want to use deepprobe to access extracted internal nets.
I'm using QRC for extraction and use the dspf file.
The purpose is to do some stability test (without bringing the pin all the way to the top).
I use following for the Hierarchical Node:
Itx_top.XIser\/XLM\/XINVT\[0\]\/MI0\:G
And it's not working (not showing the waveform). XINVT\[0\] is one of the instantiation of the block INVT<3:0>. I should say that I also tried Itx_top.XIser\/XLM\/XINVT\<0\>\/MI0\:G and it did not work either. I also used g instead of G and also "_" instead of ":" which did not help.
I was hoping you could help me debug this.

Thank you

2 Tone Test of a LC-VCO and LDO: Best setup to get a reliable Phase Noise simulation

dtzlou — Sun, 26 Jan 2025 13:28:10 GMT

Hi all,

I have an LC-VCO and an LDO with a very bad PSRR at frequency 250KHz (gain is positive!). I apply 20mV, 250KHz sinewave tone at the input of the LDO (VIN) and I want to check the PSRR impact on the VCO Phase Noise at this specific frequency 250KHz. The VCO frequency is 3GHz.

I am playing with HB + HBnoise setup but I am not 100% sure If i follow the correct setup in order to get accurate and meaningful results. Below you can see my HB and HBnoise setup settings:

HB Setup:

HBnoise Setup:

Do I need to increase the Oversampling factor to get more accurate results?
Since I apply a sinewave tone at the input of the LDO, the harmonic number of this tone (the 2nd one) must be 1, right?
Do you recommend other simulation setup or this one is good enough to check the impact of the LDO modulation at the VCO Phase Noise

Thanks, kind regards

Stabindex and S1/S2 in Sprobe Cadence

YufeiLiu — Sat, 18 Jan 2025 18:58:05 GMT

Hi,

I added Sprobe to the LNA I designed to check the stability of interstages. But the results generated by Sprobe confuse me.

For StabIndex, it is always less than 1. However, at some frequency, S1 and S2 will be greater than 1, and Z1 and Z2 will also have negative real impedance at that moment. I am wondering whether the circuit is in the unconditional stable state or unstable in this case?

Thanks!

Issue with EMX Oscillation Results for VCO and Coil

Fatemeh Ansari — Wed, 15 Jan 2025 12:25:52 GMT

Hi,

I used EMX to simulate my coil and connected it to the VCO core at the schematic level. The circuit oscillated up to 255 GHz (a semi-schematic level simulation). Next, I completed the layout for my VCO core, connected the VCO core layout to the coil, and ran EMX for the entire structure using the black box approach. The transient simulation showed oscillation at 204 GHz.

Subsequently, I ran EMX for the VCO core layout alone using the black box and connected it separately to the EMX coil in the schematic. This configuration resulted in two EMX-generated symbols: one for the EMX VCO core and another for the EMX coil. However, in this setup, the circuit did not oscillate, which is unexpected since the layouts are identical in both cases. Additionally, the transient simulation time was set to 3 ns, but it could not progress further ( as shown in the figure). I checked the real (y11) of collectors of VCO and it is negative in the desired frequency range.

Running EMX for the entire circuit is very time-consuming. Therefore, I prefer to focus on the layout of the VCO core to reduce the frequency discrepancy between the semi-schematic and post-layout simulations.

Could you please help me understand how to resolve this issue?

Thank you in advance for your support.

Best regards,
Fatemeh

HB tstab randomly giving bad results compared to regular transient

MatanR — Wed, 01 Jan 2025 07:22:42 GMT

Spectre version: 23.1.0.403_ISR6

Virtuoso: 23.1.ISR6

*can't upload images for some reason.

While running a harmonic balance configured like this:

1. Run transient - Decide automatically.

2. Run Envelope tstab - no.

3. 1 Tone - fundamental freq. is LO.

11 harmonics.

oversample factor = 4

freqdivide Ration for Tone1 = 1

For random points - tstab outputs wrong results - for example a DC circuit has it's output on the wrong voltage.

while running regular transient (in Cx) I get the right results for all points.

sometimes HB tstab gets it right.

what am I doing wrong?

N-path mixer power conversion gain calculation with PSS+PAC

OE202408074054 — Tue, 19 Nov 2024 11:21:41 GMT

I’m simulating an N-path mixer using ideal components. After performing a PSS+PAC analysis, I observed a positive power conversion gain, while I expected to see a power conversion loss instead. It's worth noting that the beat frequency is set to the LO frequency. To verify this, I performed a two-tone PSS simulation, which indeed showed a power conversion loss. Is there something unusual about the PAC analysis that I might not be aware of? I'm using Virtuoso version 6.1.8-64b and Spectre version 18.1.0.077 64bit -- 1 Aug 2018. Below are the details of my testbench.

I'm using Cadence switches with the following parameters:
- Open voltage: 100 mV
- Close voltage: 900 mV
- Open switch resistance: 1 MΩ
- Closed switch resistance: 1.0 Ω

The switches are hard driven by a square-wave LO swinging between 0 and 1 V whose rise and fall time is 1% of the LO period.

I use the following equations to compute the IF and RF powers and eventually the power gain:
Prf = harmonic((vh('pac "/RF") * conjugate(ih('pac "/PORT0/MINUS"))) '0)
Pif = harmonic((vh('pac "/IF") * conjugate(ih('pac "/PORT1/PLUS"))) '-1)
Gc = Pif / Prf

Using "nport" as a schematic circuit component

Saman Mokhtabadamri — Thu, 14 Nov 2024 09:30:21 GMT

Hello everybody,

I designed an inductor in HFSS and extracted its S-parameters. Now, I want to employ this inductor in my oscillator schematic design in cadence.

How can I use "nport" component in my design to replicate the inductor behavior in my transient, pss, and stb simulations?

P.S. I don't know why I can not attach my intended images to the post !!!!

Best regards

Transient Simulation waveform abnormal

SkkyLee — Sat, 02 Nov 2024 14:37:09 GMT

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors"

Leandro Silva — Wed, 30 Oct 2024 16:18:37 GMT

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors"

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

EMX - EM simulation for large CMOS chip

PhanKhai9898 — Tue, 22 Oct 2024 11:05:16 GMT

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?
Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

Cross-coupled oscillator Stability simulation

Saman Mokhtabadamri — Thu, 10 Oct 2024 10:21:33 GMT

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

Getting error while adding element in AWR software

NP202408116448 — Tue, 17 Sep 2024 13:23:10 GMT

While adding an element created from a netlist file in AWR, I am getting the error 'The element type being dropped is not compatible with the window it is being dropped into'. The netlist file in AWR has the following contents:

.subckt BFG520W base collector emitter npn
.model BFG520W NPN(IS=1.016E-15 NF=1.000 BF=220.1 IKF=510E-3 VAF=48.06
+ ISE=2.83E-13 NE=2.035 NR=0.988 BR=100.7 IKR=2.352E-3
+ VAR=1.692 ISC=24.48E-18 NC=1.022 RB=10.00 RE=0.7753
+ RC=2.21 CJC=447.6E-15 MJC=0.07 VJC=0.1892
+ CJE=1.245E-12 TF=8.616E-12 TR=5.437E-12 mfg=NXP)

I have attached screenshots of the element BFG520W2 created due to the above netlist and the error I am getting while adding this element.