Cadence Custom IC Design Forum

Transient simulation sweep for thermometer code

RA20250218276 — Tue, 17 Mar 2026 06:52:58 GMT

I need to do transient simulation for thermometer code input. Currently, I have 64 voltage sources and change the values one by one. I am sure there are other ways to do this efficiently. In short, I am looking for a way to pack these Q63 to Q0 as a design variable so I can sweep it using parametric analysis.

I am using ADE L and IC618.

Harmonic balance not matching transient with harm_tuner

BT202409301339 — Sun, 15 Mar 2026 19:33:55 GMT

I have been experimenting with the new load pull functionality using the harm_tuner component, and am quite confused about some results. I am seeing dramatically different results from the hb sim vs when I do a transient simulation with the tuner in place to sanity check, or similarly check the tstab waveforms. Harmonic balance shows several orders of magnitude larger power than I see in transient.

In an effort to debug this in a simpler setup I made the following testbench, which shows somewhat similar behavior. The idea is that the tuners convert from 50 Ohms to some lower impedance, but are matched to each-other so all input power should show up at the output.

Both ports are 50 Ohms. Port1 is driving a 10 GHz 0 dBm tone.

The source/load tuners are configured identically:

A sp sim shows s11=s22=0 (linear), and s12=s21=1 (also linear), as I would expect.

hb shows 1 mW tone power at the output port, as I'd expect. This shows up in both the spectrum and time views. (spectrum shown below)

Unfortunately the forum isn't letting me upload more images for some reason, ("an error occurred. Please try again or contact your administrator") but the time sweep view of the hb results shows a 0.63 Vpp waveform at both ports, which matches 0 dBm.

However, the hb tstab waveforms show something else. These show a 240 mVpp waveform at the output port and 390 mVpp waveform at the input port. Neither of these match the harmonic balance result! The same is observed for a transient simulation. I wish I could upload more images to illustrate this, but the waveforms seem to be settled.

So, am I missing something here? Does harm_tuner not work for transient, but somehow does work for harmonic balance, or is something else going on? I understand the nature of harm_tuner will give some weird transients, but the apparently settled behavior for a single tone in transient sim does not seem correct, but then harmonic balance does seem right. I am hoping I can trust the hb results..

I am using IC25.1-64b.38 and Spectre 25.1.0.274.isr6

Problems with Virtuoso ADE Explorer

FZ20251125769 — Thu, 12 Mar 2026 19:06:55 GMT

Hi!
I've been trying to run a simulation in ADE Explorer or ADE Assembler and I get this error every time:

Spectre (R) Circuit Simulator
Version 24.1.0.078 64bit -- 14 Sep 2024
Copyright (C) 1989-2024 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: fzapata Host: cadence HostID: E70A569B PID: 4708
Memory available: 23.4371 GB physical: 24.4112 GB
Linux : AlmaLinux release 8.10 (Cerulean Leopard)
CPU Type: AMD Ryzen 7 6800H with Radeon Graphics
Socket: Processors [Frequency] (Hyperthreaded Processor)
0: 0 [2221.5] (), 1 [1095.8] (), 2 [1992.9] (), 3 [1095.8] (), 4 [4442.4] ()
5 [1095.8] (), 6 [3344.5] (), 7 [1095.8] (), 8 [2301.2] (), 9 [1095.8] ()
10 [3414.2] (), 11 [1095.8] (), 12 [1971.6] (), 13 [1095.8] (), 14 [1095.8] ()
15 [1964.4] ()

System load averages (1min, 5min, 15min) : 2.8 %, 2.1 %, 1.9 %
Hyperthreading is enabled

Simulating `input.scs' on cadence at 6:47:47 PM, Thur Mar 12, 2026 (process id: 4708).
Current working directory: /home/fzapata/simulation/twork_1/netlist
Command line:
/opt/cadence/SPECTRE241/tools.lnx86/bin/spectre -64 input.scs \
+escchars +log ../psf/spectre.out -format psfxl -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5 -env ade \
+adespetkn= (long number here) \
-ahdllibdir \
/home/fzapata/simulation/tp_final/capacitances_calculation/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB \
+logstatus

Simulation Id: ktuVgaS28d6R6sO3
Licensing Information:
[18:47:48.346113] Configured Lic search path (24.01-s002): 2100@localhost

Internal error found in spectre during license check-out.
FATAL (SPECTRE-18): Segmentation fault. Encountered a critical error during simulation. Run `mmsimpack' (see mmsimpack -h for detailed usage information) to package the netlist and log files as a compressed tar file. Then, contact your Cadence representative or submit a service request via Cadence Online Support, including the tar file and any other information that could help identify the problem. Encountered a critical error during simulation. Run `mmsimpack' (see mmsimpack -h for detailed usage information) to package the netlist and log files as a compressed tar file. Then, contact your Cadence representative or submit a service request via Cadence Online Support, including the tar file and any other information that could help identify the problem.

Version 24.1.0.078 64bit -- 14 Sep 2024

****ASSERTION STACK****
0x7ebf63c
0xabaf5c
0xabb512
0x65450612990
0x6544184e5af
0x65441821ee5
0x6544188f887
0x65441896b8c
0x6544189be8a
0x6543c046836
0x6543c02956c
0x6543c01b360
0x6543c01b7f7
0x6543c016bdf
0x6543c017023
0x6543c0172d0
0x90cb895
0x90cbd19
0x90846c7
0x9084486
0x9072fbf
0x906b9e1
0x906d613
0x9068a49
0x9068bab
0x8bcab36
0x8bbea3a
0x8bbe24b
0x8bbfd8a
0x8bcb8aa
0xba321c
0xba67b4

****LIBRARIES****
spectre/bin/64bit/spectre [0x400000]
/usr/lib64/libpthread.so.0 [0x65450600000]
/lib64/libc.so.6 [0x65441800000]
/lib64/libudev.so.1 [0x6543c000000]

Standard Deviation Summary in Monte Carlo Simulations Across Multiple Corners

alho1 — Wed, 11 Mar 2026 14:02:53 GMT

The tool versions are below:

Virtuoso IC 6.1.8-64b.500.33
Spectre 23.1.0.063 64bit

Hello,

When performing a Monte Carlo simulation, the Yield tab shows a standard deviation in the results.

If the simulation is performed with several corners (not parameters), the question is which standard deviation value is used for the summary output. Each corner has its own standard deviation.

Is the worst-case standard deviation used for the summary? If so, why is it sometimes the larger and sometimes the smaller value?

At 100% yield it seems to always be the larger value (worst case), but at 0% yield it is sometimes the larger and sometimes the smaller value.

Does anyone know how this value is determined?

Thanks very much for your reply!

Alexander

Transient noise contribution works in spectre but failed in APS.

zuiying — Sun, 08 Mar 2026 12:58:31 GMT

Hello! I used "noise contribution" function in tran to remove some noise source. In the following schematic, I wanted to disable the noise contribution of M3.

Then, I wrote "/I9/M3" in the Instance list.

To accelerate simulation, I chose APS. But after simulation, I found the wave of Vvg<0> was the same as not removing the noise contribution of M3 !

I think it is strange. I changed simulator from APS to spectre. Then the results were different.

But I am sure the noise contrituion indeed worked at previous APS simultions. It is my fisrt time to encounte this situation where noise contribution works in spectre but failed in APS.

My software version is here.

What could be the reason ?

Thanks a lot !

significant digits in ADE assembler output expressions

an wx — Sun, 08 Mar 2026 06:44:54 GMT

hi all, I'm drawing spectrums in ADE Assembler when I encountered a problem. I want to calculate FFT with start/stop time at 1989.955ns/22469.955ns. In Calculator and in "Measurement"-"Spectrum" panel, I can enter the specific start/stop time and draw the spectrum as expected; however, as I send the expression to ADE, the stop time becomes 2.246996E-6, resulting in large spectrum leakage. If I set start and stop time to1989.950ns/22469.950ns so that no truncation occurs, the spectrum is normal. So it seems that the values are automatically rounded to 6 decimal places in ADE assembler output? How can I solve it?

How to set add. Spectre MC options in Assember GUI?

StephanWeber — Fri, 06 Mar 2026 09:12:06 GMT

Hi,

In Spectre netlist we can set these parameters for montecarlo:

23 stdscale=default Scale the standard deviation by the specified value. The default value is 1.0.
24 process_stdscale=default
Scale the standard deviation of process variation parameters by the specified value. The default value is 1.0.
25 mismatch_stdscale=default
Scale the standard deviation of mismatch variation parameters by the specified value. The default value is 1.0.
26 nscale=default N Scale for both of process and mismatch variation parameters in uniform distribution by the specified value. The default value is
1.0.
27 process_nscale=default
N Scale for process variation parameters in uniform distribution by the specified value. The default value is 1.0.
28 mismatch_nscale=default
N Scale for mismatch variation parameters in uniform distribution by the specified value. The default value is 1.0.
29 dist=default Force all MonteCarlo random variation distributions to the specified type. Possible values are default, unif, gauss and gamma.
30 processdist=none Set all MonteCarlo process variation distributions to be the specified type. The default type is none. Possible values are none,
unif, gauss, gamma, lnorm, sunif and lunif.

But in opposite to many other GUI windows I see no option to set these at least as user-defined option.

Is this correct?

To scale-up only the lognormal+Gaussian distributions I need stdscale=2, and this would be applied to both mismatch & process??

Bye Stephan

Specifying variable as a parametric sweep in ADE Explorer (when the parametric weep involves another variable)

msharma — Fri, 06 Mar 2026 08:39:20 GMT

I want t o sweep a variable varX through 5 values. The step size is constant, but the sweep is relative to another variable varY.

varX = varY + (-2:1:2)

What is the acceptable syntaxt to specify this sweep?

I tried

varX = varY + (-2:1:2)

varX = (varY-2:1:varY+2)

but they gave an error by the simulator.

Thanks

$fscanf and $fget do not work when any portion of Verilog-A file is encrypted

ConradJ — Wed, 04 Mar 2026 23:36:02 GMT

$fscanf and $fget appear to return empty strings if any portion of the Verilog-A file is encrypted, but work fine if the encrypted portion is removed.

This Verilog-A code reads in data from an external file and prints some information to the spectre log. The file example.txt contains the phrase "You should see this".

The above code correctly returns the following when run in a transient simulation by Spectre APS:

Channel Descriptor: 2
Path: /home/jensenct/txt.txt
First Line: You should see this

Non-zero if end-of-line: 0

After running the below command to encrypt the "doNothing" function the below code is produced. (Note the encrypted blob was removed for security reasons).

/apps/cadence/SPECTRE231/tools.lnx86/bin/64bit/xmprotect -language vlog verilog.va

// VerilogA for VerilogA_Bug_Example, ReadFile, veriloga

`include "constants.vams"
`include "disciplines.vams"

module ReadFile;

parameter string file_location="/home/USER/example.txt";
integer myChanDesc;
string temp;

//pragma protect begin_protected
//pragma protect encrypt_agent="NCPROTECT"
//pragma protect encrypt_agent_info="Encrypted using API"
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
//pragma protect key_method=RSA
//pragma protect key_block
removed for security
//pragma protect end_key_block
//pragma protect digest_block
removed for security
//pragma protect end_digest_block
//pragma protect data_block
removed for security
//pragma protect end_data_block
//pragma protect digest_block
removed for security
//pragma protect end_digest_block
//pragma protect end_protected

analog begin

@(initial_step) begin
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
myChanDesc = $fopen(file_location, "r");
$strobe("Channel Descriptor: %d", myChanDesc);
$strobe("Path: %s", $cds_get_resolved_path( myChanDesc ));
$fgets(temp, myChanDesc);
$strobe("First Line: %s", temp);
$strobe("Non-zero if end-of-line: %d", $feof(myChanDesc));
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
$strobe("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
end

end

endmodule

Which incorrectly returns the following when run using the same test bench:

Channel Descriptor: 2
Path: /home/USER/example.txt
First Line:
Non-zero if end-of-line: 0

Running $ftell after trying to read several lines still returns 0. This issue also appears to impact $fscanf.

ahdlvar not saved although saveahdlvars=all is set

StephanWeber — Mon, 02 Mar 2026 13:56:45 GMT

Hi,

I find in the netlist correctly:

saveOptions options save=allpub saveahdlvars=all

And get them for transient and pss_td, but not in pss tstab part "pss_tran". How to get them also in that?

Bye Stephan

Failing to extract parasitics from layout - capgen file is missing

EG202602196052 — Sun, 01 Mar 2026 12:21:11 GMT

Hi, when trying to launch Quantus (Pegasus) Parasitic Extraction, I'm getting this error (log output):

Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version
23.1.1-s235 Fri Sep 27 22:34:56 PDT 2024
---------------------------------------------------------------------------------------------------------------
Copyright 2024 Cadence Design Systems,
Inc.

INFO (EXTQRCXLOG-128) : Quantus command line:
Started at: 2026-Mar-01 14:12:50 (2026-Mar-01 12:12:50 GMT)
Executable:
/eda/cadence/2024-25/RHELx86/DDIEXPORT_23.33.000/INNOVUS231/tools.lnx86/extraction/bin/64bit/qrc
Options: -log_file /home/la_hk/BAF_RAK/LVSrun/svdb/qrc.OpAmp.log -cmd
/home/la_hk/BAF_RAK/LVSrun/svdb/qrc.OpAmp.ccl
Current working directory: /home/la_hk/BAF_RAK

INFO (EXTQRCXLOG-103) : The Command File Options for the current Quantus run are as follows:

capacitance \
-decoupling_factor 1.0 \
-ground_net "VSS"
extract \
-selection "all" \
-type "rc_coupled"
extraction_setup \
-array_vias_spacing "auto" \
-max_fracture_length infinite \
-max_fracture_length_unit "MICRONS" \
-max_via_array_size \
"auto" \
-net_name_space "LAYOUT" \
-split_via_by_unit_area false
filter_coupling_cap \
-coupling_cap_threshold_absolute 0.01 \
-coupling_cap_threshold_relative 0.001
filter_res \
-merge_parallel_res false \
-min_res 0.001
input_db -type pegasus \
-design_cell_name "OpAmp layout Layout_solution" \
-directory_name "/home/la_hk/BAF_RAK/LVSrun/svdb" \
-format "DFII" \
-library_definitions_file "/home/la_hk/BAF_RAK/cds.lib" \
-run_name "OpAmp"
log_file \
-file_name "/home/la_hk/BAF_RAK/LVSrun/svdb/qrc.OpAmp.log"
mos_diffusion_parameter_extraction \
-auto_accuracy_downgrade false \
-res "fast"
output_db -type smart_view \
-add_bulk_terminal "true" \
-cdl_out_map_directory \
"/home/la_hk/BAF_RAK/CDLrun" \
-device_finger_delimiter "@" \
-enable_cellview_check true \
-include_cap_model "false" \
-include_parasitic_cap_model "false" \
-include_parasitic_res_model "comment" \
-include_parasitic_res_width true \
-include_res_model "false" \
-output_xy \
"CANONICAL_CAP" \
"CANONICAL_RES" \
"DIODE" \
"MOS" \
"BIPOLAR" \
"GENERIC" \
-res_component "presistor" \
-view_name "sv_extracted"
output_setup \
-directory_name "/home/la_hk/BAF_RAK/LVSrun/svdb" \
-file_name "/home/la_hk/BAF_RAK/LVSrun/svdb/OpAmp/rcx.sp" \
-net_name_space "SCHEMATIC" \
-temporary_directory_name "OpAmp"
process_technology \
-technology_corner \
"rcx_worst" \
-technology_library_file "/home/la_hk/BAF_RAK/gpdk045_v_6_0/pvtech.lib" \
-technology_name "gpdk045_pvs" \
-temperature \
"25.0"

WARNING (LBMISC-215199): unable to execute '/eda/cadence/2024-25/RHELx86/DDIEXPORT_23.33.000/INNOVUS231/tools.lnx86/extraction/bin/64bit/capgen'

ERROR (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
/eda/cadence/2024-25/RHELx86/DDIEXPORT_23.33.000/INNOVUS231/tools.lnx86/extraction/bin/64bit/capgen

ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 65280

ERROR (LBRCXM-709): ***** Quantus terminated abnormally *****

Have checked directory /eda/cadence/2024-25/RHELx86/DDIEXPORT_23.33.000/INNOVUS231/tools.lnx86/extraction/bin/64bit/ - capgen file is missing. Could it be some licensing problem or faulty installation (or deleted file) problem?

Wildcard '*' does not match any net in spectre save statement

msharma — Sun, 01 Mar 2026 01:34:19 GMT

My spectre netlist has this statement:

----

save IARRAY.* sigtype=all depth=1

----

IARRAY is an instance name.

However, when the transient simulation is run, no signals in the subcircuit instance IARRAY are saved. The simulator log has the following message:

----

Wildcard match summary:

save IARRAY.* : 0

----

What could be the cause of the signals / nets not being saved?

Very Basic Wire naming question

HL20260227511 — Fri, 27 Feb 2026 20:14:01 GMT

Hi,

I am very new so please go easy on me. How do i name multiple wires with same name?(Like Vss, CLK) I tried to use "Attach to multiple wires" but it didnt work. I am trying to build strong-arm based latch

Thank you

Also, does Cadence forum usually not allow images to be uploaded?

Copying design variables from cellview to ADE Explorer / Assembler: unused variable "V" from vsource cell

EG202602196052 — Thu, 26 Feb 2026 16:25:08 GMT

Hi, I'm trying to start ac analysis using ADE Explorer / ADE Assembler, but getting a warning that variable {V} is not set. I'm not using this variable, but it is always copied from CellView after command "Copy from CellView". The schematic files has no check errors or warnings, also parameters of vsource cell are set correctly (see image). Of course, I can set V to 0 value in ADE Explorer, and can simulate the results, but want to know why this unused variable always imported. Thanks.

PCD is not loaded

Mooh — Thu, 26 Feb 2026 09:28:46 GMT

I'm trying to install the PCD in my Cadence, but it shows this error. I followed this document.

Any idea?

get the difference between two wave forms after parametric sweep.

Svilen64 — Wed, 25 Feb 2026 23:11:30 GMT

Hello,

I have run a parametric sweep to get different delays of a clock signal and I created an expression that extracts the delay of the rising edge with respect to a reference depending on the parameter. Then I shifted that by one index count, index being swept. Now I want to take the difference between those two so I can plot the delay for each two consecutive values of the swept parameter . Can I do that without starting scripting in Skill or Ocean?
Thanks
Svilen

Speeding up transient simulation of power detector with PRBS input using PSS

SamLM929 — Wed, 25 Feb 2026 18:48:38 GMT

I have an RF power detector used for an AGC loop. The output of this power detector is put through a low-pass filter, while the data is coming in at 112Gbps PAM4. I'd like to test that the power detector has the expected response to changes in amplitude that are lower than the low-pass cutoff, but not sensitive to the data. This means I would have to simulate for 10+ microseconds, which is not practical to do when simulating across corners and temperatures.

My original thinking was that I could use PSS simulation as a starting point, and just use Pnoise or PAC to get the transfer function, and assume that changes in the data translate to phase noise and amplitudes, and from there calculate the maximum ripple in my filtered output based on that. I don't think this works though because the signal is large enough that these are not small amplitude changes, so it breaks the PSS operating point assumption.

My next thought is to use ENVLP analysis. Documentation shows that it's good for situations like an AGC loop with binary data. However it doesn't allow PRBS inputs at all, even here I have to use a pre-determined bitstream. If I generate a PRBS9 sequence and manually enter it into a vbit source, that works but it does not provide any speed improvement at all.

To summarize the problem so far the input, it is (a) 224GHz clock (b) 112Gbps PRBS data modulation and (c) low frequency ~100kHz amplitude modulation. The intention is for the output to track only the 100kHz amplitude modulation, meaning my simulation time has to be much larger than the clock.

What's the best way to speed up this simulation? Is there a clever way I can use data from a PSS simulation to speed up the transient? Or am I misunderstanding the ENVLP analysis entirely?

Working in Virtuoso IC23.1, using ADE Assembler. Any pointers or directions either in simulation or how I'm mathematically thinking about it would be very helpful, thank you in advance!

Spectre PSS simulation for sigma-delta modulator and verilogA model

StephanWeber — Wed, 25 Feb 2026 15:25:28 GMT

Hi,

fora sigma-delta modulator I made a verilogA model, and in transient simulation the results are very nice. However, I believe for a stable Vin PSS should be able to calculate the steady-state with good accuracy, and in PSS setup I can also apply nice sweeps.

As usual, I run into the issue of hidden state, so I add the ignore hidden state command before the module definition.

Now PSS runs, but it looks bad, although I made tstab very large!

Next I found out that ffund = 1MHz = fclk is (of course) to high, e.g. my modulator use DEM with 7 periods, so I went for ffund=1M/7, but that causes sometimes convergence issues AND the results are still often bad for most inputs.

Is there a way to improve, e.g. to tell Spectre about which variables in the VA module should be taken into account as state? Or should I go with other PSS settings? I decided for 7 harmonics & shooting (all other at default).

Bye Stephan

Getting more data after MC run directly in the Results table?

StephanWeber — Wed, 25 Feb 2026 15:10:10 GMT

Hi,

the ViVA calculator has some nice statistical functions, like average, stddev, skewness, kurtosis, and building more like Cpk or Jarque-Bera JB is not so difficult. But I struggle to get this not only in the calculator but really as output, e.g. to define a spec! E.g. we want Cpk>1.67 or e.g. JB<3 for check for Gaussian data.

What works so far is this:

I switch to Detailed table mode, select an output like Rsense or VoutDC, do a "plot across points", then I go to Viva and make "Send to Calculator", then I get an expression like swapSweep(Rsense "Design Points" "nom"), next I simply set x=swapSweep(Rsense "Design Points" "nom"). So it is no easy to get the mean and stddev and then to plot the Gaussian PDF of that fit.

However, I struggle to make that not only manually every time after the MC run but as output expression which would give a much higher automation. E.g. I want to see:

- The PDF plot for a fit for each MC analysis and my key outputs (I run MC vs VT corners)

- Also look for 5-sigma values

- Check if data is Gaussian, e.g. do also other fits like lognormal fit of JB is too large

- Or check at which corner the 5-sigma value is worst, etc.

This way I also do not need to plot Histograms etc. manually after each run.
His anybody done this before?

e.g. stddev(Rsense ?overall t) (with sweeps selected) works but skewness(Rsense ?overall t) (works in CIW!!) is changed to (skewness Rsense ?overall t)
same issue for kurtosis.

Are these Cadence-functions not registered in ADE?

Bye Stephan

New ADE feature for statistical design variable definition: Global vs local? Correlation?

StephanWeber — Wed, 25 Feb 2026 14:30:57 GMT

Hi,

today I found this nice feature in the MC setup window (last button), but I miss a bit to decide for global vs local variation. And how to define a correlation?

BTW, it would be good to get a template fill-out with onb click e.g. for standard normal variable.

I think if we define two variables they are independant, but building e.g. sum and looking the corr of this sum to the variables it will have some value, so basically a definition for correlated variables is possible. Just to have an example would be great.

Bye Stephan

Is random sampling necessary if LHS LDS exist

CC202602246636 — Wed, 25 Feb 2026 05:46:45 GMT

Monte Carlo Sampling Method

Fast Yield Analysis and Statistical Corners

I was studying about Monte Carlo Sampling methods and luckily I came by these two posts.

It seems that LHS and LDS give similar results for a limited number of runs when it comes to estimating the dataset, due to spreading out limited samples in the population.

Mathematically, when the number of runs reach infinite, sampling methods do not matter.

However, for a limited number of runs (which is usually the case) LHS and LDS are preferred over random sampling.

So are there any cases, as an analog designer, random sampling is preferred over LHS and LDS?

If no, then why does random sampling still exist as an option?

Thanks!

Spectre: No GPU device found

AB202601143241 — Tue, 24 Feb 2026 16:55:23 GMT

Hello,

We are facing problems when trying to get Spectre X GPU simulation / acceleration to work.

The system has an Nvidia Quadro RTX 6000 24GB with Turing Architecture which is reported by "nvidia-smi" as well as "deviceQuery". Also Matlab recognizes the gpu and can use it without issues. Thus, the drivers are working fine.

However, when running Spectre X with the +gpu switch, it fails to recognize the card (spectre.out):

Spectre (R) Circuit Simulator
Version 25.1.0.156.isr2 64bit -- 5 Sep 2025
Copyright (C) 1989-2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: XXXX Host: XXXX HostID: 65786970 PID: 252947

Linux : Red Hat Enterprise Linux release 9.7 (Plow)
CPU Type: Intel(R) Core(TM) i7-9800X CPU @ 3.80GHz
Socket: Processors [Frequency] (Hyperthreaded Processor)
0: 0 [1200.0] ( 8 ), 1 [2998.9] ( 9 ), 2 [2209.3] ( 10 )
3 [1200.1] ( 11 ), 4 [1200.0] ( 12 ), 5 [1200.0] ( 13 )
6 [3699.9] ( 14 ), 7 [2803.5] ( 15 )

System load averages (1min, 5min, 15min) : 8.0 %, 4.2 %, 2.6 %
Hyperthreading is enabled
HPC is enabled

Error found by spectre.
ERROR: No GPU device found

Aggregate audit (4:33:00 PM, Tue Feb 24, 2026):
Time used: CPU = 235 ms, elapsed = 235 ms, util. = 100%.
Peak memory used = 133 Mbytes.
Simulation started at: 4:33:00 PM, Tue Feb 24, 2026, ended at: 4:33:00 PM, Tue Feb 24, 2026, with elapsed time (wall clock): 235 ms.
spectre completes with 1 error, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

The checkSysConf command passes without issues, the optional nvcc is also found:

...

Validating OPTIONAL-FILE .....1 to check
# FILE Exists Status Info
- ---- ------ ------ ------------
1 %PATH%/nvcc YES OPTIONAL
Status..............: PASS

Validating OPTIONAL command version... 1 to check
# Optional command / version Status
- -------------------------- ------
1 nvcc / V12.8 Found version V13.1.115

...

Normal exit. This workstation (XXXX) status is: PASS
Host XXXX has a Cadence supported Linux configuration.

The article How to run Spectre X GPU-based simulations from Virtuoso ADE and command line suggest that the Turing architecture (Quadro RTX 4000) and even older Pascal architecture (Tesla P100) should be supported.

Is there any further way to debug compatibility of Spectre X with different gpus or check our setup in this regard?

We plan to buy more (recent) hardware and would like to confirm compatibility and performance with gpu processing before that.

Best regards,

Alex Bleitner

Disable License Queue Timeout

Kevin T Buck — Tue, 17 Feb 2026 16:41:50 GMT

I've set the licQueueTimeOut environment variable to 0 in my .cdsinit file (using envSetVal( "spectre.envOpts" "licQueueTimeOut" 'string "0")) and I can see this value in the Cdsenv Editor window. I expected that this would disable the timeout for license queueing in ADE but it does not seem to be honored, it still shows the default of 900 in the Environment Options window and the simulator will throw an error after 900 seconds has passed due to license timeout. Am I missing something?

I'm using tool version IC23.1-64b.ISR16.19 and using SpectreX as the simulator.

ADE Explorer: Disable Check for Analysis Specified

sgcad — Tue, 17 Feb 2026 15:49:26 GMT

Hi all,

By default, ADE Explorer checks if there is an analysis specified through the GUI and throws an error if one attempts to run a simulation without any analysis specified in the GUI.

How can I disable this check? Usually I specify my analyses with a netlist include file, thus the simulation should run even without analysis specified in the GUI.

Thanks very much for your reply!

Importing TSMC28 Standard Cell Library to Virtuoso

designerd2d — Mon, 16 Feb 2026 08:25:27 GMT

Hi,

Recently we've acquired backend views (spice/gds) for tsmc28 standard cell library. I am interested in importing the library for custom digital design in virtuoso. From a conversation we've had with our vendor, they recommend simulating the spice netlist (importing the gds for layout views is ok).

I have a few questions regarding the process:

1.Regarding the symbols:

I imported the .v file using the Verilog-In GUI, it seems to work but the symbols created are generic (i.e. rectangles with pins). Is it possible to automate the symbol creation process such that they are a little more meaningful (perhaps to copy them from a generic library like sample?)
The resulting pins are large rectangles, I could not figure out where in the GUI I can change them to be the normal squares ones?
Power pins in the .v file are called VDD/VSS, but after the import, they are called VDD! and VSS instead. How can I change VDD! to VDD during the import?

2. Regarding simulations, I am not sure on how to use the spice netlist for simulation purposes.

I would appreciate any help on the regard.

I am using IC23.1-64b.ISR2.29

Thank You