Cayenne

Berkeley Design Automation Analog FastSPICE™ Platform Adopted by Panasonic for Mass-Production of Mixed-Signal LSIs

noreply@blogger.com (Cayenne) — Tue, 19 May 2009 19:58:00 +0000

Platform Delivers Superior Verification Efficiency for Mixed-Signal and RF Analysis

SANTA CLARA, CA, —May 19, 2009— Berkeley Design Automation Inc., provider of the Analog FastSPICE™ unified circuit verification platform for advanced analog and RF integrated circuits (ICs), today announced that Panasonic Corporation, a world leader in products, systems, and components for consumer electronics, has selected the company's Analog FastSPICE™ platform for use in their production flow for verification of mixed-signal integrated circuits.

"We spend a significant amount of effort on mixed-signal verification and noise analysis of mixed-signal integrated circuits," said Masahiko Matsumoto, Director of the Analogue LSI Business Unit, Semiconductor Company, Panasonic Corporation. "After a rigorous evaluation of the Analog FastSPICE platform on a variety of mixed-signal integrated circuits, we have decided to deploy this platform for mass-production use in Panasonic."

Analog FastSPICE is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. Always delivering true SPICE accurate results, it provides 5x-10x higher performance than traditional SPICE, >1 million-element capacity, and the industry’s only comprehensive noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. AFS Platform tools include: AFS Nano SPICE simulator, Analog FastSPICE circuit simulator, Noise Analysis Option™ device noise analyzer, and RF FastSPICE™ multi-tone periodic analyzer.

"Today, we are seeing leading companies all over the world embarking on a major retooling for next-generation analog, mixed-signal, and RF design to improve their verification efficiency," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We are delighted that Panasonic Corporation has chosen to deploy the Analog FastSPICE platform for production use. This adoption validates, once again, that Berkeley Design Automation is an essential partner as companies embark on new tooling strategies for greater verification efficiency."

About Berkeley Design Automation

Berkeley Design Automation, Inc. is the recognized leader in advanced analog, mixed-signal, and RF (AMS/RF) verification. Its Analog FastSPICE unified circuit verification platform combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Design teams from top-10 semiconductor companies to leading startups use the AFS Platform to efficiently verify AMS/RF circuits. Founded in 2003, the company has received several industry awards in recognition of its technology leadership and impact on the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corporation, and NTT Corporation For more information, see http://www.berkeley-da.com.

IPextreme to Give Tutorial on Industry’s First IP-based Design Methodology at DesignCon 2009

noreply@blogger.com (Cayenne) — Mon, 12 Jan 2009 23:06:00 +0000

SILICON VALLEY, California – January 9, 2009 – At DesignCon 2009 in Santa Clara, CA from February 2-5, 2009, IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, is giving a CoReUse™ tutorial; featuring licensable, technology-independent Power Architecture processors in the Power.Org booth; and exhibiting. .

Tutorial:
What: “CoReUse/ QCore – Industry’s First IP-based Design Methodology and IP Compliance-checking Tool,” will give attendees a good understanding of the CoReUse IP-based design methodology and QCore CoReUse Compliance tool. Developed and used at NXP Semiconductors over the last 10 years, CoReUse represents not only the industry’s leading example of IP reuse at work, but is a living and practical IP-based design methodology that can adapt to changing technologies, standards, and EDA flows and that provides a proven framework for companies to develop and use semiconductor intellectual property. Since maintaining compliance to any methodology is difficult, NXP also developed QCore, a tool that is used for checking an IP’s compliance with the CoReUse standard.
Each attendee will receive one free printed copy of the CoReUse manual.
Track: TF-MP1

http://www.designcon.com/2009/attendees/schedule/1_tf_mp_1.asp

Who: Taught by Pierre Thomas, Vice President, Engineering, IPextreme, Inc.

When: Monday, February 2nd, from 1:30 to 4:30 pm

Registration: To register, please go to -- http://www.designcon.com/2009/register/

Power.org Exhibit Booth
IPextreme has been a member Power.org since 2006 and will be present, along with other members of the Power.org ecosystem, at the Power.org booth on February 3-4th. IPextreme and other members of Power.org will be presenting overviews of their respective Power Architecture solutions on February 5th.

What: IPextreme will be featuring its portfolio of licensable, synthesizable, technology-independent Power Architecture microprocessors

Who: Warren Savage, President and CEO, IPextreme, Inc. and Rick Tomihiro, Vice President, Marketing, IPextreme, Inc.

When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST

Where: Power.org Booth #753 (exhibition floor on Feb 3-4th) and Power.org Room #212 (on
February 5th. Times will be announced at the show.)

IPextreme Exhibit Booth
What: IPextreme provides designers with famous IP from leading semiconductor companies and has an extensive portfolio of automotive, consumer and processor IP. IPextreme will be available to answer questions in their booth on CoReUse, QCore or any of their available IP cores. There will also be a drawing twice daily to win a yearly subscription to the CoReUse Foundation eBooks.

When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST

Where: Booth #841

All events will be held at DesignCon (http://www.designcon.com/2009/) in the Santa Clara Convention Center, 5101 Great America Parkway, Santa Clara, California.

About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com

IPextreme and Core Store are registered trademarks of IPextreme Inc. All other product or service names are the property of their respective owners. All rights reserved.

Apache Design Solutions Introduces RedHawk-NX, the Next Generation Full-chip Dynamic Power Integrity Solution

noreply@blogger.com (Cayenne) — Mon, 12 Jan 2009 23:05:00 +0000

The industry’s first “hierarchical dynamic” solution delivers capacity and performance required for the most advanced technology designs

San Jose, Calif. – January 7, 2009 – Apache Design Solutions, the technology leader in power and noise analyses and signoff for chip, package, and system designs, today announced RedHawk-NX, the next generation dynamic power integrity solution re-architected to handle designs of five hundred million gates. The advanced technologies in RedHawk-NX include the industry’s first hierarchical dynamic power analysis, proprietary mesh pattern recognition and reuse, and multi-core support, enabling designers to analyze the most complex designs with sign-off accuracy.

As the semiconductor companies continue to push the capacity and performance limitations of EDA tools, Apache’s ability to deliver products that meet their demands provides key competitive advantage. Apache’s continuous investment in R&D has enabled the company to deliver re-architected next generation dynamic power solutions every three years, starting with the introduction of RedHawk-SD in 2002, RedHawk-EV in 2005, and RedHawk-NX in 2008. Each generation of products offers higher capacity and performance to address the latest design complexity in CPU, GPU, NPU, and devices with large memory contents.

“RedHawk technology roadmap is able to meet our design size and complexity needs for power noise analysis from one generation of our products to the next,” said Jean Boufarhat, vice president of engineering, from Graphics Products Group at AMD. “Specifically, RedHawk-NX allowed us to perform dynamic power noise analysis on our largest design with more than 750 million nodes. The ability to verify the entire chip including memories is critical to our design success.”

Hierarchical Dynamic (HD)
RedHawk-NX supports the industry’s first hierarchical dynamic technology allowing designers to adopt a bottom-up analysis methodology with various levels of abstraction. When using HD’s ‘white-box’ mode, the designers are able to maintain the same level of sign-off accuracy as RedHawk’s flattened analysis. By using HD’s ‘gray-box’ mode, designers gain additional capacity improvement.

Historically, hierarchical solutions were only available for static analysis where time-point-by-time-point waveform accuracy of the block-level simulation is not considered. With HD technology, IP providers can deliver encrypted Apache dynamic power views for use in full-chip sign-off analysis. HD also effectively supports industry’s hierarchical design methodologies across multiple design sites.

Mesh Pattern Recognition (MPR)
RedHawk-NX’s automatic mesh pattern recognition algorithm leverages regularity in the power/ground mesh structures enabling data reuse for effective reduction of physical memory needs. MPR handles designs with complex RDL, dense multi-layered P/G grid, and high memory content. MPR technology has been demonstrated to reduce RedHawk database memory footprint by 2-3X compared with existing techniques.

Multi-core Architecture (MC)
RedHawk-NX is re-architected to maximize the capacity and performance advantages of the multi-core processing systems. The MC solver can be scaled to handle designs with up to billion nodes in existing computing environment. With the MC technology, designers will benefit from 2-3X runtime improvements in their dynamic transient simulation, as well as MTCMOS rush current analysis.

“SoC power integrity and power induced system noise are clearly the top challenges for the semiconductor industry,” said Andrew Yang, CEO of Apache. “Power and noise is Apache’s focus and we continuously invest in R&D to maintain our ‘best-in-class’ and ‘first-in-class’ leadership position. This enables us to address customers growing design challenges and cost reduction needs.”

Apache Design Solutions, CPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc

IP Cores from IPextreme Support Mentor Graphics’ Precision® Synthesis FPGA Tool

noreply@blogger.com (Cayenne) — Thu, 18 Dec 2008 22:27:00 +0000

IP cores now validated for Precision logic and physical synthesis flow

Silicon Valley, CA, California – December 19, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, has validated its Multi-CAN Controller, its CJTAG-IEEE1149.7 IP cores and its 32-bit Power Architecture e200, V1 ColdFire, V2 ColdFire, 16-bit CR16CP and 8-bit HCS08 processor cores for use with Mentor Graphics Precision® Synthesis flow. Designers can now use the advanced features of Precision Synthesis to quickly and easily achieve superior results when integrating IPextreme cores into FPGAs.

“IPextreme has a large catalog of silicon-proven, synthesizable FPGA cores,” said Daniel Platzker, product line director of FPGA synthesis at Mentor Graphics. “Mentor delivers a comprehensive, vendor-independent FPGA design flow, and compatibility between Precision Synthesis and the IPextreme cores ensures success for mutual customers.”

“We work closely with Mentor to confirm the compatibility of our IP with their EDA tools,” said Rick Tomihiro, vice president of marketing for IPextreme. “Not only is our IP validated on the Precision Synthesis tool, but also our XPack IP packaging, distribution, configuration and support technology automatically generates configuration and constraints files for Precision Synthesis, which delivers excellent results for FPGA designers.”

All validated cores are available today, through the IPextreme Core Store® (http://www.ip-extreme.com/corestore/) or by contacting the company at www.ip-extreme.com.

About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com

IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.

# # #

Contacts for IPextreme:
Karen Crannell, IPextreme Inc., 408-540-0096, Karen.Crannell@ip-extreme.com
Europe:
Annette Bley, Bley PR, +44 (0) 20 7482 4800, annette@annettebleypr.com

North America:
Linda Marchant , Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

TSMC Selects Berkeley Design Automation Analog FastSPICE™ for Analog and Mixed-Signal IP Verification

noreply@blogger.com (Cayenne) — Wed, 17 Dec 2008 19:39:00 +0000

Tool Delivers SPICE Accuracy Five to Ten Times Faster for Complex Analog/Mixed-Signal Circuits

SANTA CLARA, Calif.--(BUSINESS WIRE)--Berkeley Design Automation Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), today announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has selected the company's Analog FastSPICE™ circuit simulator for complex-block characterization and full-circuit performance simulation of its analog and mixed-signal design environment. TSMC selected Analog FastSPICE based on the tool’s SPICE accuracy and performance.

“TSMC provides the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows,” said ST Juang, Senior Director of TSMC’s Design Infrastructure Marketing Division. “We selected Analog FastSPICE for our design teams because it delivered SPICE accurate results five to ten times faster than traditional SPICE on our analog/mixed-signal IP and building blocks across our major process technologies down to 45nm.”

Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. By using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any accuracy compromising shortcuts. Design teams from top-10 semiconductor companies and leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems.

"We are delighted that TSMC selected Analog FastSPICE for their analog and mixed-signal design environment," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We see TSMC’s adoption of our products for their design teams as a testimonial to our Precision Circuit Analysis technology. We are proud to help TSMC's Design Service Division accelerate their analog/mixed-signal design verification."

About Berkeley Design Automation

Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine's 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see http://www.berkeley-da.com.

Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

Contacts
PR for Berkeley Design Automation
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
michelle.clancy@cayennecom.com

IPextreme® Announces Availability of Freescale HCS08 Microprocessor IP Core

noreply@blogger.com (Cayenne) — Wed, 10 Dec 2008 19:36:00 +0000

Synthesizable IP core available through IPextreme’s online Core Store™ for $10,000 licensing fee
SILICON VALLEY, Calif.--IPextreme, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, is adding the Freescale HCS08 8-bit microprocessor to its line of industry standard 16-bit and 32-bit microprocessors. The Freescale HCS08 is a synthesizable, state-of-the-art, high performance and low power 8-bit microprocessor that can be easily integrated into any ASIC or FPGA design. The HCS08 also provides an easy migration path to Freescale’s 32-bit ColdFire architecture. Using Freescale’s CodeWarrior integrated development environment, assembly code for the HCS08 can be retargeted to the 32-bit V1 ColdFire with just a few mouse clicks.
“We are pleased to continue to expand the portfolio of Freescale IP made available for licensing through IPextreme,” says Jeff Bock, Freescale’s Global Microcontroller Marketing Manager. “The HCS08 provides a low-cost entry point and an easy migration to our ColdFire Architecture, giving designers the flexibility they need. IPextreme’s Core Store™ enables designers to get through the IP purchase process quickly and allows them to focus on their designs.”
Freescale has shipped hundreds of millions of devices based on the HCS08 processor architecture and thousands of embedded systems are utilizing it. Since the HCS08 IP core is object code compatible with currently available Freescale 68HC08 and HCS08 devices, embedded systems currently based on these processors are easily migrated to ASICs or FPGAs, and all software is fully binary compatible. In addition, users of the HCS08 can leverage the immense ecosystem of evaluation systems, development systems, compilers and application software.
“The HCS08 is a microprocessor that has already been utilized in many market segments such as consumer, industrial, medical, automotive and low-cost networking. Providing embedded system designers with a synthesizable version allows them to integrate their designs into ASIC or FPGAs while leveraging the extensive ecosystem of hardware and software development tools and maintaining complete software compatibility,” said Rick Tomihiro, vice president of marketing for IPextreme. “As usual, IPextreme will package, license and support these synthesizable cores.”
Pricing and Availability
The Freescale HCS08 core is available for licensing now. Like all IPextreme IP, the core is offered in a complete package that includes synthesizable source code, integration test bench, and complete documentation. Encrypted versions of the core are available from the Core Store at US $10,000. Full source code versions of the HCS08 and other Core Store IP are also available for additional fees.
For additional product information, please see http://www.ip-extreme.com/IP/hcs08
To purchase the HCS08 please visit the Core Store at http://www.ip-extreme.com/corestore/
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
Contacts
IPextreme Inc.Karen Crannell, 408-540-0096 Karen.Crannell@ip-extreme.comor
Europe: ley PRAnnette Bley, +44 (0) 20 7482 4800 annette@annettebleypr.com
North America: Cayenne Communications Linda Marchant, 919-451-0776linda.marchant@cayennecom.com

Synfora Presents Seminar to Aid SoC and FPGA Developers Design High-Performance Video Engines

noreply@blogger.com (Cayenne) — Fri, 05 Dec 2008 22:29:00 +0000

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Synfora Inc., the premier provider of algorithmic synthesis tools used to design SoCs and FPGAs, will conduct a seminar on the morning of Tuesday, December 9, 2008, to show SoC and FPGA developers of video IP how to reduce design and verification time while being able to explore alternative implementations that will let them decrease silicon area and power consumption.

The seminar will be conducted by a video expert who has assisted in the architecting and implementing of several leading-edge multi-standard video engines.

The seminar will be held at the Santa Clara Techmart Meeting Center from 10:00 AM to 12:00 PM, with lunch being provided from 12:00 to 1:00.

Who:							Synfora Inc.

What:							Technical seminar on using PICO Extreme tools to design high-performance video engines

When:							Tuesday, December 9, 2008
							10:00 AM – 12:00 PM

Where:							Techmart Meeting Center
							5201 Great America Parkway
							Santa Clara CA 95054

Synfora’s PICO Extreme allows designers to rapidly create and verify such complex hardware sub-systems as video codecs, wireless modems and imaging pipelines from an untimed C source. This seminar will introduce the PICO verification tools and methodology and describe how they can be used to design a codec, provide other video system design examples, and include a Q&A session to help clarify any concerns or issues not otherwise covered.

Registration for the seminar is now open at http://www.synfora.com/seminar/index.html.

About Synfora Inc.

Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora's technology helps to reduce design costs, dramatically speed chip development, and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company's investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit http://www.synfora.com.

Contacts

Editorial Contact:
PR for Synfora
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
michelle.clancy@cayennecom.com
or
Joe Fowler, 408-410-2451
joe.fowler@cayennecom.com

Teridian Semiconductor Licenses ColdFire® Architecture from IPextreme®

noreply@blogger.com (Cayenne) — Thu, 20 Nov 2008 22:22:00 +0000

Freescale V2 ColdFire Standard Product Platform (SPP) to be used for IC power metering

CAMPBELL, California – November 20, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, today announced that Teridian Semiconductor Corp., a leading supplier of mixed-signal integrated circuits (ICs) used in energy, automation, networking, and secure access systems, has licensed Freescale’s V2 ColdFire® SPP IP core through IPextreme. Teridian selected the V2 ColdFire core after evaluating several processor cores for use in the company’s power metering solutions.

“We found the V2 ColdFire core to offer the best balance between cost and performance for large scale smart metering applications requiring integrated communications capabilities,” said Kourosh Boutorabi, vice president and general manager of metering products at Teridian Semiconductor. “The expansive ecosystem around the ColdFire cores combined with IPextreme’s demonstrated expertise in IP integration created additional value for us.”

“As a market leader, Teridian was looking for a 32-bit microprocessor with very good area, power, performance and price characteristics, along with a rich set of peripherals that would extend their lead into the future,” said Rick Tomihiro, vice president of marketing for IPextreme. “The V2 ColdFire Standard Product Platform, is the perfect fit.”

About Teridian Semiconductor
Teridian Semiconductor designs, sells and provides engineering support for its mixed-signal integrated circuits used in energy, automation, networking, and secure access systems. These ICs connect our customers’ digital systems to the analog inputs of our world found in utility metering, industrial automation, set top box, digital TV, voice over IP, electronic identity and point of sale applications.

Teridian Semiconductor is Simplifying System integration™ for its customers with a focus on accelerating system development, and reducing the engineering time required to achieve production. For more information, visit http://www.teridian.com.

About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com

IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.

# # #

Contacts for IPextreme:
Karen Crannell, IPextreme Inc., 408-540-0096, Karen.Crannell@ip-extreme.com

Europe:
Annette Bley, Bley PR, +44 (0) 20 7482 4800, annette@annettebleypr.com

North America:
Linda Marchant , Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

Asahi Kasei EMD Selects Berkeley Design Automation Analog FastSPICE™ for Precision Mixed-Signal Simulation

noreply@blogger.com (Cayenne) — Tue, 18 Nov 2008 23:47:00 +0000

Japan’s Mixed-Signal/RF IC Leader Achieves Dramatically Faster Verification Time and True SPICE Accuracy for Wireless, Consumer, and Automotive ICs

SANTA CLARA, CA, —November 18, 2008— Berkeley Design Automation Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), today announced that Asahi Kasei EMD, a leading global supplier of mixed-signal and RF integrated circuits for wireless, consumer electronics, and automotive applications, has selected the company's Analog FastSPICE™ circuit simulator for full-circuit functional simulation and complex-block characterization of its mixed-signal and RF integrated circuits. Asahi Kasei EMD is the core operating company for all electronics materials and devices of the Asahi Kasei Group, and has been one of Berkeley Design Automation’s earliest customers in Japan.

“AKE has earned a worldwide reputation for outstanding analog-digital mixed-signal/RF technology, and our products feature high performance, high precision, high integration, and low power consumption,” said Toshikazu Suzuki, Head Design Technology at Asahi Kasei EMD. “Analog FastSPICE meets a critical need for our mixed-signal/RF IC designers- super fast performance combined with true SPICE accuracy- which was impossible with any other simulator. We reduced simulation time for our complex sigma-delta ADCs, integer and fractional PLLs, and transceivers by 5x-10x with true SPICE accuracy. We have been able to easily integrate this into our proprietary design flow, thereby dramatically reducing verification times for our engineers developing complex mixed-signal circuits for wireless, consumer, and networking applications.”

Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.

Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems. Typical applications include characterizing complex blocks (e.g., PLLs, ADCs, DC:DC converters, PHYs, Tx/Rx chains) and running performance simulation of full circuits (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).

“We are excited that Asahi Kasei EMD, a leading supplier of complex mixed-signal and RF integrated circuits, has selected Analog FastSPICE as a key component of their verification environment,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “Asahi Kasei EMD designs some of the most complex, high-performance, low-power mixed-signal and RF integrated circuits in the world. We are happy that Analog FastSPICE provides AKE with the accuracy and performance required for the verification of these complex circuits. We are delighted to see their continued confidence and growing investment in our technology and products.”

About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine’s 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see http://www.berkeley-da.com.

Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

PR for Berkeley Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

Analog/Mixed-signal Papers Co-Authored by Solido Design CSO to be Presented at ICCAD

noreply@blogger.com (Cayenne) — Fri, 07 Nov 2008 22:06:00 +0000

Who: Solido Design Automation
What: Technical papers on analog integrated circuit design
When: Tuesday, November 11, 2008
Where: International Conference on Computer-Aided Design (ICCAD), DoubleTree Hotel, San Jose, CA

The 2008 ICCAD is being held November 10 - 13 at the DoubleTree Hotel in San Jose, California. The session at which the two papers, "Automated Extraction of Expert Knowledge in Analog Topology Selection and Sizing" and "Importance Sampled Circuit Learning Ensembles for Robust Analog IC Design," will be presented begins at 10:30 AM on Tuesday, November 11, in the Pine Ballroom.

About Solido Design Automation

Solido Design Automation Inc. provides process variation solutions for transistor-level designers of analog/mixed-signal, custom digital, and memory integrated circuits. The privately held company is venture capital funded and has offices in the U.S.A., Canada, Japan and Europe. For further information, visit www.solidodesign.com or call 306-382-4100.

Editorial Contact:

PR for Solido Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

ADVISORY: Analog/Mixed-Signal Papers Co-Authored by Solido Design CSO to be Presented at ICCAD

noreply@blogger.com (Cayenne) — Fri, 07 Nov 2008 17:02:00 +0000

San Jose, Calif. – November 7, 2008 – Two technical papers co-authored by Trent McConaghy, co-founder and Chief Scientific Officer of Solido Design Automation, will be presented on November 11, 2008, at the 2008 ICCAD (International Conference on Computer-Aided Design). The papers propose novel analog integrated circuit design aids and methodologies.

Who: Solido Design Automation
What: Technical papers on analog integrated circuit design
When: Tuesday, November 11, 2008
Where: International Conference on Computer-Aided Design (ICCAD)
DoubleTree Hotel
San Jose, CA
Pine Ballroom
The 2008 ICCAD is being held November 10 - 13 at the DoubleTree Hotel in San Jose, California. The session at which the two papers, “Automated Extraction of Expert Knowledge in Analog Topology Selection and Sizing” and “Importance Sampled Circuit Learning Ensembles for Robust Analog IC Design,” will be presented begins at 10:30 AM on Tuesday, November 11, in the Pine Ballroom.
About Solido Design Automation
Solido Design Automation Inc. provides process variation solutions for transistor-level designers of analog/mixed-signal, custom digital, and memory integrated circuits. The privately held company is venture capital funded and has offices in the U.S.A., Canada, Japan and Europe. For further information, visit www.solidodesign.com or call 306-382-4100.
# # #
Editorial Contact:
PR for Solido Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com
Joe Fowler, 408-410-2451, joe.fowler@cayennecom.com

ADVISORY/ ClioSoft to Host Webinar on Effective Design Data Management for Digital, RF, Analog and Mixed-signal ICs

noreply@blogger.com (Cayenne) — Thu, 06 Nov 2008 15:53:00 +0000

FREMONT, Calif., November 6, 2008 – On November 13th, ClioSoft, Inc., supplier of the design data management (DDM) suite of choice for the electronics industry, will host a webinar to help teams using the Cadence Virtuoso flow manage the explosion of design data. The webinar will focus on making teams that are designing digital, RF, analog or mixed-signal ICs more productive by improving collaboration with other designers across the aisle or across the ocean.

WHAT: Webinar outlining the benefits of design data management in custom IC flows, with an emphasis on multi-site collaboration, optimum use of resources, and issue tracking, followed by a Q&A session. Methodologies and best practices used by mid to large design teams will be covered.

WHO: Of interest to CAD managers and design managers using Cadence Virtuoso or other IC design flows

HOW: To register, please visit http://www.cliosoft.com/seminar/

WHEN: Thursday, November 13th, from 10:00 am until approximately 11:00 am Pacific.
About ClioSoft:
ClioSoft is the design data management solution provider of choice for the electronics design industry. ClioSoft's SOS Design Data Collaboration Platform enables efficient management of design data from concept through tape-out and improves global team productivity. Built to handle the unique demands of designers, the SOS platform gives design teams the freedom and flexibility to choose the way they work, share and collaborate. Custom engineered adaptors seamlessly integrate SOS with leading design flows - Cadence® Virtuoso® Custom IC, Mentor ICstudio and SpringSoft Laker. ClioSoft's innovative Universal DM Adaptor technology "future proofs" your data management needs by ensuring that data from any flow can be meaningfully managed.
For additional information, please see www.cliosoft.com.
# # #

Media Contact:
Linda Marchant, Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

ADVISORY/ IPextreme and Texas Instruments Host Webinar for European Audience on “Next Generation Test and Debug: cJTAG – IEEE 1149.7”

noreply@blogger.com (Cayenne) — Tue, 04 Nov 2008 23:57:00 +0000

CAMPBELL, California – November 3, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, and Texas Instruments Incorporated (TI) (NYSE: TXN) will hold a webinar on Tuesday, November 11, 2008 on the first semiconductor IP solution to implement the new IEEE 1149.7 test and debug standard.

The cJTAG – IEEE 1149.7 IP core was developed by TI and packaged and distributed and supported by IPextreme (see http://www.businesswire.com/portal/site/home/permalink/?ndmViewId=news_view&newsId=20080902005263&newsLang=en).
What: The webinar, entitled ““The Next Generation Test and Debug: cJTAG - IEEE 1149.7,” will cover the new IEEE 1149.7 standard and the robust features available in the cJTAG – IEEE 1149.7 IP core.
Abstract: cJTAG – IEEE 1149.7 is the first semiconductor IP solution to implement the new IEEE 1149.7 test and debug standard. IEEE 1149.7 does not change or replace IEEE 1149.1; instead, it offers a scalable set of extensions to the IEEE 1149.1. Some of the advantages of the new IEEE 1149.7 standard are that it requires fewer pins and that it adds power management and powerful new debug features while maintaining full compatibility with existing IEEE 1149.1 based hardware and software.

Who: Stephen Lau from TI and Pierre-Xavier Thomas and Rick Tomihiro from IPextreme will cover the new IEEE 1149.7 standard and the robust set of features available in the cJTAG – IEEE 1149.7 IP core. Learn how the cJTAG – IEEE1149.7 IP core can be utilized in your next chip design.

When: The webinar will be held on Tuesday, November 11, from 1600hrs to 1700hrs Central European Time/ 7:00am to 8:00am Pacific Standard Time.

How: To register, please go to https://www2.gotomeeting.com/register/746445965

About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com

IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.

# # #

Contacts for IPextreme:
Karen Crannell, IPextreme Inc., 408-540-0096, Karen.Crannell@ip-extreme.com

Europe:
Annette Bley, Bley PR, +44 (0) 20 7482 4800, annette@annettebleypr.com

North America:
Linda Marchant , Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

Apache Design Solutions Ranks in Top 15 of the Fastest Growing Software and Information Technology (IT) Companies in Deloitte’s Technology Fast 50

noreply@blogger.com (Cayenne) — Tue, 04 Nov 2008 22:05:00 +0000

Industry Leading Power and Noise Solutions and Customer Focus Lead to 2,524 Percent Revenue Growth over Five Years

San Jose, Calif., November 5, 2008— Apache Design Solutions, the technology leader in power and noise analysis and signoff solutions for chip, package and system designs, has been named among the Top 15 of Deloitte's prestigious Technology Fast 50 Program, a ranking of the fastest-growing software and IT companies in the Silicon Valley. Rankings are based on average percentage revenue growth from 2003-2007.

Apache’s revenue grew 2,524 percent over five years, and on October 16, 2008, the company announced its 23rd consecutive quarter of record bookings and revenue. Apache has also been continuously profitable since 2004. Apache’s CEO, Andrew Yang credits the company’s long-term success to its conservative business model, solid execution, and strong customer focus.

“Apache’s aggressive product vision and continuous investment in research and development has enabled us to deliver first-in-class and best-in-class solutions that address the power and noise challenges of chip, package, and system markets,” said Andrew Yang, CEO of Apache. “We are proud to be named to Deloitte’s Technology Fast 50 list as it acknowledges our success in delivering innovative technologies and consistently effective execution strategy.”

“Deloitte’s Silicon Valley Technology Fast 50 companies have shown the strength, vision and tenacity to succeed in today’s very competitive technology environment,” said Mark Jensen, Managing Partner, National Venture Capital Services, Deloitte & Touche LLP, in Silicon Valley. “We applaud the success of Apache Design Solutions, and acknowledge it as one of the very few to accomplish such a fast growth rate over the past five years.”

This year’s Silicon Valley Technology Fast 50 program is co-presented by Deloitte, Silicon Valley Bank, Korn/Ferry International, Cooley Godward Kronish LLP, Cornish & Carey Client Solutions, and ABD Insurance and Financial Services – A Wells Fargo Company. Companies from the regional Technology Fast 50 programs in the United States and Canada are automatically entered in Deloitte’s Technology Fast 500 program, which ranks North America’s top 500 fastest growing technology, media, telecommunications and life sciences companies. For more information on Deloitte’s Technology Fast 50 or Technology Fast 500 programs, visit www.fast500.com.

Apache Design Solutions, CPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

Berkeley Design Automation Delivers Industry's First Fractional-N PLL Transistor-Level Noise Analysis

noreply@blogger.com (Cayenne) — Thu, 23 Oct 2008 17:18:00 +0000

Tool Verifies and Optimizes PLL Noise and Jitter with True SPICE Accuracy

Santa Clara, CA, — October 23, 2008— Berkeley Design Automation, Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), today announced the industry's first closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level. Combining transient noise and periodic noise analysis in the company's Noise Analysis Option™ device noise analyzer, designers can now optimize and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication. The result is improved performance, lower power, and faster time-to-market. The Noise Analysis Option is an option to the company's award winning Analog FastSPICE™ circuit simulator, which is widely recognized as delivering true SPICE accurate results 5x-10x faster on 5x-10x larger circuits than any alternative.

Fractional-N PLLs are used across a wide variety of applications for their superior resolution and performance. Until now, however, it has been impossible to accurately analyze their closed-loop phase noise and jitter at the transistor-level including subtle time-varying device noise effects such as flicker noise and spurs. Instead, design teams have had to rely on behavioral modeling approximations and costly test chips. The Berkeley Design Automation Noise Analysis Option delivers the industry's first closed-loop transistor-level fractional-N PLL noise analysis, including the effects of device noise, with true SPICE accuracy.

"Accurate transistor-level noise analysis of complete fractional-N PLLs is becoming critical for nanometer RFICs, but this analysis has been impossible or impractical," said Edward Youssoufian, Director of RF Engineering and Founder, Newport Media, Inc. "Only the Noise Analysis Option can measure our fractional-N PLL closed-loop noise analysis with true SPICE accuracy. Adding Analog FastSPICE Co-Simulation for our PLL's digital blocks increased performance another 3x and produced identical results. The PLL phase noise in both cases correlated extremely well with our silicon measurements."

Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.

Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems. Typical applications include complex-block characterization (e.g., PLLs, ADCs, DC:DC converters, PHYs, Tx/Rx chains) and full-circuit performance simulation (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).

"Customers designing complex analog/RF circuits in nanometer CMOS are rapidly adopting our noise analysis solution to optimize their designs prior to tapeout," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We are proud to deliver another industry breakthrough - a practical and comprehensive noise analysis tool for complex analog and RF circuits, including fractional-N PLLs. We are very pleased with the excellent results our customers are obtaining with this tool, and are confident that this technology will make a dramatic difference for designers of tomorrow's leading-edge analog, RF, and mixed-signal circuits."

About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine's 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see http://www.berkeley-da.com.

Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

PR for Berkeley Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

IPextreme® Delivers Free Freescale™ V1 ColdFire Processor for Altera™ Cyclone® III FPGA

noreply@blogger.com (Cayenne) — Wed, 22 Oct 2008 17:16:00 +0000

CFV1CORE_Altera available now

CAMPBELL, Calif. – October 21, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, today announced immediate availability of the Freescale™V1 ColdFire IP core optimized for Altera ™ Cyclone® III FPGAs (CFV1CORE_Altera). This CFV1CORE_Altera processor core can be downloaded, free of charge, at IPextreme’s online marketplace, the Core Store™.

Customers who have already taken advantage of IPextreme’s free V1 ColdFire FPGA CIII IP include: Arrow Electronics, EBV Elektrolink, EFO Ltd., Fachhochschule Kaiserslautern, Future Electronics (Canada), Mahr, National Aeronautics and Space Administration (NASA), Technology Service Corp., and University De Las Palmas.

About V1 ColdFire Processor
The V1 ColdFire Processor offers a low-cost entry point into the ColdFire 32-bit processor architecture. A simplified version of the V2 ColdFire Processor, the V1 ColdFire Processor is a high performance low-power, low-area implementation that is fully upward compatible to other ColdFire implementations such V2, V3, and V4. Debug support is implemented through a single-wire background debug module (BDM) interface. A separate debug clock enables shut-down of debug logic when not in use.

For complete information about this IP core, please see our product brochure at http://www.ip-extreme.com/IP/coldfire_altera_v1.html

License Pricing and Availability
The V1 ColdFire IP core optimized for Altera ™ Cyclone® III FPGAs is completely free of charge to Altera customers and is available now for download. IPextreme will directly license and support the CFV1CORE_Altera core to Altera customers. For more information about all the Freescale ColdFire processor cores, or to obtain a license from IPextreme, visit the IPextreme Core Store at http://www.ip-extreme.com/corestore

About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com

IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.

Solido Design Automation Expands Support to Address Process Variation Challenges Facing the European Analog/Mixed-signal Market

noreply@blogger.com (Cayenne) — Mon, 20 Oct 2008 18:22:00 +0000

San Jose, Calif. – October 20, 2008 – Solido Design Automation, a leading developer of process variation solutions for transistor-level designers of analog/mixed-signal, custom digital, and memory integrated circuits, today announced an agreement with Sipeda Ltd., a U.K-based company, to serve as Solido’s representative for the European market. Under the agreement, Sipeda, which provides sales, marketing and commercial services to fabless semiconductor companies, EDA (electronic design automation) developers and intellectual property (IP) providers, will have overall responsibility for building awareness of Solido and its products, and for developing Solido sales in the U.K. and mainland Europe. This represents a significant move in Solido’s overall expansion strategy.

Solido Design Automation offers a new class of EDA software that enables chip designers to gain insight into the effects of process variations on their designs and to make designs more robust to these effects without over-designing. Solido’s customers using SolidoSTAT, their initial product offering, are able to quickly analyze failures in their designs caused by process variation; to identify weaknesses in the design; and to fix the design, making it robust to process variation.

“We are developing Solido into a truly global player in the EDA market, and we’re very excited to be working with Sipeda to create a presence in Europe that will help us realize this goal,” said Amit Gupta, CEO of Solido. “The European market is diverse and dynamic, and represents an opportunity to generate significant business for us. Sipeda’s relationships with the key analog/mixed-signal, custom digital and memory semiconductor companies will prove to be of great value in our business expansion efforts in Europe.”

“Solido is on the forefront of providing technology that addresses process variation challenges in transistor-level design,” said Ian Yates, CEO of Sipeda Ltd. “The combination of our sales, consulting and business development services with Solido’s technology will give European customers an unparalleled solution for their IC design needs.”

Ian Yates has over 30 years of high-technology business experience. Before founding Sipeda Ltd. in 2001, he was Senior Vice President of Operations for ARC International. In that role, he was responsible for ARC’s engineering and support centers in the U.K., U.S. and Canada, which developed processor and peripheral technology, software IP and a range of development tools. Prior to that, Mr. Yates was a founder and Director of Spectrum Services Europe at Cadence Design Systems, and also served on the board of directors of Accent Srl, a joint venture between Cadence and ST Microelectronics, and on the board of European CAD Developments Ltd., a joint venture between Cadence and European Silicon Structures. His experience also includes serving as European Managing Director of Gateway Design Automation, co-founding the European operations of Cadnetix Design Systems, a U.S. EDA company, and holding various commercial roles at Racal Redac, a U.K. EDA company.

Mr. Yates holds a first class honors degree in Electrical and Electronic Engineering from the University of Bradford, England.

About Solido Design Automation

Editorial Contact:

PR for Solido Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com
Joe Fowler, 408-410-2451, joe.fowler@cayennecom.com

Apache Design Solutions Achieves Record Sales for the Twenty-Third Consecutive Quarters

noreply@blogger.com (Cayenne) — Wed, 15 Oct 2008 21:50:00 +0000

Increasing Investments by Leading Semiconductor Companies Contribute to Growth

San Jose, Calif. – October 15, 2008 – Apache Design Solutions, the technology leader in power and noise analyses and signoff for chip, package, and system designs, today announced that the company has achieved its 23rd consecutive quarter of record bookings and revenue, while maintaining profitability. The Q3 growth came from increasing investments by existing customers that represent the top tier semiconductor companies and adoption by new customers facing power and noise challenges as they move towards 45/32nm technologies.
In today’s market, cost reduction and risk mitigation are essential for companies to remain competitive. IC and system customers are looking for solutions that enable them to make reliable cost saving decisions throughout the product development flow. Apache has an established expertise and technology leadership for a strong partnership with tier 1 companies to address the leading challenges for SoC, analog, package, and system designs.
“Over the past several years, Apache has continued to innovate and expand our product portfolio while practicing sound business fundamentals. Apache’s 10+ product offerings focusing on chip-package-system convergence are adopted by customers across the globe in a variety of industry segments,” said Andrew Yang, CEO of Apache. “Our consecutive quarters of growth reflect the value that our products offer to customers business.”
About Apache Design Solutions
Apache delivers the industry’s leading power and noise analyses solutions from early-stage to signoff for chip, package, and system designs. Apache’s innovative platforms considers multiple noise sources that impact the design--such as power, signal, package / system IO, substrate, and temperature—and enables engineers to optimize and validate their designs. Certified by TSMC and Common Platform Reference Flows, Apache’s products are adopted by 80% of the top IDM, fabless semiconductor, and foundries for risk mitigation, cost reduction, and time-to-market improvements. Apache is a global company with R&D centers and direct sales / support offices worldwide. For more information, visit www.apache-da.com.

Apache Design Solutions, CPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

Contact:
Apache Design Solutions
Yukari Ohno, (408) 457-2000, yukari@apache-da.com

Public Relations for Apache
Cayenne Communication
Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com

ClioSoft to Demonstrate Design Data Management Support for Cadence IC 6.x at the 13th Si2/OpenAccess+ Conference

noreply@blogger.com (Cayenne) — Wed, 15 Oct 2008 21:48:00 +0000

FREMONT, Calif., September 13, 2008 – ClioSoft, Inc., supplier of the leading design data management suite for hardware and software developers, will be demonstrating design data management (DDM) support for the Cadence® Virtuoso® custom design platform at the 13th Si2/OpenAccess+ conference in Santa Clara on Monday, October 13, 2008.

ClioSoft and Cadence will jointly demonstrate the seamless integration of the ClioSoft SOS Design Collaboration Platform with the Cadence Virtuoso 6.1.3 release, compliant with the OpenAccess standard. SOS provides management and versions control of design data, streamlining the design process by enhancing communication and facilitating efficient and accurate sharing of design data from concept through tape-out. The tight integration of ClioSoft’s DDM suite with the Cadence Virtuoso design flow improves design team productivity, reduces the chance of mask respins due to configuration errors and makes design reuse more efficient.

"ClioSoft is an important member of the Cadence Virtuoso eco-system,” said Steven Lewis, product marketing director at Cadence. "ClioSoft's SOS DDM, combined with the Virtuoso 6.1.3 release, provides customers not only with an optimized design flow, but also with the confidence to easily track and maintain their design IP.”

“ClioSoft's SOS Design Collaboration Platform is seamlessly integrated with Virtuoso 6.x just as it is with the earlier releases of Virtuoso using the CDBA database,” said Srinath Anantharaman, CEO of ClioSoft. “We have been surprised at the rapid rate of adoption of Virtuoso 6.x. Several of our larger customers have been using the SOS DDM integrated with the Virtuoso 6.x flow for over a year.”

In June 2008, Cliosoft introduced a free, “lite” version of the SOS DDM system that provides a complete revision control solution for Cadence Virtuoso, suitable for small teams of engineers working at the same location. To request additional information on this zero cost solution, please visit http://ic6.cliosoft.com/

For additional information on the Si2/OpenAccess+ conference, please see http://www.si2.org/

About ClioSoft:
ClioSoft is the design data management solution provider of choice for the electronics design industry. ClioSoft's SOS Design Data Collaboration Platform enables efficient management of design data from concept through tape-out and improves global team productivity. Built to handle the unique demands of designers, the SOS platform gives design teams the freedom and flexibility to choose the way they work, share and collaborate. Custom engineered adaptors seamlessly integrate SOS with leading design flows - Cadence® Virtuoso® Custom IC, Mentor ICstudio and SpringSoft Laker. ClioSoft's innovative Universal DM Adaptor technology "future proofs" your data management needs by ensuring that data from any flow can be meaningfully managed.
For additional information, please see www.cliosoft.com.
# # #

Media Contact:
Linda Marchant, Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

Verification Now 2008 Global Seminar Series to Focus on Verification Planning and Advanced Techniques for SystemVerilog Testbench Design

noreply@blogger.com (Cayenne) — Tue, 07 Oct 2008 21:53:00 +0000

Independent Experts Deliver Technical “How To” Program

SUNNYVALE, Calif., October 7, 2008 –The Verification Now 2008 global seminar program, set to launch on October 14 and run through November 3, will provide design and verification engineers with technical “how to” information that addresses key points of pain in today’s verification methodologies. The technical content of the program has been developed by independent third-party verification experts, Verilab, Inc. For more information, please visit www.verification-now.com.

Verification Now 2008 Overview
Complex system-on-chip (SoC) designs require a well-thought-out verification strategy. Proper verification planning and the use of advanced techniques in a SystemVerilog environment can help guarantee that the design and testbench verification process will be successful and efficient. The full-day technical seminar will provide design and verification engineers with information on why verification planning is needed, and how to effectively apply planning to existing design methodologies. The seminar also will look at the importance of layered stimulus generation techniques to build flexibility and reusability into a SystemVerilog testbench, and will outline how to implement those techniques.

The program will be presented by J.L. Gray of Verilab, author of the Cool Verification blog. The agenda and detailed abstracts on requirements-based verification and on building flexible and reusable testbenches using a layered approach to stimulus generation can be found on the Verification Now website at http://www.verification-now.com. Sponsors of the event are Certess, Inc., Denali Software, Inc., and SpringSoft Inc., and media sponsor is EDN magazine.

Seminars will be held in:

Santa Clara, Calif., at TechMart on Tuesday, October 14, 2008
Austin, Tex., at the Hyatt Regency Austin on Tuesday, October 21, 2008
Yokohama City, Japan, at the Pan Pacific Yokohama Bay Hotel on Monday, October 27, 2008
Taipei, Taiwan, at the Grand Hyatt Taipei on Friday, October 31, 2008
Herzliya, Israel, at the Dan Accadia Herzliya Hotel on Monday, November 3, 2008

For additional information, please see the Verification Now 2008 website -- http://www.verification-now.com/ -- or contact us at info@verification-now.com.

About the Sponsors
Certess, Inc.
Certess, Inc., is the only electronic design automation company providing functional qualification products for companies that create and integrate complex design blocks for systems on a chip (SoCs) or intellectual property (IP).The company’s technology provides design and verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs and ensure high-quality designs. The company is headquartered in Campbell, CA. For additional information, see www.certess.com.

Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and semiconductor intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California, and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

SpringSoft, Inc.
SpringSoft, Inc., (TAIEX: 2473) is a global supplier of specialized automation technologies that accelerate engineers during the design, verification and debug of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Its award-winning product portfolio features the Novas Verification Enhancement and Laker Custom IC Design solutions used by more than 400 of today's leading IDM and fabless semiconductor companies, foundries, and electronic systems OEMs. Headquartered in Hsinchu, Taiwan, and San Jose, California, SpringSoft is the largest company in Asia specializing in IC design software and a recognized industry leader in customer service, with more than 400 employees located in multiple R&D sites and local support offices around the world. For more information, visit www.springsoft.com.

Verilab, Inc.

Verilab is an elite international team of verification experts specializing in solving the toughest problems in VLSI functional verification. Our consultants have expertise in all major functional verification languages and methodologies, and have completed over 150 in a variety of domains including CPU, networking, SoC, smartcard and automotive applications. Verilab consultants have assisted clients around the world with training, methodology evaluation, project management, and testbench development from our sites in Austin, Munich, Bristol and Glasgow.

Media Contact:

Michelle Clancy, Cayenne Communication, +1 (252) 940-0981, michelle.clancy@cayennecom.com

Solido Design Automation Adds Semiconductor Industry Veteran, EDA Visionary to Advisory Board

noreply@blogger.com (Cayenne) — Mon, 29 Sep 2008 18:19:00 +0000

San Ramon, Calif. - September 29, 2008 - Solido Design Automation today announced that James Hogan, a widely recognized expert in EDA (electronic design automation) tools and technologies, has become a member of the company's Advisory Board. In that capacity, he will draw upon his more than 30 years of experience as a senior executive in EDA and semiconductor intellectual property, manufacturing equipment and fabrication companies to provide strategic and tactical guidance to Solido.

"We're very pleased to add someone of Mr. Hogan's caliber to our Advisory Board, and anticipate that his assistance will be instrumental in helping Solido reach the next levels of success," said Solido President and CEO Amit Gupta. "We feel that attracting such a valuable and experienced resource, who is widely recognized as an expert in the EDA industry, is a validation of our technologies and approach to the challenges of the EDA tools market."

"New tools are becoming an increasingly important requirement in analog EDA, particularly process variation design tools that can prevent circuit failures and over-design in analog/mixed-signal and custom integrated circuits," Mr. Hogan said. "I'm excited about the opportunity to work with Solido in advancing its development and dissemination of such tools."

Mr. Hogan, who now functions as a private investor, was most recently a General Partner at Telos Venture Partners, having previously served as Senior Vice President of Business Development at Artisan Components Inc., now part of ARM Holdings PLC. Prior to that, he held senior engineering, marketing and operational management positions at Cadence Design Systems, including Executive Fellow, President of Cadence Japan, Corporate Vice President of Marketing, and Corporate Vice President for Field Operations. He has also established global device physics laboratories for National Semiconductor and Phillips Semiconductor, and was Chief Operating Officer of Smart Machines, Inc., a semiconductor equipment automation company.

Mr. Hogan holds BA in mathematics, BS in computer science and MBA degrees from San Jose State University. He serves on the Board of Advisors at the San Jose State University School of Engineering, and on the boards of directors of CiraNova, and Xpedion Design Systems. He has previously served on the boards of directors of ClearShape Technologies and Ponte Solutions.

About Solido Design Automation

Solido Design Automation Inc. provides process variation solutions for transistor-level designers of analog/mixed-signal, custom digital, and memory integrated circuits. The privately held company is venture capital funded and has offices in U.S.A., Canada, Japan and Europe. For further information, visit www.solidodesign.com or call 306-382-4100.

Editorial Contact

PR for Solido Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com