CircuitValley : Embedded Engineering

CHC5 Open Camera ISP FPGA Architecture Part 5

2026-08-30T03:40:43.781+02:00

This post this Part 5 in the Multi part Series of the , Part 1 we Compared sensor, Part 2 was Hardware and Mechanical Design, Part 3 about Sensor Solution, Part 4 About Software Arch, This Part 5 is going in details about FPGA/PL Pipeline. This Part primarily focus how FPGA PL ISP Blocks is implemented where boundary between PL modules are defined.

CHC5 ISP

Most Basic FPGA Pipeline

CHC5 Advance Custom Pipeline Full Optmized

Capture front end

MIPI D-PHY receiver - Xilinx D-PHY primitive, 4 data lanes at 1250 Mbps.

Converts the sensor's serial MIPI electrical signalling into the parallel PPI byte interface for the CSI-2 receiver.

CHC5 CSI-2 receiver - the in-house CSI-2 parses lanes into packets and ECC/CRC-checks them.

Emits the RAW Bayer AXI-Stream video plus error/status registers; programmed by kernel driver.

RAW-domain ISP (Bayer)

Black-level corrector - Performs Black Level Correction the programmed sensor pedestal from RAW pixel.

3A statistics engine - 16x16 zone accumulator grid plus histogram, memory-mapped in the register family.

AWB Block - per channel digital gain multiplier in the RAW domain to perform WB correction.

This is where AWB corrections are physically applied, before demosaic.

Demosaic - the in-house Bayer-to-RGB interpolator.

Turns the single-channel CFA stream into full 3-channel RGB; its line buffers set the pipeline latency.

RGB/YUV-domain ISP

Colour-correction matrix (CCM) - 3x3 matrix with offsets, loaded per sensor from the manifest tuning. Corrects sensor spectral crosstalk into colorimetric RGB; part of 3A chain.

Gamma LUT - programmable per-channel gamma table (the custom core from stage 13). Applies the encoding curve so 8-bit and YUV/HDMI outputs aren't linear-dark.

RGB-to-YUV converter (CSC) - custom RGB to YUV 4:2:2 converter with chroma filtering. Produces the stream used by YUV and Mono output formats and the HDMI preview.

USB output leg (FX3 GPIF)

USB elastic FIFO - buffering between the packer and the GPIF clock domain / FX3 backpressure.

GPIF width funnel (down to 32-bit) - narrows the packed stream to the GPIF bus width. Drives the top-level GPIF data/clock/LSYNC/FSYNC pins into the FX3.

GigE output leg (GVSP via DDR)

GigE frame DMA - lands packed frames into DDR ring buffers. The gvsp kernel driver harvests them and streams GVSP packets out of the GEM.

HDMI preview leg

Stream-to-video bridge (Xilinx v_axi4s_vid_out) - turns the AXI-Stream preview into parallel video with syncs, locked to the timing generator. Also handles the crossing into the 148.5 MHz pixel-clock domain.

Video timing generator (Xilinx VTC) - generates the fixed HDMI sync/blanking timing the bridge locks to.

HDMI/DVI encoder - serialises parallel RGB plus syncs into TMDS for the HDMI connector.

Trigger and auxiliary I/O

Camera I/O and sync block - aux-I/O core: opto in/out, xtrig1/2, xmaster, XHS/XVS and strobe pins at the top level.

Infrastructure

Zynq processing system - the ARM cores running Linux, the DDR controller, GEM Ethernet, and the GP/HP AXI ports everything hangs off.

Source of the 100 MHz fabric reference and the HP slave ports both DMAs write through.

ISP Specification

Full fledged ISP All Standard and Enhance Features Dedicated handling of Color and Mono Sensors.

ISP Specifications

Camera ISP on FPGA Logic
Black Level Correction
Demosaic
3A Engine
Auto White Balance
Auto Exposure
Auto Focus
Auto Gain
Color Space Conversion
Gamma Correction
Video Processing for HDMI
Dedicated USB , Ethernet and HDMI Pipeline
Simultaneous USB , Ethernet and HDMI operation
Dedicated GigE Vision, USB3 Vision, UVC and HDMI Pipeline
Frame Rate Conversion Specifically for HDMI
Supports 1 to 4 Pixel Per Clock
150Mhz Video Pipeline Clock
Virtually no frame rate limit
600 Mpixel/second ISP processing rate at 4PPC and 1200Mpixel/second at 8PPC
ISP max 4PPC:

640×480 ~2000 FPS
1080p ~170 FPS
4K ~40 FPS

ISP max 8PPC:

640×480 ~4000 FPS
1080p ~340 FPS
4K ~80 FPS

Supported Sensor Specs

Sensors : Supports all Sensor that meets Sensor Specs
Interface : All MIPI D-PHY/LVDS/Sub LVDS/Low Voltage LVDS/SLVS Sensors
Resolution : ~128Mpixel Max, No Min limit
Shutter : Global or Rolling Shutter
Number of Data Lanes : upto 8 Lanes, 4 Lanes x1ch or 4Lane x2ch
Number of Sensors: 2 (4 Lanes), 3 (2 Lanes)
Max Data rate : 1.25Gbps/Lane, max 10Gbps with 8Lanes
Pixel format: RAW8, RAW12, RAW14 , PWL HDR
Freely user configurable Frame rate
Frame rate is sensor and Streaming Interface Dependent
Frame rate Details provided in individual Sensor specs

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

CHC5 Open Camera Software Architecture Part 4

2026-08-29T19:51:45.731+02:00

This post this Part 4 in the Multi part Series of the , Part1 we Compared sensor, Part2 was Hardware and Mechanical Design, Part3 about Sensor Solution. This part 4 going in details about SW Design. FPGA/PL Pipeline will be discussed in Part 5. This Part primarily focus how software is implemented where boundary between Software are defined. Why we decide to make make whole system around Linux.

CHC5 X-Ray Soldering Test Verification

Software Architecture

System is Running around Linux on Zynq 7000 SoC PS, We Linux make life easier, because it already bring standard frame work for system design, Specifically Driver and Media Pipelines. If any other mythology over Linux , They would have to resort to either RTOS or Absolute bare metal. These Absolute custom solution bright lot of flexibility and performance over Linux. Specially in boot time. But this Flexibility is available in tradeoff he Reliability and time spent in development especially defining driver framework, application management, Memory Management and Network Stack. in sort Linux already have most the work already laid out we just need to program our custom drivers application and optimization to it.

There are few Major Components of the Software that is running on the ARM CPU

1. platformd, a daemon that manages whole system platform. It Manages Sensor Driver loading, Network configuration, Loading of Bitstream onto PL, Firmware Programming to FX3 EEPROM, System Upload. Board hardware Config, XML Provisioning for both GigE vision and U3V System. LED Status and Error Logging and reporting. Sensor, USB, Bitstream Archive Management, Validation of Manifest and other house keeping stuff with help of System Config Script. even thoug platformd knows which sensor is active what system config is but still platformd is fully sensor agnostic. any change of sensor does not change anything in platformd code and at run time platformd can adapt to different sensors. platformd take care of the firmware stores for all 3 type of binary/Firmwares for USB, Bitstream and Sensor archives are managed by platformd, when new components need be added or deleted activated for individual user request its managed by platformd.

2. camcgfd, a daemon that manages Camera configuration, It monitors camera sensor directly with camera sensor standard V4L2 Driver. camcfgd directly handles Image specific request form gvcp server, with gvcp server communication is IPC and camcgfd also talked to USB FX3 Device over I2C communication. I2C driver provide framed config messages to camcfgd. camcfgd configures camera sensor as per request/limits and bound of platform and camcgfd. watching sensor limits and Interface speed limits. camcfgd also have complete understanding of media pipeline, all PL ISP blocks are standard V4l2 Components, camcgfd configures V4L2 pipeline as per requests. Camcgfd also take care of standardized exposure and gain control making this camera universal and sensor agnostic. camcfgd is fully sensor agnostic. any change of sensor does not change anything in camcfgd code and at run time camcfgd can adapt to different sensors. camcgfd is running primary Auto exposure look it received image statistics from FPGA and Calculates estimated Image Brightness and color balance. And needed change apply to Camera and AWB PL blocks.

3. gvcp, a daemon that runs to service as gvcp server and manages all GigE Vision requirements. gvcp hosts a standard gvcp server make camera available to standard GigE Vision standard. gvcp also manages ethernet data and Zynq ETH GEM DMA directly. There was lot of challenge work to get full Gigabit of Data bandwidth out of Zynq7000 DMA. gvcp talkes to camcgfd for camera sensor configuration and streaming control. gvcp is fully sensor agnostic. any change of sensor does not change anything in gvcp code and at run time gvcp can adapt to different sensors.

4.webd, its a webserver deamon, it serves a full-fledged web user interface, webd serves first level of hmi, All controls that camera has to offer can be programmed over GigE vision and USB 3 Vision Interface as well but web offer great view of system state and control for human users. It offers dashboard to view all system software components , Direct ISP component control. Direct HDMI Control, Control of AUX IO pins. Firmware Library Management , Reprogramming of USB firmware, Swapping camera sensor driver and Bitstream selection for Custom and standard pipeline. System Update interface for Complete System firmware including kernel and other Linux system Library and components. Device Control to backup user data , factory restore setting and reboot setting. Ethernet Config and Device time setting for Verification of System date and time.

CHC5 System Arch Design

Webd UI

webd make dashboard showing camera individual camera versions and absolute version control with sha. dashboard shows flash wear level and also camera identification control just incase you need to identify specific in environment where multiple camera are available and you need to point to specifc camera. Flipping this will blink/strobe led on camera and show you which exact camera it webd is being offered from.

Dashboard Showing a Development Device dashboard

ISP Control page

ISP even though directly controlled by GigE Vision and USB3 Vision Interface There a manual Control and Status Display is exposed to help user developed there applications , You can Control Auto exposure and Auto Gain and There Parameter such as Auto Exposure Target, Speed Auto Exposure Metering mode , For example Center-Weighted. and Priority for the AE Algo to use gain or exposure (like slow down camera to get better light or let image noisy be to get faster frame rate ), There are different methods to perform highlight protection, Also option to Run AE once. Web UI also allow control override for force AWB enable and AWB Specifc Lighting target such as daylight, Tungsten, Live AWB gain are displayed to monitor what AWB algo is calculating the background and what results are.

ISP Control Showing AE and AWB Control

HDMI Control Page allow setting of HDMI Enable Disable . Or Allow HDMI to Run in Standalone mode. Camera has feature will allow it to run as standard Camera in this mode it automatically starts streaming from sensor and output to HDMI without need of USB or ethernet host. HDMI is not a primary interface so USB and Ethernet Always over ride Stream control even in standalone mode. HDMI Frame rate control that only apply to HDMI Image frame rate not HDMI Interface frame rate. HDMI Interface Frame rate/Wire clock/Blanking is absolute standard. While To save bandwidth on DDR UI allows setting of image frame rate for HDMI. So if user selects 30FPS . Regardless of sensor read FPS only 30FPS worth of image data gets written to HDMI Frame buffers and Transmitted over HDMI output at fix Standard rate if Camera/User Config Slow FPS , HDMI still standard FPS repeating same frame multiple time. HDMI is Fix max resolution to 1080p so crop and crop positioning is available.

HDMI Control window Showing HDMI Off

Camera Features Two AUX I/O pins which allows Camera to Camera sync. Flash and Strobe and Sync Input and output these all can be configured over web interface will full flexibility. Both Signal are Optically isolated. Status display is available to show state of actual HW pins.

Aux I/O control Page

Sensor Library page is really Special, Even though is embedded camera system it sill allow Sensor Interchanablity. This worlds first camera that allow Interchangeable sensor. System is linux based user can upload sensor archive package with sensor driver alog with some settings in manifest file alog with ccm tuning file and sensor specific gamma correction table. Seprate blog post provide detailed description about how to make these driver /sensor archive. User with just click of button activate/iinstall sensor. Install/activation process is shown on progress bar and restart is required to get the new sensor working.

Bitstream library is similar to senor library page. it allow user to store multiple bitstream on the camera itself and activate and use bitstream what is needed. Archive/package contains standard bitstream bin along with manifest file info about bitstream. to be displayed on web these manifest info is compared against sensor driver during activation basic validation such max resolution of sensor is compared if bitstream can achieve this resolution or not. few validation are performed and user is served with warning or error depending on error type.

USB Firmware library is similar to other library, store of multiple USB firmware. similar to bitstream standard FX3 firmware packed along with manifest. USB firmware comes in two flavors U3V and UVC. U3V for Standard USB 3 vision application and as WebCam UVC standard on Windows, Linux, Mac and even On Android. Camera with work as is in USB UVC mode. USB firmware is little more special than bitstream and sensor drive. because this firmware need to be programmed onto FX3's EEPROM. Because FX3 configured to load firmware from EEPROM directly. FX3 works pretty much independently only interface is GPIF for image data and I2C for Sensor/U3V/UVC stream/config request.

System update page allow User to Flash new firmware to system. this primarily update system base like Linux , rootfs and core library. Sensor driver, PL Bitstream and FX3 Firmware is have dedicated path of update and upgrade while Linux kernel/Driver are part of base system so can be upgraded using this System firmware update. System is well designed wit Dual Dedicated kernel Rootfs and stuff so issues during and after update are secure and any issue during upgrade will auto roll back to the old previous version so that user still have option to flash new firmware.

Device Setting has interface to change network config and Backup user data along with Factory reset and Factory Restore will full erase.

Logs is window where user can view all the systemd log of all individual components including individual daemons what make our camera run. this help in debugging without looking at termial.

User can change admin password that i used for web UI login. If password is forgotten user can reset password from Physical button the camera itself

System Storage Map

System for reliability , System update, Guaranteed graceful degradation and fallback we have Dual Boot Config, Dual Kernel, dual rootfs so that camera is Guaranteed be in working order even if bad firmware is flashed or storage is broken, system is always in a working order so that user can fix by just always flashing a nice firmware over the web.

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

Launching September 1st Week

CHC5 FPGA Architecture Part 5

CHC5 Open Camera Lens Mount and Sensors Part 3

2026-08-25T21:51:21.202+02:00

This is Part 3 the CHC5 Camera System Posts, in Last post I showed how CHC5 Camera architecture is designed and everything is put together at system design and ISP level. I also showed Comparison of sensor in Part 1 . Now in this Third part i will Show you all the Sensor and lens Mount Hardware that is currently available with CHC5 Platform.

There are quite a Few Sensor and Sensor Mount available

Currently available lens mounts:

C-Mount
CS-Mount
Canon RF-Mount (Manual Controls)
Sony E-Mount (Manual Controls)
M42 Mount with Multiple Flange Distance
S Mount
M43 or Custom Lens Mount

Currently Available Sensors

Available Sensor list will add more sensors over time. If user is looking for Specific sensor then he can contact us for new sensor addition.

Rolling Shutter

IMX477 : 12.3M Generic High quality
IMX485: 8.4M Low Light, High Sensitivity Large Pixel/Senor
IMX678 : 8.4M Low Light, Very High Sensitivity
IMX585 : 8.4M Color Low Light, Even Higher Sensitivity Larger Pixel/Sensor
IMX585: 8.4M Mono Even Higher Sensitivity then IMX585 Color
IMX283 : 20.3M Large 1inch Sensor size
IMX294 : 10.7M Massive 4/3 Format, Low Light, High Sensitivity
OX08B40 : 8.3M 140 dB Extreme Dynamic Range PWL HDR Automotive Sensor

Global Shutter

IMX568 : 5.1M Global Shutter Sensor
IMX565 : 12.3M Global Shutter Large Sensor Size

Comparison of sensor in Part 1

IMX283

IMX283 is the highest resolution sensor currently available on CHC5, 20.3MP on a large 1 inch optical format with 2.4um pixels. The pixel count and sensor area make it the one to pick when detail matters more then speed, aerial imaging, solar photography, cinema and high detail industrial inspection. It is a 4 lane MIPI only part with no native HDR mode, and full resolution readout tops out at 25fps.

Resolution : 5496x3672 ~20.3MP
Optical Format : 1" , 15.86mm diagonal
Pixel Size : 2.4um
Pixel Formats : RAW9 RAW10 RAW12
Interface : MIPI CSI-2 , 4 Lane only , up to 1.728Gbps per lane
Max Frame Rate Full Res : 25 fps @ 20.3MP (20 fps @ 4K)
Max Frame Rate 1080P : 60 fps
HDR Frame Rate : No native HDR mode
Sensor Technology : BSI Rolling Shutter , ~74dB Dynamic Range

IMX294

IMX294 has the largest optical format in the whole lineup, a 4/3 inch sensor with massive 4.6um pixels and a Quad Bayer colour filter. Big pixels plus STARVIS BSI means a lot of light gathering per pixel, and it still does 4K at 120fps, or 60fps with Quad Bayer HDR enabled for around 100dB WDR. Astronomy, EAA, broadcast, ITS and high speed low light security are the typical applications. The sensor supports both MIPI CSI-2 and SLVS-EC, on CHC5 it is used in 4 lane MIPI mode.

Resolution :3792x2824 ~10.7MP
Optical Format : 4/3" , 21.63mm diagonal
Pixel Size : 4.64um
Pixel Formats : RAW10 RAW12 RAW14
Interface : MIPI / SLVS-EC , MIPI 4 Lane only
Max Frame Rate Full Res : 120 fps @ 4K (10-bit)
Max Frame Rate 1080P : ~120 fps (cropped ROI)
HDR Frame Rate : 60 fps Quad Bayer HDR , ~100dB WDR
Sensor Technology : BSI STARVIS (Gen 1) , Quad Bayer , ~73dB Dynamic Range

IMX585

IMX585 is the STARVIS 2 flagship of the lineup and is available on CHC5 in both colour and mono. 2.9um pixels on a 1/1.2 inch format give roughly 88dB of dynamic range in a single exposure, so it reaches around 120dB WDR without any multi frame combine and therefore without motion artefacts. NIR response is about 1.7x a Gen 1 STARVIS part, which makes it the pick for outdoor surveillance at night, medical, scientific and astronomy work. Trade off is the large image circle, it needs a proper 1/1.2 inch or larger lens.

Resolution : 3840x2160 ~8.3MP , Colour and Mono variants
Optical Format : 1/1.2" , 12.85mm diagonal
Pixel Size : 2.9um
Pixel Formats : RAW10 RAW12
Interface : MIPI CSI-2 , 2 or 4 Lane , up to 1.5Gbps per lane
Max Frame Rate Full Res : 90 fps @ 4K (10-bit) , 60 fps @ 4K (12-bit)
Max Frame Rate 1080P : ~120+ fps
HDR Frame Rate : ~30 fps , Single Exposure HDR up to ~120dB WDR
Sensor Technology : BSI STARVIS 2 , ~88dB Dynamic Range , Very High NIR

IMX678

IMX678 is the compact STARVIS 2 part, same 4K 8.3MP output as IMX585 but with 2.0um pixels on a 1/1.8 inch format. It gives dual exposure Clear HDR with no ghosting, around 80dB single exposure and 100+dB in HDR mode, and around 0.01 lux colour sensitivity. Smaller image circle means a much cheaper and smaller lens then IMX585, so this is the sensible choice for security, AI edge, robotics and general embedded vision where the camera has to stay small.

Resolution : 3840x2160 ~8.3MP
Optical Format : 1/1.8" , 8.86mm diagonal
Pixel Size : 2.0um
Pixel Formats : RAW10 RAW12
Interface : MIPI CSI-2 , 2 or 4 Lane , up to 1.5Gbps per lane
Max Frame Rate Full Res : 72 fps @ 4K (10-bit) , 60 fps @ 4K (12-bit)
Max Frame Rate 1080P : ~120+ fps
HDR Frame Rate : ~30 fps Dual Exposure Clear HDR , ~100+dB WDR
Sensor Technology : BSI STARVIS 2 , ~80dB Dynamic Range , ~0.01 lux , Very High NIR

IMX477

IMX477 is the general purpose high quality sensor of the lineup, the same 12.3MP part used on the Raspberry Pi HQ camera. 1.55um pixels on a 1/2.3 inch format, 60fps at full resolution and 240fps at 1080p, and it is the only sensor here with on chip PDAF for phase detect auto focus. Smallest optical format in the lineup which keeps lens cost and camera size down, so it is the default choice for photography, drone and robotics builds.

Resolution : 4056x3040 ~12.3MP
Optical Format : 1/2.3" , 7.857mm diagonal
Pixel Size : 1.55um
Pixel Formats : RAW8 RAW10 RAW12
Interface : MIPI CSI-2 , 2 or 4 Lane , up to 1Gbps per lane
Max Frame Rate Full Res : 60 fps @ 12.3MP (60 fps @ 4K)
Max Frame Rate 1080P : 240 fps
HDR Frame Rate : 30 fps DOL-HDR / SME-HDR , ~100dB WDR
Sensor Technology : BSI Stacked Exmor RS , ~74dB Dynamic Range , PDAF support

Global Shutter

IMX565

IMX565 is the high resolution global shutter part, 12.3MP Pregius S Gen 4 with 2.74um pixels on a large ~1/1.1 inch format. Global shutter means the whole frame is exposed at once, so there is no rolling distortion or skew on fast moving parts, spinning objects or strobe lit scenes, and the geometry stays correct for measurement. In pixel dual ADC gives around 80dB HDR and the sensor takes a precision external trigger for multi camera sync. Frame rate is lower then IMX568 simply because there are more pixels to read out.

Resolution : 4096x3000 ~12.3MP
Optical Format : ~1/1.1" , 14.0mm diagonal
Pixel Size : 2.74um
Pixel Formats : RAW8 RAW10 RAW12
Interface : MIPI CSI-2 2 or 4 Lane / SLVS-EC , up to 2.1Gbps per lane
Max Frame Rate Full Res : 42 fps @ 12.3MP
Max Frame Rate 1080P : ~90+ fps (ROI)
HDR Frame Rate : Dual ADC in pixel HDR , ~80dB WDR
Sensor Technology : BSI Stacked Global Shutter , Pregius S Gen 4 , precision trigger sync

IMX568

IMX568 is the fast global shutter option, 5.1MP with the same 2.74um Pregius S Gen 4 pixel as IMX565 but on a smaller 1/1.8 inch format. Lower pixel count buys frame rate, 79fps at full resolution and 142fps at 1080p, still with zero motion blur or skew and precision trigger sync. This is the machine vision workhorse, industrial inspection, IVD, robotics pick and place and ANPR / traffic where trigger accuracy and geometry matter more then pixel count.

Resolution : 2448x2048 ~5.1MP
Optical Format : ~1/1.8" , 8.8mm diagonal
Pixel Size : 2.74um
Pixel Formats : RAW8 RAW10 RAW12
Interface : MIPI CSI-2 2 or 4 Lane / SLVS-EC , up to 2.1Gbps per lane
Max Frame Rate Full Res : 79 fps @ 5.1MP
Max Frame Rate 1080P : 142 fps
HDR Frame Rate : Dual ADC in pixel HDR , ~80dB WDR
Sensor Technology : BSI Stacked Global Shutter , Pregius S Gen 4 , ~0.14 lux SNR1s , precision trigger sync

OX08B40

OX08B40 is the automotive HDR sensor of the lineup and the only non Sony part on CHC5. 8.3MP 4K with 2.1um dual conversion gain pixels, and the OmniVision HALE engine combines four captures into up to 140dB of dynamic range, or 82dB in single exposure DCG mode. It also does LED flicker mitigation, so LED traffic signs, tail lights and indicators do not strobe or drop out in the image. Output is piece wise linear compressed HDR up to 24-bit. Built to automotive ASIL C hardware metrics for ADAS and autonomous driving, but equally useful anywhere the scene has extreme contrast, tunnel entries, welding, furnace and headlight glare.

Resolution : 3840x2160 ~8.3MP
Optical Format : 1/1.73" , 9.30mm diagonal
Pixel Size : 2.1um
Pixel Formats : Up to 24-bit HDR , 20 / 16 / 14 / 12-bit PWL
Interface : MIPI CSI-2 , up to 4 Lane
Max Frame Rate Full Res : 36 fps @ 4K (24-bit HDR)
Max Frame Rate 1080P : 60 fps
HDR Frame Rate : 36 fps , 4 capture HDR combine , 140dB WDR
Sensor Technology : Stacked BSI PureCel Plus-S with DCG , LED Flicker Mitigation , ASIL C

Camera Adapter and Cable

As the name suggests, this whole camera system is actually a complete system where I deliver a wide range of components you can use to debug, deploy, and test your camera setups and applications.

There is a special cable (or you could call it a PCB with a cable) that lets you connect any of our cameras to a standard Raspberry Pi, a standard Jetson, or any other SBC or FPGA system. You take this adapter board and fit it onto the back of the camera. All of our cameras match this exact pinout and pin function, so you can take any of our cameras, attach the adapter to the back, and then use that camera on whichever platform you prefer.

This adapter gives you exactly the same pinout as standard Raspberry Pi cameras: either the classic Raspberry Pi style, or the newer Raspberry Pi 5-style 22-pin FPC connector, which also accepts the standard 4-lane-to-2-lane cables for connecting to older Raspberry Pi boards if needed. Alternatively, you can use the standard four-lane, 22-pin cable to connect to any of your favorite systems. We also already have FPGA solutions in the form of FPGA FMC boards for high-end FPGAs, so you can use the camera on the system of your choice.

There is also a separate adapter that plugs into the camera and lets you connect any sensor of your choice to our CHC5 camera.

Flange Distance

CHC5 Has Flange Distance as low as 8.75mm Allow connection to almost any Lens, No camera system in this class does not allow flange distance lower than this.

Flange Distance 8.75mm

Lens Mounts

RF Mount

Canon RF Mount

M42 Standard, C , CS, Sony E Mount

Sony E Mount , M42 Mount , C Mount, CS Mount

M42 Mount , Non Standard

M42 Mount With Low non Standard Flange Distance

RF Mount

Canon RF Mount

RF Mount Lens

C Mount

C Mount Standard Raspberry PI Lens

CS Mount

Fish Eye Lens On CS Mount With Ring

M42 Standard Flange

M42 Mount with Standard Flange Distance

M42 Lens Mounted On standard M42 Mount

Filter Mount

There are Two filter Available there is one internal UV IR Filter and External 43mm Thread Standard Filter. Both filter are user replaceable to fit Custom scientific needs

External 43mm Standard Filter

Internal Filter Glass

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

Software and Architecture_Part 4

CHC5 Open Camera System, For Hardware Accelerated Advance Machine Vision , Part 2

2026-08-23T19:03:00.000+02:00

This project is the next project in the series of camera projects that have been published on CircuitValley. I started with the first-ever open-source USB UVC stack, making the first-ever PIC32 USB camera. Then I moved to a camera based on the CYUSB USB 3.0 controller. Then came the Lattice MachXO3-based high-speed camera. After that I made the Lattice CrossLink-NX cameras. This is going to be the 5th generation of the CircuitValley open camera system that you can actually buy and use in your application, customize, or get adapted to your application.

CHC5 is the world's first commercially available modular camera system that can be customized and adapted to different applications with not just a different lens objective, but also a different sensor, at the click of a button. This is the world's first camera that allows interchangeable sensors.

The CHC5 camera platform is based on the Zynq-7000 FPGA SoC. It contains a decent-size FPGA integrated with a dual-core Arm Cortex-A9 CPU. This creates a really high-speed integrated system that contains a really high-performance CPU for really complex tasks, while the FPGA part takes care of high-speed calculation and correction on the image itself. With this large FPGA available at the disposal of the CPU, AI/machine-vision-specific algorithms and complex low-latency hardware acceleration can be put onto the PL, in part or in full.

Camera Platform Specification

Interchangeable Lens Mount

Minimum flange distance of 8.75mm makes it possible to connect almost any lens
Currently available lens mounts:

C-Mount
CS-Mount
Canon RF-Mount (Manual Controls)
Sony E-Mount (Manual Controls)
M42 Mount with Multiple Flange Distance
S Mount
MFT M4/3 Micro Third Mount
M43 Thread or Custom Lens Mount

Frame Rate

Virtually no frame rate limit
600 Mpixel/second ISP processing rate
ISP max:

640×480 ~2000 FPS
1080p ~170 FPS
4K ~40 FPS

Supported Sensor Specs

Sensors : Supports all Sensor that meets Sensor Specs
Interface : All MIPI D-PHY/LVDS/Sub LVDS/Low Voltage LVDS/SLVS Sensors
Resolution : ~128Mpixel Max, No Min limit
Shutter : Global or Rolling Shutter
Number of Data Lanes : upto 8 Lanes, 4 Lanes x1ch or 4Lane x2ch
Number of Sensors: 2 (4 Lanes), 3 (2 Lanes)
Max Data rate : 1.25Gbps/Lane, max 10Gbps with 8Lanes
Pixel format: RAW8, RAW12, RAW14 , PWL HDR
Freely user configurable Frame rate
Frame rate is sensor and Streaming Interface Dependent
Frame rate Details provided in individual Sensor specs

CHC5 Enclosure and Mounting System

Camera Enclosure Designed to Accommodate Any Sensor mount or no sensor mount at all. There is Internal Filter and M43 Thread for Standard External Filter

Sensor PCB mount Supports Internal Filter and Internal Reflection Mitigation Device

Lens Mount Can be exchanged Externally , 6x M3 Counter Sunk Screws are used to Secure These Mount

Canon RF Mount

CHC5 Enclosure Core

CHC5 Enclosure Back

CHC5 Back Thermal Contact

Currently Available Sensors

Available Sensor list will add more sensors over time. If user is looking for Specific sensor then he can contact us for new sensor addition.

Rolling Shutter

IMX477 : 12.3M Generic High quality
IMX485: 8.4M Low Light, High Sensitivity Large Pixel/Senor
IMX678 : 8.4M Low Light, Very High Sensitivity
IMX585 : 8.4M Color Low Light, Even Higher Sensitivity Larger Pixel/Sensor
IMX585: 8.4M Mono Even Higher Sensitivity then IMX585 Color
IMX283 : 20.3M Large 1inch Sensor size
IMX294 : 10.7M Massive 4/3 Format, Low Light, High Sensitivity
OX08B40 : 8.3M 140 dB Extreme Dynamic Range PWL HDR Automotive Sensor

Global Shutter

IMX568 : 5.1M Global Shutter Sensor
IMX565 : 12.3M Global Shutter Large Sensor Size

Here is Full Post About What Individual Camera Sensor Specification

Filter

Internal, user-changeable IR cut filter
External, user-changeable standard 43mm filter mount

Camera Interface

USB3 5 Gbps - USB UVC, USB3 Vision
Ethernet 1 Gbps - GigE Vision, Optional PoE
HDMI 1080p
Simultaneous streaming over all 3 interfaces

Streaming Protocols

USB3 : UVC (Standard Web Cam), USB3 Vision
Ethernet: GigE Vision , Optional PoE
HDMI: Standard

Aux I/O

1× Isolated input, user-configurable
1× Isolated output, user-configurable
Multiple Camera Sync of Aux Lines
Flash, Strobe Control with user defined timing
Exposure time monitoring

ISP Specification

Full fledged ISP All Standard and Enhance Features Dedicated handling of Color and Mono Sensors.

ISP Specifications

Camera ISP on FPGA Logic
Black Level Correction
Demosaic
3A Engine
Auto White Balance
Auto Exposure
Auto Focus
Auto Gain
Color Space Conversion
Gamma Correction
Video Processing for HDMI
Dedicated USB , Ethernet and HDMI Pipeline
Simultaneous USB , Ethernet and HDMI operation
Dedicated GigE Vision, USB3 Vision, UVC and HDMI Pipeline
Frame Rate Conversion Specifically for HDMI
Supports 1 to 4 Pixel Per Clock
150Mhz Video Pipeline Clock
~600Mpixel/Second Peak Processing Rate

CHC5 ISP

Hardware Platform

So I picked the SoC to use for CHC5 because the There is lot going on it being a Camera Platform Rather than Just a embedded fix function camera with Zynq has the FPGA part and also the ARM Cortex-A9 thingy that does it all inside one single chip. All FPGA solution would either need a Soft Core CPU or lot of Fabric will be wasted on Web and Stuff.

I Picked Zynq 7000 because its well respected SoC Well Supported. I chose to have linux as platform rather than Embedded due the number of components involved. Linux V4L2 Proved a standard Path and Template for Component and Driver Development and worked Real Well. Ethernet Stack along With DDR3 Control with Multiple DMAs and VDMA and Web Software having everything in Bare metal would have need lot of low level tweaks and Attention to work So Linux was obvious and This made a SoC Rather than just Bare FPGA an obvious thing to chose.

Core Board is 14 Layer, Really High Density board This is words Smallest publicly known Fully featured Zynq7000 board. Populated Primarily with Zynq7000 SoC and Most Expensive part of the System DDR3 1GByte Memory with 32Bit interface 1066 , Total Bandwidth around 34Gbps. There is Ethernet PHY , USB 2.0 OTG of Zynq 7000 For USB Peripheral Expansion, Can be used to Connect Maybe additional Low Speed Network or Debugging Connection.

There are 3 High Density High Speed connector . These Connectors

MIPI Connector 100pin Carries I2C + Some Single Ended Controls, 8 Data + 2 Clock MIPI Lanes , Total 14 Differential Pairs Routed , Supports 8 Lanes MIPI, LVDS , Sub LVDS/Low Voltage LVDS, SLVS And other Interfaces , Supports 1 to 4 Sensors , May be even Many More 1 Lane Sensors
PL Connector 29 Pairs Differential Routed ,for 32GPIF along with Many Control Lines HDMI Pairs
PS Connector Carry Ethernet/USB OTG and Other PS Specific Connections

Board has 1Gbit Flash memory along with uSD connector . Both available at same time as Shipped Firmware will be loaded to Flash. Both Can be used for Boot, I will ship Firmware on Flash and uSD card Can be used for Recovery just in case something totally made device not to boot.

CHC5 Core Board Schematic

Schematic of the board Available on Github

Interface Board

As whole point of this camera is adaptability and molecularity, There are multiple Interface Boards available fitting to Various needs. Board are available with 10Gbps USB 3.0 5Gbps USB 3.0 , With or Without PoE. Down blow is Arch of CHC5IO5G Board with 5Gbps Interface with Infineon CYUSB FX3 5Gbps This Chip is Core at 5G board. While PL Connector Connects to 100MHz 32bit GPIF This is the Primary Interface over Which FPGA Streams into FX3. On Other Side there HDMI Connector from FPGA and USB C 2.0 OTG

CH5IO5G PoE board Does not have HDMI and Also no USB2.0 OTG, Uses PCB room to Implement PoE Power Supply.

CH5IO5G Board Specially Prepared for High Speed Streaming and Debugging with Full Size JTAG and Both Zynq and FX3 Interface Available. There a solderable jumper to Select Boot media either Flash or uSD , There is Factory Restore Button to Reset Camera config Along with Status LED for USB and Core System.

CH5IO5G Board Schematic

Board Schematics are available on Github

PCB Internal Layer Inspection

I have Regress quality control over everything that is manufactured by external suppliers. PCB is one of them i am coming from aerospace background PCB are filed and internal layer verified to inspect with PCB Visa are correctly formed and PCB Copper layer thickness is appropriate and copper expension around visa is also correct

PCB Solder Masked Filed Away

Internal Layer Become Visible after lot of filing

Two Filed PCB showing Internal copper Layers

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

Sensor and Lens Mount Part 3

CHC5 open Camera System Image Sensor Specification Comparison , CHC5 Part 1

2026-08-23T18:03:02.549+02:00

There many Sensors Available on this Whole CHC5 Camera Platform These Sensor PCB are Part of this Modularity Them so these Sensor PCB can be used with CHC5 and also Other System CircuitValley Make Specially MIPI FMC Board. These Sensors Can also be used with Raspberry Pi , Jetson and Other Single Board Computer.

CircuitValley CHC5 System Provided Adapter/Cables to Connect any CHC5 sensors as Standard Raspberry pi 2 - 4 Lane Camera . Down in The table show Which Sensor has what interface and What specs, Some sensor such as IMX294 and IMX283 Only work with 4 Lanes MIPI Rather than more flexible 2 Lane Systems

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

Image Sensor Comparison

Best-in-class / Global Shutter

Notable / Above average

Rolling shutter / No feature

Feature label

Feature / Spec	IMX477	IMX678	IMX485	IMX585	IMX283	IMX294	IMX568	IMX565	OX08B40
📷 SENSOR FUNDAMENTALS
Sensor Size (Optical Format)
Resolution	4056×3040 12.3 MP	3840×2160 8.3 MP	3840×2160 8.29 MP	3840×2160 8.3 MP	5496×3672 20.3 MP	3792×2824 10.7 MP	2448×2048 5.1 MP	4096×3000 12.3 MP	3840×2160 8.3 MP
Pixel Size	1.55 µm	2.0 µm	2.9 µm	2.9 µm	2.4 µm	4.63 µm	2.74 µm	2.74 µm	2.1 µm
Output Format (Bit Depth)	RAW8/10/12	RAW10/12	RAW10/12	RAW10/12	RAW9/10/12	RAW10/12/14	RAW8/10/12	RAW8/10/12	Up to 24-bit HDR (20/16/14/12-bit PWL)
MIPI Interface	CSI-2 2 or 4 Lanes	CSI-2 2 or 4 Lanes	CSI-2 2/4/8 Lanes	CSI-2 2 or 4 Lanes	CSI-2 4 Lanes only	CSI-2 / SLVS-EC 4 Lanes	CSI-2 2 or 4 Lanes	CSI-2 2 or 4 Lanes	CSI-2 Up to 4 Lanes
⚡ SPEED & FRAME RATES
Max Frame Rate (Full Resolution)	60 fps @ 12.3MP	72 fps @ 4K (10-bit)	90 fps @ 4K (10-bit)	90 fps @ 4K (10-bit)	25 fps @ 20.3MP	120 fps @ 4K (10-bit)	79 fps @ 5.1MP	42 fps @ 12.3MP	36 fps @ 4K (24-bit HDR)
Max Frame Rate (1080p / Sub-Res)	240 fps @ 1080p	~120+ fps	90 fps @ 1080p (binned)	~120+ fps	60 fps @ 1080p	~120 fps (cropped ROI)	142 fps @ 1080p	~90+ fps (ROI)	60 fps @ 1080p
Max Frame Rate (4K / High-Res)	60 fps @ 4K	60 fps @ 4K (12-bit)	90 fps @ 4K (10-bit)	60 fps @ 4K (12-bit)	20 fps @ 4K (via 4L MIPI)	120 fps @ 4K (10-bit)	N/A (< 4K sensor)	N/A (< 4K sensor)	36 fps @ 4K (24-bit HDR)
HDR Frame Rate	30 fps (DOL-HDR mode)	~30 fps (dual-exposure)	N/A in datasheet (DOL/SME-HDR modes)	~30 fps (STARVIS2 HDR)	N/A (no native HDR)	60 fps (Quad Bayer HDR)	N/A (Global Shutter)	N/A (Global Shutter)	36 fps (4-capture HDR combine)
🌟 SENSITIVITY & LOW-LIGHT
Sensor Technology	BSI Stacked Exmor RS	BSI STARVIS 2	BSI STARVIS (Gen 1)	BSI STARVIS 2	BSI Rolling Shutter	BSI STARVIS (Gen 1)	BSI Stacked Pregius S (Gen 4)	BSI Stacked Pregius S (Gen 4)	Stacked BSI PureCel Plus-S, DCG
Min. Illumination (Typical)	~0.1 lux (F1.0, 1/30s)	~0.01 lux (F1.0 color)	Not published as lux Sensitivity: 9530 digit (F5.6, 1/30s)	~0.01 lux (F1.0 color)	~0.1 lux (general)	~0.14 lux (SNR1s)	~0.5 lux (industrial)	~0.5 lux (industrial)	Not officially disclosed
NIR Sensitivity	Good (BSI Stacked)	Very High (STARVIS 2)	High (STARVIS Gen1 BSI)	Very High (+1.7× vs STARVIS)	Moderate (standard BSI)	High (STARVIS BSI)	Good (BSI Stacked)	Good (BSI Stacked)	Not emphasized (automotive/visible focus)
📊 DYNAMIC RANGE & HDR
Dynamic Range (Single Exposure)	~74 dB (typical)	~80 dB (+8 dB vs STARVIS)	Not officially disclosed	~88 dB (STARVIS 2 flagship)	~74 dB (standard)	~73 dB (10-bit)	~73 dB (Pregius S)	~73 dB (Pregius S)	Not specified separately (see HDR combined)
HDR Mode / HDR Type	SME-HDR (single-frame) DOL-HDR (dual-frame)	Dual-Exposure HDR (no ghosting) Clear HDR	SME-HDR (single-frame) DOL-HDR (dual-frame)	Single-Exposure HDR (STARVIS 2) ~88 dB WDR	No native HDR mode	Quad Bayer HDR (60fps in HDR) Artifact-free	Dual ADC HDR (in-pixel)	Dual ADC HDR (in-pixel)	4-Capture HDR (OmniVision HALE engine) + LED Flicker Mitigation
Effective WDR (HDR mode)	~100 dB (DOL-HDR)	~100+ dB (dual exposure)	~88 dB (DOL/SME-HDR, 3rd-party reported)	~120 dB (single exposure)	N/A	~100 dB (Quad Bayer)	~80 dB (Dual ADC)	~80 dB (Dual ADC)	140 dB (4-capture combined); 82 dB single-exposure (DCG)
🔬 IMAGING FEATURES
Shutter Type	Rolling Shutter	Rolling Shutter	Rolling Shutter	Rolling Shutter	Rolling Shutter	Rolling Shutter	Global Shutter ✅ No motion blur	Global Shutter ✅ No motion blur	Rolling Shutter (ERS)
Pixel Binning	2×2 binning	2×2 binning	2×2 binning	2×2 binning	2×2 binning	Quad Bayer 2×2 binning	No binning (GS readout)	No binning (GS readout)	2×2 digital binning
Multi-ROI Support	Limited	Yes	Yes (window cropping)	Yes	Limited	Yes	Yes (Tracking ROI)	Yes (Tracking ROI)	Yes (ROI support)
External Trigger / Sync	Supported	Supported	Supported (sensor sync fn.)	Supported	Supported	Supported	✅ Precision sync	✅ Precision sync	Supported (frame sync input)
PDAF / Autofocus Support	✅ PDAF (phase-detect AF)	No native PDAF	No native PDAF	No native PDAF	No native PDAF	No native PDAF	No (GS sensor)	No (GS sensor)	No native PDAF
⚙️ TECHNICAL & INTERFACE
ADC Resolution	10 / 12-bit	10 / 12-bit	10 / 12-bit	10 / 12-bit	9 / 10 / 12-bit	10 / 12 / 14-bit	8 / 10 / 12-bit	8 / 10 / 12-bit	Up to 24-bit (HDR combined)
Max MIPI Speed (Per Lane)	Up to 1 Gbps	Up to 1.5 Gbps	Not specified (4-lane, 90fps @4K)	Up to 1.5 Gbps	Up to 1.728 Gbps	CSI: 1.728 Gbps SLVS-EC: 2.304 G	Up to 2.1 Gbps (SLVS-EC)	Up to 2.1 Gbps (SLVS-EC)	Not officially disclosed
🏭 USE CASES & POSITIONING
Sensor Class / Generation	BSI Stacked Consumer/Pro	STARVIS 2 Security/Embedded	STARVIS (Gen 1) Security/Industrial	STARVIS 2 Security/Pro	1-inch BSI Pro/Scientific	STARVIS (Gen 1) 4/3″ Security	Pregius S (Gen 4) Industrial GS	Pregius S (Gen 4) Industrial GS	PureCel Plus-S Automotive HDR (ASIL C hardware metrics)
Primary Applications	Photography, Drones, Robotics, Rasp. Pi HQ Cam	Security, AI Edge, Robotics, ADAS, Embedded Vision	Surveillance, FA, Industrial Cameras, 4K Security	Outdoor Surveillance, Medical, Scientific, Astronomy, 4K Video	Aerial Imaging, Solar Photography, Cinema, Industrial	Astronomy, EAA, Broadcast, ITS, High-Speed Security	Machine Vision, Industrial Inspection, IVD, Traffic (ANPR)	Factory Automation, ITS, High-Res Inspection, Robotics	Automotive ADAS, Autonomous Driving, DVR, Machine Vision
Key Strength	PDAF + 60fps + compact size	Dual-exposure HDR + STARVIS 2 NIR	90fps 4K, same die footprint as IMX585	88 dB single-shot WDR + large pixel	20.3 MP highest res in lineup	4K@120fps + large 4.63 µm pixels	Global Shutter: no rolling distortion	12 MP Global Shutter: hi-res no-blur imaging	140 dB HDR + LFM + ASIL C safety architecture
Key Limitation	Smallest sensor in lineup (1/2.3″)	Smaller pixel vs IMX585 (2.0 µm)	STARVIS Gen1 (no dual-gain HCG readout)	Large sensor needs bigger lens format	4-lane only; 25fps full-res	STARVIS Gen 1 (older technology)	Lower sensitivity than STARVIS	Lower frame-rate vs IMX568 (42fps)	Automotive-grade pricing & availability
Price Tier (Relative)	★★☆ Mid-Range	★★☆ Mid-Range	★★☆ Mid-Range	★★★ Premium	★★★ Premium	★★★ Premium	★★★ Premium	★★★ Premium	★★★ Automotive Premium

Notes: Sensor size diagrams are drawn to scale relative to each other — the IMX294 (4/3″, 21.63 mm diagonal) sets the reference scale. Frame rates are maximum sensor-level values; actual rates may vary by platform, interface speed, and bit depth. Min. illumination values at F1.0 (50% sensitivity). WDR/HDR values represent typical achievable range with HDR modes enabled. STARVIS & Pregius S are Sony registered trademarks. Global Shutter & best-in-class cells highlighted in green.

CHC5 Camera System Part 2

FMC Card For MIPI TX/RX Camera CSI and Display DSI Emulation

2026-02-14T05:14:00.031+01:00

This post is going to about a really special FMC LPC board for Xilinx FPGA boards. This board allow you to Test MIPI Systems, Specially by not only Providing a Port for doing Normal MIPI RX from Camera or TX to display but also Emulating MIPI Camera by doing MIPI TX Camera Emulation and also emulating a Display by doing MIPI RX. This board is specially Designed for Testing MIPI Systems on FPGA and Specially FPGA SoC Running Linux.

Specification

This breakout Give you 3x MIPI Connections using just HMC LPC Pins.
Board Specifically Designed for MIPI Emulation. Has Very special Powered and 2x Passive connector.
Board is specifically for MIPI TX/RX for DSI Display and Camera, While Also has Dedicated Emulation Connector to Emulate Camera RX and Display Emulation.
Current limited Active Powered MIPI Connector.
Passive MIPI Connector for emulation with Powered Detect LED Indication.
This Board Has 3x 22Pin 0.5mm Pitch 4Lane MIPI Connector, Same As Raspberry Pi 5 onwards.
Compatible to all Raspberry Style Cameras, 2 Lane and 4Lane cameras and displays for Both TX and RX.
Compatible Standard 2Lane Rapsberry Pi 15Pins 1mm Pitch Cameras using RPI to Mini FPC Cable.
Compatible to Digilent PCam cameras.
Example Video ISP pipeline working under Linux as V4L2 medica driver on ZCU102 Provided as Reference example.
Normal FPGA FMC Board comes from big manufacturer, Availability of such board is very very rare.
Board is VITA57.1 Compliant Has EEPROM to Configure voltages.
This is Rev D of Board, Works with ZCU106 and ZCU104, ZCU102
Both ZCU106 and ZCU104 are supported by Free Xilinx Vivado

Schematic

High Resolution Schematic is available on Project Github Repo

Hardware Revisions

RevA to Rev C -- Not Publicly known

RevD, Primary Production Unit. No know issue

Pin Assignment

MIPI Signal	FMC Connector Pin	ZCU102 HPC0	ZCU102 HPC1	ZCU106 HPC0	ZCU106 HPC1	ZCU104 HPC0
CAM1_MIPI_CLK_P	G6	Y4	G6	F17	B18	F17
CAM1_MIPI_D0_P	D14	W2	AE2	H16	G20	H16
CAM1_MIPI_D1_P	H7	V2	AD2	L20	K22	L20
CAM1_MIPI_D2_P	C10	AC2	AH2	H19	H21	H19
CAM1_MIPI_D3_P	G9	Y2	AH1	K19	J21	K19
CAM1_I2C_SCL	D11	AB3	AG3	K17	G25	K17
CAM1_I2C_SDA	D12	AC3	AH3	J17	G26	J17
CAM1_ENABLE	G2	T8	P10	G10	x	G10
CAM1_REF_CLK	G3	R8	P9	F10	x	F10
PWR_OUT_ENABLE	G12	V4	AE3	E18	J25	E18
TX_EN_DIR	G13	V3	AF3	E17	H26	E17
CAM1_REF_CLK_DIR	H4	AA7	AE7	E15	F23	E15
	FMC	ZCU102 HPC0	ZCU102 HPC1	ZCU106 HPC0	ZCU106 HPC1	ZCU104 HPC0
PORT 3
CAM3_MIPI_CLK_P	C22	N9	x	D11	x	D11
CAM3_MIPI_D0_P	G27	M11		C7		C7
CAM3_MIPI_D1_P	H28	L12		B6		B6
CAM3_MIPI_D2_P	D26	L15		B9		B9
CAM3_MIPI_D3_P	H25	P12		B10		B10
CAM3_I2C_SCL	H34	V6		E9		E9
CAM3_I2C_SDA	H35	U6		D9		D9
CAM3_ENABLE	H38	T11		E8		E8
CAM3_REF_CLK	H37	U11		F8		F8
PORT3_RX_EN_DIR	D18	AC8		F15		F15
CAM3_REF_CLK_DIR	C26	M10		A8		A8
PWRT3_IN_DETECT	C27	L10		A7		A7
	FMC	ZCU102 HPC0 (Bank 66)	ZCU102 HPC1 (Bank 65)	ZCU106 HPC0	ZCU106 HPC1	ZCU104 HPC0
PORT 4
CAM4_MIPI_CLK_P	D20	P11	x	x	x	x
CAM4_MIPI_D0_P	D23	L16
CAM4_MIPI_D1_P	G24	M15
CAM4_MIPI_D2_P	H22	L13
CAM4_MIPI_D3_P	G21	N13
CAM4_I2C_SCL	G34	V7
CAM4_I2C_SDA	G33	V8
CAM4_ENABLE	G36	V12
CAM4_REF_CLK	G37	V11
PWR_IN_DETECT	H20	Y9
RX_EN_DIR	H19	Y10
CAM4_REF_CLK_DIR	H16	AB6

Hardware

PCB

Top of the board Showing all 3 Ports and Indication LEDs

Back of the FMC Card Showing Power protection and Control Level translators

Project Github

https://github.com/circuitvalley/DEVEMU_FMC_MIPI_Emulator_card

FPGA FMC NVMe Drive SSD, NVMe SSD Drive on PCIe M.2 Adapter FMC HPC FPGA

2026-01-08T18:46:00.046+01:00

As I am working with more High end FPGA boards. I need more different type of peripheral pugged into my FPGA board with FMC connector. This board is going to about Why and how i designed FMC HPC PCIe M.2 carrier adapter card so that You can Plug NVMe SSD Drive or any other PCIe Peripheral in M.2 Form factor.

As case with most modern FPGA board. They come with High density high speed expansion connector. Out of which FMC connectors are most common. FMC Connectors also have few types, There FMC HPC connector which has all the pins of HPC connector , While there is a FMC LPC connector which has only a subset of HPC connector. Both FMC HPC and LPC connectors are basically same in terms of mechanical dimensions, They both fit into one another. Its just LPC has few electrical pins. The there is also a even bigger connector even with more pins called Vita 57.4 FMC+ , it is mostly Common with very expensive high end boards.

As I was working on my camera project i needed very fast storage for my FPGA, Where I could store RAW or even Compressed Video from Camera. This Little Board that I designed will allow you Connect very Fast NVMe SSD storage to your FPGA board. This board can Carry Two NVMe SSD Connected to FPGA. Both devices can be operated parallelly on full x4 PCIe link . This FPGADrive solution give you Multigigabyte per second performance. Allowing to work for any application.

Features

FPGA FMC HPC M.2 Carrier board for NVMe SSD M.2 M Key and Other M.2 m-key card, such as WiFi for AI Accelerator
PCIe Gen4 X4 on both of the slots
High Quality 8 Layer Board with Controlled Stripline routing.
Independently Power both both Slots Allow Full potential.
Two M Key slots with 4 Different Sizes.
Supports 2280, 2260, 2242, 2230 M.2 Sizes.
Power and Activity LED indication
Supported by All Xilinx boards with Fully HPC connectors.
FMC HPC ANSI/VITA 57.1 compliant.
Board is VITA57.1 Compliant Has EEPROM to Configure voltages to support High end FPGA VADJ

YouTube Video

PCB

Vivado Design For PCIe Bridge IP

Project source and example design available on Github

xdma and very important Reset Signal

Configuring XDMA

Linux Operation

Linux NVMe Driver Config

You need to enable few drivers in linux configuration of ultrascale+ FPGA

PCIe Express Port Bus Support

NVMe Express Block Device Support

Xilinx DMA PL PCIe Host Bridge Support

Device tree

lspci Ouptut showing Both SSD

Gen 4 link speed with SN770M

Benchmark

Write Benchmark Showing Speed of 1.4 GByte/Second

Read Bench Mark Showing Speed of 2.5GByte/Second

Hardware Revisions

Rev A Not Publicly Know

Rev B , First Public Version only few made. have

Rev C, Not Publicly Know

Rev D , Primary Production Version PERST and few other control pins change to Increase Compatibility

Rev E, Exactly Same as Rev D Some Production optimization no Functional or connection change

Board Support

Zynq ultrascle+ ZCU104, ZCU106, ZCU111, ZCU208

Versal VCK190, VCK280, VHK158, VMK180, VPK180

Pin Assignment

NVMe1 Interface

Board is supported by Almost all xilinx board that have PCIe FMC or even FMC+ connector

FMC Pin	FMC Pin Name	NVMe Net Name	Description	ZCU106 HPC0	ZCU106 HPC1
C2	FMC_HPC0_DP0_C2M_P	NVMe1_PER0_P	PCIe Lane 0 (SSD to FPGA) Positive	R6	AJ6
C3	FMC_HPC0_DP0_C2M_N	NVMe1_PER0_N	PCIe Lane 0 (SSD to FPGA) Negative	R5	AJ5
C6	FMC_HPC0_DP0_M2C_P	NVMe1_PET0_P	PCIe Lane 0 (FPGA to SSD) Positive	R2	AK4
C7	FMC_HPC0_DP0_M2C_N	NVMe1_PET0_N	PCIe Lane 0 (FPGA to SSD) Negative	R1	AK3
A22	FMC_HPC0_DP1_C2M_P	NVMe1_PER1_P	PCIe Lane 1 (SSD to FPGA) Positive	T4
A23	FMC_HPC0_DP1_C2M_N	NVMe1_PER1_N	PCIe Lane 1 (SSD to FPGA) Negative	T3
A2	FMC_HPC0_DP1_M2C_P	NVMe1_PET1_P	PCIe Lane 1 (FPGA to SSD) Positive	U2
A3	FMC_HPC0_DP1_M2C_N	NVMe1_PET1_N	PCIe Lane 1 (FPGA to SSD) Negative	U1
A26	FMC_HPC0_DP2_C2M_P	NVMe1_PER2_P	PCIe Lane 2 (SSD to FPGA) Positive	N6
A27	FMC_HPC0_DP2_C2M_N	NVMe1_PER2_N	PCIe Lane 2 (SSD to FPGA) Negative	N5
A6	FMC_HPC0_DP2_M2C_P	NVMe1_PET2_P	PCIe Lane 2 (FPGA to SSD) Positive	P4
A7	FMC_HPC0_DP2_M2C_N	NVMe1_PET2_N	PCIe Lane 2 (FPGA to SSD) Negative	P3
A30	FMC_HPC0_DP3_C2M_P	NVMe1_PER3_P	PCIe Lane 3 (SSD to FPGA) Positive	U6
A31	FMC_HPC0_DP3_C2M_N	NVMe1_PER3_N	PCIe Lane 3 (SSD to FPGA) Negative	U5
A10	FMC_HPC0_DP3_M2C_P	NVMe1_PET3_P	PCIe Lane 3 (FPGA to SSD) Positive	V4
A11	FMC_HPC0_DP3_M2C_N	NVMe1_PET3_N	PCIe Lane 3 (FPGA to SSD) Negative	V3
D4	FMC_HPC0_GBTCLK0_M2C_P	FMC_NVMe1_REFCLK_P	100MHz Reference Clock Positive	V8	Y8
D5	FMC_HPC0_GBTCLK0_M2C_N	FMC_NVMe1_REFCLK_N	100MHz Reference Clock Negative	V7	Y7
H19 ( Old Rev B H22)	FMC_HPC0_LA15_P	NVMe1_PERST	PCIe Fundamental Reset	D16	A18
H20	FMC_HPC0_LA15_N	NVMe1_PEDET	Presence Detect / Interface ID	C16	A19
H17 ( Old Rev B H23)	FMC_HPC0_LA11_N	NVMe1_DEVSLP	Device Sleep / Power Management	C11	A21

NVMe2 Interface

FMC Pin	FMC Pin Name	NVMe Net Name	Description	ZCU106 HPC0	ZCU106 HPC1
A34	FMC_HPC0_DP4_C2M_P	NVMe2_PER0_P	PCIe Lane 0 (SSD to FPGA) Positive	H4	X
A35	FMC_HPC0_DP4_C2M_N	NVMe2_PER0_N	PCIe Lane 0 (SSD to FPGA) Negative	H3
A14	FMC_HPC0_DP4_M2C_P	NVMe2_PET0_P	PCIe Lane 0 (FPGA to SSD) Positive	G2
A15	FMC_HPC0_DP4_M2C_N	NVMe2_PET0_N	PCIe Lane 0 (FPGA to SSD) Negative	G1
A38	FMC_HPC0_DP5_C2M_P	NVMe2_PER1_P	PCIe Lane 1 (SSD to FPGA) Positive	L6
A39	FMC_HPC0_DP5_C2M_N	NVMe2_PER1_N	PCIe Lane 1 (SSD to FPGA) Negative	L5
A18	FMC_HPC0_DP5_M2C_P	NVMe2_PET1_P	PCIe Lane 1 (FPGA to SSD) Positive	L2
A19	FMC_HPC0_DP5_M2C_N	NVMe2_PET1_N	PCIe Lane 1 (FPGA to SSD) Negative	L1
B16	FMC_HPC0_DP6_M2C_P	NVMe2_PET2_P	PCIe Lane 2 (SSD to FPGA) Positive	N2
B17	FMC_HPC0_DP6_M2C_N	NVMe2_PET2_N	PCIe Lane 2 (SSD to FPGA) Negative	N1
B36	FMC_HPC0_DP6_C2M_P	NVMe2_PER2_P	PCIe Lane 2 (FPGA to SSD) Positive	M4
B37	FMC_HPC0_DP6_C2M_N	NVMe2_PER2_N	PCIe Lane 2 (FPGA to SSD) Negative	M3
B12	FMC_HPC0_DP7_M2C_P	NVMe2_PET3_P	PCIe Lane 3 (SSD to FPGA) Positive	J2
B13	FMC_HPC0_DP7_M2C_N	NVMe2_PET3_N	PCIe Lane 3 (SSD to FPGA) Negative	J1
B32	FMC_HPC0_DP7_C2M_P	NVMe2_PER3_P	PCIe Lane 3 (FPGA to SSD) Positive	K4
B33	FMC_HPC0_DP7_C2M_N	NVMe2_PER3_N	PCIe Lane 3 (FPGA to SSD) Negative	K3
B20	FMC_HPC0_GBTCLK1_M2C_P	FMC_NVMe2_REFCLK_P	100MHz Reference Clock Positive	T8
B21	FMC_HPC0_GBTCLK1_M2C_N	FMC_NVMe2_REFCLK_N	100MHz Reference Clock Negative	T7
G19 (Old Rev B G9)	FMC_HPC0_LA03_P	NVMe2_PERST	PCIe Fundamental Reset	C17
G18 (Old Rev B H7)	FMC_HPC0_LA02_P	NVMe2_PEDET	Presence Detect Signal	D17
H16 (Old Rev B G10)	FMC_HPC0_LA03_N	NVMe2_DEVSLP	Device Sleep / Power Management	A13

PCB Image

High Quality 8 Layer PCB with Stripline, Impedance Controlled Routing

Board Image

Board Fits All different Type of M.2 form factors

Threaded Mounting Studs for SSD, Can be Moved Between Positions.

Supported on Wide Varity of FPGA Boards

Supports Stacking of FMC LPC or even HPC Connector who don't Share pins

Standard from factor Allow side by Side Fitting With Other FMC

Top Quality M.2 Connector From TE

Project source and example design available on Github

FPGA FMC 4x MIPI CSI Camera, MIPI DSI Display Breakout Adapter , V4L2 Linux Media Pipeline Ultrascale+

2025-12-03T23:46:00.041+01:00

Prototyping with advanced FPGA boards is quite challenging, As they often have very high density connectors for expansions and peripherals. As with case with most Modern Systems Xilinx and many other vendors also have very High density very high speed connectors. On Xilinx FPGA have High speed connectors called FMC Connectors. These connectors allow users to attach high speed peripherals to FPGA board.

FMC Connectors also have few types, There FMC HPC connector which has all the pins of HPC connector , While there is a FMC LPC connector which has only a subset of HPC connector. Both FMC HPC and LPC connectors are basically same in terms of mechanical dimensions, They both fit into one another. Its just LPC has few electrical pins. The there is also a even bigger connector even with more pins called Vita 57.4 FMC+ , it is mostly Common with very expensive high end boards

One of the most common peripheral that you can connect to these board is MIPI CSI-2 Camera or MIPI Display. So i decide to make a breakout board for MIPI CSI, There are 4x Powered , 4 Lane MIPI Connectors that support both camera and display.

Rev D of Bord with Multiple Carrier Support, ZCU106, ZCU104, ZCU102

This Board Has 4x 22Pin 0.5mm Pitch 4Lane MIPI Camera Connector, Same As Raspberry Pi 5 onwards,

Compatible to all Raspberry Style Cameras, 2 Lane and 4Lane cameras both

Compatible Standard 2Lane Rapsberry Pi 15Pins 1mm Pitch Cameras using RPI to Mini FPC Cable

Compatible to Digilent PCam cameras

PCB

Schematic

To make board compatible to ZCU102 and ZCU106 Schematic has been changed quite a bit So Latest Schematic Can be found github

Hardware Revisions

RevA to Rev B -- Not Publicly known

RevC , Only Few units , Only Works with ZCU102 but all ports have 4 Lane support

RevD, Primary Production Unit, Works with ZCU102 and ZCU106, ZCU104 but not all ports support 4 Lanes.

Pin Assignment

Pin assignment is very critical with every FPGA board it's also similarly critical with the on both ZCU102 and ZCU106. It Comes down to that ZCU106 only supports MIPI RX on very limited number of Pins even though MIPI TX is supported on quite a few pins. But input pins are very few and very limited number of banks as well so only the bank number 28 64 65 66 67 and 68 are available directly on the ZCU106 HPC connectors which can be used for MIPI input and even on those banks bank you get very limited pins which can be used as a clock Lane and again they are specific Pins which can be used as a data aim when you are using specific clock pins

Rev C Boards are only compatible to ZCU102

Red D onwards work with ZCU102 and ZCU106 Both

Rev D pin ist listed blow ,For Rev C Pin Assignment for Please Refer to Github

MIPI Signal	FMC Connector Pin	ZCU102		ZCU106		ZCU104 HPC0
MIPI Signal	FMC Connector Pin	HPC0	HPC1	HPC0	HPC1	ZCU104 HPC0
CAM1 PCB Rev D
CAM1_MIPI_CLK_P	G6	Y4	G6	F17	B18	F17
CAM1_MIPI_D0_P	D14	W2	AE2	H16	G20	H16
CAM1_MIPI_D1_P	H7	V2	AD2	L20	K22	L20
CAM1_MIPI_D2_P	C10	AC2	AH2	H19	H21	H19
CAM1_MIPI_D3_P	G9	Y2	AH1	K19	J21	K19
CAM1_I2C_SCL	D11	AB3	AG3	K17	G25	K17
CAM1_I2C_SDA	D12	AC3	AH3	J17	G26	J17
CAM1_ENABLE	G2	T8	P10	G10	x	G10
CAM1_REF_CLK	G3	R8	P9	F10	x	F10
CAM2 PCB Rev D
CAM2_MIPI_CLK_P	H19	x	x	D16	A18	D16
CAM2_MIPI_D0_P	G18			D17	C18	G18
CAM2_MIPI_D1_P	G12			E18	J25	E18
CAM2_I2C_SCL	D18			F15	C22	F15
CAM2_I2C_SDA	D17			G15	C21	G15
CAM2_ENABLE	C27			A7	x	A7
CAM2_REF_CLK	C26			A8	x	A8
CAM3 PCB Rev D
CAM3_MIPI_CLK_P	C22	N9	x	D11	x	D11
CAM3_MIPI_D0_P	G27	M11		C7		C7
CAM3_MIPI_D1_P	H28	L12		B6		B6
CAM3_MIPI_D2_P	D26	L15		B9		B9
CAM3_MIPI_D3_P	H25	P12		B10		B10
CAM3_I2C_SCL	H34	V6		E9		E9
CAM3_I2C_SDA	H35	U6		D9		D9
CAM3_ENABLE	H38	T11		E8		E8
CAM3_REF_CLK	H37	U11		F8		F8
CAM4 PCB Rev D
CAM4_MIPI_CLK_P	D20	P11	x	x	x	x
CAM4_MIPI_D0_P	D23	L16
CAM4_MIPI_D1_P	G24	M15
CAM4_MIPI_D2_P	H22	L13
CAM4_MIPI_D3_P	G21	N13
CAM4_I2C_SCL	G34	V7
CAM4_I2C_SDA	G33	V8
CAM4_ENABLE	G36	V12
CAM4_REF_CLK	G37	V11

Youtube Video

Linux V4L2 Pipeline

Device Tree

Loading Device Tree

Media Pipeline

V4L2 Pipeline Configuration

yavta Capture 3 RGB Frames

Setup Image

Project Github

RFSTAMP44 RF Signal Generator ADF4351 35M to 4.4Ghz Stamp size castellated

2025-09-15T23:08:00.045+02:00

This project is going to show you a very very small RF Signal Generator 35Mhz to 4.4Ghz on a Tiny PCB that can be easily integrated into project. this Project is complement to USB RF signal generator which I published few weeks ago. Project is based on Analog device ADF4351

Device Pinout

Device Control Modes

Schematic

High Resolution Schematic PDF is available Project github

PCB

Firmware

Firmware Running on PIC USB MCU running USB Stack bridges USB and UART to SPI to control ADF4351 PLL IC . PIC MCU has EEPROM to handle standalone operation. FW also manages AUX pin function. AUX pin Support Sync Out to sync device sweep with sync external devices such as Oscilloscope or spectrum analyzer. AUX pin supports Sync In for similar reason. Dedicated pin for Support External Reference clock for PLL alternative to on Board 25Mhz oscillator

Cross Platform PC Software

Open Source QT Application

Qt Application Allow programming frequency in 10 Khz step, Allow Sweep and hop between frequency with programmable time and programmable step. AUX pin function can also be selected. And PC Free Standalone can also be programmed.

Python Application

All features that can be programmed over QT application can also be programmed using Python script

UART Intarface

UART Commands/Protocol

UART Command Manual — RFSTAMP44

All commands start with $, followed by a letter (or ?) and optional parameters. End commands with CR/LF.

Command	Usage	Description
$F	$F <frequency_MHz> e.g. `$F 433.12`	Set output frequency. Accepts float MHz values with 10 kHz resolution. Range: 35.00 MHz – 4400.00 MHz.
$A	$A <mode> e.g. `$A 2`	Select AUX I/O function: `0` = AUX_SYNC_OUT `1` = AUX_SYNC_IN `2` = AUX_EXT_REF_IN `3` = AUX_EXT_REF_IN_SYNC_OUT `4` = AUX_EXT_REF_IN_SYNC_IN
$B	$B <frequency_MHz>	Set sweep START frequency (MHz Float, min10Khz resolution).
$C	$C <frequency_MHz>	Set sweep STOP frequency (MHz Float, min 10Khz resolution).
$E	$E	Erase stored settings (EEPROM).
$G	$G <frequency_MHz>	Set sweep step frequency (MHz Float, min 10Khz resolution).
$J	$J <time_ms>	Set dwell time in ms.
$R	$R <frequency_MHz>	Set reference frequency (10–250 MHz).
$O	$O <0\|1>	Enable/disable RF output.
$P	$P	Write configuration to PLL.
$T	$T	Save parameters to EEPROM.
$S	$S <0\|1>	Enable/disable sweep mode. Updates “Start on Boot”.
$H	$H <0\|1>	Enable/disable auto-start sweep on boot.
$I	$I	Identify device / FW version notification.
$M	$M<n> <hex_value>	Write hex value to register Rn (0–5).
$?	$?	Print current settings + registers.

Notes

UART Baud Rate 115200
Frequencies given in MHz (e.g. 433.12), store with 10 kHz resolution.
Reference frequency clamped 10–250 MHz.
$M expects hexadecimal values (e.g. 0x12345678).
Commands must end with \r or \n.
No echo for commands.

HIDRAW Device access under Linux

hidraw device may need privilized use permission to access usb device with sudo

Accessing USB hidraw device under linux without sudo

Accessing USB HID device under linux

What’s a “USB HID raw device”?

HID = Human Interface Device (like keyboards, mice, game controllers, barcode scanners).
hidraw devices expose raw HID reports directly to user space.
Path looks like:
```
/dev/hidraw0
/dev/hidraw1
```

Why you can’t just open them

On most distros, these devices are owned by root and a system group like plugdev or input.
Permissions are typically:

crw-rw---- 1 root plugdev 243, 0 Aug 14 12:34 /dev/hidraw0

Why udev rules help

udev manages device nodes dynamically when hardware is connected.
By adding a udev rule, you can:

Change file permissions (e.g., MODE="0666" for read/write by everyone).
Change ownership (e.g., GROUP="plugdev").
Apply these settings automatically whenever the device is plugged in.

Example rule:


SUBSYSTEM=="hidraw", ATTRS{idVendor}=="abcd", ATTRS{idProduct}=="1234", MODE="0666"

udev file from github repo

# Put this file into /etc/udev/rules.d and unplug and re-plug your device.

# You don't need to restart Udev, new permissions will be picked up automatically.

ATTRS{idVendor}=="1209", ATTRS{idProduct}=="7877", MODE="0666"

RF output

40Mhz Output @ -1.04dBm

100Mhz Output @ -0.97dBm

300Mhz Output @ -1.04 dBm

400Mhz Output @ -1.00 dBm

800Mhz Output @ -1.3 dBm

1Ghz Output @ -0.61 dBm

1.5Ghz Output @ 0.01 dBm

2Ghz Output @ -0.87 dBm

2.4Ghz Output @ -0.94 dBm

3Ghz Output @ -3.2 dBm

Project Source

Github Project

How to build Custom FSBL for Zynq Ultrascale+ FPGA on new Vitis 2024.2

2025-09-14T21:21:00.010+02:00

This post is going to be about how to Create FSBL for Zynq SOC, Using newer version of Vitis 2024.2 . Since Vitis Received update there are changes to well established process of creating FSBL previously with the old version of Wheatus it was very very easy to create FSBL but with the update 2024.2 there are some quite tricks which you need to do to be able to successfully create at FSBL. FSBL is the primary first stage Bootloader which is needed to be able to boot into secondary Bootloader and later on to the target operating system I will be using Xilinx zcu102 as an example board to show you how you can generate custom fsdl for any Xilinx Zynq SoC platform device. you can of course create FSBL for your custom platform.

To create FSBL for a custom platform first of all you need to get started with vivado in vivado you need to create a hardware platform .xsa file and this file is used to create fsp if you are having any standard xilinx Sport for example ZCU102 or ZCU106 then of course you don't need to create a hardware platform file.

Example blow shows you that the part of project has been set up and this is how to export .xsa file

we got our design ready and of course bit stream is also generated you do not necessarily need to generate stream you can export the pre synthesized design as well now we export

you can choose on this step whether you want a presynthesized design or include bit strain in the exported hardware if you include the stream then this stream can be used to configure the fpga part in the boot first stage itself

by following these steps you must have your .xsa file ready and this file can be used in Vitis to generate a hardware platform which can be used to generate FSBL for that particular hardware platform

we got our .xsa ready we can move to vitis and generate hardware platform and then FSBL with it

On this step you can choose to create the platform on the basis of custom hardware file you created with vivado or you can of course choose default silence development both this step is important on this step you provide necessary input for the FSBL creation and its necessary to pay attention that you choose the correct file and choose the correct platform.

You must uncheck create boot artifacts because we are not looking to "create Boot Artifacts" in this platform

Now our platform have been created FSBL has not yet been created only the platform have been created you must understand there are multiple domains in which code runs so the code which platform which we created does not run in the FSBL domain so we need to create separate at SPL and we will use Xilinx examples FSBL for it you don't necessarily need to write anything .

Now we have fsbl elf file so we can now create a boot.bin file with this creating boot.bin file requires quite a few of Step you not only need the FSBL you would also need pmu firmware , bl31 File, U boot and also device tree binary aswell . They need be this exact order

as you can see we have successfully created our fsbl and now ZCU102 boots

DISTISO6 Isolated Distribution Amplifier for GPSDO

2025-09-08T20:05:00.017+02:00

This project is in continuation of the project that I have previously published making Sin Wave Galvanically Isolated Distribution Amplifier for GPSDO and Lab Reference.

This Device is capable for producing very high voltage range ~14dBm Output on 10 Mhz . This device can be used for any frequency from 100Khz to 190Mhz

This project is based on the previous GPDO Distribution board that I designed few years ago.

Specifications

Signal Distribution Amplifier, With Galvanically Isolated Output Using Signal Transformers For Clock and Signal Distribution, With Bandwidth 100Khz to 190Mhz with Gain of +4dBm

Input

50 Ohm Input impedance ,

AC coupled to Primary Stage, Max 2V DC Offset

Max +10dBm for 100Khz to 100Mhz, 2Vpp + 2V DC Offset

Max +17 dBm Max 101 to 190Mhz

A standard 3.3 CMOS or TTL when driving into 50R will fall into compatible range.

If you have requirement of even Higher input voltage then external BNC attenuator can be used

Output

50 Ohm Galvanically Isolated

+13dBm 100Khz to 50Mhz into 50Ohm , ~6Vpp into 1Mohm

+12 dBm 50 to 100 Mhz into 50Ohm

+7 dBm 101 to 190Mhz into 50Ohm

Frequency Deviation between Channels

Base line Measured Ratio difference on same Channel max 7.956p

Channels Between same driver (e.g CH1 vs CH2) max Ratio difference of around 8.16p

Channels Between different driver (e.g CH1 vs CH3) max Ratio difference of around 10.2p , Max ~ 10 PPT

Phase Noise

Measured only with Spectrum analyzer, Device should perform same or better. Measurement are limited by noise floor of Generic SSA

-70dBc/Hz@1Hz

-90dBc/Hz@10Hz

-114dBc/Hz@100Hz

-125dBc/Hz@1Khz

Phase Deviation between Channels

TDS8000 70Ghz Bandwidth scope Was used with 50Ghz and 20Ghz sampling head, even on 1fs resolution no measurable phase difference

Power

Dual Power input

USB C PD 15 V or 12V

DC Banana Jack 6.5mm 2mm Pin Center Positive

PCB Design

Output Level

Specs & Docs

KLIP30 Fast Pulse Generator for TDR, Impedance and Bandwidth Measurement

2025-08-12T10:06:00.020+02:00

KLIP30 USB Programmable 30ps Fast Pulse Generator

Programmable DC Coupled Output with 50mV to 1300mV Signal Amplitude with 50Ω Output
Very Fast ~20ps Falling Time and 30ps Rise time with Uncertainties + 1.6ps to – 1.8ps
Programmable output frequency PLL Supports 30Khz to 300Mhz
Top Quality 27Ghz SMA Output Connector
Aux In/Out Supports output AC Coupled 1.8Vpp output and input
Support External Reference Input and Output For trigger and Sync between Multiple devices/ GPSDO
Internal Oscillator 25ppm Initial accuracy and 2.5ppm/year ageing Stability, External Reference Input Supported 10Mhz to 25Mhz.
USB C Power/ Configuration Communication , consumes ~250mA on 5V USB
Extruded Aluminium Enclosure. Device fully user serviceable with support.
Crossplatform Configuration GUI Application , Supports Windows, Linux, MacOS
Deliverables, Pulse Generator Device, SMA Male to SMA Male Adapter, SMA Male to BNC Male Adapter, Individually measurement report

Accessing Device From Windows

Device under Linux

hidraw device may need privilized use permission to access usb device with sudo

Accessing USB hidraw device under linux without sudo

What’s a “USB HID raw device”?

HID = Human Interface Device (like keyboards, mice, game controllers, barcode scanners).
hidraw devices expose raw HID reports directly to user space.
Path looks like:
```
/dev/hidraw0
/dev/hidraw1
```

Why you can’t just open them

On most distros, these devices are owned by root and a system group like plugdev or input.
Permissions are typically:

crw-rw---- 1 root plugdev 243, 0 Aug 14 12:34 /dev/hidraw0

Why udev rules help

udev manages device nodes dynamically when hardware is connected.
By adding a udev rule, you can:

Change file permissions (e.g., MODE="0666" for read/write by everyone).
Change ownership (e.g., GROUP="plugdev").
Apply these settings automatically whenever the device is plugged in.

Example rule:


SUBSYSTEM=="hidraw", ATTRS{idVendor}=="abcd", ATTRS{idProduct}=="1234", MODE="0666"

udev file from github repo

# Put this file into /etc/udev/rules.d and unplug and re-plug your device.

# You don't need to restart Udev, new permissions will be picked up automatically.

ATTRS{idVendor}=="1209", ATTRS{idProduct}=="8777", MODE="0666"

RFGEN44 Open Source 4.4Ghz USB RF Signal Generator

2025-08-08T18:02:00.041+02:00

This Project is going to be about making a fully open source USB Programmable RF signal Generator. Device cable of Generating Frequency upto 4.4Ghz Fully Programmable using USB. Device Support Driver free operation using USB HID . Fully programmable under Window, Linux or macOS using Provided Python or QT5 GUI Application using libHID. Cross platform Support and Raw HID support allow Programming using any scientific platform such as MATLAB.

HW is based on ADF4351 from analog devices. supported by USB Microcontroller from Microchip.

Device Ports

PCB

PCB Design made up of 6 Layer PCB Fully Controlled Stack up

Firmware

Firmware Running on PIC USB MCU running USB Stack bridges USB to SPI to control ADF4351 PLL IC . PIC MCU has High endurance Flash memory to handle standalone operation. FW also manages AUX pin function. AUX pin Support Sync Out to sync device sweep with sync external devices such as Oscilloscope or spectrum analyzer. AUX pin supports Sync In for similar reason. AUX pins also Support External Reference clock for PLL alternative to on Board 25Mhz oscillator

Cross Platform PC Software

Open Source QT Application

Python Application

All features that can be programmed over QT application can also be programmed using Python script

HIDRAW Device access under Linux

hidraw device may need privilized use permission to access usb device with sudo

Accessing USB hidraw device under linux without sudo

Accessing USB HID device under linux

What’s a “USB HID raw device”?

HID = Human Interface Device (like keyboards, mice, game controllers, barcode scanners).
hidraw devices expose raw HID reports directly to user space.
Path looks like:
```
/dev/hidraw0
/dev/hidraw1
```

Why you can’t just open them

On most distros, these devices are owned by root and a system group like plugdev or input.
Permissions are typically:

crw-rw---- 1 root plugdev 243, 0 Aug 14 12:34 /dev/hidraw0

Why udev rules help

udev manages device nodes dynamically when hardware is connected.
By adding a udev rule, you can:

Change file permissions (e.g., MODE="0666" for read/write by everyone).
Change ownership (e.g., GROUP="plugdev").
Apply these settings automatically whenever the device is plugged in.

Example rule:


SUBSYSTEM=="hidraw", ATTRS{idVendor}=="abcd", ATTRS{idProduct}=="1234", MODE="0666"

udev file from github repo

# Put this file into /etc/udev/rules.d and unplug and re-plug your device.

# You don't need to restart Udev, new permissions will be picked up automatically.

ATTRS{idVendor}=="1209", ATTRS{idProduct}=="7877", MODE="0666"

RF output

40Mhz Output @ -1.04dBm

100Mhz Output @ -0.97dBm

300Mhz Output @ -1.04 dBm

400Mhz Output @ -1.00 dBm

800Mhz Output @ -1.3 dBm

1Ghz Output @ -0.61 dBm

1.5Ghz Output @ 0.01 dBm

2Ghz Output @ -0.87 dBm

2.4Ghz Output @ -0.94 dBm

3Ghz Output @ -3.2 dBm

Github Source Repo Programming Software and Python Script

Download Windows GUI Program

Source and Other Files on Github

Ikea INSPELNING Teardown, Ikea SmartPlug Socket with energy meter INSPELNING Internal PCB

2025-03-30T22:31:00.010+02:00

This Post is going to be Ikea INSPELNING Tear down images. Showing Internal construction and quality. Schematic and Power supply and How they Measure Power consumption.

Power Supply with BP2525

Power measurement with HLW8110

FPGA FMC Breakout Board for Accessing LPC Connections from High End Xilinx FPGA Ultrascale+ Zynq

2025-03-13T22:45:00.024+01:00

This post is going to be about Breakout board PCB for FMC Connector which are widely used on Xilinx High End FPGA board. LPC Low pinout connections do not have any GTY or GTH or GTX or MGT connections they have only differential normal SerDes connections ANSI/VITA 57.1 compliant

YouTube

Schematic

Schematic has only 4 LPC rows connected directly to Top layer and board layer connector. 1.27 mm Header route out all connections including GND pins all the Signals are routed in Differential connection

PCB

Signal Rows in FMC LPC vs. HPC Connector pins Difference

Row	LPC (160 Pins)	HPC (400 Pins)	Function
A	❌ No	✅ Yes	Power, control, & reference clocks
B	❌ No	✅ Yes	Additional I/O and clocks
C	✅ Yes	✅ Yes	Single-ended I/O & differential pairs
D	✅ Yes	✅ Yes	More I/O & differential pairs
E	❌ No	✅ Yes	Additional differential pairs (DP0-9)
F	❌ No	✅ Yes	More differential pairs (DP10-17)
G	✅ Yes	✅ Yes	Primary differential pairs & clocks
H	✅ Yes	✅ Yes	More primary differential pairs & clocks
J	❌ No	✅ Yes	Gigabit transceiver signals (MGTs)
K	❌ No	✅ Yes	More MGTs & ground

EEPROM Content

3D Printed PCB Test Jig for ADR1339 Reference Board

2025-02-07T22:14:00.008+01:00

Ribbon cable are used to Distribute power to all other boards Input Primary power of 16 to 20 V and USB 5V both are distributed over Ribbon cable

3D Printed Part

Plastic Part is Designed with Solidworks and Printed with PETG.

PCB

Source And 3D Design Files are Available github Repo

https://github.com/circuitvalley/LM399_Voltage_reference

TEN399 3V1 : Improved OpenSource ADR1399KHZ LM399 10V Ultrastable Precision Voltage Reference

2025-01-09T21:28:00.011+01:00

This is Next 3V1 revision of LM399 ADR1399KHZ based reference board, when i made my last version i received quite few small feedback form users , So I have again made few improvements in This forth version over Third reversion accumulating those suggestions.

Fist improvements is, Board has LT3042 Ultralow Noise, Ultrahigh PSRR RF Linear Regulator To Supply 15V to the ADR1399 and LT1001 , This regulator Offers reverse polarity protection and PG LED.

Board offers Dual Power supply input with a Normal Liner supply input and a USB input with boot converter to use as backup and transport.

This version has ADR1399KHZ Snubber and also Trim pot has been removed and replaced with multiple resistors with solderable jumper

There are few minor change in the PCB as well there is great care has been taken in designing slots around the PCB to remove mechanical strain on Chips and reference. Also board has been designed for Testing. Board also now also have a enclosure. Now on the output side both calibrated 10V and Direct reference voltage is also available as output.

Schematic

PCB

Source is available in my Github Repo.

microZed Breakout Carrier Card for MicroZed Zynq FPGA SOM board AES-MBCC-BRK-G

2025-01-09T20:03:00.010+01:00

For new FPGA SoC related project, and i will be using Avnet MicroZed Zynq SOM board. But Avnet microZed Board has two 100 Pin fine pitch connectors for expansion, Which is impractical for prototyping so i decided to make my own breakout board. Finding Avent microzed GPIO breakout was little hard and official board has same VCCIO regulator for all banks and avnet board also does not have differential LVDS layout.

So i made this Open source Board, With three separate switching regulator for each bank VCCIO on 4 Layer Gold finish board with most of microZed pins broken out in LVDS pair. PCB is 4 Layer impedance control for 100R LVDS pair. Board has 3 solder jumpers per regulator to change bank voltage of each bank separately.

In this project, I set out to design a custom carrier PCB tailored for the MicroZed Zynq FPGA System-on-Module (SOM), inspired by the functionality of the AES-MBCC-BRK-G. This carrier board is designed to seamlessly interface with the MicroZed module, providing robust connectivity and enhanced peripheral integration for a variety of FPGA applications. From initial concept to detailed PCB layout, the design process focused on optimizing functionality, signal integrity, and scalability to suit custom project requirements. Whether you're exploring embedded systems, hardware acceleration, or IoT development, this custom carrier board simplifies working with the powerful Zynq FPGA platform.

Schematic

There is not much in schematic , only few switching regulator for all Bank Voltage and IO headers .

PCB Source on Github

https://github.com/circuitvalley/microzed_carrier_board

5$ Low Noise, Electronics Bench LED lighting Solution with Linear Power supply, Flicker Free

2024-12-14T18:49:00.009+01:00

This small Article shows my solution to Low noise electronics bench lighting problem, Many electronics Measurement needs to be done in no electrical noise environment. I have repurposed 5$ 30V 3A Linear power supply for this purpose with Custom made LED Strip using philips Luxeon LEDs

Primary Switching transistor is mounted directly on the Heat sink

Standard Heat Sink Fit exactly on PCB holes

LED Strip PCB

Ikea BADRING Water leakage sensor Teardown , Smart Zigbee sensor

2024-12-10T23:06:00.013+01:00

This Small Article shows internals of BADRING Water leakage sensor

Video

Ikea PARASOLL Smart Door/Window Zigbee Sensor Teardown Hall Effect sensor Analysis

2024-12-10T22:34:00.002+01:00

This Small Article shows internals of PARASOLL Smart Door/Window Zigbee Sensor and analysis of its hall effect sensor using a oscilloscope

Front PCB EFR32MG24 along with a LED , Oscillator and Passives for antenna.

Back of the PCB has paring button along with a OC6811 DC-DC converter and MG3521 Halleffect sensor IC

Video

Ikea Vallhorn PIR Zigbee Motion Sensor Teardown

2024-12-06T22:49:00.006+01:00

This Small Article shows internals of Ikea Vallhorn PIR Motion Sensor

Board uses EFR32MG21 Silicon labs Multiprotocol SOC along with 8601 Opamp IC from analog devices.

How to Reverse Engineer a 12 EUR Intel PCIe FPGA Card IBM 98Y2610

2024-12-05T23:20:00.009+01:00

This Post is showing how to Reverse Engineer a Unknown FPGA Board which I got off Ebay.

This board has Intel Cyclone IV FPGA EP4CGX22BF14 board can be found on internet with part number IBM 98Y2610

Schematic

Source Example project is available on Github.

https://github.com/circuitvalley/Intel_FPGA_Board_98Y2610

TEN399 : OpenSource ADR1399KHZ LM399 10V Ultrastable Precision Voltage Reference

2024-12-01T20:32:00.010+01:00

This is Third version of LM399 ADR1399KHZ based reference board, when i made my last version i received quite few small feedback form users , So I have again made few improvements in Third reversion accumulating those suggestions.

Fist improvements is, Board has LT3042 Ultralow Noise, Ultrahigh PSRR RF Linear Regulator To Supply 15V to the ADR1399 and LT1001 , This regulator Offers reverse polarity protection and PG LED.

Board offers Dual Power supply input with a Normal Liner supply input and a USB input with boot converter to use as backup and transport.

There are few minor change in the PCB as well there is great care has been taken in designing slots around the PCB to remove mechanical strain on Chips and reference. Board also now also have a enclosure. Now on the output side both calibrated 10V and Direct reference voltage is also available as output.

YouTube Video

Schematic

PCB

Source is available in my Github Repo.

Ikea TRETAKT Teardown, Ikea SmartPlug Socket TRETAKT Internal PCB

2024-09-28T20:43:00.006+02:00

This Post is going to be Ikea TRETAKT Tear down images. Showing Internal construction and quality.

CircuitValley : Embedded Engineering

CHC5 Open Camera ISP FPGA Architecture Part 5

Capture front end

RGB/YUV-domain ISP

USB output leg (FX3 GPIF)

HDMI preview leg

Infrastructure

ISP Specification

ISP Specifications

Supported Sensor Specs

Project Source Available on Github

CHC5 Open Camera Software Architecture Part 4

Software Architecture

Webd UI

System Storage Map

Project Source Available on Github

https://github.com/circuitvalley/CHC5_Open_Camera

CHC5 FPGA Architecture Part 5

CHC5 Open Camera Lens Mount and Sensors Part 3

Currently available lens mounts:

Currently Available Sensors

Rolling Shutter

Global Shutter

IMX283

IMX294

IMX585

IMX678

IMX477

Global Shutter

IMX565

IMX568

OX08B40

Camera Adapter and Cable

Flange Distance

Lens Mounts

RF Mount

M42 Standard, C , CS, Sony E Mount

RF Mount

C Mount

CS Mount

M42 Standard Flange

Filter Mount

Project Source Available on Github

Software and Architecture_Part 4

CHC5 Open Camera System, For Hardware Accelerated Advance Machine Vision , Part 2

Camera Platform Specification

Interchangeable Lens Mount

Frame Rate

Supported Sensor Specs

CHC5 Enclosure and Mounting System

Currently Available Sensors

Rolling Shutter

Global Shutter

Filter

Camera Interface

Streaming Protocols

Aux I/O

ISP Specification

ISP Specifications

CHC5 ISP

Hardware Platform

CHC5 Core Board Schematic

Interface Board

CH5IO5G Board Schematic

PCB Internal Layer Inspection

Project Source Available on Github

Sensor and Lens Mount Part 3

CHC5 open Camera System Image Sensor Specification Comparison , CHC5 Part 1

Project Source Available on Github

CHC5 Image Sensor Comparison

CHC5 Camera System Part 2

FMC Card For MIPI TX/RX Camera CSI and Display DSI Emulation

Specification

Schematic

Hardware Revisions

Pin Assignment

Hardware

Project Github

FPGA FMC NVMe Drive SSD, NVMe SSD Drive on PCIe M.2 Adapter FMC HPC FPGA

Hardware Revisions