Use foreach to break apart a list in to its components.

In this example I’m working with a description of a temperature range. I’m told the description is a list that starts with the initial temperature, the middle value is the final temperature, and the last value is the step size between them.

set range [list -30 15 5]

If I want to write a script that enumerates all the temperatures in the range. I’m going to need to get each value from the list separately.  Typically, accessing individual elements of the list is done with Tcl’s lindex command.  However, a clever one-liner every once in a while can be really useful.

foreach {initial_value final_value step_size} $range break

The break at the end ensures that if range happened to be a longer list we’d only grab the 1st set of values.

Here’s an example procedure that enumerates all the temperatures.

# get the temperatures in the given range
proc get_temperatures { range } {
    foreach {initial_value final_value step_size} $range break

    set temperatures [list]
    for { set t $initial_value } { $t <= $final_value } { incr t $step_size } {
        lappend temperatures $t
    }

    # make sure the final temperature is included even if the step size was too big to include it 
    if { [lindex $temperatures end] != $final_value } {
        lappend temperatures $final_value
    }

    return $temperatures
}

Tcl’s foreach is a very versatile command. No doubt, we’ll use it again.

I’m going to try to start to semi-regularly post Tcl tips and tricks that might be helpful to EDA engineers and non-EDA engineers alike. So here goes….

Tip #1 Use {} braces to isolate a variable in a longer a string.

If I have a variables for  process, voltage, and temperature.

set process 1.0
set voltage 0.8
set temperature -40

And I want to create a file name with the process, voltage, and temperature embedded in it along with the units V and C. Here’s one way:

set filename library_${process}_${voltage}V_${temperature}C.lib

Note how the curly braces are used to wrap process, voltage, and temperature variables. No tricky escaping or temporary variables needed.

Read more about Tcl’s variable syntax here: http://www.tcl.tk/man/tcl8.4/TclCmd/Tcl.htm

More details about the award can be found here.

LITTLETON, Mass., Nov. 15, 2011 — CLK Design Automation today announced that it received a 2011 Customers’ Choice Award at TSMC’s Open Innovation Ecosystem Forum. The award was given for the presentation of a paper entitled, Applications of Stage-based OCV. The paper described methods of improving stage-based on chip variation derates. The presentation covered ways to combine the additional variation data collected during derate table generation with static timing analysis to enhance existing timing and optimization flows. The presentation is available upon request from CLK Design Automation.

“I am honored to have been able to present at the TSMC OIP Forum and to have been recognized by TSMC’s customers for the work that the team has done.” said Ahran Dunsmoor, Director of Product Management for CLK DA. “We’re excited to be able to work with our customers to develop enhancements to stage-based OCV that they can use in production today.”

About AOCV FX

AOCV FX provides an unprecedented amount of data in a very short amount of time – something that would have taken months of analysis with SPICE – and is opening up entirely new areas for exploration.

AOCV FX is the fastest, most complete, stage-based OCV table generator available today. AOCV FX was designed in partnership with TSMC to generate stage-based derates for static timing and optimization at 40nm and below. Built on a multi-threaded, distributed analysis engine, AOCV FX can create complete derate tables for an entire library in a few hours with very little set up.

Design Specific Stage-based OCV

Stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional OCV. However, standard methods for generating SBOCV tables are unnecessarily pessimistic because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design.

AOCV FX, on the other hand, records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database is used to generate SBOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve overall TNS and WNS and accelerate timing closure. In addition, the underlying data can be used to explore cell variation and inform design decisions early in the optimization flow.

More information can be found at www.clkda.com/products/aocv-fx.

About CLK Design Automation

CLK Design Automation is the leader in variation and timing margin analysis – helping leading edge semiconductor companies solve their most pressing timing and manufacturing challenges at 40nm and below.  CLK DA’s products include AOCV FX for full library and design specific stage-based OCV tables and Path FX for fast delay and variance analysis for critical paths and block timing characterization. Visit CLK DA online at www.clkda.com.

Amber, Path FX, and AOCV FX trademarks of CLK Design Automation. Any other trademarks or registered trademarks are the property of their respective owners.

Littleton, MA, October 18, 2011 – CLK Design Automation today announced that CSR plc (LSE: CSR and Nasdaq: CSRE) has adopted AOCV FX for the generation of AOCV timing derates, including design specific derates. AOCV timing derates are becoming an essential part of 40nm and 28nm physical design flows to accurately account for manufacturing variance. Design Specific AOCV tables further enhance existing STA and physical optimization tools ability to improve timing closure and design performance.

“As a global leader in wireless, location and audio-visual technology, we recognised that we needed to adopt AOCV to deliver functionality, performance and quality at 40nm and below,” said Babak Bastani, Vice President Chip Design for CSR. Mark Scoones, Consultant, Digital Implementation added, “CLK Design Automation’s AOCV FX was by far the best solution on all dimensions; performance, accuracy, functionality, ease-of-use and maturity.”

“With AOCV FX, we are helping CSR to implement state of the art variation aware timing capability,” said Isadore Katz, President and CEO of CLK Design Automation. “We’ve been working closely with CSR to build high accuracy derate tables and methodologies that help them deliver high performance designs, without compromising quality, all in their existing tool flows.”

AOCV Timing Derates

Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional methods. It can improve design performance and identify complex bugs that might have been masked with traditional timing methods. However, building complete, accurate AOCV tables for full libraries calls for millions of SPICE Monte Carlo runs, which is simply impractical even with unlimited compute resources and software licenses. Moreover, basic methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.

AOCV FX: Advance Timing Derates Made Practical

AOCV FX is the first practical, turn-key solution that has the performance and accuracy needed to generate a full database of SBOCV derate factors. Derate tables created by AOCV FX can be used with all of the leading timing and optimization tools.

AOCV FX is the only solution that can deliver Design Specific AOCV derates. AOCV FX records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database of values is used to generate AOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve and accelerate timing closure without compromising design quality.

Part of the TSMC Reference Flow 12.0, AOCV FX has been extensively tested for accuracy and performance for the TSMC 40nm and 28nm processes.

About CLK Design Automation

CLK Design Automation is the leader in high accuracy timing variation solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.

Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.

About CSR

CSR is a global provider of innovative silicon and software solutions for the location-aware, media-rich, cloud-connected world. Our platforms are optimised for the automotive navigation and infotainment, digital cameras and imaging, connected home infotainment and wireless audio markets. We provide solutions to complex problems in the audio-visual, connectivity and location technology domains across a broad range of markets, with a technology portfolio that includes GPS/GNSS systems, Bluetooth, Wi-Fi, FM, NFC, aptX and CVC audio codecs, JPEG, MPEG, H.264 imaging, IPS printing, microcontrollers, DSPs and broadband receivers. CSR’s technology solutions and market platforms enable its customers to deliver a superior user experience and are adopted by leaders in the auto, computer, home and mobile markets. More information can be found at www.csr.com. Keep up to date with CSR on our blog, or follow us on Twitter at twitter.com/CSR_plc

“We’ve been working closely with TSMC to build high accuracy timing tools and methodologies that are easy to add to existing flows and fast enough to be practical for day-to-day use,¨ said Isadore Katz, CEO of CLK Design Automation. “With our Design Specific SBOCV Table Generation, and Constraint Uncertainty Table Generation, we are now delivering variation aware timing capability that works with the leading STA and optimization tools supported in Reference Flow 12.0.¨

Design Specific SBOCV Table Generation

Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional OCV. However, standard methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.

AOCV FX, on the other hand, records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database of values is used to generate SBOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve overall TNS and WNS over standard SBOCV and accelerate timing closure.

AOCV FX provides a turn-key solution and has the performance and accuracy needed to generate a full database of SBOCV derate factors. SBOCV tables created by AOCV FX can be used with any qualified timing and optimization tools.

Timing Constraint Uncertainty Table Generation

Constraint uncertainty tables model the process variation sensitivity of sequential cells such as registers, latches, and SRAMs. Applying constraint uncertainty reduces the risk of hidden constraint violations when applying derates.

AOCV FX can now generate constraint uncertainty tables for use with any qualified timing or optimization tools. In addition, Amber STA also reads and applies the constraint uncertainty tables during timing analysis.

About CLK Design Automation

CLK Design Automation is the leader in high accuracy timing solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.

Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.

Littleton, MA – May 26, 2011 CLK Design Automation Inc. today announced Signal FX: high accuracy signal integrity timing analysis. Signal FX provides SPICE accurate signal integrity timing analysis, 10,000 times faster than Fast SPICE or SPICE. It works with Path FX to provide a practical, accurate, high performance solution that easily integrates into existing design flows.

“Signal FX addresses the demand for SPICE accurate timing solutions in 40 nanometer and below” said Isadore Katz, President and CEO of CLK Design Automation. “Based upon the FX model, which has been qualified by TSMC in Reference Flow 11.0 as a Fast SPICE accurate solution, Signal FX is the first high accuracy SI solution that integrates path timing, statistical analysis and statistical parasitics, while delivering orders of magnitude improvement in run time.

Signal FX adds signal integrity analysis to Path FX. Path FX complements existing STA solutions by enabling high accuracy path timing analysis. Customers run their STA tool, and the Path FX automatically delivers SPICE accurate analysis of the critical paths that have been identified. With Signal FX, customers can now analyze the crosstalk effects on those paths. Customer run their STA tool with SI, identify critical paths and their aggressors, and Signal FX uses those to deliver SPICE accurate signal integrity analysis.

At 40 nanometer and below, accuracy is critical

At 40 nanometer and below, physical implementation of high performance and low power IC designs requires high accuracy timing. Effects that could be ignored in the past such as process variance, miller capacitance, signal waveforms, can be the difference between good and bad silicon. Traditional STA tools and models lack the accuracy. SPICE and Fast SPICE lack the performance.

There are multiple points in the physical design flow where high accuracy timing is essential: modeling of IP blocks, timing closure, and yield analysis. In each of these areas, pessimistic errors of 50 or 100 picoseconds can be absolutely critical. Modeling of IP blocks, for example, creates a timing footprint that the rest of the design must conform to. The latency of the block, such as processor core, can set the performance of the entire design. Likewise, a 1 GHz clock speed translates to a 1 nanosecond clock period. Timing closure has very tight set-up and hold constraints, and the best possible estimate of the true path margin is essential. Finally, timing closure against traditional corners is no longer a guarantee of good yield. Post layout timing analysis against potential yield problems – temperature, process, and voltage – is now an important part of the sign-off process.

Accurate Signal Integrity Analysis is Essential

Signal integrity, or crosstalk, analysis is a standard part of every sign-off flow. Most STA tools use heuristics to calculate the impact of noise aggressors, and apply “conservative” metrics from when noise can occur to where it should be measured. However, with such aggressive timing margins in 40 nanometer and below, this pessimism can be excessive. For an IP block, this can mean lower clock speeds or increased power consumption. During timing closure this can mean over-buffering and excess power consumption. At yield analysis it can make 1000’s of paths appear critical, instead of 10’s of paths.

Signal FX: SPICE accurate Signal Integrity

Signal FX provides SPICE accurate signal integrity analysis to address these challenges. First, the FX model itself is typically with 2% of SPICE for timing. And because it is a transistor level model, it properly models waveform propagation, non-linear waveforms, miller capacitance, local voltage variance, etc. Second, Signal FX sweeps aggressors against the victim using same approach as would be used in SPICE or Fast SPICE. This means that the noise effect is properly calculated. Finally, Signal FX can measure noise at the receiver input (similarly to STA tools) or at the receiver output. Measuring at the output, such as would be done with SPICE, provides a much less pessimistic calculation of crosstalk.

As importantly, Signal FX is 10,000x faster than SPICE or Fast SPICE, and is very simple to use, requiring no changes to existing design flows. The performance means that 1000s of paths can be analyzed instead of 10s of paths. Using Signal FX requires none of the complexities of setting up a SPICE simulation. Designers run their existing STA/SI tool, to identify the critical paths and their aggressors. This information is easily exported into Signal FX, and then crosstalk is calculated. All of the path setup is automatically taken care of.

About CLK Design Automation

CLK Design Automation is the leader in high accuracy timing solutions – helping leading edge semiconductor companies solve their most pressing timing and manufacturing challenges at 40 and 28nm.

CLK DA’s products include AOCV FX for full library AOCV tables in days compared to weeks and months, Path FX for fast delay and variance analysis for critical paths and block timing characterization, Signal FX for SPICE accurate crosstalk analysis, and Silicon Debug to identify variation sensitive critical paths and cells.

CLK DA’s high accuracy timing technology – the FX Model, the Amber Timing Engine, and the FX Variance Solver – delivers full chip capacity, SPICE accuracy, and unprecedented performance: variance analysis 1 million times faster than Monte Carlo SPICE and path delay and crosstalk analysis 10,000 times faster than SPICE.

Amber, Path FX, AOCV FX and Signal FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.

“I am truly excited to have Matthew join our team” said Isadore Katz, President and CEO of CLK Design Automation. “Matthew is a proven leader in the EDA industry. His wealth of experience in taking start-ups to the next level will be essential for CLK as we continue to grow and expand.”

“CLK is delivering the kinds of innovative solutions that are essential for 40 and 28 nanometer IC design,” Mr. Raggett said. “These products are proving themselves in production, and this is an excellent opportunity to grow great technology into a great company.”

Prior to joining CLK, Matthew most recently was Chairman of Javelin Design Automation. Prior to that, he was President and CEO of Analog Design Automation, which was acquired by Synopsys in 2004, and was VP Field Operations at Insilicon which was also acquired by Synopsys. Matthew held executive positions at Cadence, National Semiconductor and Fairchild Semiconductor.

About CLK Design Automation

CLK Design Automation is the leader in high accuracy timing solutions – helping leading edge semiconductor companies solve their most pressing timing and manufacturing challenges at 40 and 28nm. CLK DA’s high accuracy timing technology – the FX Model, the Amber Timing Engine, and the FX Variance Solver – delivers full chip capacity, SPICE accuracy, and  unprecedented performance: variance analysis 1 million times faster than Monte Carlo SPICE and path delay and crosstalk analysis 10,000 times faster than SPICE.

CLK Design Automation’s products include AOCV FX for full library AOCV tables in days compared to weeks and months, Path FX for fast delay and variance analysis for critical paths and block timing characterization, Signal FX for SPICE accurate crosstalk analysis, and Silicon Debug to identify variation sensitive critical paths and cells.

We support threaded operation for machines with many processors or distributed operation for server farms or cloud based table generation.  The speed up is linear as CPUs or machines are added.

With the introduction of our AOCV database you can build a database of AOCV table values and then generate tables over and over again in less than a minute each.  This will let you experiment with different criteria for building tables or to create special purpose tables for whatever you are doing at the moment. The database has all the information needed to build tables for any load/slew combination for each cell.