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<channel>
	<title>CLK Design Automation</title>
	
	<link>http://www.clkda.com</link>
	<description>The leader in high accuracy timing solutions.</description>
	<lastBuildDate>Thu, 14 Feb 2013 13:47:20 +0000</lastBuildDate>
	<language>en-US</language>
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		<title>CLK DA Team</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/zDI-wa3bzT4/</link>
		<comments>http://www.clkda.com/2013/02/14/team-photo/#comments</comments>
		<pubDate>Thu, 14 Feb 2013 13:45:50 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=954</guid>
		<description><![CDATA[A lot of smiling faces as we wrapped up 2013 planning meetings at CLK DA HQ.]]></description>
				<content:encoded><![CDATA[<p>A lot of smiling faces as we wrapped up 2013 planning meetings at CLK DA HQ.<br />
<img class="alignleft size-medium wp-image-955" alt="team_2013" src="http://www.clkda.com/wp-content/uploads/2013/02/team_2013-300x200.jpg" width="300" height="200" /></p>
<img src="http://feeds.feedburner.com/~r/clkda/~4/zDI-wa3bzT4" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>Liberty Technical Advisory Board Announces Membership Grows to 16</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/-LNYPlu7qA8/</link>
		<comments>http://www.clkda.com/2012/12/19/liberty-technical-advisory-board-announces-membership-grows-to-16/#comments</comments>
		<pubDate>Wed, 19 Dec 2012 13:45:29 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[News]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=940</guid>
		<description><![CDATA[&#8220;Liberty is the cornerstone for library models and we are delighted to become part of the Technical Advisory Board,&#8221; said Isadore Katz, President and CEO of CLK Design Automation. &#8220;We look forward to working with the LTAB to extend Liberty with robust derate and variance formats. We believe this will be invaluable to the designers [...]]]></description>
				<content:encoded><![CDATA[<p>&#8220;Liberty is the cornerstone for library models and we are delighted to become part of the Technical Advisory Board,&#8221; said Isadore Katz, President and CEO of CLK Design Automation. &#8220;We look forward to working with the LTAB to extend Liberty with robust derate and variance formats. We believe this will be invaluable to the designers who are making commitments to 20nm, 14nm and beyond.&#8221;</p>
<p><a title="Liberty TAB Press Release" href="http://www.marketwire.com/press-release/liberty-technical-advisory-board-announces-membership-grows-to-16-1738294.htm">Read the full press release here&#8230;</a></p>
<p>&nbsp;</p>
<img src="http://feeds.feedburner.com/~r/clkda/~4/-LNYPlu7qA8" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>CLK Design Automation, Inc. Joins Liberty TAB</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/xGkQlNtfK1E/</link>
		<comments>http://www.clkda.com/2012/12/17/clk-design-automation-inc-joins-liberty-tab/#comments</comments>
		<pubDate>Mon, 17 Dec 2012 14:06:18 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[AOCV]]></category>
		<category><![CDATA[News]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=936</guid>
		<description><![CDATA[LITTLETON, Mass., Dec. 17, 2012 /PRNewswire/ &#8212; CLK Design Automation today announced that it has joined the Liberty Technical Advisory Board. Timing derates for process variance, temperature and voltage have become an essential part of 28nm, 20nm and 14nm physical design flows. Today, timing derates depend on a number of different formats including AOCV, OCV and proprietary [...]]]></description>
				<content:encoded><![CDATA[<div class="rpuEmbedCode">
<div class="rpuArticle rpuRepost-5e897179baa48d97185c64cd2a9d37d9-top" style="margin: 0; padding: 0;">
<p>LITTLETON, Mass., Dec. 17, 2012 /PRNewswire/ &#8212; CLK Design Automation today announced that it has joined the Liberty Technical Advisory Board. Timing derates for process variance, temperature and voltage have become an essential part of 28nm, 20nm and 14nm physical design flows. Today, timing derates depend on a number of different formats including AOCV, OCV and proprietary extensions. CLK&#8217;s goal is to help in the standardization of timing derates and variance models based upon the Liberty™ library format, the de facto standard for integrated circuit (IC) and signoff.</p>
<p>&#8220;Creating a robust standard for variance models and timing derates will be critical for broad adoption of advanced semiconductor process nodes,&#8221; said Isadore Katz , President and CEO of CLK Design Automation, Inc. &#8220;It will enable EDA tool vendors, IP suppliers and Semiconductor Foundries to address the challenges of achieving good manufacturing yields with today&#8217;s aggressive chip design specifications for power, performance and high levels of system integration.&#8221;</p>
<p>&#8220;The LTAB welcomes participation from CLK-DA,&#8221; said Jim Sproch , LTAB chair.  &#8220;CLK-DA brings new ideas and an additional perspective on OCV and we look forward to their involvement in aligning the industry on consistent ways of thinking about and modeling OCV.&#8221;</p>
<p><strong>Timing Derates</strong></p>
<p>Timing derates help designers model process variance, temperature, and voltage during the physical design and timing sign-off process. These derates combine manufacturing process information along with other factors, some environmental, some design or library specific, into a set of values that adjust the calculated timing delays to ensure high manufacturing yield.</p>
<p>Today&#8217;s leading edge methodologies use AOCV or Advance On Chip Variation. Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional methods. It can improve design performance and identify complex bugs that might have been masked with traditional timing methods. However, building complete, accurate AOCV tables for full libraries calls for millions of SPICE Monte Carlo runs, which is simply impractical even with unlimited compute resources and software licenses. Moreover, basic methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.</p>
<p><strong>AOCV FX from CLK Design Automation: Advance Timing Derates Made Practical</strong></p>
<p>AOCV FX is the first practical, turn-key solution that has the performance and accuracy needed to generate a full database of SBOCV derate factors. Derate tables created by AOCV FX can be used with all of the leading timing and optimization tools.  AOCV FX can help designers correct for unnecessary process pessimism, and incorporate other margin factors for voltage, temperature, and delay accuracy.</p>
<p><strong>About CLK Design Automation</strong></p>
<p>CLK Design Automation is the leader in high accuracy timing variation solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.</p>
<p>Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.</p>
<p>CONTACT:<br />
Ahran Dunsmoor<br />
CLK DA<br />
<a href="mailto:ahran@clkda.com" target="_blank">ahran@clkda.com</a><br />
978-486-1056 x208<br />
<a href="http://s.tt/1x9OG"><img src="http://1.rp-api.com/3731294/via.png" alt="" width="12" height="11" />PR Newswire</a> (<a href="http://s.tt/1x9OG">http://s.tt/1x9OG</a>)</div>
</div>
<img src="http://feeds.feedburner.com/~r/clkda/~4/xGkQlNtfK1E" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>ICCAD workshop on Variability Modeling</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/L2a6Z70knVM/</link>
		<comments>http://www.clkda.com/2012/11/05/iccad-workshop-on-variability-modeling/#comments</comments>
		<pubDate>Mon, 05 Nov 2012 19:03:31 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[AOCV]]></category>
		<category><![CDATA[Statistical]]></category>
		<category><![CDATA[Timing]]></category>
		<category><![CDATA[White Papers]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=920</guid>
		<description><![CDATA[We&#8217;ll present a poster at the IEEE Workshop on Variability Modeling and Characterization at ICCAD on Thursday. Shiva Raja will be there to show how our FX transistor model and simulation engine can be used to reduce corners in traditional static timing analysis (STA). The paper also shows that setup and hold constraints are not [...]]]></description>
				<content:encoded><![CDATA[<p><a href="http://www.clkda.com/wp-content/uploads/2012/11/iccad_2012_poster.png"><img class="alignleft size-medium wp-image-921" title="ICCAD 2012 Poster" src="http://www.clkda.com/wp-content/uploads/2012/11/iccad_2012_poster-300x224.png" alt="" width="300" height="224" /></a>We&#8217;ll present a poster at the IEEE Workshop on Variability Modeling and Characterization at ICCAD on Thursday.</p>
<p>Shiva Raja will be there to show how our FX transistor model and simulation engine can be used to reduce corners in traditional static timing analysis (STA). The paper also shows that setup and hold constraints are not correctly predicted by corner models while statistical FX models provide more accurate results.</p>
<p><a title="Workshop Details" href="http://iccad.com/2012_event_details?id=149-3-W">http://iccad.com/2012_event_details?id=149-3-W</a></p>
<img src="http://feeds.feedburner.com/~r/clkda/~4/L2a6Z70knVM" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>Tcl Tip #2</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/f_wJwY8fzQM/</link>
		<comments>http://www.clkda.com/2012/01/16/tcl-tip-of-the-day-2/#comments</comments>
		<pubDate>Mon, 16 Jan 2012 14:46:00 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[Tips]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=832</guid>
		<description><![CDATA[Here&#8217;s the next in my ongoing list of tcl tips and tricks. Use foreach to break apart a list in to its components. In this example I&#8217;m working with a description of a temperature range. I&#8217;m told the description is a list that starts with the initial temperature, the middle value is the final temperature, and [...]]]></description>
				<content:encoded><![CDATA[<p>Here&#8217;s the next in my ongoing list of tcl tips and tricks.</p>
<h2>Use foreach to break apart a list in to its components.</h2>
<p>In this example I&#8217;m working with a description of a temperature range. I&#8217;m told the description is a list that starts with the initial temperature, the middle value is the final temperature, and the last value is the step size between them.</p>
<pre>set range [list -30 15 5]</pre>
<p>If I want to write a script that enumerates all the temperatures in the range. I&#8217;m going to need to get each value from the list separately.  Typically, accessing individual elements of the list is done with Tcl&#8217;s lindex command.  However, a clever one-liner every once in a while can be really useful.</p>
<pre>foreach {initial_value final_value step_size} $range break</pre>
<p>The break at the end ensures that if range happened to be a longer list we&#8217;d only grab the 1st set of values.</p>
<p>Here&#8217;s an example procedure that enumerates all the temperatures.</p>
<pre># get the temperatures in the given range
proc get_temperatures { range } {
    foreach {initial_value final_value step_size} $range break

    set temperatures [list]
    for { set t $initial_value } { $t &lt;= $final_value } { incr t $step_size } {
        lappend temperatures $t
    }

    # make sure the final temperature is included even if the step size was too big to include it 
    if { [lindex $temperatures end] != $final_value } {
        lappend temperatures $final_value
    }</pre>
<pre>    return $temperatures
}</pre>
<p>Tcl&#8217;s foreach is a very versatile command. No doubt, we&#8217;ll use it again.</p>
<p>&nbsp;</p>
<img src="http://feeds.feedburner.com/~r/clkda/~4/f_wJwY8fzQM" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>Tcl Tip of the Day</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/LEZObyY2hAI/</link>
		<comments>http://www.clkda.com/2012/01/10/tcl-tip-of-the-day/#comments</comments>
		<pubDate>Tue, 10 Jan 2012 19:54:19 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[Tips]]></category>
		<category><![CDATA[tcl]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=818</guid>
		<description><![CDATA[In EDA tcl is the scripting language.  Tcl has its quirks but it&#8217;s extremely flexible and powerful&#8230; and often misunderstood. I&#8217;m going to try to start to semi-regularly post Tcl tips and tricks that might be helpful to EDA engineers and non-EDA engineers alike. So here goes&#8230;. Tip #1 Use {} braces to isolate a variable in [...]]]></description>
				<content:encoded><![CDATA[<p>In EDA tcl is <strong>the</strong> scripting language.  Tcl has its quirks but it&#8217;s extremely flexible and powerful&#8230; and often misunderstood.</p>
<p>I&#8217;m going to try to start to semi-regularly post Tcl tips and tricks that might be helpful to EDA engineers and non-EDA engineers alike. So here goes&#8230;.</p>
<h2>Tip #1 Use {} braces to isolate a variable in a longer a string.</h2>
<p>If I have a variables for  <code>process,</code> <code>voltage, and</code> <code>temperature</code>.<br />
<code></code></p>
<pre>set process 1.0
set voltage 0.8
set temperature -40</pre>
<p>&nbsp;</p>
<p>And I want to create a file name with the process, voltage, and temperature embedded in it along with the units V and C. Here&#8217;s one way:</p>
<pre>set filename library_${process}_${voltage}V_${temperature}C.lib</pre>
<p>&nbsp;</p>
<p>Note how the curly braces are used to wrap process, voltage, and temperature variables. No tricky escaping or temporary variables needed.</p>
<p>Read more about Tcl&#8217;s variable syntax here: <a href="http://www.tcl.tk/man/tcl8.4/TclCmd/Tcl.htm">http://www.tcl.tk/man/tcl8.4/TclCmd/Tcl.htm</a></p>
<p>&nbsp;</p>
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		<title>Isadore accepts TSMC OIP Customers’ Choice Award</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/XcMTxHhPwJk/</link>
		<comments>http://www.clkda.com/2011/12/19/isadore-accepts-tsmc-oip-customers-choice-award/#comments</comments>
		<pubDate>Mon, 19 Dec 2011 19:33:12 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=794</guid>
		<description><![CDATA[On his last trip to San Jose, Isadore stopped by TSMC headquarters to accept the TSMC OIP Forum Customers&#8217; Choice Award. Pictured are Tom Quan, Open Innovation Platform® Marketing, TSMC and Isadore Katz, CEO, CLK Design Automation. More details about the award can be found here.]]></description>
				<content:encoded><![CDATA[<p>On his last trip to San Jose, Isadore stopped by TSMC headquarters to accept the TSMC OIP Forum Customers&#8217; Choice Award. Pictured are Tom Quan, Open Innovation Platform® Marketing, TSMC and Isadore Katz, CEO,  CLK Design Automation.</p>

<a href='http://www.clkda.com/2011/12/19/isadore-accepts-tsmc-oip-customers-choice-award/dsc_4175s/' title='DSC_4175s'><img width="150" height="150" src="http://www.clkda.com/wp-content/uploads/2011/12/DSC_4175s-150x150.jpg" class="attachment-thumbnail" alt="DSC_4175s" /></a>
<a href='http://www.clkda.com/2011/12/19/isadore-accepts-tsmc-oip-customers-choice-award/dsc_4149s/' title='DSC_4149s'><img width="150" height="150" src="http://www.clkda.com/wp-content/uploads/2011/12/DSC_4149s-150x150.jpg" class="attachment-thumbnail" alt="DSC_4149s" /></a>

<p>More details about the award can be found <a href="http://www.clkda.com/2011/11/15/clk-design-automation-awarded-tsmcs-oip-customers-choice-award/" title="TSMC OIP Customers' Choice Award">here</a>.</p>
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		<title>CLK Design Automation Awarded TSMC’s OIP Customers’ Choice Award</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/DV27voMEtIU/</link>
		<comments>http://www.clkda.com/2011/11/15/clk-design-automation-awarded-tsmcs-oip-customers-choice-award/#comments</comments>
		<pubDate>Tue, 15 Nov 2011 12:34:54 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[AOCV]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=780</guid>
		<description><![CDATA[CLK DA&#8217;s presentation of Applications for Stage-based OCV was given the award based on customer feedback at the 2011 TSMC Open Innovation Ecosystem Forum. LITTLETON, Mass., Nov. 15, 2011 &#8212; CLK Design Automation today announced that it received a 2011 Customers&#8217; Choice Award at TSMC&#8217;s Open Innovation Ecosystem Forum. The award was given for the presentation [...]]]></description>
				<content:encoded><![CDATA[<h2>CLK DA&#8217;s presentation of Applications for Stage-based OCV was given the award based on customer feedback at the 2011 TSMC Open Innovation Ecosystem Forum.</h2>
<p>LITTLETON, Mass., Nov. 15, 2011 &#8212; CLK Design Automation today announced that it received a 2011 Customers&#8217; Choice Award at TSMC&#8217;s Open Innovation Ecosystem Forum. The award was given for the presentation of a paper entitled, <span style="text-decoration: underline;">Applications of Stage-based OCV</span>. The paper described methods of improving stage-based on chip variation derates. The presentation covered ways to combine the additional variation data collected during derate table generation with static timing analysis to enhance existing timing and optimization flows. The presentation is available upon request from CLK Design Automation.<span id="more-780"></span></p>
<p>&#8220;I am honored to have been able to present at the TSMC OIP Forum and to have been recognized by TSMC&#8217;s customers for the work that the team has done.&#8221; said Ahran Dunsmoor, Director of Product Management for CLK DA. &#8220;We&#8217;re excited to be able to work with our customers to develop enhancements to stage-based OCV that they can use in production today.&#8221;</p>
<p><strong>About AOCV FX</strong></p>
<p>AOCV FX provides an unprecedented amount of data in a very short amount of time &#8211; something that would have taken months of analysis with SPICE &#8211; and is opening up entirely new areas for exploration.</p>
<p>AOCV FX is the fastest, most complete, stage-based OCV table generator available today. AOCV FX was designed in partnership with TSMC to generate stage-based derates for static timing and optimization at 40nm and below. Built on a multi-threaded, distributed analysis engine, AOCV FX can create complete derate tables for an entire library in a few hours with very little set up.</p>
<p><strong>Design Specific Stage-based OCV</strong></p>
<p>Stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional OCV. However, standard methods for generating SBOCV tables are unnecessarily pessimistic because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design.</p>
<p>AOCV FX, on the other hand, records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database is used to generate SBOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve overall TNS and WNS and accelerate timing closure. In addition, the underlying data can be used to explore cell variation and inform design decisions early in the optimization flow.</p>
<p>More information can be found at <a href="http://www.clkda.com/products/aocv-fx" target="_blank">www</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">.</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">clkda</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">.</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">com</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">/</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">products</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">/</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">aocv</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">-</a><a href="http://www.clkda.com/products/aocv-fx" target="_blank">fx</a>.</p>
<p><strong>About CLK Design Automation</strong></p>
<p>CLK Design Automation is the leader in variation and timing margin analysis &#8211; helping leading edge semiconductor companies solve their most pressing timing and manufacturing challenges at 40nm and below.  CLK DA&#8217;s products include AOCV FX for full library and design specific stage-based OCV tables and Path FX for fast delay and variance analysis for critical paths and block timing characterization. Visit CLK DA online at <a href="http://www.clkda.com/" target="_blank">www</a><a href="http://www.clkda.com/" target="_blank">.</a><a href="http://www.clkda.com/" target="_blank">clkda</a><a href="http://www.clkda.com/" target="_blank">.</a><a href="http://www.clkda.com/" target="_blank">com</a>.</p>
<p>Amber, Path FX, and AOCV FX trademarks of CLK Design Automation. Any other trademarks or registered trademarks are the property of their respective owners.</p>
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		<title>CSR Selects CLK Design Automation’s AOCV FX</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/ROTJxw5AguE/</link>
		<comments>http://www.clkda.com/2011/10/18/csr-selects-aocv-fx/#comments</comments>
		<pubDate>Tue, 18 Oct 2011 11:07:45 +0000</pubDate>
		<dc:creator>Ahran Dunsmoor</dc:creator>
				<category><![CDATA[AOCV]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=760</guid>
		<description><![CDATA[Global leader in wireless technology adopts CLK DA’s solution for timing derate generation Littleton, MA, October 18, 2011 &#8211; CLK Design Automation today announced that CSR plc (LSE: CSR and Nasdaq: CSRE) has adopted AOCV FX for the generation of AOCV timing derates, including design specific derates. AOCV timing derates are becoming an essential part [...]]]></description>
				<content:encoded><![CDATA[<p>Global leader in wireless technology adopts CLK DA’s solution for timing derate generation</p>
<p>Littleton, MA, October 18, 2011 &#8211; CLK Design Automation today announced that CSR plc (LSE: CSR and Nasdaq: CSRE) has adopted AOCV FX for the generation of AOCV timing derates, including design specific derates. AOCV timing derates are becoming an essential part of 40nm and 28nm physical design flows to accurately account for manufacturing variance. Design Specific AOCV tables further enhance existing STA and physical optimization tools ability to improve timing closure and design performance.<span id="more-760"></span></p>
<p>“As a global leader in wireless, location and audio-visual technology, we recognised that we needed to adopt AOCV to deliver functionality, performance and quality at 40nm and below,” said Babak Bastani, Vice President Chip Design for CSR. Mark Scoones, Consultant, Digital Implementation added, “CLK Design Automation’s AOCV FX was by far the best solution on all dimensions; performance, accuracy, functionality, ease-of-use and maturity.”</p>
<p>“With AOCV FX, we are helping CSR to implement state of the art variation aware timing capability,” said Isadore Katz, President and CEO of CLK Design Automation. “We’ve been working closely with CSR to build high accuracy derate tables and methodologies that help them deliver high performance designs, without compromising quality, all in their existing tool flows.”</p>
<h2>AOCV Timing Derates</h2>
<p>Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional methods. It can improve design performance and identify complex bugs that might have been masked with traditional timing methods. However, building complete, accurate AOCV tables for full libraries calls for millions of SPICE Monte Carlo runs, which is simply impractical even with unlimited compute resources and software licenses. Moreover, basic methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.</p>
<h2>AOCV FX: Advance Timing Derates Made Practical</h2>
<p>AOCV FX is the first practical, turn-key solution that has the performance and accuracy needed to generate a full database of SBOCV derate factors. Derate tables created by AOCV FX can be used with all of the leading timing and optimization tools.</p>
<p>AOCV FX is the only solution that can deliver Design Specific AOCV derates. AOCV FX records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database of values is used to generate AOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve and accelerate timing closure without compromising design quality.</p>
<p>Part of the TSMC Reference Flow 12.0, AOCV FX has been extensively tested for accuracy and performance for the TSMC 40nm and 28nm processes.</p>
<h2>About CLK Design Automation</h2>
<p>CLK Design Automation is the leader in high accuracy timing variation solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.</p>
<p>Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.</p>
<h2>About CSR</h2>
<p>CSR is a global provider of innovative silicon and software solutions for the location-aware, media-rich, cloud-connected world. Our platforms are optimised for the automotive navigation and infotainment, digital cameras and imaging, connected home infotainment and wireless audio markets. We provide solutions to complex problems in the audio-visual, connectivity and location technology domains across a broad range of markets, with a technology portfolio that includes GPS/GNSS systems, Bluetooth, Wi-Fi, FM, NFC, aptX and CVC audio codecs, JPEG, MPEG, H.264 imaging, IPS printing, microcontrollers, DSPs and broadband receivers. CSR&#8217;s technology solutions and market platforms enable its customers to deliver a superior user experience and are adopted by leaders in the auto, computer, home and mobile markets. More information can be found at <a href="http://www.csr.com">www.csr.com</a>. Keep up to date with CSR on our <a href="http://www.csr.com/blog">blog</a>, or follow us on Twitter at <a href="http://twitter.com/csr_plc">twitter.com/CSR_plc</a></p>
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		<title>CLK DA Announces Design Specific Stage-based OCV and Constraint Uncertainty for TSMC Reference Flow 12</title>
		<link>http://feedproxy.google.com/~r/clkda/~3/IVa8erz8Agg/</link>
		<comments>http://www.clkda.com/2011/06/01/tsmc-reference-flow-12/#comments</comments>
		<pubDate>Wed, 01 Jun 2011 15:02:33 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[AOCV]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.clkda.com/?p=525</guid>
		<description><![CDATA[Littleton, MA, June 1 &#8211; CLK Design Automation today announced support for TSMC’s Reference Flow 12.   CLK DA extended its leadership in high accuracy timing solutions with design specific stage-based OCV (SBOCV) table generation and added support for timing constraint uncertainty table generation. Both of these capabilities can be used with any STA or optimization [...]]]></description>
				<content:encoded><![CDATA[<p>Littleton, MA, June 1 &#8211; CLK Design Automation today announced support for TSMC’s Reference Flow 12.   CLK DA extended its leadership in high accuracy timing solutions with design specific stage-based OCV (SBOCV) table generation and added support for timing constraint uncertainty table generation. Both of these capabilities can be used with any STA or optimization solution that supports stage-based OCV  or constraint uncertainty for TSMC Reference Flow 12.0.<br />
<span id="more-525"></span><br />
“At 28 nanometer and below, on chip variation has become a major factor in design predictability,¨ said Suk Lee, director of Design Infrastructure Marketing at TSMC. “With a continued and close collaboration between the two companies, CLK DA provides needed solutions for attacking on chip variation in digital IC designs.¨</p>
<p>“We’ve been working closely with TSMC to build high accuracy timing tools and methodologies that are easy to add to existing flows and fast enough to be practical for day-to-day use,¨ said Isadore Katz, CEO of CLK Design Automation. “With our Design Specific SBOCV Table Generation, and Constraint Uncertainty Table Generation, we are now delivering variation aware timing capability that works with the leading STA and optimization tools supported in Reference Flow 12.0.¨</p>
<h2>Design Specific SBOCV Table Generation</h2>
<p>Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional OCV. However, standard methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.</p>
<p>AOCV FX, on the other hand, records a complete set of derate values for cells based on a full range of allowed load and slew combinations. This database of values is used to generate SBOCV tables based on a variety of design specific selection criteria. Design specific derates can substantially improve overall TNS and WNS over standard SBOCV and accelerate timing closure.</p>
<p>AOCV FX provides a turn-key solution and has the performance and accuracy needed to generate a full database of SBOCV derate factors. SBOCV tables created by AOCV FX can be used with any qualified timing and optimization tools.</p>
<h2>Timing Constraint Uncertainty Table Generation</h2>
<p>Constraint uncertainty tables model the process variation sensitivity of sequential cells such as registers, latches, and SRAMs. Applying constraint uncertainty reduces the risk of hidden constraint violations when applying derates.</p>
<p>AOCV FX can now generate constraint uncertainty tables for use with any qualified timing or optimization tools. In addition, Amber STA also reads and applies the constraint uncertainty tables during timing analysis.</p>
<h2>About CLK Design Automation</h2>
<p>CLK Design Automation is the leader in high accuracy timing solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.</p>
<p><em>Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.</em></p>
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