Cool Verification

DVCon 2013: The Road to 1M Design Starts

2013-02-20T22:42:13-06:00

As many of you know, DVCon 2013 is next week in San Jose, CA. Verilab will be there in force, including at the UVM tutorial on Monday, poster and paper sessions, a lunch panel, and last, but not least, my 4th Industry Leaders panel, The Road to 1M Design Starts:

How many times have you seen a great idea for a new design effort crushed because the cost of creating it was too great given the probability of getting a good return on investment? It happens at both big companies and small. And, what about the potentially revolutionary ideas that are never even considered because an engineering team or individual would never imagine that a chip would be a possible solution?

Like it or not, developing complex semiconductors comes at an enormous cost. New design flows including use of ESL, Design and Verification IP, Emulation, FPGAs, and the like have all helped contain some of the expansive growth in complexity associated with these efforts. But, is that enough?

What would need to take place in the next 10 years to, on the one hand, reduce the barrier of entry for smaller teams and on the other, dramatically enhance the capabilities of large teams working on the toughest challenges?

The DVCon 2013 Industry Leaders panel will answer the question - what will it take to get to 1M design starts per year?

Panelists:

Yervant Zorian, Fellow and Chief Architect - Synopsys, Inc.
Ziv Binyamini,Corporate Vice President, Systems and Software Solutions - Cadence Design Systems, Inc.
Sunil Shenoy, Corporate Vice President, General Manager, Visual and Parallel Computing Group - Intel Corp.
John Costello, Vice President, IC Design - Altera Corp.
Serge Leef, Vice President, New Ventures - Mentor Graphics Corp.

The panel will be held this coming Wednesday, February 27 from 3:30-4:30pm in the Oak/Fir Ballroom at the DoubleTree Hotel in San Jose, CA. I hope to see you there!

Conservative vs. Liberal Programming Practices

2013-01-23T13:25:04-06:00

Listening to the discussion about UVM extensibility today on the Accellera VIP-TSC call, I was reminded of a great post from Steve Yegge of Google.

It's *very* long, but a good read. In summary, Steve proposes that there are two competing world views when it comes to programming:

"Conservative" programming views

Software should aim to be bug free before it launches.
Programmers should be protected from errors.
Programmers have difficulty learning new syntax.
Production code must be safety-checked by a compiler.
Data stores must adhere to a well-defined, published schema.
Public interfaces should be rigorously modeled.
Production systems should never have dangerous or risky back-doors.
If there is ANY doubt as to the safety of a component, it cannot be allowed in production
Fast is better than slow.

"Liberal" programming views

Bugs are not a big deal.
Programmers are only newbies for a little while.
Programmers figure stuff out amazingly fast when their jobs depend on it.
Succinctness is power.
Rigid schemas limit flexibility and slow down development.
Public interfaces should above all else be simple, backward-compatible, and future-compatible.
System flexibility can mean the difference between you getting the customer (or contract) vs. your competitor nabbing it instead.
Companies should take risks, embrace progress, and fiercely resist ossification.
Premature optimization is the root of all evil.

Steve's point is that everyone falls somewhere on the spectrum between conservative and liberal (programming), whether they realize this or not.

On the Accellera VIP-TSC, and often in our everyday verification work, each of us often has debates where one side or the other claims a technical position assuming their position is based on a fundamental law of nature. It can be useful to admit to yourself that there are different views of acceptable programming practices, and there are pros and cons of each. Understanding this can improve your interaction with your team members, and can allow a team to more efficiently make conscious decisions about preferred styles as we move through a development process.

Want to Share Your Experience Adopting UVM?

2013-01-15T14:29:23-06:00

Update January 18, 2013

I appreciate the responses to this post. The Accellera folks have been able to fill the slots needed for the UVM Tutorial at DVCon. So no more responses are required!

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Have you spent some portion of the last year or two adopting the UVM verification methodology? Would you be interested/able to present your experiences to the wider verification community as part of a tutorial session at DVCon next month in San Jose? If so, please contact me directly ASAP.

Lou Covey Interviews Gary Smith on the $10,000 ASIC

2013-01-03T16:01:59-06:00

Back in August I wrote a post here on Cool Verification called The $10,000 ASIC about a question I was posing to folks at DAC last summer about whether you could produce a prototype of an advanced chip for a total EDA tool and design/verification IP cost of $10,000.

Lou Covey from New Tech Press has spent the last several months investigating this question and has posted the first in a series of articles and interviews - this time with Gary Smith of Gary Smith EDA:

Gary Smith considers the quest for the $10K chip

In the interview, Gary mentions that it's relatively common to do 2M gate designs to the prototype stage in a couple of months with a budget of just shy of $30K. But he also mentions that it takes upwards of $29M to complete a "very good design". Additionally, investors are more likely to invest in chip design start-ups when the cost involved is closer to $25M.

I'd still like to know if you could reduce the tool and IP costs for the $29M project down to my mythical $10K mark, would it make the chip easier to design and verify, and more palatable to investors?

I'm looking forward to the rest of Lou's series to see what others have to say on the topic!

UVM Runtime Phasing and Phase Jumping Survey

2012-12-03T17:03:36-06:00

Many of you using the UVM library are aware that runtime phasing was one of the areas most heavily tweaked from the original OVM codebase. But there have been disagreements since the UVM 1.0 was released back in 2011 about whether the phasing mechanism as released was useful and if so, sufficient for creating reusable verification components and environments. Verilab is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose.

Verilab UVM Phasing Survey

I'd love to get some detailed responses from Cool Verification readers to share with the Accellera VIP-TSC. Your help on this is greatly apprecated!

Note - this survey is geared towards active UVM users only.