Cool Verification

DVCon 2012: The Resurgence of Chip Design

2012-02-09T18:02:36-06:00

As many of you are likely aware, DVCon 2012 is fast approaching. As I have done the past two years, I will be moderating the Industry Leaders panel. The topic? "The Resurgence of Chip Design". The panel is from 2:30-3:30pm at the DoubleTree Hotel in San Jose, CA on Tuesday, February 28, 2012.

The Resurgence of Chip Design

Over the course of the last decade, many technologists claimed that in the future, the most important part of a new product would be software, not the underlying hardware. Hardware would be a commodity. Everyone would write unique software on top of off the shelf hardware to create a value add. The relevance of chip design, and career prospects for chip designers would be limited.

But what actually happened was quite different. Large technology firms have hired ever-growing teams of engineers to design the custom chips critical to the success of their upcoming products. Building your own ASIC is often the only way to reach the desired power, performance, and cost goals.

The DVCon 2012 Industry Leaders Panel will focus on better understanding the trends driving this resurgence.

Speakers:
Ted Vucurevich - Enconcert, Inc.
John Costello - Altera Corp.
Gary Smith - Gary Smith EDA
Jim Hogan - Vista Ventures LLC

I'm looking forward to hearing a candid assessment from the panelists on the state of chip design today. I'd also like to learn more about the criteria companies should use to determine whether they should make their own custom chips or use off-the-shelf parts. Now, I could make up all my own questions, or perhaps revisit some topics from past industry leaders panels... But it would be great (and probably preferred by the panelists!) if your questions could be addressed too. So, what would you like me to ask the panelists this year? Let me know in the comments to this post, or by emailing me at jl at coolverification dot com.

UVM and the Death of SystemVerilog

2011-08-16T08:42:31-05:00

Earlier this year, the Accellera VIP-TSC approved version 1.0 of the UVM. Supported by all of the major EDA vendors, the UVM has been billed as the next generation in verification methodology goodness. Better than the VMM. Better than the OVM. A chance for the verification community to shed some of the baggage carried over from years of backward-compatibility requirements and methodology fits and starts. Another purported benefit is that testbenches written with SystemVerilog/UVM can be more easily ported to simulators from different vendors. There is also a developing market in UVM verification IP to allow testbenches, in theory, to be quickly constructed from commercially available components.

All of this sounds great, right? Vendors standardizing on languages and methodologies and competing on tools. It's how the world should be. Except there are a few small problems that vendors are unlikely to tell you about before you start your next project.

First and foremost is a problem that is glaringly obvious to anyone who's tried learning SystemVerilog and the UVM (or one of the other VMs over the years): it's difficult and time consuming to learn SystemVerilog and any of the VMs... especially if you have never used a verification language before. Folks with limited software backgrounds (read: most design and verification engineers) find seemingly simple concepts like inheritance and factories to be mind boggling, even if they won't admit it. And folks with deep software backgrounds will find SystemVerilog an absolute pit of despair when compared with modern languages such as Python and Ruby, and the UVM complex in a way that clearly is meant to patch over serious deficiencies in the underlying language. Plus, any testbench that has to deal with multi-language issues is clearly out of luck in the simplicity and ease of use department.

Now that the UVM has arrived and the methodology bickering between the major vendors has mostly (well, somewhat) ceased, the complexity of the UVM and the earlier VMs on which it is based can be viewed more clearly and with less controversy. And the results are not good. After years of experience working with many multiple clients, it seems the only way out of our current dilemma is to start looking at other languages and development frameworks. For that to happen, major semiconductor companies may need to start funding this type of development again, since it is abundantly clear the EDA vendors are incapable of this level of innovative thinking. Or more kindly, perhaps they feel there is no money in innovation. Either way, major advances in design and verification productivity need to get here sooner rather than later.

48th DAC Day 1: Cloud Computing, Registers

2011-06-08T11:15:43-05:00

This marks my 5th year attending the Design Automation Conference. Unlike prior years where I've lugged around my camera and had a schedule of events to participate in, this year, I came with a relatively free slate. No hard plans, just a todo list (thank goodness for OmniFocus for iPad) and my walking shoes. I wanted to share a quick list of a couple of my highlights from Monday.

As usual, my first few hours at DAC involved me wandering the show floor catching up with all of my friends and colleagues that I only get to see in person at conferences. Included in that list were Harry Gries and James Colgan, who were kind (and patient) enough to give me demo of Xuropa's latest cloud offerings in the Synopsys Partner's booth. I've been struggling with the benefits of EDA in the cloud for a few years now, but have recently seen some good use of outsourcing one's EDA IT infrastructure. But the product Xuropa (and Synopsys - more later) is pushing is a bit different than what I've been used to up to this point.

The idea seems to be that users would start and stop instances of servers on the "cloud" on an as-needed basis. I'm more used to the data center model where a few servers are always at my beck and call 24x7, and I pay even if I may not be using them at any given time. While I was looking at the Xuropa solution as a possible complete replacement for a company's internal infrastructure, it appears it may be better suited to occasionally augmenting capacity due to the seeming (to me) conceptual complexity of the user interface involved in starting up servers for interactive use. I'm sure Harry and/or James will jump in and be happy to explain where I've got it wrong :-).

Much later in the day I spoke with Synopsys about the new VCS cloud, which I believe is based on a very similar infrastructure to what is used by Xuropa (in fact, I believe Synopsys and Xuropa are partners on some aspects of the Xuropa product). But the VCS cloud use model somehow made more sense to me. The idea is that you have your own farm of compute servers running VCS. But sometimes you want, say, an extra 10000 CPU hours to help slog through a large regression. So you compile your simulation on your own servers, and push that entire image up to the Cloud for execution on Amazon's massive server farm. You only pay for what you use, and critically, the price includes the required Synopsys licenses (unlike the Xuropa offering where licenses purchases are handled separately by you with your vendors).

Unfortunately, if you use tools or vendor IP other than what is provided by Synopsys, I would expect there would be some complications with setup. There could even be legal complications as I discovered recently when trying to use an outsourced data center to manage design IP from one vendor where another vendor who was on bad terms with the first vendor controlled access to the hosted solution. If you are running a pure Synopsys flow the VCS cloud could be worth a serious look. If you run with a mixed flow the Xuropa solution may have a better long-term potential.

Beyond the cloud discussions with Synopsys and Xuropa, I was able to make time for the enjoyable discussion between Steve Wozniak and Mike Cassidy of the San Jose Mercury News. Check out my Twitter stream for some after-the-fact-real-time commentary. There was a big crowd present for the session, though I left feeling that somehow all the questions posed felt bit rehearsed - like nothing was asked that Wozniak had not been asked in (probably many multiple) interviews before. I would have enjoyed something a bit more in-depth and focused on the particular problems faced by DAC attendees. That being said, kudos to the DAC organizing committee for bringing in a big name to liven up the keynote.

Next, I spent about 30-45 minutes speaking with Dave Murray, Joe Hee, and Tamas Olaszi over at the Duolog booth (#2931). Tamas gave me a great demo of Socrates Bitwise, a register management tool. For those of you not familiar, a big problem on almost every chip design I've ever worked on is managing register definitions from documentation, to RTL, to verification test bench, to software and beyond. Most companies write a set of scripts to manage this task, and most companies end up falling far short of creating an easy to use, robust solution. Though I haven't used the tool, Bitwise seems the closest to an ideal implementation to commercial or in-house tool I've seen. They have a robust set of import APIs and export templates that can be used to easily process your existing register data and output in a format that exactly matches what you have already been using in your design and verification flow. Even better, since Duolog works with a wide variety of companies they should, in theory, be able to steer you towards generated code that most closely aligns with industry best practices so you don't have to go through the trial and error process that most companies use. If you have registers in your design, and if you are involved in chip design you most certainly do, then you owe it to yourself to stop by the Duolog booth to take a look.

Project Planning Birds-of-a-Feather at 48th DAC?

2011-05-12T19:47:59-05:00

Quick question for those of you attending DAC next month. Would anyone be interested in working with me to organize a project planning/management Birds of a Feather session? I've been dabbling in Agile techniques for the last several months and would enjoy sharing experiences with others about what project planning and management techniques (Agile or otherwise) work best.

Let me know via blog comment, Twitter, or email at jl at coolverification dot com.

Cool Verification on Facebook, Twitter

2011-03-08T20:58:29-06:00

As many of you have noticed, I've fallen into quite an irregular posting schedule here on Cool Verification. After almost 6 years I don't feel too bad about not having a post up ever week (um, well, once a quarter?). But one reason for the irregular posting schedule is that I've been communicating much more heavily with many of you via Facebook and Twitter. If you'd like to join in the conversation, I'd recommend you head over to one of the following sites and "like" or "follow" me to participate!

As a side note, I've got an audio recording of my "Making Great Products Great" panel from last week. I'm trying to work out the best way to post it. If you have suggestions on how to do it (beyond embedding a streaming link in a blog post) let me know.