Cool Verification

DAC 2010 Denali Party Photos

2010-06-20T20:13:38-05:00

I've just posted my photos from this year's Denali party. Even if Cadence keeps the party going next year, it just won't be the same. Enjoy!

DAC 2010: My Personal "Must See" List

2010-06-14T02:28:07-05:00

It's summertime, and in the EDA world, that can only mean one thing - it's time for the Design Automation Conference. I've been attending DAC since 2007, and for the second time since then DAC is in Anaheim, California. One of the things I find the most difficult about DAC is keeping track of what is going on when, so I thought I'd share what I've come up with so far with all of you. First, here are the events I will personally be participating in:

Tuesday

9a-noon: Synopsys Interoperability Booth
1:30p - Conversation Central: Verifying the Universe
- I'll be hosting a conversation with Tom Alsop and Hillel Miller about the UVM development effort. The conversation will be streamed live, and you'll be able to call and ask questions if you're not able to attend in person.

Wednesday

4:30pm - Moderating the Pavilion Panel: SoC Verification - Are we there yet?

In addition to these events, I've got the following public sessions penciled in on my calendar. Given the complexity of grabbing events from the DAC website and adding them to my calendar, I'm certain I've forgotten an item or two.

Monday

Simulation-Based FlexRay™ Conformance Testing – An OVM Success Story, Jason Sprott - Verilab

Tuesday

7:30am - Accellera Breakfast Panel and Discussion: "UVM: Charting the New Territory"
12:00pm- CEDA Luncheon: "Beyond von Neumann Computing"

Wednesday

2:30-3:15pm: Pavilion Panel - High School Panel: You Don't Know Jack!
4:30-6pm: User Track - Front-end Testing and Verification

If you have any additional sessions you'd recommend I add to my list, let me know.

UVM-EA Release Details

2010-05-20T21:30:31-05:00

As I mentioned earlier in the week, the Universal Verification Methodology – Early Adopter release (UVM-EA) was announced on Monday and can be downloaded from the Accellera website. The process for putting together this release has been both exhilarating and frustrating, and it has highlighted (at least for me) the potentially transformative impact wide adoption of this library could have on the industry. Many users, from those with the most basic skills to those with the most advanced, have held off selecting a commercially available verification methodology for SystemVerilog. Initially, this may have been because they did not want to be locked in to a specific SystemVerilog simulator, though until recently (and, to be honest, still somewhat today), it was extremely difficult to write code that compiled on all three major simulators regardless of methodology. Some felt the VMM and OVM were too complex; others felt the libraries were ill-suited to their particular needs.

Though I doubt anyone is going to stop what they’re doing and adopt the UVM mid-project, I believe engineers starting new verification efforts will take a serious look at the UVM.

So, what, exactly, is in the UVM-EA release? The release was based on, but is not completely backward-compatible with, the OVM 2.1.1. If you are not using callbacks or the objection mechanism in the OVM 2.1.1 you should not see any compatibility issues. For current OVM users, your first step to UVM adoption will be to run the OVM_UVM_Rename.pl script located in the bin directory of the UVM distribution.

## For e.g:
## % perl OVM_UVM_Rename.pl -top_dir /xyz/abc/src

The script will convert ovm’s to uvm’s, and rename “tlm_” to “uvm_tlm_”. Next, take some time to familiarize yourself with new and updated features such as:

Enhanced callback capabilities – not directly backward compatible with the OVM
Enhanced objection mechanism
Added a “report catcher” to allow users to catch and throw log messages

You’re probably wondering what is meant by a “report catcher”. The easiest way to explain what the report catcher does is by example. Here is an example taken from the UVM Reference Guide:

class my_error_demoter extends uvm_report_catcher;
function new(string name="my_error_demoter");
    super.new(name);
endfunction
//This example demotes "MY_ID" errors to an info message
function action_e catch();
    if(get_severity() == UVM_ERROR && get_id() == "MY_ID")
      set_severity(UVM_INFO);
    return THROW;
endfunction
endclass

my_error_demoter demoter = new;
initial begin
// Catchers are callbacks on report objects (components are report
// objects, so catchers can be attached to components).

// To affect all reporters, use null for the object
uvm_report_cb::add(null, demoter);

// To affect some specific object use the specific reporter
uvm_report_cb::add(mytest.myenv.myagent.mydriver, demoter);

// To affect some set of components using the component name
uvm_report_cb::add_by_name("*.*driver", demoter);
end

There are good reasons for and against adopting the UVM. Here are a few things to consider:

Does the verification IP you use interoperate with the UVM?
How substantial is your current verification environment? If you are not already using the OVM the amount of work required could be substantial to fully adopt the UVM.
Are others who rely on your code willing and/or able to switch to the UVM?
For those not using the VMM or OVM, is your team skilled in object oriented programming techniques? If not, be prepared – advanced verification techniques require more than a basic understanding of good programming practices.
Do you like to be an early adopter, or do you prefer to wait until the dust settles?
Do you prefer to use the methodology library that comes prepackaged with your simulator, or are you ok with using the latest source version directly?
Does the version of your simulator support all of the SystemVerilog constructs used in the UVM?

Here are some equally bad reasons you should not use when making your decision:

There is no documentation or support for the UVM

Wrong – The UVM comes with an enhanced user guide and reference documentation. Most OVM documentation still applies to the UVM.

The UVM is not “production quality”

Wrong – My understanding is that at least one (if not both) authors of the OVM have run their production test suites on the UVM.

No one else is using the UVM

Well… True enough, but many people are using the OVM, upon which the UVM is based.

I am morally opposed to the letter ‘U’

One final note. The current release is marked “EA” for “Early Adopter”. The official 1.0 release of the UVM will may be sometime late summer and could contain any number of new features, depending on user feedback and the number of volunteers willing to contribute time to architecting, coding, and testing these features.

UVM-EA Release Now Available

2010-05-17T10:28:05-05:00

Just a quick note - the Universal Verification Methodology Early Adopter (UVM-EA) release is now available on the Accellera website. I'll post additional details on what the release includes later today.

Video: UVM Register Package Survey Results

2010-05-05T17:49:33-05:00

I gave a presentation earlier today on the UVM register package survey results. I decided to record a video of the presentation for your viewing pleasure. One thing I didn't address in the video is a question I've received a few times about how many companies (as opposed to individuals) responded for each package. The biggest responses were for Synopsys and Cadence packages. 36 companies responded that they used the Synopsys SystemVerilog register package. 10 companies responded that they use the Cadence package. Remember - these numbers are influenced by package usage and by how much vendors promoted my survey to their customers. So I make no claims (nor should you) about register package market share from the answers for Question 1 in the survey.

As always, comments welcome! And just in case, here is the link to the video if it doesn't show up below.