SUNNYVALE, Calif., June 23, 2009 -- Denali Software, Inc., as one of the DDR-PHY Interface (DFI) specification participating members, today announced the release of the official DFI specification version 2.1. The significant momentum and support for the DFI specification has led to over 3,880 user downloads of the specification. The DFI specification version 2.1 is now available on the DFI community website (www.ddr-phy.org) and includes low-power features supporting DDR3 and the newly released LP-DDR2 memory technologies from JEDEC. Some of the significant features in the latest specification enables low-power PHY, frequency change and frequency ratio options. The collaborative technical working group includes members from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics, and will be represented in the DFI exhibit booth at Denali MemCon, June 22-24 in Santa Clara, CA (www.memcon.com).

“As the industry continues to demand higher performance and an enriched user experience in consumer products, energy efficiency and overall system costs becomes paramount design considerations,” said Simon Segars, EVP and general manager, Physical IP division at ARM. “As the leader in high performance, energy efficient processor IP we fully support the DFI standards for DDR design. DFI 2.1 aligns with our goal of delivering unparallel low power end-to-end solutions to the embedded design community.”

“As SoC designs migrate from DDR2 to DDR3 technologies to take advantage of the performance benefits, there is a strong need to reduce the integration effort by using a standardized interface between the DDR3 controller and PHY,” said Don Friedberg, director of Foundation IP Solutions at LSI Corporation. “The contributions from LSI and others on the DFI technical working group have resulted in a standardized interface that is both easy to integrate and provides access to critical memory technology features. We look forward to wide usage of this specification across the industry.”

DDR3 support, introduced in DFI 2.0, benefits from all of the low power features added in the latest revision, making a more compelling solution for power sensitive designs. The new frequency ratio support, which allows the memory to operate at a data rate of up to 8X the memory controller clock frequency, is critical to supporting DDR3 memories operating at the upper end of the supported frequency range.

“The recent growth in the DDR IP marketplace has proven to be a fruitful environment for the development of the DFI interface specifications,” said Navraj Nandra, director of product marketing at Synopsys, Inc. “Synopsys has begun to incorporate DFI 2.1 support into our broad portfolio of high-quality DesignWare DDR IP solutions beginning with our high-performance DDR3/2 PHYs supporting data rates up to 2133Mbps.”

“The DFI2.1 specification is designed to allow users to future-proof their SoCs in the ever-advancing DDR2/3 and LP-DDR2 technology space,” said Kamalesh N. Ruparel, vice president and general manager, ASIP Solutions, Virage Logic. “As the industry’s trusted IP partner, Virage Logic is committed to providing technically differentiated, silicon proven IP solutions that are standards compliant. With this goal in mind, the Intelli™ DDR multi-protocol solution has been architected to be DFI 2.1 standard compliant while delivering high efficiency, increased performance and bandwidth, at the lowest power possible.”

“We have seen significant customer pull for the features now delivered in the DFI 2.1 specification, namely support for the LP-DDR2 memory protocol and the new low-power features,” states David Lin, vice president of Marketing for Denali. “Denali would like to thank our fellow DFI team members for their efforts and contributions to the continued development of this specification. The DFI ecosystem continues to grow and this release will surely enable new and speedier semiconductor support for LP-DDR2 memories.”

About the DFI Specification
The DDR-PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

SUNNYVALE, Calif., May 28, 2009 —Denali Software, Inc., today announced the final agenda for MemCon Silicon Valley 2009, the largest worldwide conference addressing business, market applications, device technologies, and standards for memory and storage. This year’s conference and exhibition will feature keynotes, technical tutorials, panels on timely topics, and exhibits demonstrating the newest products, applications and technologies from the industry’s leading companies this June 22-24 at the Hyatt Regency Santa Clara, CA. To access the free registration and agenda details, visit: www.memcon.com/agenda.

“For memory design engineers, Denali MemCon remains a high-value event with applicable technical presentations, relevant exhibits and key networking opportunities,” said Ed Doller, chief technology officer at Numonyx and Denali MemCon 09 keynote speaker. “Numonyx is looking forward to its participation again this year as speakers, panelists, exhibitors and partners within the engineering community.”

The highlight of the Denali MemCon 2009 agenda will be four keynotes from industry luminaries Ed Doller, CTO at Numonyx, Jim Elliot, vice president of Memory at Samsung Semiconductor, Mark Gogolewski, CTO at Denali Software, and Ken Hansen, senior fellow and vice president at Freescale Semiconductor. The MemCon agenda also includes over 25 presentations and 4 panels addressing NAND Flash controller segmentation and capability, the critical challenges and opportunities for SSDs, DDR3 DRAM market adoption, and the trends and solutions for low-power memory subsystems.

“It’s readily apparent that there are plenty of educational, marketing and networking opportunities at MemCon of value to designers, technologists and OEM staffers,” stated Jim Elliott, vice president, Memory marketing, Samsung Semiconductor. “Attendees will find Samsung’s presentations and exhibits in particular to be highly informative as we speak directly to innovations and trends that are driving success in these challenging times.”

The agenda also includes a special parallel track, “Beyond Flash - Defining Storage Class Memories (SCM),” brought to you by Web-Feet Research. For more information about the special MemCon track sponsored by Web-Feet Research, contact: alan.niebel@web-feetresearch.com or +1 (831) 373-1985. Following MemCon is the “JEDEC LPDDR2 Symposium” on Thursday, June 25 at the Hyatt Regency Santa Clara. This in-depth introduction to the new LPDDR2 Low-Power Memory Standard will focus on LPDDR2’s operational characteristics, the changes from prior generation memory technology, its groundbreaking shared NVM/SDRAM interface and more. To register: http://www.jedec.org/Home/trade_events/lpddr.

This year’s Denali MemCon corporate platinum sponsors are Samsung Semiconductor and Rambus. Additional sponsoring and exhibiting companies and organizations include: Agilent, Arasan, Denali, DFI, Easy Co., Freescale Semiconductor, Fusion-io, IBM, Intel, JEDEC, Marvell, Micron, Numonyx, ONFi, SanDisk, SandForce, Seagate, SPMT, STEC, ST Microelectronics, Unity Semiconductor, Virident, Web-Feet Research and Western Digital.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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The Denali logo, Denali, and Databahn, and MMAV are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.

SUNNYVALE, Calif., May 27, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Netronome Systems has deployed Denali Databahn™ PCI Express (PCIe) design cores, MMAV™ and PureSpec™ verification IP, which support the latest PCIe I/O virtualization (IOV) specifications from the PCI-SIG, in designing their new, high-performance Network Flow Processor NFP-3240, targeting unified computing architectures. Netronome's architects and engineers used Denali's Databahn IP cores, MMAV and PureSpec verification IP products to accelerate the design and verification of this processor, and speed overall deployment of PCI Express technology.

“To scale network performance to 10Gbps and beyond, the NFP-3240 offers a fully compliant PCIe v2.0 implementation including SR-IOV with 256 queues for network I/O co-processing in heterogeneous IA/x86 designs. When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali Software was the preferred vendor that met our critical high throughput and feature requirements,” states Jim Finnegan, senior vice-president of silicon engineering at Netronome. “We rely on Denali’s high-quality, interoperable design and verification IP solutions and excellent customer support to meet the PCIe 2.0 and IOV specifications, our product development timeframes, and achieve a competitive advantage.”

Netronome’s NFP-3240 provides intelligent packet processing in a power-efficient design, and is targeted for designers of communications equipment whose network processing requirements extend beyond simple forwarding. The high-performance NFP is powered by 40 multi-threaded programmable networking cores, and runs at 1.4 GHz to deliver over 56 billion instructions per second and 320 hardware threads that optimize memory utilization, allowing for 1800 instructions per packet at 30 million packets per second. This enables 20Gbps of L2-L7 deep packet processing with line-rate security and I/O virtualization for millions of simultaneous flows. The NFP is also power efficient, operating at only 15 to 35 watts, and delivering over 1.84 BIPS, more than double the efficiency of any similar products.

“As the leading provider of IP solutions for PCIe and IOV technology, we continually strive to provide high-quality and configurable PCIe interface IP solutions for our customers, such as Netronome, to reduce their design risk and enable them to develop complex chips on schedule,” remarks David Lin, vice president of Marketing for Denali Software. “We value Netronome's confidence in Denali and are pleased that our design and verification IP products sped their design time and that their performance goals were met.”

About Databahn PCI Express Solutions
Denali's Databahn PCIe cores and PureSpec verification IP software for PCI Express provide full support of the Address Translation Service specification, Single-Root I/OV, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities. For more info about Databahn and PureSpec, visit www.denali.com/products/.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn, MMAV, and PureSpec are trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

SUNNYVALE, Calif., April 22, 2009 –– Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Percello Ltd., a fabless semiconductor company developing digital baseband processor chips, has achieved first-pass silicon success with Denali’s Databahn™ DDR memory controller IP and MMAV verification IP, successfully deployed in its low-power PRC6000 system-on-a-chip (SoC). Percello’s PRC6000 is the first worldwide SoC solution dedicated for the emerging 3G UMTS and HSPA+ femtocell market. Denali’s design and verification IP accelerated Percello’s designers’ ability to design DDR2 memory system, lower their integration risk, and speed their time-to-market for their new innovative cellular chip.

“Today's SoC design specifications necessitate high-quality IP and VIP and Denali’s solutions and expertise unlike any other vendor. We were pleased with the unmatched performance and overall ease of integration of Denali's Databahn memory controllers into our chip design,” said Rafy Carmon, vice president of R&D at Percello Ltd. “We used Databahn controller and MMAV in our design to support our required DDR2 memory interface and TSMC’s 65nm CMOS technology. During the design and verification phases, we found that Denali's IP and VIP were easy-to-use and to integrate which facilitated our very fast design cycle.”

Percello’s PRC6000 chip is a highly integrated device supporting all femtocell backhauling architectures and functions such as timing, security and others. PRC6000 is compliant to 3GPP Rel 7 baseline, supports 8 users simultaneously and is capable of delivering 21.6Mbps downlink and 5.76 Mbps uplink.

DDR DRAM is a key component in many memory subsystems found in a variety of computing, networking and communications manufactured today. With DDR DRAMs achieving speed grades up to 1600 Mbps, high-performance DDR interfaces are a critical variable in overall system performance. To better address these challenges, designers need a high-quality, proven solution consisting of more than the digital DDR memory controllers.

“Today's high-performance SoCs require specialized DDR memory systems that must address several design criteria plus an aggressive time-to-market schedule,” said Marc Greenberg, director, technical marketing of IP products for Denali. “Our Databahn DDR controller and verification IP stellar reputation has really escalated in the industry allowing our customers to make an easier choice to address their application specific performance requirements. We are very content with Percello’s first-pass silicon-success with their complex, high-performance SoC.”

About MMAV
Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at: http://www.denali.com/mmav.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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The Denali logo, Denali, and Databahn, and MMAV are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.

SUNNYVALE, Calif., March 31, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced availability and first customer shipments of the latest Denali Databahn™ controller IP cores, based on the current preliminary version of the PCI Express® (PCIe) 3.0 specification, for use in next-generation chip designs. Denali's Databahn IP product was selected by leading fabless semiconductor companies to accelerate the overall deployment of PCIe 3.0 technology into high-performance storage and networking systems. Among other key features, the preliminary PCIe 3.0 specification increases the PCIe 2.0 interconnect performance bandwidth from 5 GT/s to 8 GT/s while preserving compatibility with software and mechanical interfaces.

“Together with the strong market acceptance of our PCIe 3.0 verification IP solution, this announcement positions us as the leading provider of IP solutions for the emerging PCIe 3.0 technology,” said David Lin, vice president of Marketing for Denali Software. “Denali continues to collaborate with high-end customers to leverage our PCIe design and verification expertise to deliver a complete and robust IP solution to hit their market windows.”

As the industry’s first-to-market PCIe 3.0 solution, Denali's Databahn IP product provides full support of the preliminary PCIe 3.0 specification features including: TLP Prefix, Atomic Operations, Resizable BARS, Alternative Routing-ID, scalable architecture up to 16 lanes, PIPE specification Gen 3, as well as support for Single-Root I/O Virtualization. Access more detailed info about Databahn PCIe IP features and request an evaluation at: www.denali.com/databahn/pcie.

About Denali’s PCI Express Solutions
Denali's extensive portfolio for deploying PCIe technology includes the industry's leading verification IP, design IP, and compliance suite, which are leveraged in an efficient ecosystem of IP and EDA vendors, PHY providers, and ASIC vendors and foundries. Learn more about the industry's most trusted solutions for PCIe technology at: www.denali.com/pcie.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying PCI Express, USB, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademarks of Denali Software, Inc. All other trademarks are of their respective owners.

Sunnyvale, Calif., March 16, 2009 – Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Celeno Communications, a leading provider of semiconductors for multimedia Wi-Fi home networking applications, has incorporated its high-performance Databahn™ DDR memory controller IP into its new 5 GHz Wi-Fi system on a chip (SoC) that aims to support whole-home distribution of multiple high definition IPTV video streams for carrier-class gateways, DVRs and set-top boxes. Denali’s Databahn enabled Celeno’s engineers to achieve optimal system-level performance for its DRAM systems in the design of the CL1300 and fast time to market.

“During the design of our new WiFi SoC (CL1300), we prioritized performance and time to market,” said Lior Weiss, vice president of Marketing at Celeno Communications. “Denali’s unmatched reputation for a high-performance, configurable DDR controller IP provided an optimal solution for the DDR DRAM subsystem and has allowed us to meet the requirements for carrier-grade video streaming.”

Celeno’s innovative WiFi CL1300 SoC reflects a fresh technological approach to HD video streaming, optimizing WiFi to achieve carrier-grade performance. Celeno’s technology introduces significant range, robustness and throughput improvements, for effective HD video streaming over standard WiFi. The Celeno 1300 enables applications such as IPTV residential gateway to Set Top Box connectivity, multi-room DVR content distribution to multiple terminals around the house, and Internet and PC multimedia and entertainment content distribution.

Denali’s Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for any given application. Denali’s Databahn DDR memory controller IP offers a powerful, multi-port solution with configurable features, DFI compliance and functionality to satisfy system performance requirements.

“High-performance IP is key to solving DDR memory system requirements, especially when dealing with next-generation wireless home applications,” said Marc Greenberg, director, Technical Marketing of IP products at Denali Software. “With our high-quality Databahn DDR controller IP, we are providing customers with reliable and flexible memory systems that integrate well into the system environment. We also realize the importance to provide a solid roadmap of IP to our customers and are pleased to be working with Celeno to achieve this.”

About Databahn DDR Memory Solutions
Denali’s Databahn DDR Memory solutions ensure compatibility with all the latest high-speed memory technologies, including the many DDR2, DDR3, and LP-DDR2 devices from all major memory vendors and supports 27 different process nodes. Databahn controllers are DFI compliant and highly configurable, enabling an opportune match for a wide range of system architectures. For more info, visit: www.denali.com/dram.

About Celeno
Celeno is a leading provider of high performance Wi-Fi chips for HD multimedia and entertainment home networking applications. Powered by Celeno's system-on-chip (SoC) and its OptimizAIR™ technology, home gateways, multi-room DVRs and media servers can distribute multiple and simultaneous HD video streams to standard set-top boxes, PCs, television sets and other Wi-Fi enabled consumer devices. Founded in 2005, the company has offices and representatives in EMEA, the US and Asia-Pacific and is backed by blue chip investors including Cisco Systems, Greylock Partners and Pitango Venture Capital. www.celeno.com.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

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Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.

SUNNYVALE, Calif., February 24, 2009 — Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that NextIO, the premier provider of next-generation I/O solutions, has successfully utilized PureSpec™ verification IP (VIP) to verify compliance with the latest PCI Express 2.0 Multi-Root-I/O Virtualization (IOV)protocol specifications and validate interoperability on their new generation N1400-PCM High-Speed Switch Module. NextIO's verification engineers chose Denali PureSpec VIP for its high-quality and seamless integration into their design and verification environment, providing a reliable and comprehensive framework for accelerating design cycle times.

“Traditional blade server designs limit users to only one additional I/O technology other than Ethernet on the motherboard and forces users to remove power from their server blades to update their I/O technology. NextIO’s N1400-PCM High-Speed Switch Module extends PCIe signaling outside of the BladeCenter chassis and provides users exponential I/O connectivity choices to one or more blade servers and to reassign or change I/O technologies without powering down blades,” states Rich Warwick, vice president of Engineering and Operations at NextIO. “NextIO is the industry pioneer and leader in PCI Express I/O Virtualization, and Denali is the leader in PCI Express base and IOV compliance verification tools. This made the selection of Denali an obvious choice when building the world’s first Spec-Compliant Multi-Root I/O Virtualization switch. We have reaped significant benefits from Denali's high-quality models and their reliable verification IP as it has helped us reduce development risk, cost and minimized our overall time-to-market.”

NextIO’s N1400-PCM High-Speed Switch Modules brings best-in-class PCIe connectivity to the IBM® BladeCenter® and provides a flexible and manageable expansion solution for these platforms. NextIO’s switch technology allows all blade servers to extend their PCIe signals to an external I/O expansion unit.

“Denali understands the challenges facing design teams, including reaching time-to-market timelines while minimizing the impact on engineering resources,” states Sanjiv Kumar, director of Verification Products at Denali Software. “Our customers, such as NextIO, confidently use our high-quality verification IP so that their designs can meet PCI Express MR-IOV compliance and significantly shorten the verification time required to bring their product to market.”

About Denali’s Verification IP for PCI Express
Denali's PureSpec verification IP software for PCIe is the most widely used solution for verifying functionality, compliance and interoperability of PCIe designs at the pre-silicon stage of chip or IP core development. PureSpec supports the latest PCI-SIG specifications for Address Translation Service, Single-Root and Multi-Root I/OV, including configuration spaces (physical function, virtual function and base function), Alternative Routing-ID interpretation, Functional Level Reset (FLR), and PCI Manager (PCIM) capabilities. For more info about PureSpec and its benefits in your next design, visit https://www.denali.com/vip.

About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
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Denali and Denali Software are registered trademarks of Denali Software, Inc. PureSpec is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.