All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.

However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.

First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.”   Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.

Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.

One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“.  Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run.  They claim to be able to reduce the overall test-set by as much as 50%.

This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices.  I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).

The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology.  After talking with them, I shuffled to the right (to the next booth) where TSSI was set up.  I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.

Stay tuned…

Magma ATPG is mothballed yet again.  Here are the two stories that just came to me through Google Alerts:

Chris Edwards’ Shrinking Violence post “Magma bids adieu to ATPG” , which in turn links to the following story, “Magma Cans Test Tools” at the IET website (update: The IET story is also Chris’ - see his comment).

So, I am assuming Mr. Sanjay Bali (a Magma Product Director) did give someone permission to publish the news.  Now it’s here.

The quote in the articles above from Mr. Bali was “We could not differentiate hugely with the ATPG solution” was a bit different from what he told me at DAC - “It’s cooking”, he said, indicating that the tool was just not ready for prime-time.  This is more along the same line of what I heard from others last fall when the original announcement was made, that this tool was a long way from being a real product.

I would have thought differentiation would have been fairly easy, since none of the ATPG vendors are offering “power-aware” algorithms yet, that I know of.  Synopsys’ latest work targets ’small-delay defects’, whereas Mentor’s latest efforts have been ultra-compression techniques.  Cadence’s Encounter Test boasts “true-time”  or faster than at-speed test with their ATPG.

Anyone out there know more of this story?

Do tell…

Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side is in order.

[the bolding above is mine]

Then she mentions “inserting ‘testers’ into the chip” (hello! DFT!), and the inevitable declining demand for high end testers, which reminds me of another recent ATE deal that I meant to bring up: Verigy acquires Inovys.  Now that’s fairly old news, but it ties in, because you can see that even the biggest of ‘big iron’ tester companies are investing in the DFT tester space.

But then another deal came to light yesterday that for me, drove home the fact that I work for an industry that seems to be circling the wagons and huddling together to weather an economy that’s taken the wind out of most everybody’s sails. And since this is just on the other side of the DFT fence from EDA, I thought I’d blog it. The deal: a 50/50 merger between Credence and LTX, two ‘big iron’ ATE vendors, both distant trailing competitors in the semiconductor test market that is dominated by the test industry’s ‘big three’: Advantest, Teradyne and Verigy.  The move follows on the heels of Credence’s announcement last week that they sold a $5M piece of their automotive test business to Advantest.  Anything to make a couple bucks…

As in any merger or acquisition, the main reasons given for the merger with LTX are ROI improvements due to combining/slimming certain groups to reduce overhead, and to be able to present themselves as a bigger company supporting more facets of a diverse industry. But just as in the Cadence/Mentor possibility, the interesting speculation is in the product ‘overlap’ (as in the Chris Edwards analysis of ‘Cadentor’), or product ‘rationalization’ as it’s termed by Rick Nelson of T&M World, in this blog post.

The big question is, will it keep them both afloat? The combined value of these two companies (if I read the Yahoo financials correctly) combined will still be ~20% of the smallest of the ‘big three’. And the ATE business is every bit as brutal as EDA… maybe it was a big deal for Cadence to pull out of DAC this year, but most of the ‘big iron’ ATE companies pulled out of ITC some years ago.

Oh yeah, and he new company’s name?  I got nothing. Submissions?

Please…

First off, for me - well I’ve said it before, DAC is not really my show, mostly because test and DFT are not very well represented. But I showed up about mid-afternoon and talked with some of the test-related vendors, such as WinterLogic, TSSI, SynTest, Genesys and LogicVision. More on those conversations in another post.

I was traveling light, so no laptop. I had also neglected to re-check the location of the BoF session and wandered around for a few minutes searching, before recognizing Richard Goering and asking directions (irony alert: blogger asks journalist for directions to a blogging event - I know, right?).

I walked in as David Lin of Denali was being harassed mid-way through his presentation on corporate blogging. There was an animated discussion trying to triangulate the definition of blogging. Are you really a blogger if you’re just publishing white-papers for your company? Isn’t a blog just the modern day equivalent of a ‘column’? Of course there was the predictable exchange between the journalist and the corporate marketer about the current plight of the EDA press.

A fairly good mix of folks showed up (there seemed to be 30-40 people all-in-all, you’d have to ask JL what his count was). John Blyler and a couple other journalist-bloggers from Chip Design magazine were there, as well as Richard Goering, and Peggy Aycinena, all except Goering professing to be bloggers in their own way. Also in attendance seemed to be several marketing/PR people, there to figure out how communicate with bloggers - I hadn’t realized we were that hard to contact - but I think the real question was “how can I use you as another channel to my customers?” There was also Janick Bergeron of Verification Guild - and the aptly dubbed “Original EDA blogger”, John Cooley, was also there. My only complaint is that the “independent” EDA blogger was somewhat under-represented.

After another short talk by Steve Liebson, the attendees took some time to introduce themselves and their interest in EDA blogging. Then JL attempted to open he floor to some different topics for discussion - when a curious thing happened: He asked me what I thought of publishing solicited content, and as I answered - no lie - half the room suddenly stood up and left. What is something I said, or… ? It was quite comical, really. But I’m a good sport, so I checked my arm-pits and continued.

Anyway, aside from the fact that most of the conversation seemed to center around the blog as a marketing tool, it was all good. I’d like to thank JL, Harry, Sean and David for putting together a fascinating event!

I encourage all of you interested in this form of communication to come and participate!

One commenter, James Colgan, replied:

“….or how about an Online Trade Show!? No traveling at all!”

I thought, yeah, OK - good idea… and then I was e-surfing this evening and came upon a post over at State of the Media, talking about an online trade show website called Xuropa - apparently run by… wait for it… James Colgan!

Seems like it’s just getting off the ground, but as a vendor you can put marketing material in your online booth, demonstrate products in online labs, and as an individual you can visit these online locations, and network with peers. Check it out…

It seems in the past several years, the design-for-test job has grown more complicated (as any other facet of the electronics design discipline), what with new (or more prominent) defect mechanisms and fault models, and new DFT methods and technologies to address them.

I was reading an interview at T&M World with Atun Domic of Synopsys, and the question came up about whether DFT Engineers are necessary to implement the constantly evolving (my words) structures for manufacturing test.  Actually, here’s the exchange:

Q: Is design for test (DFT) strictly the domain of DFT engineers?

A: Certainly, there are DFT specialists, and their responsibility is to construct the DFT strategy for the chip. But verification engineers also need to understand DFT, since they must verify the chip functionality in its test mode. As for design engineers, we see that users of our Design Compiler tool—traditional logic design engineers—also run DFT Compiler and DFT MAX, our scanning and compression tools. We’ve made these tools part of the design flow, so these engineers don’t have to call in test experts.

So DFT engineers can basically sit back and say “let’s do scan!  And JTAG!, Oh, how about some BIST!” And then everyone else will do the implementation and verificaton?  Generate patterns?  How many of you DFT engineers out there have it that easy?

Here’s the thing:  Designers aren’t interested in doing our job.  Verification engineers have enough of a challenge trying to figure out when their job is done.  Again, not interested.

I suppose, as many organizations do, it is possible to plug the DFT gap with people from the design and verification teams, and even the test engineering organization (if one exists).  However, every one of those teams has no better ally than the DFT engineer, because being the multi-disciplinarian he or she is, the DFT engineer understands how trade-offs in testability will affect the test development as well as what impact the DFT implementation may have on the performance of the design, for example.  The good DFTe lives in both the design and test worlds, and can verify the testability as well.  All that and a bag of chips, as they say…

But if you dig around the DAC website, you’ll see a link to something called “Collocated Events“. I guess, as is the case with any large conference, the DAC event makes it convenient for other events to happen around the same time and place: various meetings, symposia, even full conferences.

The one link to a collocated event that caught my eye, being a Design for Test guy, is the Global STC Conference, presented by the Semiconductor Test Consortium, taking place just before DAC, June 4-6, in San Diego.

STC is probably most known for promoting the OPENSTAR intiative (open architecture for ATE). They also work on standards for docking interfaces and probe cards, all very test-floor centric activities, not normally the concern of designers. The agenda is dominated by those issues, but on June 5th, the second day of the conference, there are couple of sessions that piqued my interest: “Cooperation Between EDA and ATE: Now More Important Than Ever“, presented by Ed Malloy of Cadence, and “Design for Test - Small Price to Pay on Silicon for High Product Quality“, by Prasad Mantri of Sun.

Hey I have an idea! How about selling conference sessions a la carte? Or in mix-and-match packages (”go to any 10 technical sessions - any conference or symposium of your choice - for only $249!”). Naahh… probably too much travel. But it sounds better sometimes than purchasing a complete conference pass for the 2 or 3 really interesting sessions…

The conference is held every year by the folks at SiliconAid Solutions, and sponsored by EDA vendors Cadence, Mentor and Synopsys. SiliconAid provides DFT consulting services and offers a family of JTAG-related products.

One more thing: as an update to yesterday’s ‘who’s at DAC’ post, I did miss Virage Logic - they offer DFT solutions for their memories. Also TSSI, the company that created TDS (Test Design System) ATE vector translation software.