Tuesday was the first day of the conference proper, so participants gathered in a large ball room for the keynote and invited address – I, the lone twitterer of ITC2009 (@dftdigest, hashtag #ITC2009), tapped out a few notes during the speeches.

Antun Domic of Synopsys delivered the keynote, in which he talked about the various complications of non-design-aware test implementations, and called for a “DFT flow”  that is aware of every part of the design process.  He considers this “DFT flow” (as opposed to “DFT tools”)  is necessary for the successful implementation future IC designs, and notes that the industry is not quite up to the task yet.

Domic asserted that it is necessary for exploration and investment to develop these flows, and  compared these activities to that of Christopher Columbus (explorer) and Queen Isabel of Spain (investor), and displayed the following quote, which if I remember correctly, he attributed to Columbus:

“One does not discover new lands without consenting to lose sight of the shore for a very long time.”

I like the quote, but as I looked it up on the web (to make sure I quoted it correctly), I noticed that it’s actually attributed to Andre’ Gide, a 20th century Nobel winning author.  Either way, I got the point – and as I said, I like the quote.  One could apply it to many things.

Domic was followed by Shekhar Borkar from Intel, who laid out a very technical analysis of the current state of chip design, and how it might scale (or not) into the future.  Ron Wilson, covering ITC for EDN and Test & Measurement, wrote an excellent summary of Borkar’s address.

[BTW, Wilson also blogged the Stanford CRC panel, as I did in my last blog post]

After the plenary, exhibits opened, and technical sessions started.  A quick look around the floor showed the continuous contraction that this show has been experiencing over the years.  Years ago, the ATE companies left – the only ones left this year were Verigy (with a tiny booth) and Roos.  The biggest surprise to me was the scaled down Synopsys booth.  Last year, Cadence was off on the sidelines, with Mentor and Synopsys at the center.  This year, Mentor anchored the entire floor, with the rest of the field cramming into cubicle sized booths.

One humorous note: after the flack at DAC amongst the journo/bloggers about the XJTAG booth babes (see this, this, and this), I didn’t expect to see them at ITC.  Not that it bothers me.   Siliconaid staffs its booth similarly every year at ITC, and I’ve never heard any complaints, just amused chuckles…

Two panels on Tuesday afternoon, Can EDA Help Solve Analog Test and DFT Challenges? and Testing of 3-D Chips: Is There Anything New Under the Sun? both seemed worth attending, but I opted for the first – I’ll blog that later. Can’t wait? Ron Wilson wrote it up here…

Checked into my hotel in Austin, checked a couple e-mails, changed and walked down to Ironworks BBQ on Red River, right next to the convention center. Mmmm, BBQ…

Picked up my badge and ITC swag bag, complete with proceedings disks, a chance to win an iPod Touch, and a coffee mug.   Ah, well, I love a good mug, but I was hoping for a t-shirt. I still wear my shirts from 2007 and 2008. Those were some sturdy shirts! Uhh, getting off point. Sorry.

I was there in time for the first panel discussion, ‘40 years of reliable Computing at Stanford CRC.‘ Less of a panel discussion than a history of CRC presented through the eyes of several former students and associates, many stories were told of the work accomplished since the early/mid-seventies, and of it’s founder Edward McCluskey: celebrity, if not legend, in the IC Test community.

Born amidst the turbulence of anti-war protests, CRC has, over the years produced and documented research on many of the concepts that we DFT’ers today take for granted: fault equivalence, bridging faults, n-detect, psuedo-random test – don’t take it from me, go look at their extensive bibliography.  Besides that, if you hang around the Test crowd long enough, you realize that many of the more prominent figures have had some association with Stanford CRC.  A smart bunch…

From the panel, we walked over to the reception, a celebration of this being the 40th year of ITC – where a couple hundred people ate, drank, and reconnected.  Personally, I was delighted to meet many more people this year, already, due to this thing I call DFT Digest.  I really appreciate your comments, and hope you keep reading!

See you tomorrow, ITC!

Before I get to that, I should remind you all that ITC Test Week starts today with a few tutorials (which have already started, BTW).   More tutorials will be held tomorrow.  Tomorrow night, there is a special reception celebrating the 40th year of ITC, in the Austin Convention Center Ballroom.   All registered conference attendees are invited to eat, drink, and socialize – renew friendships and contacts…  fun, eh?

What I had forgotten from last year (and I guess many previous years) was that Monday night is traditionally the night that Synopsys holds their annual Test SIG event – feed you dinner and present some testimonials from customers about how well Synopsys’  tools have worked out for them.  Mentor does the same thing – but they hold their reception one night later, usually on Tuesday evening.

However this year, due to the Monday night 40th ITC reception, Synopsys graciously moved their Test SIG from Monday to Tuesday.  So now you have it – Tuesday night: Synopsys Test SIG at the Four Seasons Hotel, from 6:30-9PM, and Mentor’s ITC Reception, at the Hilton Hotel, from 7-9PM.  As a blogger, obviously, I’d like to hit both, and pass along anything interesting to you, the readers.  Unfortunately, not yet being able to clone myself, I have a decision to make.

Neither company has completely detailed their program for the receptions yet.  What I do know is that the Synopsys event will feature speakers from Cisco, Toshiba and TI, and that Mentor will spend some time talking about the direction they will be going with regard to their recent LogicVision acquisition (BTW, I just checked their website, and noticed that they have a product line name for the tools that came from LogicVision: Tessent – interesting, I wonder how that name came about?  Any guesses?).

Well, as I say, I haven’t decided how to be two places at once, so we’ll see how it works out.  The receptions are on opposite sides of the convention center, so I can’t run back and forth.  I’m not in good enough shape for that.

My question to you: Which one are you going to?

The tutorials and workshops! ITC is a 3-day conference, with an exhibition floor, surrounded by technical sessions, keynotes and panels like any other conference. But in addition to all that, the International Test Conference also hosts two full days of tutorials before the conference starts, and a day of workshops at the end – which is why they call it “Test Week“. So what? So, not only can one go and hear about the latest freaky ATPG algorithm for minimizing test power in wireless circuits, but one can also learn about the latest best-in-industry methodologies and practices.

So this year, according to the program, there are 5 tutorials on Sunday (Nov 1) and 4 on Monday (Nov 2).  Three workshops will be held on Thursday and Friday (Nov 5-6).   Subjects vary from nuts and bolts mixed signal test (tutorial 1, Analyzing, Modeling and Understanding High-Speed Interfaces Using Time Domain Reflectometry) to economics (tutorial 12, The Economics of Test and Testability). The workshops start in the afternoon on Thursday, and extend into a full day on Friday. The three workshops deal with high-speed analog circuits, design for reliability, and defect-driven test.

Tutorials and workshops cost extra, but seem well worth the cost for a deep dive into one of the many subjects covered.

See you next week!

The same day, I was cleaning my desk, and found a couple of papers that I had printed out a couple of months ago and forgot about, from DATE ‘09. One was entitled Test Architecture and Optimization for Three-Dimensional SoC’s.

Just one more: Scott Hack commented on my last post, directing me to an article written by Al Crouch at SoCCentral [hey Al, how about an article for DFT Digest?], entitled Test Standards Emerge to Improve 3D-Chip Yield. Good article, I enjoy Al’s writing style – he makes it very easy to grasp the concepts he’s trying to convey.  Basically, he runs down the applicability of the new IEEE 1149.7 and P1687 (IJTAG) to 3D-IC testability.

But back to that D&T special issue: I’ve probably said this before, but I always look forward to getting this magazine (it’s a bi-monthly occurrence).  It’s usually got something that gets my interest, even if it might be steeped in a crapload of math.  I can usually get the gist of the articles.

This issue has several interesting articles, and not just on 3D technology.  There is also a special section that highlights some of the best stuff from ITC 2008: three articles, including one on mixed-signal production test methods, by Gordon Roberts, and one on Staistics in Semiconductor Test, by W. Robert Daasch, of Portland State.

The 3D section of this D&T issue contains four articles, including one that directly addresses the Test Challenges for 3D Integrated Circuits (by Hsien-Hsin S. Lee and Krishnendu Chakrabarty).  Test is one of two main challenges that crop up when designing in 3D – the other is power (thermal issues).   I think I’d like to summarize that article, and the others on 3D test that I’ve mentioned here in a future post.  There’s a lot to think about.  By the way, you can download and read a pdf of the Guest Editor’s Introduction to the special issue here.

It’s been pointed out here and in other places that 3D technology is one of the hottest topics at ITC next month.  A quick look at the advance program reveals only two items that specifically mention 3D: A panel discussion (Testing of 3D Chips: Is there anything new under the sun?), and an embedded tutorial (Testing 3D Chips containing Through-Silicon Vias),  However, as both Bill Eklow and Erik Volkerink pointed  out in interviews with DFT Digest and Test & Measurement World, there are some board-level test items and emerging standards sessions that will most assuredly contain 3D content (for example, Embedded Tutorial 3: New Boundary-scan-based Standards).

See you at ITC!

Then, about a week back, John Blyler from ChipDesign tweets the following:

Oct 2, 2009 – Stacked die, SiP, 22nm, EDA numbers, verifying verification, going postal, 3D and more. http://bit.ly/xsgvw #chipdesign

The stacked die and SiP sticks in my head.  To be honest, it took a little looking to find the actual article (here), because the link at the blog where the short-url above leads you is broken.  It’s an interview with a panel of experts about the challenges of design at 22nm.

Then earlier this week, Rick Nelson, of EDN and and Test & Measurement World, tweets this:

“BIST gives way to built-in self-everything with 3-D ICs; test event to reach out to designers, says Verigy’s Volkerink: http://bit.ly/2OXUf2“

This was a pointer to Nelson’s second interview pertaining to the upcoming International Test Conference, with Erik Volkerink, of Verigy. In his first interview of Program Chair Bill Eklow (and mine), 3D technology was also brought up as a hot topic.

Later, as I reached into my mailbox at home, after work, I retrieved the latest copy of Chip Scale Review, containing two cover stories, 3D: The Latest Developments, and Hybrid Bonding of 3D Stacked ICs.  After opening the magazine, I found a couple more interesting articles on test as well, including one on Protocol-Aware ATE (although the term wasn’t used in the article).  You can read the whole magazine at their website.

So how many times can this topic smack me in the forehead before I pay attention? Well, I guess in this case, a few.  But OK, I get it.  So what did I get from all this?  Well first, if you follow the right people on Twitter, you’re bound to find some interesting things you may not have otherwise.

But on the subject of 3D: It seems to be one of the next pushes in packing more real estate into the same real estate (sort of like Japan – when you can’t build out, build up).  But more importantly to us folks with job titles that include the word test,  it presents as many access challenges (0r more) as any of the other measures that have been taken over the years to further integrate more functions into smaller spaces.

And if I had to predict, I’d say that JTAG/boundary scan (IEEE 1149.1 and its follow-ons) will be a key player in meeting these challenges.  What do you think?

I’m somewhat of a summer slacker – and slack I have done, when comes to DFT Digest… but it’s test conference season, so let’s pick it up!  So I wanted to point out a  couple things I’ve come across in the last couple of weeks, before I really get out of the habit of blogging!

First off, I want to put out the word to any of you, my readers that may be also blogging Test, Design-for-Test, or related subjects (or thinking of doing so), and will also be attending ITC – let’s meet up for a blogger beer, or something like that, at some point during the week. We can also network coverage of the conference if you’re up for it. Let me know, e-mail me: jford@dftdigest.com

As the press releases rolled out announcing this years ITC,  I posted comments from my e-mail interview with Bill Eklow, Program Chair for this year’s conference.  Rick Nelson of Test & Measurement World also interviewed Eklow – see his interview here.

As a matter of standards, Karen Bartleson of Synopsys, wrote, a couple weeks ago on her blog The Standards Game about ratifying the OCI (Open Compression Interface) standard – IEEE 1450.6.1.   This is of particular interest to DFT Digest, and other Design-for-Test folks, since this standard decouples compression IP from ATPG and diagnosis tools – lifting the requirement to use one vendor’s tools for all three, which is the situation today.

Karen’s reason for posting this was to point out that the IEEE standards body does react to the need for such things, and listens to the needs of EDA customers.  I agree, and appreciate this, but I have to say that I don’t necessarily think that EDA vendors follow through on creating tools to take advantage of the standards.

Take IEEE 1500 for example: it sure doesn’t seem that any EDA vendors have developed tools that customers can use to implement 1500-like structures on their own silicon.  1500 is used, so far, for more efficient internal interfaces for memory BIST operations, in some tools.

Did customer demand shape that standard?

This year, I thought I’d poll some of the organizers of the event to see what piqued their interest in what they were planning for ITC this year.  Bill Eklow (Cisco), Program Chair, and and Scott Davidson (Sun), Marketing Vice Chair, were kind enough to share their thoughts.

One of the things that ITC has quietly let slip away is a conference theme.  As Eklow states,

“In the past few years we’ve stayed away from a central ‘theme’ for the conference. You can see that we have a very diverse program.”

As ITC’08 program chair Nur Touba says in this interview in T&M World, the 2008 committee decided not to have a theme.  In 2007 (the most recent year with a theme) it was Facing Nanometer-Technology Test Challenges. Well, with an area as diverse as DFT/Test, why try to narrow the interest, eh?

Eklow does point out that there are some prominent points in the program:

“…we have a very strong program for Mixed Signal/RF and ATE.  Several papers overlapped both areas to some extent and will be of interest to attendees from both areas [...] DFT was another area that got a lot of submissions this year and consequently more sessions. We’ve also got an embedded tutorial and panel session around Testing 3D chips which should be very interesting in that it combines elements of both board and chip test.”

3D chips… cool concept. One hears more and more about them these days. At ITC this year there is an embedded tutorial and a panel devoted to the subject. Are the techniques new? Are there existing methods to be applied?

Davidson’s interest is in trying to make sense of what comes back from the ATE:

“data that can show us subtle problems and which has helped us diagnose problems using statistics. So I’m looking forward to session 1 and some of session 4 especially, because they have some interesting papers on analyzing data.”

Another interesting subject for Davidson is test economics.

“I’ve been interested in test economics for a long time, ever since I had to justify my budget when I was at Bell Labs. We know we are saving our companies and our customers money, but sometimes it is hard to prove it, and it has always seemed that decisions on what type of DFT or test to use was not made entirely rationally.”

Davidson has been active in a group devoted to just that: the Testability Management Action Group (TMAG). Monday, November 2, Davidson, with fellow TMAG members, will offer a full day tutorial on the subject.

I’ve always considered ITC to be a week-long event, but it’s only that way because the conference itself is bounded by tutorials on the front end (Sunday and Monday) and workshops on the back end (Thursday and Friday). As Eklow puts it:

“The tutorials are a good way to get yourself ready for the program. The workshops are a good way to expand your horizons afterwards.”

Another aspect of ITC that I’ve always wondered about (ever since Ben Bennetts brought it up to me a couple years back) is the board-level test content (or lack thereof) of the conference. As an IC DFT engineer, I always feel deficient with respect to where my devices are eventually soldered down. I asked about the board-level content at this year’s ITC. Eklow, a board test engineer at Cisco responded:

“I think all of the embedded tutorials on Wednesday will be of interest to the Board/System test people in addition to the In-Circuit test session on Wednesday morning. There are also elements of board/system test that are “hidden” in Thursday sessions on “Getting Working Silicon” and “Post Silicon Test, Debug and Validation”. Couple that with open working group meetings for several boundary-scan based standards (IEEE P1149.8.1, IEEE P1687, IEEE P1581, IEEE 1149.6), and that makes for a pretty full schedule.”

So now we’re hiding the content (because PCB test guys are so clever)   Just kidding – I’m convinced.

Personally I’m looking forward to visiting Austin again, seeing old friends and acquaintances, making new ones. In the meantime, leading up to the conference, I will go find a better set of readers, figure out my schedule, and blog it.

What are you looking forward to?  Comment here, or e-mail me.  I’d like to know!

The summer has passed; the deal has closed.  So I asked Joe Sawicki, VP and GM of Mentor’s Design-to-Silicon Division, if he was ready to share more detail as to the direction of their DFT products.  In a phone conversation with Mr. Sawicki and Greg Aldrich, Marketing Director of the Silicon Test Solutions group, we talked about what DFT at Mentor looks like after bringing in LogicVision.  Sawicki started off the call by re-iterating his belief that Test is an important link in the IC design chain.

Overlap? Well, yes, and no… Yes, there was product overlap, but when one considers strengths, and in particular, revenue, there was “very little overlap”.   According to Aldrich, LogicVision commands over 50% of the available BIST market, while Mentor has over 50% of the ATPG market.   Obviously Mentor’s focus has been on the ATPG-related tools, whereas LogicVision is (was) a BIST  company.   I think that from a DFTer’s point of view,  this is fairly obvious, and I said so in my second post on the merger.

Mentor plans to go forward with LogicVision’s BIST tools (memory and logic BIST), and ETBoundary, LogicVision’s boundary scan design (BSD) tool, since BSD infrastructure is used as the window to most BIST implementations.  These are tools common to both companies, and decisions have been made to supplant existing tools for incoming tools – although Aldrich did make a point of saying that existing tools will continue to be supported.

Mentor seems ready to try to put an end to the age-old “BIST vs. ATPG” debate.  Now, with both types of tools in hand, what’s the plan?  According to Aldrich, “our roadmap and our vision has been, for the last 18 months, to combine the technologies… to create a merged solution of logic BIST and embedded compression”.  A single flow.

This seems like the steepest hill to climb.  ATPG and LBIST proponents have been poking at each other for years.  Only in the last few years have the techniques begun to be used in conjunction with each other.  One hears of using ATPG patterns to ‘top-up’ LBIST coverage, or BIST cores being integrated into scanned SoCs with the help of IEEE 1500, or other isolation wrappers, but it’s certainly not an out-of-the box flow.

Mentor and LogicVision took their first step in integrating the two technologies in 2007, when LogicVision’s ScanBurst product was announced.  It will be interesting to see how long it takes for them to take it the rest of the way: an SoC-level planning tool, maybe? (Let’s put BIST here, compression there, plop down this scanned IP-core here, and then tie it all up with BIST, for system-level use!)

Slaying the unruly AMS-test dragon – For me, one of the more interesting facets of LogicVisions BIST products are the  Analog/Mixed-Signal (AMS) BIST IP/tools:  ETSerdes and ETPLL.   Mentor had no tools in this space, and  Aldrich claims they see much interest in these products as their customers struggle with high speed I/O and analog test.  He admits that Mentor is new to this space, and plans to continue putting effort into these tools.

Attempts at automating AMS-test have come and gone.   Despite ‘Whatever happened to‘ questions out there, it hasn’t been completely dormant.  For example, read a guest post on Paul McLellan’s ‘EDA Graffiti’ blog by CEO of a company called ATEEDA, who is marketing an AMS-BIST tool called LinBIST.

Then there is the subject of post-silicon tools: Mentor’s YieldAssist and LogicVision’s Silicon Insight.  According to Aldrich, there is plenty of synergy here.  YieldAssist has focused mostly on data-gathering for diagnosis and yield enhancement, using ATPG data, of course.  s Silicon Insight, likewise, leverages BIST infrastructure for interactive debug.  There seems to be plenty of opportunity here for interactive debug of ATPG vectors, as well as applying BIST failure data to yield improvement.

ITC season is upon us, and I’m sure there will be more detail in the PR-mill.  Beyond a challenging task of marrying ATPG and BIST technologies, it’s also interesting to note that this approach even more highly differentiates Mentor and  Synopsys with respect to DFT.   Mentor is attacking the higly integrated SoC environment, whereas Synopsys is specifically trying to address the small geometry problems.

Comments?

So why do I say you missed almost nothing?  Because, like no other year prior, DAC was covered, in real-time, by journalists and bloggers alike, in blogs and on Twitter.  It will forever be known as the year that social media took DAC by storm.  Me? I was on vacation, and pretty much off-the-grid for the week.  When I sat down at the computer last night, I was greeted by hundreds of tweets, and many blog posts from the journos and bloggers that were there.

So how do you find all this?  Well, for the as-it-happened commentary (which is still on-going as I write this), you might want to go directly to Twitter, and type #46DAC in the search box.  This will keep you busy for some time.  The #46DAC hashtag was the ‘1st EDA standard ever created in just 10 days‘, thanks to the efforts of Karen Bartlson of Synopsys (who was crowned ‘Top EDA Blogger‘), and if you used it, your tweets appeared on the ‘Twitter-Tower’, real-time, on the exhibition floor.  And if you think that Twitter is the domain of the blogger types, I’d have to say that I was most impressed by journalist Peggy Aycinena’s twitter feed.

Then you might want to go peruse the reporting of the various bloggers that were present: Daniel Payne, in particular, had a slew of posts on the things he saw this year.  JL Gray of Cool Verification posted what seems to be a record (for him) 4 posts in one week.  John Busco, an engineer-blogger, posted a few times as well.  Add corporate bloggers from Cadence, Mentor and Synopsys – there is a wealth of viewpoints.  Journalists Lou Covey and Brian Fuller were also in the mix.  There was even an ‘official’ DAC blog!

Leading up to DAC, there was a bit of the same old weeping and gnashing of teeth (maybe not literally, but I’ve always loved the phrase) over journalist vs. indie blogger vs. corporate blogger, press credentials, etc…  Some of it was inevitably re-visited during sessions held in ‘Conversation Central‘, a cozy little space carved out of the Synopsys booth, again, driven by Karen Bartleson.  John Cooley, the acknowledged godfather of EDA blogging (even though he’s never ‘blogged’, as we know it today), apparently sees no value whatsoever in any of this, as reported by Karen in her twitterfeed during one of those sessions:

John Cooley says Twitter, Linkedin, Facebook don’t have an ROI for esnug and DeepChip. They’re a free-for-all. #46DAC4:09 PM Jul 28th

@glenihan John Cooley recommends posting on DeepChip instead of blogging for joe engineers (not corporate bloggers). #46DAC3:58 PM Jul 28th

John Cooley strongly recommends against blogging. Most blogs die quickly, people don’t have the personality, doesn’t pay off. #46DAC3:38 PM Jul 28th

I’m guessing Mr. Personality himself will be saying that until he starts doing it himself.  The same general sentiments were echoed during the week by a couple of journalists – basically that engineers are crappy communicators, so all this social media activity is pretty much lost on the audience that matters: the engineers.  I don’t completely disagree, but my take on this will be the subject of a future blog post.

If you’re an EDA industry watcher – there was plenty of activity to keep track of.  But I have to ask – was there not a technical program at DAC this year?  Maybe I watch the wrong blogs, but I’ve seen precious little about any of the technical program so far in any of the content.  I’ll keep on looking.

And, by the way, next year, DAC will be in my neighborhood: Anaheim!  I hope to meet many of my ’social media’ compatriots there!

Cheers,