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NOR gate is a universal gate which can implement any kind of Boolean logic function.
NOR gate is commercially used because it allows the access to wired logic,which is a logic function formed by connecting the outputs of NOR gates. Wired logic does not consist of a physical gate but the wires behave as a logic function. The other reason for commercial usage of NOR gate is that it can be easily fabricated and has a low fabrication cost. It also shrinks the schematic by decreasing the number of gates, which results in small size, fast speed, and Low power consumption.
As we know a typical Boolean function implementation consists of AND Gate, OR Gate and NOT Gate. To implement a whole Boolean function using NOR gate first, we need to implement these gates using NOR gates.
NOT or Inverter gate complements its input into output. A single input NOR gate also inverts its input. Single input NOR gate means that its inputs are combined into single input line as shown in the figure given below.
OR logic gate function is complement ( Invert ) of NOR function. So in order to implement OR gate we need two NOR gates. The second NOR gate will be used for complementing the output of the first NOR gate. Schematic of OR gate using NAND gate is given below.
To acquire AND logic gate operation we need three NOR gates. Two NOR gate are used as Inverter to invert the input to the 3^{rd} NOR gate.
According to De Morgan’s law
( A’ + B’ ) = A.B
Schematic of AND gate implementation using NOR gate is given below.
To convert a Boolean circuit with AND, OR and NOT gates into NOR gates, we need to convert the logic function schematic into NOR equivalent schematic. A NOR equivalent schematic contains NOR equivalent gates for every logic gate. These gates need alternate logic symbols. We will discuss these alternate NOR gates one by one.
OR-INVERT symbol consists of OR gate symbol with a bubble at the output, which complements the output of OR into NOR.
INVERT-AND mean INVERTER connected to the input of AND gate. According to DE Morgan’s law, Inverting the inputs of the AND gate convert it into NOR gate.
( A’.B’.C’ ) = ( A + B + C )’
INVERT-AND symbol is given below.
INVERT-AND symbol consists of AND gate with a bubble at each input for complementation (inversion).
These symbols are used for converting a circuit into NOR gates. When both of these symbols are used in a schematic, it is said to be in mixed notation.
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Two-level implementation means that any path from input to output contains maximum two gates hence the name two-level for the two levels of gates.
Implementing Two-Level logic using NOR gate requires the Boolean expression to be in Product of Sum (POS) form.
In Product of Sum form, 1^{st} level of the gate is OR gate and 2^{nd} level of the gate is AND gate.
To implement a Boolean function using NOR gate, there are basically three step;
First, you need to have a simplified Product of Sum expression for the function you need to implement.
Simplified Product of Sum expression can be made using Karnaugh Map (K-map) by combining the ‘0’s and then inverting the output function.
Suppose we have simplified POS expression.
F = ( A + B ) ( C + D )
Draw its schematic using AND-OR NOT gates as shown in the figure given below.
Next step is to draw the above-mentioned schematic using OR-Invert and Invert-AND gates. OR-Invert should replace OR gates and invert-AND replaces AND gates. This schematic is said to be in mixed notation and its schematic is given below.
A bubble means complement. Two bubbles along a line mean double complementation and they cancel each other. However, a single bubble along a line should be compensated by inserting an Inverter in that line or if it is an input line then you can also feed a complemented input if available.
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The last step is to redraw the whole schematic replacing OR-Invert and Invert-AND gate symbol by NOR gate symbol because OR-Invert and Invert-AND are equivalent to NOR gate. The final schematic is shown in the figure given below.
Example of having single bubble in a line:
F = ( A + B ) ( B + C ) D
This function is in simplified Product of Sum form. First, we need to draw its OR-AND schematic.
Now we convert the above-given schematic into mixed notation by converting OR gate into OR-INVERT and AND gate into INVERT-AND.
Input line D to the input of AND gate has a single bubble.To compensate this bubble we need to either insert an inverter in this line or complement the input D if available.
Now replace every OR-Invert and Invert-AND with NOR gate as shown in the figure given below.
Schematic having more than two levels of gates is known as a multi-level schematic.
We can implement multi-level POS expression using NOR gate. The conversion of multi-level expression into NOR gate has the same method as two-level implementation.
The multi-level expression can be converted into two-level expression but for the sake of realization, we will implement a multi-level expression.
Suppose a 4-level function:
F = ( A + B ( C + D )) ( B + D’ )
First, we will draw its schematic using AND, OR, NOT gates.
Notice the OR-AND pattern like two-level implementation. It can be easily converted since the bubble cancels each other.
Now we will convert it into mixed notation for NOR.
The two bubbles along a single line cancel each other. However, there is a single bubble at the 2^{nd} level gate’s input. so we will complement the input B to compensate the bubble.
Now redraw the whole schematic replacing OR-Invert and Invert-AND with NOR gate symbol as shown in the figure below.
A 3-level implementation using NOR gate’s Example is given below;
F = ( AB’ + CD’ ) ( A’ + B )
First, we will draw its schematic using AND,OR,NOT gates as given in the figure below.
Now we will convert it into mixed notation for NOR.
The single bubbles at the input line of all first level gates need an inverter or the inputs to be complimented. The two bubbles along the same line cancel each other.
Now that all the bubbles have been accounted for, we will redraw this schematic by replacing OR-Invert and Invert-AND with NOR gates as shown in the figure below.
NAND Gate is a universal logic gate which means any Boolean logic can be implemented using NAND gate including individual logic gates. In other words, any kind of Boolean function can be implemented using only NAND gates.
NAND gate is commercially used because it allows the access to wired logic which is a logic function formed by connecting the outputs of NAND gates. Wired logic does not consist of a physical gate but the wires behave as a logic function. The other reason for commercial usage of NAND gate is that it can be easily fabricated and has a low fabrication cost. It also shrinks the schematic by decreasing the number of gates, which results in small size and as mall delay, fast speed and Low power consumption.
As we know a typical Boolean function implementation consists of AND, OR and NOT gates. To implement a whole Boolean function using NAND gate first, we need to convert these gates into NAND gate.
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NOT gate ( Inverter ) complements its input into the output. A single input NAND gate also complements it input into output. Single input NAND gate means that the inputs of 2-input NAND gates are combined together into a single input line as shown in the figure given below.
NAND gate is negative AND gate. In fact, NAND and AND are inverse to each other. To achieve AND gate operation need two NAND gates. The second NAND gate will be used as an Inverter to complement (Invert) the output of first NAND gate into AND gate.
OR gate operation needs three NAND gates. Two NAND gates are used as inverter at the input of the 3^{rd} NAND gate. The two NAND gates invert the input and then the inverted input is fed to the 3^{rd} NAND gate, which results in OR function as shown in figure below;
(A’.B’) = A+B DE Morgan’s law
To convert a Boolean function from NOT, AND, OR gates to NAND gates, we need to convert the schematic into NAND equivalent schematic. NAND equivalent schematic contains NAND equivalent gates. These equivalent gates need alternative symbols to represent; these alternative gates are discussed below;
Binary Multiplier – Types & Binary Multiplication Calculator
AND-INVERT means INVERTER (NOT gate) connected to the output of AND gate. As we have discussed before that inverting the output of an AND gate makes it a NAND gate. AND-INVERT symbol represent NAND gate and it is given below;
AND-INVERT symbol consists of AND gate followed by small bubble for complementing the output.
INVERT-OR means Inverter (NOT gate) connected to the input of OR gate. According to DE Morgan’s law, Inverting the inputs to the OR gate makes it a NAND gate. So INVERT-OR symbol represents NAND gate and it is given in the figure below.
INVERT-OR symbol consists of OR gate with small circles (bubble) at the input for inversion.
These both symbols are used for converting a schematic into NAND gates. When both of these symbols are used in a schematic the circuit is known to be in mixed notation.
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Two-level implementation means that any path from input to output contains maximum two gates hence the name two-level for the two levels of gates.
Implementing a two-level schematic with NAND gates require the expression to be in Sum of Product (SOP) form. In Sum of Product form, the 1^{st} level of the gate is AND gate and the 2^{nd} level of the gate is OR gate. It can be easily converted into NAND gates. To convert any function into two-level NAND schematic there are 3 steps;
First, you need to have simplified Sum of Product (SOP) form for the Boolean function. Karnaugh map (K-map) or Boolean algebraic theorems can be used to get a Simplified SOP expression.
Suppose an SOP function F = A B + C D
This SOP function is in Simplified SOP form and its AND-OR schematic is given below.
2^{nd} step is to convert the AND-OR schematic into mixed notation. In mixed notation for NAND gate, AND gate is converted into AND-invert and OR gate is converted into INVERT-OR. Mixed notation design for the above function is given below.
Notice the bubble in a single line. A single bubble means a complement (inversion). Two bubbles on the same line mean double complementation which cancels each other. If there was a single bubble on a line then we have to insert an inverter in that line. We will discuss that in another example.
Also read:
The third step is to convert the AND-INVERT and INVERT-OR symbols into its equivalent NAND gate symbol. NAND gate schematic of above function is given below.
Example
Suppose a function F = A B + B C + D to be implemented using NAND gates
This function is in simplified Sum of Product form. First, we need to draw its AND-OR schematic.
Now we convert the above-given schematic into mixed notation by converting AND gate into AND-INVERT and OR gate into INVERT-OR.
Notice the single input D line to the OR gate. There is one bubble on this line. To compensate this bubble we need to either insert an inverter in this line or complement the input D if available. Then convert AND-INVERT and INVERT-OR symbol into NAND symbol as shown in the figure given below;
The inverter used here is also a single input NAND gate.
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Schematic having more than two levels of gates is known as a multi-level schematic.
We can implement multi-level SOP expression using NAND gate. The conversion of multi-level expression into NAND gate has the same method as two-level implementation.
The multi-level expression can be converted into two-level expression but for the sake of realization, we will implement a multi-level expression.
Suppose a multi-level function be;
F = A ( B + CD ) + BD’
This is a four-level function
First, we will draw its AND-OR schematic
Notice the AND-OR pattern. So it can be easily converted into NAND gates. Now we will convert this into mixed notation i.e. AND gate will be converted into AND-INVERT and OR will be converted into INVERT-OR as shown in the figure given below.
Remember double bubbles along a single line cancel each other, and a single bubble along a line should be compensated by inserting an inverter in that line.
Notice the 3^{rd} line of input B, there is a single bubble. To compensate this bubble, either an inverter should be added or the input B should be complimented.
Then redraw the whole schematic using all NAND gates by replacing AND-INVERT and INVERT-OR with NAND gates as shown in the figure below.
Suppose 3-level function be F = ( AB’+CD’ ) ( A’+B )
First, we will draw its AND-OR schematic as shown in the figure below;
Then we will convert it into Mixed notation by converting AND into AND-INVERT and OR into INVERT-OR.
Notice the last two lines with single bubbles. These single bubbles should be compensated by inserting inverters in those lines or complementing the inputs. The output also contains a single bubble so an inverter at the output should also be connected to compensate the bubble.
And the last step is to redraw the whole schematic using all NAND gates instead of AND-INVERT and INVERT-OR as shown in the figure given below.
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A sequential logic circuit or electronic device used for storing binary information is known as Latches. Latches are bi-stable multi-vibrator; it means that latches have 2 stable states, LOW and HIGH.
It stores the information provided to it in binary form and does not need a constant input.
The latches are level sensitive i.e. they operate on logic’s level & flip-flops are edge sensitive i.e. they operate on clock edges.
Latches change its state whenever the input logic level changes considering the latch is enabled first. However, flip-flops do not change its state with a change in input’s logic until there is an edge of controlling signal.The simplest latch is S-R Latch
Both Latches and flip flops are memory elements used to design sequential circuits used for to store information. One flip-flop and latch store 1 bit (binary digit) of data. The main difference between latches and flip-flop is that a latch changes the output whenever there is a change in input as they continuously checks the input signals and changes in it while, flip-flop is a combination of latch and clock which changes the output time adjusted by clock by checking continually the input signals and changes in it.
Below is a table shows the difference between latch and flip-flop.
Latches | Flip-Flops |
Latch is asynchronous i.e. outputs can change as soon as the inputs they find changes in input. | Flip-flop is synchronous i.e. it is edge-triggered and only changes state when a control signal at input goes from high to low or low to high. |
Latches are building blocks of sequential circuits and these can be made from logic gates. | Flip-flops are also building blocks of sequential circuits, But, these can be built from latches. |
Latch make changes in output correspondingly as it checks its input and change in input signals continuously | Flip-flop make changes in output correspondingly at times determined by clocking signal and check its input and change in input signals continuously |
Latch operation is based on the enable function input. | Flip-flop works on the basis of clock pulses. |
Latch is a level triggered, i.e. the output of the present state ad input of the next state depends on the level that is binary input 1 or 0. | Flip-flop is an edge triggered, i.e. the next state input and output changes when there is a change in clock pulse (It may be negative (-ve) or positive (+ve) clock pulse. |
Latches are level sensitive which operate with enable signal. | Flip-flops are edge sensitive. |
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There are two types of latches;
S-R stands for Set-Reset latch. There are 2 inputs S & R & 2 outputs Q & Q’ of S-R latch.
S-R latch can be made using NOR gate or NAND gate.
Schematic design of S-R latch using NOR gate is given below.
The truth table of S-R latch using NOR gates is given below:
When input S = 0, R = 1, Output Q = 0, Q̅ = 1.
This input resets the output state Q to 0.
When input S = 1, R = 0, Output Q = 1, Q̅ = 0.
This input sets the output state Q to 1.
When input S = 0, R = 0, the output state remains unchanged thus it is known as “Hold state”.
When input S = 1, R = 1, the output Q & Q̅ = 0. Which violates the condition Q & Q̅ are inverse of each other, they should not be equal.
That is why this state is known as “Invalid / prohibited input state”.
Schematic design of S-R latch using NAND is given in the figure below:
The truth table of S-R latch using NAND gate is given below:
The S-R latch using NAND gate is active low. That is why its truth table is completely opposite of S-R latch using NOR gate.
When input S = 0, R = 1, Output Q = 1, Q̅ = 0.
This input sets the output state Q to 1.
When input S = 1, R = 0, Output Q = 0, Q̅ = 1.
This input resets the output state Q to 0.
When input S = 1, R = 1, the output state remains unchanged thus it is known as “Hold state”.
When input S = 0, R = 0, the output Q & Q̅ = 0. Which violates the condition Q & Q̅ are inverse of each other, they should not be equal.
That is why this state is known as “Invalid / prohibited input state”.
Invalid or prohibited state can be avoided by converting it into any of the other 3 states.
Also read: Karnaugh Maps (K-Map), Truth Tables, Boolean Expressions & Examples
To avoid the invalid state logic, combinational circuit is connected before S-R latch to convert the invalid input into set state;
Truth table for converting “invalid input” into “set input”
According to the truth table:
S_{L }= S_{i }, R_{L }= S̅_{i }R_{i}
Schematic of S-R set dominant latch is given below:
This latch sets output when invalid state input is given to it that is why it is known as set dominant.
This latch resets upon invalid input. The invalid input is converted into reset input before feeding into the latch.
Truth table for converting “invalid input” into “reset input”
According to the truth table:
S_{L }= S_{i}R̅_{i }, R_{L }= R_{i}
Schematic of S-R reset dominant latch is given below:
This latch resets output when invalid state input is given to it, that is why it is known as reset dominant latch.
This latch holds its state when invalid / prohibited input is applied. The invalid input is converted into hold state input before the latch.
Truth table for converting “invalid input” into “Hold input”
According to the truth table:
S_{L }= S_{i}R̅_{i}, R_{L }= S_{i}R_{i}
Schematic of S-R Hold dominant latch is given below:
This latch holds its output state when invalid state input is applied to it, that is why it is known as hold dominant latch.
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Latch changes its state whenever input level changes but if we use a controlling signal to disable the inputs then the states won’t change. This control input is known as enable input.
Enable can be active low or active high.
“Active low enable input” allows the latch to process the input when it is low. When it is high, the input is disabled and the latch holds its state.
“Active high enable input”allow the latch to process the input when it is high and holds its state when enable input is low.
The schematic of gated S-R latches using NOR gate and NAND gate are given below.
Also read:
D latch stands for data latch. In S-R latch there is a restricted input condition i.e. both S, R input should not be same and either one of them should be high for set or reset. To avoid this problem, an inverter is connected with R input of S-R latch and then both inputs are combined together to form a single input D (data input).
Schematic of D-latch is given below:
When D = 1
S = 1 & R = 0, which is “set input” so Q = 1.
And when D = 0
S = 0 & R = 1, which is “reset input” so Q = 0.
Thus in D-latch Q output follows the value of D input.
Also read:
D-latch also changes its state whenever input level changes. Enable pin gives the feature of enabling & disabling the input when we don’t want it to change its state.
When the input is disabled the latch retains / hold its state.
Schematics of D-latch with enable pin are given in the figure below.
Advantages:
Disadvantages:
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Digital Logic NOT Gate – Digital Inverter Logic Gate Digital Logic OR Gate Digital Logic AND Gate Exclusive-NOR (XNOR) Digital Logic GateThe post Digital Latches – Types of Latches – SR & D Latches appeared first on Electrical Technology.
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Two level logic means that the logic design uses maximum two logic gates between input and output. This does not mean that the whole design will contain only two logic gates but the single path from input to output may contain no more than two logic gates.
For two-level logic implementation, we consider four logic gates i.e. AND Gate, OR Gate, NAND Gate, and NOR Gate. If we use one of these four gates at first level and one at the second level then we get a total of 16 combinations of two-level logic.
Each two-level combination implements different logic functions, There are two main types in these 16 combinations.
The two-level combination that degenerates into a single logic function as known as degenerate form.
There are 8 degenerate forms in those 16 combinations. Each of these degenerate forms is given below with examples.
This AND-AND gate combination is a degenerate form because the whole function results in an AND function of all the inputs.
In AND-AND combination, the first level gate is AND gate and the second level gate is also AND gate as shown in the schematic given below.
It’s Expression
(A & B) & C = A & B & C (A & B) (C & D) = A & B & C & D
The only benefit of this combination is that it can increase the number of inputs for AND gate with less number of inputs but increases the gate delay.
Also read:
OR-OR gate combination gives out Logic Function OR as output. This combination can implement OR function with multiple inputs.
Schematic of OR-OR combination is given below:
( A+ B+ ) + C = A + B + C
This Two-level combination of logic gates results in NAND function. So this combination can be used for NAND function with multiple inputs.
Its expression and schematic are given below.
( ( A . B ) C )’ = ( A . B . C )’
OR-NOR combination of gates results in NOR logic function. And this degenerate form can be used for NOR function with multiple inputs.
Its expression and schematic are given below.
( ( A + B ) + C )’ = ( A + B + C )’
When NAND-NOR combine in Two-level logic the resultant function is AND logic .its expression and schematic is given below;
(( A.B )’ + ( C.D )’)’ = (A.B.C.D)
Its graphical conversion is given below.
Figure (a) contains Schematic of NAND-NOR combination.
In figure (b), NOR gate is converted into its equivalent INVERT-AND gate.
In figure (c), the two bubbles on the same line cancel each other because a bubble means inversion and double inversion means no change. So the resulting figure contains only AND gates.
Also read:
NOR-NAND combination also results in OR function that’s why it is also a degenerate form. Its Example with schematic is given below;
( ( A + B )’ ( C + D )’)’ = ( A + B + C + D )
Graphical conversion of NOR-NAND to OR function is given below.
Figure (a) contains Schematic of NOR-NAND combination.
In figure (b), NAND gate is converted into its equivalent INVERT-OR gate.
In figure (c), the two bubbles on the same line cancel each other because a bubble means inversion and double inversion means no change. So the resulting figure contains only OR gates.
This combination also results in NAND logic function just like AND-NAND combination.
Its expression and schematic are given below.
( ( A . B )’ + ( A . B )’ ) = ( A . B . C . D ) ’
Its graphical conversion is given below.
Figure (a) contains schematic of NAND-OR combination.
In figure (b), the bubbles from the output of 1^{st} level NAND gate is moved to the input of 2^{nd} level OR gate making it INVERT-OR gate.
In figure (c), the INVERT-OR gate is replaced with NAND gate because they are equivalent. Thus the design becomes AND-NAND combination.
Also read:
This combination is same as OR-NOR combination because this combination also results in a NOR function.
Its expression and schematic are given below.
( A + B )’. ( C + D )’ = ( A + B + C + D )’
Its graphical conversion is given below.
Figure (a) contains schematic of NOR-AND combination.
In figure (b), the bubbles from the output of 1^{st} level NOR gate is moved to the input of 2^{nd} level AND gate making it INVERT-AND gate.
In figure (c), the INVERT-AND gate is replaced with NOR gate because they are equivalent. Thus the design becomes OR-NOR combination.
Those combinations of Two-level logic, which implements Sum of Product form or Product of sum form are Non-degenerate forms.
The remaining 8 of the total 16 are all non-degenerate forms which are discussed below one by one.
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In AND-OR combination the first level gate is AND gate and the second level gate is OR gate. This combination implements Sum of Product (SOP) form as shown in the figure below;
A . B + C . D
NAND is a universal gate and its NAND-NAND combination is used for implementing Sum of Product form just like AND-OR combination. The conversion of NAND-NAND from AND-OR has been briefly discussed in NAND implementation.
(( A . B )’ ( C . D )’)’ = ( A . B ) + ( C . D )
In OR-AND combination first level gate is OR gate and the Second level gate is AND gate. OR-AND combination is used for implementing the Product of Sum form.
Its schematic is given in the figure below.
( A + B ) ( C + D )
NOR is also a universal gate and its NOR-NOR combination can be used instead of OR-AND combination because it also implements Product of Sum form.
Its schematic is given below.
(( A + B )’ + ( C + D )’)’ = ( A + B ) ( C + D )
AND-NOR combination is used for implementing a compound logic known as AND-OR-INVERT (AOI). AND-NOR combination resembles AND-OR combination but there is inversion at the output of NOT gate which implements the INVERT part of AND-OR-INVERT.
The expression of AOI function is given below.
F = ( AB + C D + E )’
Its schematic is given below.
NAND-AND can also be used to implement AND-OR-INVERT (AOI) form. Its expression can be converted into AOI as given below
( AB )’ ( CD )’ = ( AB + CD )’
Schematic of AND-NOR can be converted into NAND-AND as shown in the example below.
Figure (a) is the AND-OR form of AND-OR-INVERT.
In figure (b) we replace NOR gate with its equivalent INVERT-AND gate. NOR and INVERT-AND are the same gates with different graphical symbols.
In figure (c) the bubble of the input of 2^{nd} level AND gate will move to the output of first level AND gate thus making it NAND gate. The single input will be complemented or an inverter will be inserted to compensate the bubble
OR-NAND form is used to implement a compound logic OR-AND-INVERT (OAI). OR-NAND resembles OR-AND but there is inversion at the output of NAND gate which is why it can implement OAI logic.
OAI logic function is given below.
[( A+B ) ( C + D ) E]’
Its schematic is given below.
This combination is used for implementing OAI same as OR-NAND combination.
Its expression is given below.
( A + B )’ + ( C + D )’ = [( A + B ) ( C+D )]’
The OR-NAND form can be graphically converted into NOR-OR as shown in the figure given below.
In figure (a), the given schematic is in OR-NAND form.
In figure (b), NAND gate has been replaced with its equivalent INVERT-OR gate.
In figure (c), the bubbles at the input of 2^{nd} level OR gate is moved to the output of 1^{st} level OR gate. This bubble makes it NOR gate. The single input will be either complemented or an inverter will be inserted to compensate the last bubble. In this case, I have added an inverter in the path of the last bubble.
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Common failure modes and faults of cables are:
Explanation of each fault is follow respectively.
These involve lightning, switching surges, and partial discharges.
Partial discharges may be caused by poor insulation system design or by manufacturing defects.
A mechanically induced failure can occur during installation due to use of excessive pulling tension and/or exceeding minimum bending radii.
Cable can also be damaged during construction when earth moving equipment can dig into the cable or cable duct banks such as in submarine cables.
Repeated bending and twisting during installation or in service can result in irreversible straining of conductor wires.
Thermal degradation causes the insulation of the cable to lose its physical properties and they are due to overloading beyond its design capability for extended periods and/or excessive ambient temperature conditions.
This failure mode describes where the shield ceases to perform its function.
In order for the shield to perform its function, its volume resistivity must always remain sufficiently low. However, when metallic shield is damaged or corroded its volume resistivity is impacted by temperature.
At higher temperatures, the volume resistivity of the metallic shield increases significantly (due to peak loads, unbalance currents, or circulating currents) giving rise to high voltage gradients at sharp metal edges that will lead to corona effect / discharge and arcing damage (from outside in).
Corona and arcing will lead to eventual cable insulation failure.
This is the case where metallic shield is insulated from the semiconducting tape shield because of poor contact, what can be caused by a layer of corrosion or scale buildup on the metallic shield.
Such a condition will give rise to a potential difference between the semiconducting shield and the metallic shield that will cause arcing between the two shields.
This will lead to arcing damage from the outside into semiconducting shield and insulation and eventual cable failure, being more severe if there are multiple areas of poor contact or breaks between the two shield systems.
Failures in most cases occur at the end-terminations or joints (where the factory-manufactured insulation gets disturbed).
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Most specific causes of power cable failures are the following:
Some of the major causes for cable failures are:
Related Article: All About Electrical Protection Systems, Devices And Units
The ideal way of protecting any piece of power system equipment is to compare the current entering that piece of equipment, with the current leaving it.
Under normal healthy conditions the two are equal. If the two currents are not equal, then a fault must exist.
This is done through differential protection (87) that was discussed at Section 4 (Overhead Lines Protection) and that will be also discussed at Section 6 (Transformer Protection).
It is not economic or practical to provide a communication channel between the ends of a feeder to enable the currents entering and leaving the feeder to be compared.
For this reason this type of protection is not commonly used on LV and MV cable feeders and is used by some electric transmission companies in HV cables, mostly for voltages above 123 kV.
In this situation differential protection is used as main protection and overcurrent protection is used as back-up protection.
To define the type of overcurrent protections for cable feeders is necessary to look first at the network configuration.
MV distribution networks may have several types of configurations:
A combination of types above referred is used, and the most common configurations are radial and double-end feed with NO point.
LV distribution networks are usually radial.
MV and LV internal and private networks of plants and buildings are commonly radial, but in large plants a double-end feed with NO point may be observed in MV networks.
LV cable feeders may be protected against overcurrents by fuses (a common solution for distribution networks in Europe and North America) or by thermal magnetic devices within circuit breakers.
MV cable feeders, namely in public distribution networks in Europe and North America, may be protected by fuses against overcurrents.
With radial feeders and double-end feed with NO point there is only one possible point of supply, and the flow of fault current is in one direction only. Overcurrent protection can therefore be used to provide adequate protection.
Common relays used for this protection are instantaneous phase overcurrent (50), instantaneous earth overcurrent (50N), time delay phase overcurrent (51) and time delay earth overcurrent (51N).
The current entering the feeder at the circuit breaker is measured by means of a CT, as shown in Figure 1.
Figure 1 – Overcurrent protection wiring diagram
Let us consider the situation of a cable feeder between stations A and B, being B located downstream of A.
The overcurrent protection at the supply end of the feeder at station A must operate for all faults on the feeder, but should not operate for faults beyond station B.
If we first consider an instantaneous overcurrent relay, then setting is determined by the magnitude of the fault current at the end of the feeder at station B that is the lower fault current on the cable.
Ideally the relay will be set for that fault current and it should not operate for any fault beyond station B.
However, in practice it is not possible to be so precise for the following reasons:
One solution to solve this problem is to set the instantaneous overcurrent relay to overreach the remote terminal and introduce a definite time delay in tripping the circuit breaker.
This time delay will allow the overcurrent relays at the remote station to operate to clear faults beyond bus B before the time delayed tripping can take place at the supply station A.
This type of time delay has the major disadvantage that all faults will be slow cleared even very close-in faults, which have the highest magnitude of fault current.
This time-delayed clearing of high fault currents is usually unacceptable, and the most common feeder protection scheme, which overcomes the problem, utilizes an inverse time overcurrent relay (51) in conjunction with the instantaneous overcurrent relay (50).
In order to ensure that the instantaneous overcurrent relay will not unnecessarily operate for faults at the remote station, (which should be cleared by the overcurrent protection or fuses at that station) then it must be set to protect only part of the feeder. A safe maximum for most types of relay is 80% of the feeder length.
The limit is determined by the characteristics of the relay used, and the length of the feeder. If the feeder is long a high percentage of the line can be protected; but with short lines it may be less; and with very short lines it may not be possible to apply instantaneous overcurrent protection.
This type of protection is known as High-Set Instantaneous (HS) overcurrent protection.
With such a relay set to detect faults on 80% of the feeder, the remaining 20% is left unprotected. This is, of course, not acceptable. To provide protection for the last 20% of the feeder a time-graded, or inverse definite minimum time relay can be used.
The inverse definite minimum time” relay has a characteristic “time-current” curve as shown in Figure 2.
Figure 2 – Characteristic “time-current” curve of inverse definite minimum time relay
Using this characteristic “time-curve” it shall be defined the co-ordination of upstream and downstream protections, a topic that was discussed at Section 3.3.
Now let us look at a typical utility feeder which supplies customer transformers at many different points along its length.
The same High-Set Instantaneous Overcurrent and Inverse Timed Overcurrent relays are used, and the HS relay must be set such that it does not operate for faults beyond the first tap.
HS relay will therefore be set to operate for faults up to 80% of the distance to the first tap.
The criteria used for setting the Inverse-Timed Overcurrent relay are:
This type of protection scheme will provide adequate protection for feeders.
However, there are some disadvantages with this arrangement, particularly on long overhead feeders. The main disadvantage is that most faults will be slow in clearing because the inverse time overcurrent relay must operate. This slow fault clearing is usually disturbing to customers on the affected feeder.
Related Article: Power Transformers Maintenance, Diagnostic & Monitoring
The criteria used for setting the High-set Instantaneous Overcurrent Relay are:
In networks with a ringed type configuration fault current can flow in either direction, and the feeder overcurrent protection at the supply station may require directional supervision on those feeders that in normal situation have only one current direction.
A directional relay – directional phase overcurrent (67) and directional earth overcurrent (67N) – must be used when the phase-to-earth short-circuit current (I”_{K}_{1}) is lower than the maximum residual capacitive current (See note below)^{ }(I_{CM}). in the same situation – I_{CM }≥ I”_{K1}.
Phase-to-earth short-circuit current depends on the neutral grounding system of the network.
Directional overcurrent protection comprises overcurrent relay and power directional relay.
The power directional relay is not used to measure power, but is arranged to respond to the direction of power flow.
The protection relay is connected to CT and VT, as shown in Figure 3.
Figure 3 – Directional overcurrent protection wiring diagram
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The most common causes of faults in overhead lines are:
Related Article: Power Transformer Protection & Faults
LV overhead lines are protected against overcurrents using fuses or circuit breakers.
Protection of MV overhead lines is usually achieved by overcurrent relays (50; 50N; 51; 51N; 67; 67N) connected to CT.
Time-graded overcurrent protection cannot be successfully applied to HV overhead transmission lines because there are usually many interconnected sources of fault currents which may be limited by fault current limiter.
The requirements of protection schemes for HV overhead transmission lines are:
To accomplish these requirements common protections devices used in HV overhead lines are:
Differential protection is mainly used on short overhead lines and distance protection on long overhead lines.
The distinction between short and long overhead lines is based on a comparison between the inductance and the resistance and capacitance of the overhead line.
When both resistance and capacitance are negligible when compared with the inductance, the over head line is considered short.
This comparison is usually done using the π diagram of the overhead line.
Voltage level, physical construction of the transmission line, type of and size of conductors and spacing of conductors determines the impedance of the line, and the physical response to short circuit conditions, as well as line charging current.
In addition, the number of line terminals determines load and fault current flow, which must be accounted for by the protection system.
Parallel lines also impact relaying, as mutual coupling influences the ground current measured by protective relays.
The presence of tapped transformers on a line, or reactive compensation devices such as series capacitor banks or shunt reactors, also influences the choice of protection system and the protection device settings.
Due to this reasons a detail study of the overhead line is required to choose the most suitable protection relays to be used.
However it is usual to consider a short line to have a length up to 80-100 km, depending on the voltage level and the characteristics of the network.
About 90% of overhead line faults are transient and faults may be:
With such faults, single pole-trip may be required and the line can be restored to service immediately after the breakers have tripped.
Hence, single pole trip and auto-reclose schemes are normally used in circuit breakers associated to overhead transmission lines (usually V ≥ 220 kV).
If the fault current is interrupted by the circuit breakers, the flashover arc is immediately extinguished and the ionized air dissipates.
Auto-reclose will normally be successful after a delay of only a few cycles.
When performing energized works automatic reclosing devices on lines being worked on must be set to non-reclosing.
Circuit breakers must be design specifically for these performances and be exempted from inconstancy of poles until a definitive trip order is given.
The fundamental principle of differential protection (Kirchhoff currents’ law) is applied to the transmission line by comparing the current entering the line at one terminal, with the current leaving line at the other terminal.
The line differential relays at each end of the transmission line compare data on the line current via a fiber optic communications link, usually through OPGW (Optical Power Ground Wire) cable, used for lighting design protection of the overhead line, wich has in the interior fiber optic cables.
Figure 1 shows the diagram of the differential protection.
Figure 1 – Overhead line differential protection diagram
Another protective relaying system for HV transmission lines, based on differential protection principle that is nowadays in use even for long lines is phase comparison protection.
This system uses the principle of comparing the phase angle between the currents at the two ends of the protected line. During external faults the current entering the line is of the same relative phase angle as the current leaving the line, and the phase comparison relays at each terminal measure little or no phase angle difference.
The protection therefore stabilizes and no tripping occurs. For an internal fault the current will enter the line at both ends, and the phase comparison relays detect this phase angle difference. The relay then operates to clear the fault.
With phase comparison schemes starting relays are used to start the phase comparison process whenever a fault condition is detected. These starting relays must operate for both internal and external faults.
A reliable communication channel is required for phase comparison protection and fiber optic within OPGW cables have been used.
Figure 2 shows the the single line diagram of Merz Price voltage balance system for the protection of three-phase line.
Figure 2 – Phase comparison protection diagram
Identical CT are placed in each phase at both ends of the line. The pair of CT in each end is connected in series association with a relay in such a way that under normal conditions, their secondary voltages are equal and in opposition, i.e., they balance each other.
Under healthy conditions, current entering the line at one-end is equal to that leaving it at the other end.
Therefore equal and opposite voltages are induced in the secondaries of the CT at the two ends of the line. The result is that no current flows through the relays.
When a fault occurs at point F on the line as shown in Figure 2 it will cause a greater current to flow through CT_{1} than through CT_{2}.
Consequently, their secondary voltages become unequal and circulating current flows through the pilot wires and relays. The circuit breakers at both ends of the line will trip out and the faulty line will be isolated.
A distance relay measures the impedance of a line using the voltage and the current applied to the relay.
When a fault occurs on a line, the current rises significantly and the voltage collapses significantly.
Since the impedance of a transmission line is proportional to its length, for distance measurement it is appropriate to use a relay capable of measuring the impedance of a line up to a predetermined point (the reach point).
The distance relay (also known as impedance relay) determines the impedance by the equation Z = U/I (Ohm law).
Such a relay is designed to operate only for faults occurring between the relay location and the selected reach point, thus giving discrimination for faults that may occur in different line sections.
The apparent impedance so calculated is compared with the reach point impedance.
If the measured impedance is less than the reach point impedance, it is assumed that a fault exists on the line between the relay and the reach point.
If the impedance is within the reach setting of the relay, it will operate.
Distance protections are installed at both ends of the line and a communication is established between them, as shown in Figure 3.
Figure 3 – Overhead line distance protection diagram
Distance relay performance is defined in terms of reach accuracy and operating time.
Reach accuracy is a comparison of the actual ohmic reach of the relay under practical conditions with the relay setting value in ohms and particularly depends on the level of voltage presented to the relay under fault conditions.
Impedance measuring techniques employed in particular relay designs also have an impact.
Operating times can vary with fault current, with fault position relative to the relay setting, and with the point on the voltage wave at which the fault occurs.
Depending on the measuring techniques employed in a particular relay design, measuring signal transient errors, such as those produced by Capacitor VT (CVT) or saturating CT, can also adversely delay relay operation for faults close to the reach point.
Characteristics of distance relays – protection shape – are defined as a graphic function of the resistance (R) and the impedance (X) of the line – R/X or admittance diagram.
Typical shapes are circular (mho characteristic) and quadrilateral, which are represented in Figures 10 and 11.
Figure 5 – Quadrilateral characteristic
The mho impedance element is generally known as such because its characteristic is a straight line on an admittance diagram.
Polygonal impedance characteristics are highly flexible in terms of fault impedance coverage for both phase and earth faults and for this reason, nowadays most distance relays offer this form of characteristic.
Distance relays may have up to five zones, some set to measure in the reverse direction (used as bus bar backup protection). To each zone corresponds an actuation time of the relay.
Distance relays are used in both sides of the line and each one of them sees the fault on different periods of time, depending of the distant of the faulty point (F) to each end of the line.
Considering an overhead line connecting Substations A and B, F will be seen first by the distance relay installed in the substation closer to F and the respective circuit breaker will trip first than the circuit breaker placed at the other substation.
To avoid that short-circuit fault continue to be feed by the other side of the line until the respective distance protection will actuate a communication link between protection relays, usually by optic fiber within OPGW cables, is required to simultaneous trip both circuit breaker.
It is not practical to set an impedance relay to measure exactly the impedance of the line up to the breaker at the remote end. This is because of errors and inaccuracies in such things as CT, VT, relays, calculation of line impedance, etc.
Because of this we set the relay to measure, or reach, some impedance less than the full length of the line (setting zone 1 of up to 85% may be safe and the 15-20% safety margin ensures that there is no risk of the zone 1 protection over-reaching the protected line due to those errors and inaccuracies; otherwise there would be a loss of discrimination with fast operating protection on the following line section).
Careful selection of the reach settings and tripping times for the various zones of measurement enables correct co-ordination between distance relays on a power system.
As analysed in Section 4.2 most of faults on overhead lines are asymmetric and transient.
The auto-reclose is performed through a relay (auto-recloser relay) initiated by the protection devices of the overhead line, like the one shown in Figure 6.
Figure 6 – Auto-recloser relay
There are various reasons for reclosing a line. It is imperative to have input and guidance from planning and operational groups to determine the appropriate reclosing practices for a particular Utility and Region. The following are some of the major considerations for transmission level reclosing:
The most important parameters of an auto-reclose scheme are:
These parameters are influenced by:
Reclosing can be either unsupervised high speed or time-delayed, supervised by voltage/synchronization elements. The decision as to which to apply must weigh the benefit and consequences of each to determine the acceptability of the risk in the particular application.
Reclosing on non-critical lines, as previously determined by the planning groups, may vary, and depending on protection philosophy and equipment applied.
Practices vary among utilities; reclosing practices also vary depending on voltage levels and the type of line considered.
Some companies auto-reclose for all faults and only block on loss of communications. Some utilities reclose if the speed of clearing is fast enough, independent of the fault configuration.
System stability is a determining factor on whether high speed auto-reclose is attempted.
The problems involved are dependent on whether the transmission system is weak or strong.
With a weak system, loss of a transmission link may lead quickly to an excessive phase angle across the circuit breaker used for re-closure, thus preventing a successful re-closure.
In a relatively strong system, the rate of change of phase angle will be slow, so that delayed auto-reclose can be successfully applied.
This includes concerns with reclosing too slowly and concerns that the system will enter instability if reclosed back onto a faulted line.
In situations where reclosing onto a faulted line does not impact the stability of the system, multi-trip reclose attempts may be possible. In this case, the restoration of the line is required more for load continuity to the customers.
In Europe is usual to use auto-recloser schemes only in HV networks, although in some countries, like the United States and Brazil, these schemes are also used in MV networks.
The most common type of power system fault is the flashover of insulators on overhead transmission lines, due to lightning.
The number of faults per year is proportional to the length, and is approximately inversely proportional to the voltage level.
Indicative figures of faults are:
For overhead lines up to 49.5 kV the figures are proportionally higher.
Table 1 shows the statistics of success of auto-reclosing faults clearance:
Table 1 – Statistic success of faults clearance
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A digital or binary decoder is a digital combinational logic circuit which can convert one form of digital code into another form.
BCD to 7-segment display decoder is a special decoder which can convert binary coded decimals into another form which can be easily displayed through a 7-segment display.
BCD stands for binary coded decimal. It is a digital numbering system in which we can represent each decimal number using 4 bits of binary numbers.
There are 10 digits in the decimal system. To represent all 10 digits we need 10 combinations of 4 binary bits.
A digital system like a computer can understand and easily read a large number in binary format. However, a human cannot read large binary numbers. To solve this problem we need to display it as a decimal digit using 7-segment display.
It is a digital device that can be used for displaying decimal number, alphabets, and characters.
7-Segment display contains 7 LED segments arranged in a shape given in figure above. Generally, there are 8 input pins in a 7-Segment display. 7 input pins for each of the 7 LEDs and one pin for the common terminal.
There are two types of 7-Segment displays.
In such type of 7-segment display, all the cathodes of the 7 LEDs are connected together to form a common terminal. It should be connected to GND or logic ‘0’ during its operation.
To illuminate any LED of the display, you need to supply logic ‘1’ to its corresponding input pin.
The type of 7-Segment display in which all the anode terminals of 7 LEDs are connected together to form common anode terminal. This terminal should be connected with Vcc or logic ‘1’ during its operation.
To illuminate any of the LED segments we need to provide logic ‘0’ to it.
7 LED segments of the display and their pins are “a”, “b”, “c”, “d”, “e”, “f” & “g” as shown in the figure given below. Each of the pins will illuminate the specific segment only.
We assume common cathode LED segment as our example.
Suppose we want to display digit ‘0’, in order to display 0, we need to turn on “a”, “b”, “c”, “d”, “e”, “f”. & turn-off the “g”. which would look like the figure given below.
Display combination of decimal numbers is given below.
Digit 1: to display the digit 1 we need to turn on the segments b, c. and turn off the LED segments a, d, e, f, and g. This configuration will result in the display as shown in the figure below.
Related article: MUX – Digital Multiplexer | Types, Construction & Applications
Digit 2: to display the digit 2 we need to turn on the segments a, b, d, e, g. and turn off the LED segments c, f. This configuration will result in the display as shown in the figure below.
Digit 3: to display the digit 3 we need to turn on the segments a, b, c, d, g. and turn off the LED segments e, f. This configuration will result in the display as shown in the figure below.
Digit 4: to display the digit 4 we need to turn on the segments b, c, f, g. and turn off the LED segments a, d, e. This configuration will result in the display as shown in the figure below.
Digit 5: to display the digit 5 we need to turn on the segments a, c, d, f, g. and turn off the LED segments b, e. This configuration will result in the display as shown in the figure below.
Digit 6: to display the digit 6 we need to turn on the segments a, c, d, e, f, g. and turn off the LED segments b. This configuration will result in the display as shown in the figure below.
Digit 7: to display the digit 7 we need to turn on the segments a, b, c. and turn off the LED segments d, e, f, g. This configuration will result in the display as shown in the figure below.
Digit 8: to display the digit 8 we need to turn on the segments a, b, c, d, e, g only. This configuration will result in the display as shown in the figure below.
Digit 9: to display the digit 2 we need to turn on the segments a, b, c, d, f, g. and turn off the LED segments e. This configuration will result in the display as shown in the figure below.
To display these digits using binary numbers we need to decode these binary numbers into the combination used for each pattern or display using Decoder.
Related post: Binary Adder & Subtractor – Construction, Types & Applications
Assume common cathode 7-Segment display. Suppose the binary input ABCD to the decoder and output a, b, c, d, e, f, & g for the display.
For other combinations of input, the output is “don’t care X” as there are no more digits to display. We will derive the expression for each output using Karnaugh map (K-MAP).
For output a:
For output b:
For output c:
For output d:
For output e:
For output f:
For output g:
Also read:
We have derived an expression for each output now we need to make its schematic using logic gates as shown in the figure given below. Fig: Schematic of BCD to 7-Segment Display Decoder.
7447 BCD to 7-Segment Decoder
The commonly used IC for BCD to 7-segment decoding is 7447. The pin configuration of 7447 is given in the figure below.
Also read:
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A binary multiplier is a combinational logic circuit or digital device used for multiplying two binary numbers. The two numbers are more specifically known as multiplicand and multiplier and the result is known as a product.
The multiplicand & multiplier can be of various bit size. The product’s bit size depends on the bit size of the multiplicand & multiplier. The bit size of the product is equal to the sum of the bit size of multiplier & multiplicand.
Binary multiplication method is same as decimal multiplication. Binary multiplication of more than 1-bit numbers contains 2 steps. The 1^{st} step is single bit-wise multiplication known as partial product and the 2^{nd} step is adding all partial products into a single product.
Partial products or single bit products can be obtained by using AND gates. However, to add these partial products we need full adders & half adders.
The schematic design of a digital multiplier differs with bit size. The design becomes complex with the increase in bit size of the multiplier.
Also read:
lets discuss one by one as follow:
This multiplier can multiply two numbers having bit size = 2 i.e. the multiplier and multiplicand can be of 2 bits. The product bit size will be the sum of the bit size of the input i.e. 2+2=4. The maximum range of its output is 3 x 3 = 9. So we can accommodate decimal 9 in 4 bits. It is another way of finding the bit size of the product.
Suppose multiplicand A_{1 }A_{0 }& multiplier B_{1 }B_{0 }& P_{3 }P_{2 }P_{1} P_{0 }as a product of the 2×2 multiplier.
First, multiplicand A_{1}A_{0} is multiplied with LSB B_{0 }of the multiplier to obtain the partial product. This is obtained using AND gates. Then the same multiplicand is multiplied (AND) with the 2^{nd} LSB to get the 2^{nd} partial product. The multiplicand is multiplied with each bit of the multiplier (from LSB to MSB) to obtain partial products.
The number of partial products is equal to the number of bit size of the multiplier. In 2×2 multiplier, multiplier size is 2 bits so we get 2 partial products.
Now we need to add these partial products. There are two ways of adding;
Also read:
if we use 2-bit full adder all we have to do is to know which term should be added.
The partial product of LSBs of inputs is the LSB of the product. So it should remain untouched.
The other terms of each partial product should be considered and added using 2-bit full adder.
Construction and design schematic of 2×2 bit multiplier is given in the figure below;
The single bit from LSB partial product, 2 bits from the Sum & a carry bit makes the 4 bits of the products.
Truth Table for 2 Bit Multiplier
Multiplier Bits | Multiple of Multiplicand | ||
Yi+1 | Y1 | Multiples | Implementation |
0 | 0 | 0 | 0 |
0 | 1 | 1 | x |
1 | 0 | 2 | Shift left X by 1 |
1 | 1 | 3 | (Shift left X by 1) + X |
Single bit adders can be half adder & full adder. The difference between half adder & full adder is that half adder can only add 2 numbers and full adder can add 3 numbers including the carry in from previous addition.
However, in this condition, we only need half adder because the numbers to be added are only 2.
Schematic of 2×2 bit multiplier using single bit adder is given in the figure below.
This multiplier can multiply two numbers having a maximum bit size of 3 bits. The bit size of the product will be 6. The maximum range of its product is 7 x 7 = 49. It can be accommodated in 6 bits which is the size of its output product.
Suppose multiplicand A_{2 }A_{1 }A_{0 }& multiplier B_{2 }B_{1 }B_{0 }& product as P_{5 }P_{4 }P_{3 }P_{2 }P_{1 }P_{0.}
There are 3 partial products in this multiplication because there is a 3-bit multiplier. These 3 partial products will be added using any of the two methods;
This method is easy compared to the other method. We only have to use two 3-bit full adders to add these 3 partial products.
The LSB of the first partial product should not be touched. It will flow out as LSB of Product.
The first two partial products should be added together using 3-bit full adder. Then the sum of that adder should be added to the third partial product using another full adder.
While adding these partial products, the LSB of the sum of each adder should be routed directly as output and the remaining 3 bits of the sum should be added to the next partial product.
The schematic of 3×3 multiplier using 3-bit full adder is given below;
We need 9 AND gate for partial products and 3 Half adders & 3 full adders.
The schematic of 3×3 multiplier using single-bit adder is given below;
As you can see, each term is added to each other & the carry bits are sent to the next adders on the left side.
This multiplier can multiply a binary number of 4-bit size & gives a product of 8-bit size because the bit size of the product is equal to the sum of bit size of multiplier and multiplicand. The maximum number it can calculate us 15 x 15 = 225. You can also evaluate the number of bits from the maximum output range.
Suppose multiplicand A_{3 }A_{2 }A_{1 }A_{0 }& multiplier B_{3 }B_{2 }B_{1 }B_{0 }& product as P_{7 }P_{6 }P_{5 }P_{4 }P_{3 }P_{2 }P_{1 }P_{0 }for 4×4 multiplier.
In 4×4 multiplier, there are 4 partial products and we need to add these partial products to get the product of multiplier.
They can be added using 4-bit full adders or single bit adders (half-adder & full-adder). The design using Single bit adders is very complicated compared to using 4-bit full adders.
The implementation of 4×4 multiplier using 4-bit full adders is same as implementing a 3×3 multiplier.
Schematic of 4×4 bit multiplier using 4-bit full adders is given below.
The LSB of the first partial product is the LSB of product, so it will flow out directly to the output. The LSB of the sum of each adder is taken as a bit of product and the rest of the sum bits are added with the next partial products.
Below is a Binary Multiplication Calculator which performs two main and related functions i.e. it will show the result for binary multiplication in binary as well as equivalent decimal. For binary multiplication, you have to enter the values in binary format (i.e. 1011010) in both input fields. Click on calculate to show the result and binary multiplication in binary and decimal as well.
Binary Number Multiplication (Binary Multiplier) calculator
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In our previous post, we have already discussed about electrical protection Systems, devices and units. Today, we will discuss about different types of transformer protection and faults in details.
Transformers are vital equipment in transmission and distribution network and so the protection against internal and external faults is a very important factor in the design of those networks.
Transformers faults may occur:
Transformer oils are designed to provide electrical insulation under high electrical fields; any significant reduction in the dielectric strength may indicate that the oil is no longer capable of performing this vital function.
Some of the things that can result in a reduction in dielectric strength include polar contaminants, such as water, oil degradation by products and cellulose paper breakdown.
Transformer faults may occur in the oil due to gas formation, ageing, contamination with air and lack of level and pressure.
In the event of a minor fault like damage to core bolt insulation, local overheating, etc., the arcing causes slow generation of gas in the oil.
All faults in transformer core and windings result in the localized heating and breakdown of oil.
When the fault is of very minor type such as hot joint, gas is released slowly and rises towards conservator.
A major fault where severe arcing takes place causes rapid release of large volume of gas and oil vapor.
This violent evolution of gas and oil vapor does not have time to escape and instead builds up pressure and bodily displaces the oil, causing surge of oil to the conservator.
Faults may also occur in the windings insulation material, as a consequence of oil failure, ageing, overheating and insulation breakdown.
If any portion of the core insulation becomes defective or the laminated structure of the core is bridged by any conducting material which can permit sufficient eddy current to flow, it will cause serious overheating.
The insulated core bolts are used for tightening the core. If the insulation of these bolts fails and provides easy path for stray current, this will lead to overheating.
Mechanical impacts during handling and transportation may apply to the transformer an equivalent force above 3g (where g is the gravidity acceleration; g = 9.81 m/s^{2}.), which can cause distortion of the core.
Common windings faults are:
These faults usually are a result of dielectric failure, both between windings and between the turns of the same winding, due to ageing of insulation material, which may increase due to overloads.
It also must be considered that the windings are subject to both radial and axial forces related to the current and flux interactions. Radial forces in the inner winding (normally the LV winding) are in compression while the outer winding (normally the HV winding) forces are in tension.
Design of the windings and bracing must consider the magnitude of these forces and provide adequate strength to withstand them without significant mechanical deformation which could result in a dielectric failure.
Also mechanical impacts during handling and transportation may apply to the transformer an equivalent force above 3g, which can cause distortion and/or displacement of the windings and decrease of the insulation of the windings.
The loading of transformer is decided by permissible temperature rise of windings and oil. Permissible oil temperature is 65 °C and hot spot temperature of the winding is 80 °C at rated load.
As the load of the transformer does not remain steady and varies according to load curve, the loading of transformer becomes an important operating problem.
The rated output of a power transformer is mentioned on its name plate with reference to specified temperature rise under specified test conditions.
The output which can be obtained from a transformer without causing undue deterioration of the insulation may be either more or less than the name plate rating depending upon the operating conditions, such as ambient temperature, initial loading, cooling provision, life expectancy, etc.
Overheating in transformer may be caused by overloads above the permissible overloads specified by the manufacturers, according to IEC Standards (60354 for oil-filled transformers and 60905 for dry type transformers), and external faults, such as short-circuits on installations downstream. Most of these faults may be limited by proper maintenance of a transformer.
Overheating may cause a breakdown of the insulation of the windings.
Transformers are provided with bullet on (internal protections) for dielectric failure (formation of gas), temperature, oil pressure, level, winding temperature and on load tap changer.
According to the construction type of transformers the following protections must be provided:
Oil-filled transformers with conservator
Buccholz relay has multiple methods to detect a failing transformer.
Buchholz relays have a test port to allow the accumulated gas to be withdrawn for testing. Flammable gas found in the relay indicates some internal fault such as overheating or arcing, whereas air found in the relay may only indicate low oil level or a leak.
For transformers equipped with cooling fans and pumps, the temperature devices are used to automatically start and stop the forced cooling. They are also equipped to initiate an alarm and a trip for very high transformer temperatures.
Oil-filled sealed transformers
Dry type transformers
These protections have a direct action on the tripping coils of the circuit breakers.
The ideal way of protecting any piece of power system equipment is to compare the current entering that piece of equipment, with the current leaving it.
Under normal healthy conditions the two are equal. If the two currents are not equal, then a fault must exist.
This is done through “differential protection” (ANSI / IEEE / IEC code 87T), which diagram is shown in Figure 1 and the functioning principle is based in Kirchhoff current law.
IEC: International Electrotechnical Comission.
ANSI: American National Standards Institute.
IEEE: Institute of Electrical and Electronic Engineers.
Figure 1 – Differential protection diagram
EHV and HV transformers and autotransformers for volatges above 49.5 kV and MV transformers with rated power above 3-4 MVA have usually as main protection a differential protection for winding faults – short-circuits between turns of a winding or between windings that correspond to phase-to-phase or three-phase type short-circuits.
If there is no earthing / grounding connection at the transformer location point, this protection can also be used to protect against earth faults.
If the earth fault current is limited by impedance, it is generally not possible to set the current threshold to a value less than the limiting current.
This protection is connected to current transformers CT (Current Transformers) at both side of the transformer (primary and secondary), as it was shown in Figure 1.
The use of transformer differential protection poses some problems that must be taken into account:
Problem relating to the transformation ratio and the coupling method
The primary and secondary currents have different amplitudes owing to the transformation ratio and different phases depending on the coupling method (delta-star transformer makes a phase displacement of 30°). Therefore, the current values measured must be readjusted so that the signals compared are equal during normal operation.
This is done using matching auxiliary transformers whose role is to balance the amplitudes and phases.
When one side of the transformer is star-connected with an earthed neutral, the matching transformers on this side are delta-connected, so that the residual currents that would be detected upon occurrence of an earth fault outside the transformer are cleared.
Figure 16 shows an example of the connection of the differential protection, using matching auxiliary transformers.
Figure – Transformer differential protection diagram
Nowadays, with electronic and microprocessed protection units, this compensation is done through software.
Function of the protection is based on the transformation ratio “n” that can be expressed by the equation:
n = (U_{1} / U_{2}) = (I_{2} / I_{1})
(U_{1}: primary voltage; U_{2}: secondary voltage; I_{1}: primary current; I_{2}: secondary current).
The above relation is a consequence of the equation of the rated power (S) of the transformer:
S = √3 x U_{1} x I_{1} = √3 x U_{2} x I_{2}
Problem relating to the transformer inrush current
Transformer switching causes a very high transient current (from 8 to 15 I_{n}), which only flows through the primary winding and lasts several tenths of a second.
It is thus detected by the protection as a differential current and it lasts far longer than the protection operating time (30 ms). Detection based only on the difference between the transformer primary and secondary currents would cause the protection to be activated. Therefore, the protection must be able to distinguish between a differential current due to a fault and a differential inrush current.
Experience has shown that the inrush current wave contains at least 20% of second harmonic components (current at a frequency of 100 Hz), while this percentage is never higher than 5% upon occurrence of an overcurrent due to a fault inside the transformer.
The protection must therefore simply be locked when the percentage of second harmonic component in relation to the fundamental harmonic component (current at 50 Hz) is higher than 15%, i.e., “I_{2 }/ I_{1} > 15%”.
Problem relating to the magnetizing current upon occurrence of an overvoltage of external origin
Magnetizing current, or exciting current, is the current that flows through the primary winding of a power transformer when no loads are connected to the secondary winding; this current establishes the magnetic field in the core and furnishes energy for the no-load power losses in the core. It is responsible for “iron losses”.
The magnetizing current constitutes a difference between the transformer primary and secondary currents. It is therefore detected as a fault current by the differential protection even though it is not due to a fault.
In normal operating conditions, this magnetizing current is very low and does not reach the protection operating threshold.
However, when an overvoltage occurs outside the transformer, the magnetic material saturates (in general the transformers are dimensioned to be able to operate at saturation limit for the nominal supply voltage), and the magnetizing current value greatly increases. The protection operating threshold can therefore be reached.
Experience has shown that the magnetizing current due to the magnetic saturation has a high rate of fifth harmonic components (current at a frequency of 250 Hz).
Transformer differential therefore requires fairly complex functions as it must be able to measure second and fifth harmonic current or, in order to avoid measuring fifth harmonic currents, it must be able to detect overvoltages of external origin.
The characteristics of transformer differential protection are related to the transformer specifications:
MV transformers with rated power up to 2.5 MVA are usually only protected against overcurrents using over current relays.
This set of protections is used on HV and MV transformers with rated power above 3-4 MVA as a “back-up” protection, in addition to the differential protection.
In some installations and networks MV transformers with rated power up to 630 kVA may be protected against overcurrents by fuses associated to switch-disconnectors, as shown in Figure 2.
In these situations the switch-disconnectors must have a tripping coil to allow the action of the built-on protections of transformers.
Figure 2 – Switch-disconnector associated with fuses
Fuses must have a mechanical latch to indicate the fusion and to provoke three-pole opening of the switch-disconnector, to avoid the functioning of the installation only with two phases.
Manufacturers provide tables to choose the rated current of a fuse, taking into account the rated voltage and power, like the one shown in the Table 1, according to IEC standards.
Tables vary from manufacturer to manufacturer, according to the standards used, being recommended to use the table provided by the selected manufacturer.
Table 1 – Rated current of fuses for power transformers protection
Transformer Rated Power (KVA) |
Line Voltage(KV) | ||||
6 – 7.2 | 10 – 12 | 15 – 17.5 | 20 – 24 | 30 – 36 | |
Fuse Rated Current (A) | |||||
50 | 10-16 | 10 | 6.3 – 10 | 6.3 | 4 – 6.3 |
100 | 16-31.5 | 16 – 25 | 16 | 10 | 6.3 – 10 |
125 | 20-40 | 16 – 31.5 | 20 | 10 – 16 | 6.3 – 10 |
160 | 31.5-50 | 20 – 31.5 | 20 – 25 | 16 – 20 | 10 – 16 |
200 | 31.5-63 | 25 – 40 | 20 – 31.5 | 16 – 20 | 10 – 16 |
250 | 40-80 | 25 – 40 | 31.5 | 16 – 25 | 10 – 20 |
315 | 50-100 | 31.5 – 50 | 31.5 – 50 | 16 – 25 | 16 – 25 |
400 | 63-100 | 40 – 63 | 31.5 – 63 | 20 – 40 | 16 – 25 |
500 | 80-125 | 50 – 80 | 40 – 80 | 25 – 50 | 20 – 31.5 |
630 | 100-160 | 63 – 100 | 63 – 100 | 31.5 – 63 | 20 – 40 |
800 | 125-160 | 80 – 125 | 63 – 100 | 40 – 63 | 25 – 50 |
1000 | 160-200 | 100 – 160 | 100 | 50 – 80 | 31.5 – 50 |
1250 | 250 | 160 | 125 | 80 | 50 |
Restricted earth fault protection (ANSI/IEEE/IEC code 64G/64REF) is used as a complement or to replace differential protection for windings faults to earth.
An external fault in the star side will result in current flowing in the line current transformer of the affected phase and at the same time a balancing current flows in the neutral current transformer, hence the resultant current in the relay is therefore zero.
So this protection will not be actuated for external earth fault. But during internal fault the neutral current transformer only carries the unbalance fault current and operation of the protection takes place.
This scheme of restricted earth fault protection is very sensitive for internal earth fault of electrical power transformer. The protection scheme is comparatively cheaper than differential protection scheme.
Restricted earth fault protection is provided in electrical power transformer for sensing internal earth fault of the transformer. In this scheme the CT secondary of each phase of electrical power transformer are connected together as shown in Figure 3.
Figure 3 – Diagram of restricted earth fault protection
Whenever there is an unbalancing in between three phases of the power transformer, a resultant unbalance current flow through the close path connected to the common terminals of the CT secondary.
An unbalance current will also flow through the neutral of power transformer and hence there will be a secondary current in Neutral CT because of this unbalance neutral current.
In restricted earth fault scheme the common terminals of phase CT are connected to the secondary of Neutral CT in such a manner that secondary unbalance current of phase CT and the secondary current of Neutral CT will oppose each other.
If these both currents are equal in amplitude there will not be any resultant current circulate through the said close path. The restricted earth fault protection is connected in this close path. Hence the relay will not response even there is an unbalancing in phase current of the power transformer.
The basic criterion for transformer loading is the temperature of the hottest spot of the solid insulation (hot-spot). It must not exceed the prescribed value, in order to avoid insulation faults, since loading capability of power transformers is limited mainly by winding temperature.
The temperature of solid insulation is the main factor of transformer ageing.
With temperature and time, the cellulose insulation undergoes a depolymerization process. As the cellulose chain gets shorter, the mechanical properties of paper such as tensile strength and elasticity degrade. Eventually the paper becomes brittle and is not capable of withstanding short circuit forces and even normal vibrations that are part of transformer life. This situation characterizes the end of life of the solid insulation. Since it is not reversible, it also defines the transformer end of life.
Transformer overloads can occur during contingency conditions that are the product of one, two, or various system elements being isolated from the power the system. They can also occur when transformers are already at 80%-90% of their full nameplate rating and extra capacity is needed, especially during hot summers.
Traditionally, inverse-time overcurrent relays (an inverse-time curve is characterized by the inverse variation of current with the time, as shown in Figure 4) for overload protection, but a difficulty is that transformers are usually outdoors where ambient temperature affects their loadability, and hence the optimum pickup settings of such relays.
Figure 4 – Inverse-time characteristic curve
However, for liquid-immersed power transformers, the temperature of the winding hot-spot is the important factor in the long-term life of the transformer.
The insulating oil temperature is dependent on the winding temperature, and is used to indicate the operating conditions of the transformer. Many numerical transformer protection relays available today include protection functions that operate on insulating oil temperatures, calculated loss-of-life due to high oil temperature, and predicted oil temperatures due to load.
These types of functions are not routinely applied, but modern utility operating practices try to maximize the utilization of power transformers, which may increase the occurrence of over-temperature conditions and transformer ageing. Over-temperature conditions and accelerated aging are adverse system events that must be identified and protected against.
The most common function provided for thermal protection of power transformers is the thermal overload (ANSI/IEEE/IEC code 49) function.
The thermal capacity used is calculated according to a mathematical model which takes into account:
The protection gives a trip order when the heat rise E, calculated according to the measurement of an equivalent current I_{eq}, is greater than the set point E_{s}.
The protection tripping time is set by the time constant T.
The thermal overload protection function may be used to protect equipment with two operating rates, for example transformers with two ventilation modes, with or without forced ventilation (ONAN / ONAF).
Lightning protection of power transformers is achieved by surge arresters installed in the transformer tank, as shown in Figure 5.
The most common surge arresters are non-linear metal oxide resistors type in porcelain or silicone rubber housing, and are fitted in parallel with the object protected and connected to the earth grid.
Resistance of non-linear resistors is in inverse proportion to the current, that is to say that the resistance is high for current service values and very low for high lightning discharge currents.
We have already discussed about it in detail in our previous post “Transformers Fire Protection System – Causes, Types & Requirements“.
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A combinational circuit capable of converting “2^{n}” input signals into “n” signals (such as BCD (Binary Coded Decimal) Binary etc) is called binary encoder also known as digital encoder.. Its operation is exactly opposite of Binary Decoder. In simple words, Binary Encoder used to encode a Binary Codes.
It has 2^{n} input lines and “n” output lines. When we want to process data received from many data lines and we have few available input ports or we want to conserve the input ports of a system then we apply an encoder to reduce the number input data lines. Block diagram of binary encoder is given below.
Line encoders are an example of Encoder in which multi-input lines are converted into a few binary outputs.
In line-encoders, one input at a time has a HIGH value otherwise the output will be invalid. Each data input line is treated as a single digit, for each line a specific binary output is generated in line encoders.
To clarify the problem of having more than one input line “HIGH”, priority encoders are used. Priority Encoders prioritize the input based on the design like in Line encoders, Most significant value out of the two inputs will decide the output. There is also an input condition check “V” which is low when there is no high input. And it is high when there is at least one high input.
Some of the Line encoders are given below with details.
Also read: Counter and Types of Electronic Counters
Some of the line encoders are given below:
Simplest line encoder is 2 to 1 line encoder in which there are 2 input lines and 1 output line. 2 to 1 line Encoder schematic and truth table are given below.
When D_{0 }is high, the output is 0 and when D_{1 }high output is 1 considering the other input is 0.
This encoder has 4 input lines and 2 output lines. A single input line can be high at a time otherwise the output will be ambiguous. Block diagram of 4 to 2 line binary encoder is given below.
The output is in binary format. Each input line gives a combination of binary output.
Consider D_{0}-D_{3 }as 4 inputs and X, Y as output bits.
The truth table of 4-2 Encoder is given below:
According to the truth table of 4 to 2 encoder:
X = D_{2 }+ D_{3}
Y = D_{1 }+ D_{3}
As from the above expressions, we deduce that binary encoder only needs OR gates. This encoder can be implemented with 2 OR gates as shown in the figure below. Schematic diagram of 4 to 2 line encoder using or gates it given below.
However, there is a limitation, when D_{1 }and D_{2 }are high at the same time then the output will be 1 1, which neither represent D_{1 }nor D_{2 }output. To remove this ambiguity, Priority encoders are designed.
This encoder prioritizes the highest input and produces output for that highest priority input regardless of the value of the other inputs. This encoder will prioritize D_{3 }over D_{2},D_{1,} and D_{0. }D_{0 }being the lowest priority input.
If D_{2} input is high then the output will be 10 whether the D_{1 }input is low or high. There is input condition check “V” to make sure there is any input. “V” is high when there is any input.
Input and output variable are “D_{0}-D_{3}” and “X, Y, V” respectively.
The truth table and K-Map for 4 to 2 priority encoder is:
Using K-map solution:
X = D_{2 }+ D_{3}
Y = D_{1}D̅_{2 }+ D_{3}
V = D_{0 }+ D_{1} + D_{2 }+ D_{3}
These expressions are same as the normal encoder but there is a condition that Y = 1 for D_{1 }only when D_{2 }(higher priority than D_{1}) is low because for D_{2 }=1, “Y” should be “0” according to the truth table.
Schematic of priority encoder using NOT, AND and OR gate is given below.
This encoder has 8 input lines and 3 output lines. It converts the octal into a binary system that is why it is known as octal to binary converter.
Consider D_{0}-D_{7 }as input and X,Y, Z as output.
The truth table for 8 to 3 line encoder is given below:
According to the truth table :
X = D_{4 }+ D_{5} +D_{6 }+ D_{7}
Y = D_{2 }+ D_{3} +D_{6 }+ D_{7}
Z = D_{1 }+ D_{3} +D_{5 }+ D_{7}
Schematic of 8 to 3 line encoder using OR gate is given below.
Consider D_{0}-D_{7 }as input and X,Y, Z as output and V as input condition check.
The truth table for 8-3 priority encoder is given below.
According to the truth table :
X = D_{4 }+ D_{5} + D_{6 }+ D_{7}
Y = D_{2 }D̅_{4 }D̅_{5 }+ D_{3 }D̅_{4 }D̅_{5} + D_{6 }+ D_{7}
Z = D_{1 }D̅_{2 }D̅_{4 }D̅_{6 }+ D_{3 }D̅_{4 }D̅_{6} + D_{5 }D̅_{6 }+ D_{7}
V = D_{0 }+ D_{1} + D_{2 }+ D_{3 }+ D_{4 }+ D_{5} + D_{6 }+ D_{7}
“X” being the MSB of binary output is high when any of D_{4,}D_{5},D_{6 }and D_{7 }is high.
“Y” is high when D_{7 }or D_{6 }is high. It is also high when D_{3 }or D_{2 }is high considering D_{4 }and D_{5 }are low because if they are high then the output Y=0.
“Z” is high whenever D_{7} is high, it is also high when D_{1},D_{3},D_{5 }are high but with these inputs other high priority input should be checked for which output “Z” goes low such as;
For D_{1}; D_{2},D_{4,}and D_{6 }has to be low,
For D3; D_{4 }and D_{6 }has to be low,
For D_{5}; D_{6 }has to be low.
If any of them are high the output “Z=0″
Schematic of 8 to 3 priority encoder is given below.
8 to 3 priority encoder can be made by cascading 4 to 2 priority encoder with enable inputs.
When enable input is high the encoder is enabled
Inputs to the encoders are D_{0}-D_{3 }for first encoder and D_{4}-D_{7 }for the second encoder. The output of the first encoder is Y_{0}, Z_{0} and second encoder output is Y_{1}, Z1. Input condition check for the first decoder is V_{0} and second is V_{1.}
The output of the whole 8 to 3 priority encoder is X, Y, Z. so the truth table would be:
According to the truth table:
X = V_{1}
Y = Y_{0} + Y_{1}
Z = Z_{0 }+ Z_{1}
V = V_{0 }+ V_{1}
En_{0 }= V̅_{1 }
when there is no input to the higher priority Encoder the lower Priority encoder will turn on.
Cascading 4 to 2 Priority Encoders implementation diagram is given below.
CMOS IC 4532 Priority Encoder
A CMOS IC 4532 Priority encoder’s pin configuration and details are given below.
Encoders are widely used in digital electronic systems. Some of common application and uses of encoders are as follow:
You may also read:
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A digital binary adder is a digital device that adds two binary numbers and gives its sum in binary format.
The two numbers to be added are known as “Augand” and “Addend”. The first number in addition is occasionally referred as “Augand”.
Digital adders are mostly used in computer’s ALU (Arithmetic logic unit) to compute addition. Digital calculators use adders for athematic addition. Micro controllers use adders in arithmetic additions,PC (program counter) and timers etc. Every device that uses some kind of increment or arithmetic process contains adders.
The building block of digital adder is Half Adder. Half adders come together to form full adder.
We will briefly discuss them one by one.
We will discuss one by one as follow:
Half adder can add 2 single bit numbers.
Consider the two numbers A, B, and the output being “Sum” and “carry”.
The truth table of half adder is given below.
Sum
According to the truth table of half adder and the K-map, the SOP expression for “Sum” is:
Sum = A̅B + AB̅
Schematic for “Sum” using discrete logic gates is given below.
The expression for “Sum” is same as XOR with input A and B so it can be replaced with a single XOR gate as shown below:
Sum = A XOR B
Carry
According to the truth table of half adder the SOP expression for “Carry” is:
Carry = AB
“Carry” is AND of input A,B as shown below.
Complete half adder is made by combining “sum” and “carry” schematic as shown in figure below;
NAND gate is a Universal gate which means any kind of logic gate or function can be implemented with NAND gate.
SOP (Sum of products) expression can easily get implemented with NAND gates.
Sum
SOP expression for“Sum of half adder”.
Sum = A̅B + AB̅
(Sum)’ = (A̅B + AB̅)’
(Sum)’ = {(A̅B)’ & (AB̅)’}
(Sum)’ = [ { (A &A)’&B}’ & {A &(B & B)’}’]
Sum = [ { (A &A)’&B}’ & {A &(B & B)’}’]’
This expression for “sum” can be implemented using NAND gates as shown below:
Carry
SOP expression for “half adder’s carry” output is :
Carry = AB
(Carry)’ = (AB)’
Carry = (AB)’’
In other word INVERT of NAND gate is AND gate, and schematic of “Carry” using NAND gate is given below.
Half adder
NOW we will combine these two schematics to make half adder using NAND gates.
NOR gate is also a universal gate and POS (product of sums) expressions can easily be implemented using NOR gates.
Sum
According to half adder truth table, POS expression for the sum is:
Sum = (A̅+B̅) & (A+B)
(Sum)’ = {(A̅+B̅) & (A+B)}’
(Sum)’ = {(A̅+B̅)’ + (A+B)’}
Sum = {(A̅+B̅)’ + (A+B)’}’
Sum = [{(A+A)’+ (B+B)’}’ + (A+B)’]’
Schematic of “Sum” using NOR gates are given below:
Carry
Expression for “carry” is
Carry = AB
(Carry)’ = (AB)’
(Carry)’ = (A’+B’)
Carry = (A’+B’)’
Carry = {(A+A)’+(B+B)’}’
The schematic for “Carry” using NOR gates is given below:
Now if we combined these two schematics together it will form half adder using NOR gates.
Half adder can add only two 1-bit numbers and it cannot add the third number (carry) which comes from previous numbers addition which is why it is known as HALF ADDER.
It cannot be used for addition of more than 1-bit.
A full adder can add numbers with carry from previous additions.
It consists of 3 inputs. 2 inputs being “Augend” and “addend” and the third one is “carry in” from previous additions.
It has 2 output;“Sum” and C_{out} as carry out.
Consider 2 numbers A,B, and C_{in }as input and “sum”, C_{out }as output.
Truth table of full adder is given below;
Sum
According to the truth table of a full adder, the SOP expression for “Sum” is:
Sum = C̅_{in}A̅B + C̅_{in}AB̅ + C_{in}A̅B̅ + C_{in}AB
Sum = C̅_{in}(A̅B + AB̅) + C_{in}(A̅B̅ + AB)
Sum = C̅_{in}(A XOR B) + C_{in}(A XNOR B)
Sum = C̅_{in}(A XOR B) + C_{in}(A̅̅ X̅O̅R̅̅ B̅)
Sum = C_{in}XOR (A XOR B)
According to this expression schematic for full adder’s Sum is.
According to Karnaugh’s map for Sum given below, there is no pair so the expression will be same and cannot be minimized;
Carry out
According to the full adders truth table, SOP expression for C_{out }is
C_{out }= C̅_{in}AB + C_{in}A̅B + C_{in}AB̅ + C_{in}AB
C_{out }= C̅_{in}AB + C_{in}AB + C_{in}A̅B + C_{in}AB̅
C_{out }= AB(C̅_{in} + C_{in}) + C_{in}(A̅B + AB̅)
C_{out }= AB + C_{in}(A XOR B)
Schematic for C_{out} is given below
According to karnaugh’s map for C_{out} the expression will be:
C_{out }= AB + C_{in}B + C_{in}A
C_{out }= AB + C_{in}(A+B)
Schematic for C_{out }using karnaugh map’s expression
The schematics of Full adder are shown in the figures below:
A full adder can be implemented using two half adders in cascaded setup.
A half adders output is:
HA_Sum = (A XOR B) = A̅B + AB̅
HA_C = AB
Half adder sum is denoted by HA_sum and carry out is denoted by HA_C
Full adder output expression is:
Sum = C_{in}XOR (A XOR B)
Sum = C_{in}XOR (HA_sum_1) (HA_sum_1; sum of first half adder whose input is A,B)
Sum = HA_sum_2 (HA_sum_2; sum of second half adder whose input is HA_sum_1 and C_{in})
C_{out} = AB + C_{in}(A XOR B)
C_{out} = AB + C_{in}(HA_sum_1)
C_{out} = HA_C_1 + HA_C_2 (HA_C_1; carry out of first adder whose input is A,B
HA_C_2; carry out of the second adder whose input is C_{in},HA_sum_1)
According to the equation of Sum and C_{out}. the schematic of a full adder using half adder is given below.
We have designed half adders using NAND gates.
We will use NAND gate half adder in the cascaded setup as discussed above.
Sum = Sum of second half adder
C_{out }= HA_C_1 + HA_C_2
C_{out}’_{ }= (HA_C_1 + HA_C_2)’
C_{out}’_{ }= (HA_C_1)’ & (HA_C_2)’
C_{out }= {(HA_C_1)’ & (HA_C_2)’}’
In “NAND half adder carry out” schematic, “carry out” has been inverted at the end. We will bypass the inverter and feed it to NAND gate as shown in the expression above.
For NOR gate we will use NOR gate half adders.
Sum = Sum of second half adder
C_{out} = HA_C_1 + HA_C_2
C_{out}’ = (HA_C_1 + HA_C_2)’
C_{out}‘’ = (HA_C_1 + HA_C_2)’’
Thus the schematic for Full adder using NOR gate will be :
These full adders can be used for adding ‘n’ bit number sif ‘n’ number of full adders are connected in a cascaded setup with c_{out }connected to the C_{in }of the next full adder.
‘n’ bit adder can be made using ‘n’ full adders in series. This way, 4-bit adder can be made using 4 full adders.
Each full adder for separate bit addition and C_{out }of one adder will be fed to the succeeding adder’s C_{in }and the last Adder’s C_{out }will be the C_{out }of 4-bit adder.Each full adder will give single bit of Sum as output.
The C_{in }of the first Full adder will be hard wired to the ground (0).
A combinational digital device capable of subtracting the second binary number forms the first one is called digital Subtractor.
First, we will discuss how subtraction works.
Consider two numbers A and B being subtracted.
OUT = A – B
OUT = A + (-B)
This equation means that these numbers are added together like in adder but the second number is negative of itself.
In Binary system the negative of a number is 2’s complement of that number.
To take 2’s complement of a number; first, we need to invert all the bits of that number this inversion is known as 1’s complement. And then add 1 with it as shown below.
B = B_{3}B_{2}B_{1}B_{0}
1’s complement B = B̅_{3}B̅_{2}B̅_{1}B̅_{0 }
2’s complement B = B̅_{3}B̅_{2}B̅_{1}B̅_{0 }+ 1
The MSB of signed number is sign bit. It is 1 for negative sign and 0 for positive,
Thus we need to invert the 2^{nd} input of Adder and set C_{in}to “1” to get added in B for subtraction as shown in the figure below.
We can use adder as subtractor if we make C_{in }input as a selector between addition and subtraction. And we use a multiplexer (input line selector) for the second input.
If C_{in }is low ”0” ; it will select B as input thus addition will occur.
If C_{in }is high ”1” ; it will select B̅ as input and C_{in }will get added in, thus subtraction will occur.
Logical Equation for Half Adder and Full Adder.
D = A ⊕ B and W = Ā B
Simulation diagrams of Adder and Subtractor is given below.
Some of Adder ICs with pin configuration is given below:
You may also read:
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