The post Voltage Divider appeared first on Basic Electronics Tutorials.

]]>Voltage dividers are also known as potential dividers, because the unit of voltage, the “Volt” represents the amount of *potential difference* between two points. A voltage or potential divider is a simple passive circuit that takes advantage of the effect of voltages being dropped across components which are connected in series.

The potentiometer, which is a variable resistor with a sliding contact, is the most basic example of a voltage divider as we can apply a voltage across its terminals and produce an output voltage in proportion to the mechanical position of its sliding contact. But we can also make voltage dividers using individual resistors, capacitors and inductors as they are two-terminal components which can be connected together in series.

The simplest, easiest to understand, and most basic form of a passive voltage divider network is that of two resistors connected together in series. This basic combination allows us to use the *Voltage Divider Rule* to calculate the voltage drops across each series resistor.

Here the circuit consists of two resistors connected together in series: R_{1}, and R_{2}. Since the two resistors are connected in series, it must therefore follow that the same electric current must flow through each resistive element of the circuit providing an I*R voltage drop across each resistive element.

With a supply or source voltage, V_{S} applied across this series combination, we can apply Kirchhoff’s Voltage Law, (KVL) and also using Ohm’s Law to find the voltage dropped across each resistor derived in terms of the common current, I flowing through them. So solving for the current (I) flowing through the series network gives us:

The current flowing through the series network is simply I = V/R following Ohm’s Law. Since the current is common to both resistors, (I_{R1} = I_{R2}) we can calculate the voltage dropped across resistor, R_{2} in the above series circuit as being:

Likewise for resistor R_{1} as being:

How much current will flow through a 20Ω resistor connected in series with a 40Ω resistor when the supply voltage across the series combination is 12 volts dc. Also calculate the voltage drop produced across each resistor.

Each resistance provides an I*R voltage drop which is proportionaly equal to its resistive value across the supply voltage. Using the voltage divider ratio rule, we can see that the largest resistor produces the largest I*R voltage drop. Thus, R_{1} = 4V and R_{2} = 8V. Applying Kirchhoff’s Voltage Law shows that the sum of the voltage drops around the resistive circuit is exactly equal to the supply voltage, as 4V + 8V = 12V.

Note that if we use two resistors of equal value, that is R_{1} = R_{2}, then the voltage dropped across each resistor would be exactly half the supply voltage for two resistances in series as the voltage divider ratio would equal 50%.

Another use of a voltage divider network is that to produce a variable voltage output. If we replace resistor R_{2} with a variable resistor (potentiometer), then the voltage dropped across R_{2} and therefore V_{OUT} can be controlled by an amount dependant on the postion of the potentiometers wiper and therefore the ratio of the two resistive values as we have one fixed and one variable resistor. Potentiometers, trimmers, rheostats and variacs are all examples of variable voltage division devices.

We could also take this idea of variable voltage division one step further by replacing the fixed resistor R_{2} with a sensor such as a *light dependent resistor*, or LDR. Thus as the resistive value of the sensor changes with changes in light levels, the output voltage V_{OUT} also changes by a proportional amount. Thermistors and strain guages are other examples of resistive sensors.

Since the two voltage division expressions above relate to the same common current, mathematically they must therefore be related to each other. So for any number of individual resistors forming a series network, the voltage dropped across any given resistor is given as:

Where: V_{R(x)} is the voltage drop across the resistor, R_{X} is the value of the resistor, and R_{T} is the total resistance of the series network. This voltage divider equation can be used for any number of series resistances connected together because of the proportional relationship between each resistance, R and its corresponding voltage drop, V. Note however, that this equation is given for an unloaded *voltage divider network* without any additional resistive load connected or parallel branch currents.

Three resistive elements of 6kΩ, 12kΩ and 18kΩ are connected together in series across a 36 volt supply. Calculate, the total resistance, the value of the current flowing around the circuit, and the voltage drops across each resistor.

Data given: V_{S} = 36 volts, R_{1} = 6kΩ, R_{2} = 12kΩ and R_{3} = 18kΩ

The voltage drops across all three resistors should add up to the supply voltage as defined by Kirchhoff’s Voltage Law (KVL). So the sum of the voltage drops is: V_{T} = 6 V + 12 V + 18 V = 36.0 V the same value of the supply voltage, V_{S} and so is correct. Again notice that the largest resistor produces the largest voltage drop.

Consider a long series of resistors connected to a voltage source, V_{S}. Along the series network there are different voltage tapping points, A, B, C, D, and E.

The total series resistance can be found by simply adding together the individual series resistance values giving a total resistance, R_{T} value of 15kΩ. This resistive value will limit the flow of current through the circuit produced by the supply voltage, V_{S}.

The individual voltage drops across the resistors are found using the equations above, so V_{R1} = V_{AB}, V_{R2} = V_{BC}, V_{R3} = V_{CD}, and V_{R4} = V_{DE}.

The voltage levels at each tapping point is measured with respect to ground (0V). Thus the voltage level at point D will be equal to V_{DE}, and the voltage level at point C will be equal to V_{CD} + V_{DE}. In other words, the voltage at point C is the sum of the two voltage drops across R_{3} and R_{4}.

So hopefully we can see that by choosing a suitable set of resistive values, we can produce a sequence of voltage drops which will have a proportional voltage value obtained from a single supply volatge. Note also that in this example each output voltage point will be positive in value because the negative terminal of the voltage supply, V_{S} is grounded.

1. Calculate the noload voltage output for each tapping point of the voltage divider circuit above if the series-connected resistive network is connected to a 15 volt DC supply.

2. Calculate the noload voltage output from between points B and E.

In the simple voltage divider circuit above all the output voltages are referenced from a common zero-voltage ground point, but sometimes it is necessary to produce both positive and negative voltages from a single source voltage supply. For example the different voltage levels from a computer PSU, -12V, +3.3V, +5V and +12V, with respect to a common reference ground terminal.

Using Ohm’s Law, find the values of resistors R_{1}, R_{2}, R_{3} and R_{4} required to produce the voltage levels of -12V, +3.3V, +5V and +12V if the total power supplied to the unloaded voltage divider circuit is 24 volts DC, 80 watts.

In this example, the zero-voltage ground reference point has been moved to produce the required positive and negative voltages, while maintaining the voltage divider network across the supply. Thus the four voltages are all measured with respect to this common reference point reulting in point D being at the required negative potential of -12V with respect to ground.

We have seen so far that series resistive circuits can be used to create a voltage divider, or potential divider network which can be widely used in electronic circuits. By selecting appropriate values for the series resistances, any value of output voltage can be obtained which is lower than the input or supply voltage. But as well as using resistances and a DC supply voltage to create a *resistive voltage divider network*, we can also use capacitors (C) and inductors (L), but with a sinusoidal AC supply as capacitors and inductors are reactive components, meaning that their resistance “reacts” against the flow of electric current.

As the name suggests, **Capacitive Voltage Divider** circuits produce voltage drops across capacitors connected in series to a common AC supply. Generally capacitive voltage dividers are used to “step-down” very high voltages to provide a low voltage output signal which can then be used for protection or metering. Nowadays, high frequency capacitive voltage dividers are used more in display devices and touch screen technologies found in mobile phones and tablets.

Unlike resistive voltage divider circuits which operate on both AC and DC supplies, voltage division using capacitors is only possible with a sinusoidal AC supply. This is because the voltage division between series connected capacitors is calculated using the reactance of the capacitors, X_{C} which is dependent on the frequency of the AC supply.

We remember from our tutorials about capacitors in AC circuits, that capacitive reactance, X_{C} (measured in Ohms) is inversely proportional to both frequency and capacitance, and is therefore given by the following equation of:

- Where:
- Xc = Capacitive Reactance in Ohms, (Ω)
- π (pi) = a numeric constant of 3.142
- ƒ = Frequency in Hertz, (Hz)
- C = Capacitance in Farads, (F)

Therefore by knowing the voltage and frequency of the AC supply, we can calculate the reactances of the individual capacitors, substitute them in the above equation for the resistive voltage divider rule, and obtain the corresponding voltage drops across each capacitor as shown.

Using the two capacitors of 10uF and 22uF in the series circuit above, we can calculate the rms voltage drops across each capacitor in terms of their reactance when connected to a 100 volts, 50Hz rms supply.

When using pure capacitors the sum of all the series voltage drops equals the source voltage, the same as for series resistances. While the amount of voltage drop across each capacitors is proportional to its reactance, it is inversely proportional to its capacitance.

As a result, the smaller 10uF capacitor has more reactance (318.3Ω) so therefore a greater voltage drop of 69 volts compared to the larger 22uF capacitor which has a reactance of 144.7Ω and a voltage drop of 31 volts respectively. The current in the series circuit, I_{C} will be 216mA, and is the same value for C_{1} and C_{2} as they are in series.

One final point about **capacitive voltage divider** circuits is that as long as there is no series resistance, purely capacitive, the two capacitor voltage drops of 69 and 32 volts will arithmetically be equal to the supply voltage of 100 volts as the two voltages produced by the capacitors are in-phase with each other. If for whatever reason the two voltages are out-of-phase with each other then we can not just simple add them together as we would using Kirchhoffs voltage law, but instead phasor addition of the two waveforms is required.

As its name suggests, **Inductive Voltage Dividers** create voltage drops across inductors or coils connected together in series to a common AC supply. An *inductive voltage divider* can consist of a single winding or coil which is divided into two sections where the output voltage is taken from across one of the section, or from two individual coils connected together. The most common example of an inductive voltage divider is the *auto-transformer* with multiple tapping points along its secondary winding.

When used with steady state DC supplies or with sinusoids having a very low frequency, approaching 0 Hz, inductors act as a short circuit. This is because their reactance is almost zero allowing any DC current to easily pass through them, so like the previous capacitive voltage divider network, we must perform any inductive voltage division using a sinusoidal AC supply. Inductive voltage division between series connected inductors can be calculated using the reactance of the inductors, X_{L} which like *capacitive inductance*, is dependent on the frequency of the AC supply.

In the tutorials about inductors in AC circuits, we saw that inductive reactance, X_{L} (also measured in Ohms) is proportional to both frequency and inductance so any increases in the supply frequency increases an inductors reactance. Thus *inductive reactance* is defined as:

- Where:
- X
_{L}= Inductive Reactance in Ohms, (Ω) - π (pi) = a numeric constant of 3.142
- ƒ = Frequency in Hertz, (Hz)
- L = Inductance in Henries, (H)

If we know the voltage and frequency of the AC supply, we can calculate the reactances of the two inductors and use them along with the voltage divider rule to obtain the voltage drops across each inductor as shown.

Using the two inductors of 10mH and 20mH in the series circuit above, we can calculate the rms voltage drops across each capacitor in terms of their reactance when connected to a 60 volts, 200Hz rms supply.

Like the previous resistive and capacitive voltage division circuits, the sum of all the series voltage drops across the inductors will equal the source voltage, as long as there are no series resistances. Meaning a pure inductor. The amount of voltage drop across each inductor is proportional to its reactance.

The result is that the smaller 10mH inductor has less reactance (12.56Ω), so therefore less of a voltage drop at 30 volts compared to the larger 20mH inductor which has a reactance of 25.14Ω and a voltage drop of 40 volts respectively. The current, I_{L} in the series circuit is 1.6mA, and will be the same value for L_{1} and L_{2} as these two inductors are connected in series.

We have seen here that the voltage divider, or network is a very common and useful circuit configuration allowing us to produce different voltage levels from a single voltage supply, thus eliminating the need to have separate power supplies for different parts of a circuit operating at different voltage levels.

As its name suggests, a voltage or potential divider, “divides” a fixed voltage into precise proportions using resistors, capacitors or inductors. The most basic and commonly used voltage divider circuit is that of two fixed-value series resistors, but a potentiometer or rheostat can also be used for voltage division by simply adjusting its wiper position.

A very common application of a voltage divider circuit is to replace one of the fixed-value resistors with a sensor. Resistive sensores such as light sensores, temperature sensores, pressure sensores and strain guages, which change their resistive value as they respond to environmental changes can all be used in a voltage divider network to provide an analogue voltage output. The biasing of bipolar transistors and MOSFETs is also another common application of a **Voltage Divider**.

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]]>The post Universal Logic Gates appeared first on Basic Electronics Tutorials.

]]>By using logical sets in this way, the various laws and theorems of Boolean Algebra can be implemented with a complete set of logic gates. In fact, it is possible to produce every other Boolean function using just the set of AND and NOT gates since the OR function can be created using just these two gates. Likewise, the set of OR and NOT can be used to create the AND function.

Any logic gate which can be combined into a set to realise all other logical functions is said to be a universal gate with a complete logic set being a group of gates that can be used to form any other logic function.

For example, AND and NOT constitute a complete set of logic, as does OR and NOT as cascading together an AND with a NOT gate would give us a NAND gate. Similarly cascading an OR and NOT gate together will produce a NOR gate, and so on. However, the two functions of AND and OR on their own do not form a complete logic set.

So by using these three *Universal Logic Gates* we can create a range of other Boolean functions and gates. However, the NAND and NOR gates are classed as minimal sets because they have the property of being a complete set in themselves since they can be used individually or together to construct many other logic circuits. Therefore we can define the complete sets of operations of the main logic gates as follows:

- AND, OR and NOT (a Full Set)
- AND and NOT (a Complete Set)
- OR and NOT (a Complete Set)
- NAND (a Minimal Set)
- NOR (a Minimal Set)

Thus we can use these five sets of gates, together or individually as the building blocks to produce more complex logic circuits called *combinational logic circuits*. But first let us remind ourselves of the switching characteristics of the three basic logic gates, AND, OR and NOT.

In mathematics, the number or quantity obtained by multiplying two (or more) numbers together is called the *product*. In Boolean Algebra the AND function is the equivalent of multiplication and so its output state represents the product of its inputs. The AND function is represented in Boolean Algebra by a single “dot” (.) so for a two input AND gate the Boolean equation is given as: Q = A.B, that is Q equals both A AND B.

Symbol | Truth Table | ||

B | A | Q | |

0 | 0 | 0 | |

0 | 1 | 0 | |

1 | 0 | 0 | |

1 | 1 | 1 |

In mathematics, the number or quantity obtained by adding two (or more) numbers together is called the *sum*. In Boolean Algebra the OR function is the equivalent of addition so its output state represents the addition of its inputs. In Boolean Algebra the OR function is represented by a “plus” sign (+) so for a two input OR gate the Boolean equation is given as: Q = A+B, that is Q equals either A OR B.

Symbol | Truth Table | ||

B | A | Q | |

0 | 0 | 0 | |

0 | 1 | 1 | |

1 | 0 | 1 | |

1 | 1 | 1 |

The NOT gate, which is also known as an “inverter” is given a symbol whose shape is that of a triangle pointing to the right with a circle at its end. This circle is known as an “inversion bubble”.

The NOT function is not a decision making logic gate like the AND, or OR gates, but instead is used to invert or complement a digital signal. In other words, its output state will always be the opposite of its input state.

The NOT gate symbol has a single input and a single output as shown.

Symbol | Truth Table | |

A | Q | |

0 | 1 | |

1 | 0 |

The single input NOT gate or invert function can be cascaded with itself to produce what is called a digital buffer. The first NOT gate will invert the input and the second will re-invert it back to its original level performing a double inversion of the single input. Non-inverting Digital Buffers have many uses in digital electronics as this double inversion of the input can be used to provide digital amplification and circuit isolation.

Using just the AND and NOT set of logic gates we can create the following Boolean functions and equivalent gates.

Using the OR and NOT set of logic gates we can create the following Boolean functions and equivalent gates.

Using the full AND, OR and NOT set of logic gates we can create the Boolean expressions for the Exclusive-OR (Ex-OR) and the NOT Exclusive-OR (Ex-NOR) gates as shown.

Note that neither the Exclusive-OR gate or the Exclusive-NOR gate can be classed as a universal logic gate as they can not be used on their own or together to produce any other Boolean function.

One of the main disdvantages of using the complete sets of AND, OR and NOT gates is that to produce any equivalent logic gate or function we require two (or more) different types of logic gate, AND and NOT, or OR and NOT, or all three as shown above. However, we can realise all of the other Boolean functions and gates by using just one single type of universal logic gate, the NAND (NOT AND) or the NOR (NOT OR) gate, thereby reducing the number of different types of logic gates required, and also the cost.

The NAND and NOR gates are the complements of the previous AND and OR functions respectively and are individually a complete set of logic as they can be used to implement any other Boolean function or gate. But as we can construct other logic switching functions using just these gates on their own, they are both called a minimal set of gates. Thus the NAND and the NOR gates are commonly referred to as **Universal Logic Gates**.

The 7400 (or the 74LS00 or 74HC00) quad 2-input NAND TTL chip has four individual NAND gates within a single IC package. Thus we can use a single 7400 TTL chip to produce all the Boolean functions from a NOT gate to a NOR gate as shown.

Thus ALL other logic gate functions can be created using only NAND gates making it a universal logic gate.

The 7402 (or the 74LS02 or 74HC02) quad 2-input NOR TTL chip has four individual NOR gates within a single IC package. Thus like the previous 7400 NAND IC we can use a single 7402 TTL chip to produce all the Boolean functions from a single NOT gate to a NAND gate as shown.

Thus ALL other logic gate functions can be created using only NOR gates making it also a universal logic gate.

Note also that the implementation of the Exclusive-OR gate is more efficient using NAND gates compared to using NOR gates, while the implementation of the Exclusive-NOR gate is more efficient with NOR gates compared to using NAND gates as in each case only four individual logic gates are required. In other words we can create all the Boolean functions using just one 7400 NAND or one 7402 NOR chip including its various sub-families.

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]]>The post DeMorgan’s Theorem appeared first on Basic Electronics Tutorials.

]]>While George Boole’s set of laws and rules allows us to analyise and simplify a digital circuit, there are two laws within his set that are attributed to **Augustus DeMorgan** (a nineteenth century English mathematician) which views the logical NAND and NOR operations as separate NOT AND and NOT OR functions respectively.

But before we look at **DeMorgan’s Theory** in more detail, let’s remind ourselves of the basic logical operations where A and B are logic (or Boolean) input binary variables, and whose values can only be either “0” or “1” producing four possible input combinations, 00, 01, 10, and 11.

Input Variable | Output Conditions | ||||||

A | B | AND | NAND | OR | NOR | ||

0 | 0 | 0 | 1 | 0 | 1 | ||

0 | 1 | 0 | 1 | 1 | 0 | ||

1 | 0 | 0 | 1 | 1 | 0 | ||

1 | 1 | 1 | 0 | 1 | 0 |

The following table gives a list of the common logic functions and their equivalent Boolean notation where a “.” (a dot) means an AND operation, a “+” (plus sign) means an OR operation, and the complement or inverse of a variable is indicated by a bar over the variable.

Logic Function | Boolean Notation |

AND | A.B |

OR | A+B |

NOT | A |

NAND | A .B |

NOR | A+B |

*DeMorgan’s Theorems* are basically two sets of rules or laws developed from the Boolean expressions for AND, OR and NOT using two input variables, A and B. These two rules or theorems allow the input variables to be negated and converted from one form of a Boolean function into an opposite form.

DeMorgan’s first theorem states that two (or more) variables NOR´ed together is the same as the two variables inverted (Complement) and AND´ed, while the second theorem states that two (or more) variables NAND´ed together is the same as the two terms inverted (Complement) and OR´ed. That is replace all the OR operators with AND operators, or all the AND operators with an OR operators.

DeMorgan’s First theorem proves that when two (or more) input variables are AND’ed and negated, they are equivalent to the OR of the complements of the individual variables. Thus the equivalent of the NAND function and is a negative-OR function proving that A.B = A+B and we can show this using the following table.

Inputs | Truth Table Outputs For Each Term | ||||||

B | A | A.B | A.B | A | B | A + B | |

0 | 0 | 0 | 1 | 1 | 1 | 1 | |

0 | 1 | 0 | 1 | 0 | 1 | 1 | |

1 | 0 | 0 | 1 | 1 | 0 | 1 | |

1 | 1 | 1 | 0 | 0 | 0 | 0 |

We can also show that A.B = A+B using logic gates as shown.

The top logic gate arrangement of: A.B can be implemented using a NAND gate with inputs A and B. The lower logic gate arrangement first inverts the two inputs producing A and B which become the inputs to the OR gate. Therefore the output from the OR gate becomes: A+B

Thus an OR gate with inverters (NOT gates) on each of its inputs is equivalent to a NAND gate function, and an individual NAND gate can be represented in this way as the equivalency of a NAND gate is a negative-OR.

DeMorgan’s Second theorem proves that when two (or more) input variables are OR’ed and negated, they are equivalent to the AND of the complements of the individual variables. Thus the equivalent of the NOR function and is a negative-AND function proving that A+B = A.B and again we can show this using the following truth table.

Inputs | Truth Table Outputs For Each Term | ||||||

B | A | A+B | A+B | A | B | A . B | |

0 | 0 | 0 | 1 | 1 | 1 | 1 | |

0 | 1 | 1 | 0 | 0 | 1 | 0 | |

1 | 0 | 1 | 0 | 1 | 0 | 0 | |

1 | 1 | 1 | 0 | 0 | 0 | 0 |

We can also show that A+B = A.B using logic gates as shown.

The top logic gate arrangement of: A+B can be implemented using a NOR gate with inputs A and B. The lower logic gate arrangement first inverts the two inputs producing A and B which become the inputs to the AND gate. Therefore the output from the AND gate becomes: A.B

Thus an AND gate with inverters (NOT gates) on each of its inputs is equivalent to a NOR gate function, and an individual NOR gate can be represented in this way as the equivalency of a NOR gate is a negative-AND.

Although we have used DeMorgan’s theorems with only two input variables A and B, they are equally valid for use with three, four or more input variable expressions, for example:

For a 3-variable input

A.B.C = A+B+C

and also

A+B+C = A.B.C

For a 4-variable input

A.B.C.D = A+B+C+D

and also

A+B+C+D = A.B.C.D

and so on.

We have seen here that DeMorgan’s Theorems replace all of the AND (.) operators with OR (+) and vice versa and then complements each of the terms or variables in the expression by inverting it, that is 0’s to 1’s and 1’s to 0’s before inverting the entire function.

Thus to obtain the DeMorgan equivalent for an AND, NAND, OR or NOR gate, we simply add inverters (NOT-gates) to all inputs and outputs and change an AND symbol to an OR symbol or change an OR symbol to an AND symbol as shown in the following table.

Standard Logic Gate | DeMorgan’s Equivalent Gate |

Then we have seen that the complement of two (or more) AND’ed input variables is equivalent to the OR of the complements of these variables, and that the complement of two( or more) OR’ed variables is equivalent to the AND of the complements of the variables as defined by *DeMorgan*.

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]]>The post Semiconductor Diode eBook appeared first on Basic Electronics Tutorials.

]]>The **Semiconductor Diode** is a solid-state device that allows current to pass through itself in one direction only, acting as a sort off one way valve to electron current flow. Diodes are formed by joining together two pieces of semiconductor material. One of these being a n-type material, and the other a p-type material.

To learn more about how *semiconductor diodes* can be used to create half-wave, full-wave and even bridge rectifiers for the rectification of an AC voltage to a DC voltage, or to obtain more detailed information about the characteristics and uses of diodes, then register below to get your copy of the new **Semiconductor Diode eBook** today.

You will learn about:

- Insulators and Conductors
- Semiconductor Material
- The PN-junction Diode
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- The Diode as a Transient Suppressor
- The Zener Diode

and gaining access to eBooks, tutorials and much much more

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]]>The post Field Effect Transistor eBook appeared first on Basic Electronics Tutorials.

]]>**Field Effect Transistors**, or FET’s, are three terminal unipolar semiconductor devices which use a conductive central channel to control the flow of current through themselves by the application of different voltages onto their connecting terminals. FET’s come in two basic types, the Junction FET (JFET) and the Insulated-gate FET known commonly as a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).

To learn more about how field effect transistors use a voltage applied to their gate terminal to control the current flowing through their channel, or to obtain more detailed information about the characteristics of *field effect transistors*, then register below to get your copy of the new **Field Effect Transistor eBook** today.

You will learn about:

- The Different JFET Types
- The Different MOSFET Types
- The FETs Operating Regions
- The MOSFET as a Switch
- The MOSFET as a Amplifier

and gaining access to eBooks, tutorials and much much more

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]]>The post Bipolar Transistor eBook appeared first on Basic Electronics Tutorials.

]]>**Bipolar Junction Transistors** are three-layer solid-state semiconductor devices which control the flow of current through themselves by the application of different voltages onto their terminals. For a transistor to operate as either an amplifier or an electronic switch, it requires external voltages to be applied between all of its junctions.

To learn more about the operation of the two transistor types, PNP and NPN, and how they can be used as solid state switches to turn load currents “ON” or “OFF” by controlling the base signal, or to obtain more detailed information about the characteristics of *bipolar transistors*, then register below to get your copy of the new **Bipolar Transistor eBook** today.

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- The Two Transistor Types
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]]>The post 555 Circuits Part 2 appeared first on Basic Electronics Tutorials.

]]>We recall from the our previous tutorial about the 555 timer that to get it to oscillate as a square-wave oscillator we need to continuously retrigger it with the timing period, T and therefore output frequency, ƒ being set by the timing capacitor C and feedback resistors R_{A} and R_{B}. The duty cycle, D as well as the frequency is controlled by the ratio of these timing resistors.

With that in mind, we can design our basic 555 multivibrator to give us an output frequency of about 1500 hertz using preferred component values as shown.

Using the component values given will produce values of: t_{1} = 375uS, t_{2} = 325uS, T = 700uS, ƒ = 1430Hz or 1.43kHz and a duty cycle, D of about 0.535, or 53.5%.

Note also that as the duty cycle is 53.5%, when the 555 astable oscillator is connected to a supply voltage of 9 volts, the average output DC equivalent voltage present on the output, pin 3 will be: 9*0.535 approximately equal to 4.8 volts, and when connected to a supply voltage of 15 volts, the equivalent DC output voltage will be 15*0.535 which equals about 8 volts. This voltage level represents the DC input voltage (V_{IN} to the connected voltage multiplier circuit.

Transformers are very efficient devices for converting an AC primary input voltage to a secondary output voltage, either stepping the secondary voltage up or down with respect to the primary. But what if we wanted to convert a steady state DC voltage from one value to another, then we can not uses transformers for this.

The 555 timer can be used to convert a DC voltage to a much higher DC voltage, and even reversing the polarity of a DC voltage with just a few additional components added to its output pin. Many electronic applications require different low-current voltage supplies to power different parts of a circuit with the simple 555 oscillator above configured as a transformerless DC-to-DC voltage multiplier used to satisfy many of these low-power applications.

The most basic and easily constructed DC-to-DC voltage multiplier is that of the *voltage doubler*. The 555 is configured as an astable multivibrator to supply the input conditions for the “charge pump” circuit created using the diode and capacitor network as shown.

This simple 555 voltage doubler circuit consists of a 555 oscillator and a single capacitor-diode voltage doubler network formed by C_{3}, D_{1}, D_{2} and C_{4}. This voltage doubler circuit multiplies the supply voltage and produces an output that is approximately twice the voltage value of the input voltage minus the diode voltage drops.

When the output at pin 3 is LOW, the 50uF capacitor (C_{3}) charges up to the supply voltage through diode, D_{1} with diode D_{2} off. When the output from the 555 goes HIGH, the voltage across C_{3} discharges through diode D_{2}, as D_{1} is reverse biased, adding its voltage to the source voltage as V_{CC} and C_{3} are now like two voltage sources in series.

The timing cycle from the 555 changes state again from HIGH to LOW and the cycle repeats once again, thus producing a DC load voltage which is twice the original input voltage, that is a multiplication factor of two (voltage doubler). Then a 555 voltage doubler circuit can produce an output voltage from about 10 to 30 volts at very low current.

Another point to note is that the frequency of oscillation of the 555 astable multivibrator used to generate the square-wave input signal will determine the value of the capacitors used, as they along with the connected load value create a RC charging/discharging circuit to filter the output voltage. Too low a capacitance value, or too low the frequency of oscillation will produce ripples in the output voltage waveform and therefore a lower average DC output voltage.

With no-load connected, the output voltage will be twice the 555’s original supply voltage. The actual output voltage will depend on the value of the connected load, R_{L} and the load current, I_{L}. As given, the 555 voltage doubler circuit above can supply about 30mA at the rated voltage.

There are many variations of the voltage doubler circuit above, but each one uses two diode/capacitor pairs to provide the x2 multiplication factor. By adding or cascading more diode/capacitor networks to the voltage doubler, we can create circuits which can create voltage multiplication ratios as high as we want.

So for example, by adding half a diode/capacitor combination to the 555 voltage doubler circuit creates a voltage tripler circuit with a multiplication factor of x3, and adding a second full diode/capacitor section to the 555 voltage doubler circuit will create a voltage quadrupler circuit with a multiplication factor of x4, and so on as shown.

Voltage quadrupler using the 555 timer by cascading together two voltage doubler networks giving an output voltage of approximately 4V_{IN} if losses and diode voltage drops are ignored.

As well as producing voltage multipliers with different positive output voltages, we can also configure them to produce negative output voltages by simply reversing the directions and the polarities of the diodes and capacitors used as shown.

Then we have seen that 555 timer based voltage multipliers can be used to double, triple or even quadruple a single supply voltage to provide various positive and negative output voltages. While in theory there is no limit to the amount of voltage multiplication that can be produced by cascading together multiple diode/capacitor sections to produce progressively higher voltages such as those used in air ionizers or bug zappers. However, care must be taken to ensure against electric shock when dealing with such high output voltages.

We can take this idea of a *555 voltage multiplier* one step further by using the basic 555 timer circuit to produce a DC-to-AC inverter. With the 555 configured to operate as a square-wave oscillator and a few additional components, we can produce a sine-wave output at the desired voltage level, either 120 volts or 240 volts as shown.

So how does the 555 DC-to-AC Inverter circuit work. The 555 timer is configured to oscillate as an astable multivibrator producing a square-wave output the same as before. This time however we want the output frequency to be the same as the AC mains frequency, that is either 50Hz or 60Hz and this is achieved using a 47kΩ potentiometer.

Timing resistance R_{B} consists of a fixed value resistor of 100kΩ in series with a potentiometer of 47kΩ. When the potentiometer is adjusted so that its wiper is in its zero position, R_{B} = 100kΩ (0 + 100kΩ), and when it is adjusted in the opposite direction to its maximum position, R_{B} = 147kΩ (47kΩ + 100kΩ).

So by using the previous formulas, the output frequency from the 555 can be adjusted using the potentiometer from about 46Hz to 65Hz, providing the required 50Hz or 60Hz output frequencies as we would expect to see from the AC mains supply.

The square-wave output frequency from pin 3 of the 555 is fed via a current limiting resistor, R_{1} to the bases of two complementary transistors. When the output is HIGH (current source) the NPN transistor conducts and the PNP transistor is OFF, and when the output is LOW (current sink) the PNP transistor conducts and the NPN transistor is OFF. Thus as the square-wave output signal alternates between HIGH and LOW, it switches one or the other transistor as they are complementary pairs.

Transistors TR_{1} and TR_{2} can be any reasonable complementary NPN and PNP transistor such as the TIP41, 2N2222 and TIP42, 2N2907 respectively, or a matched Darlington pair such as the NPN TIP140, TIP3055 and PNP TIP145, TIP2955 respectively. The choice of output transistors will depend on voltage and current ratings of the transformers primary winding but ideally it should have a low VA rating.

The complementary output stage of TR_{1} and TR_{2} is used to drive the primary winding of a small transformer whose ratio of primary to secondary turns will produce the desired output voltage. However if we were to feed the transformers primary directly from the transistor stage, the output waveform from the transformers secondary winding would be that of a square-wave. Thus as we are building a DC-to-AC inverter, we need some way of converting the 555 timers square-wave output on pin 3 into a sinusoidal shaped waveform from the transformers secondary winding.

The RLC filter circuit connected between the transistor stage and the primary winding acts as an RLC resonance circuit tuned to the required output frequency. However, as we can adjust the output frequency from between 46Hz to 65Hz using the potentiometer, the RLC resonance circuits resonant frequency will not be exact for the 50Hz or 60Hz frequencies, but we can calculate the values for somewhere inbetween.

Using standard preferred component values, the filter network of resistor R_{2}, inductor L_{1} and capacitor C_{3} produce an RLC resonance circuit tuned to about 52Hz. The transformers primary winding is connected across the capacitor producing a reasonably sinusoidal waveform on the secondary at the required voltage determined by the transformers turns ratio.

Then we can use the 555 timer to produce a very basic DC-to-AC inverter at the required AC output voltage and frequency, for example 120V at 60Hz, or 240V at 50Hz, from a single 12 volt DC supply with an output wattage rating depending on the output transistor stage and transformer used.

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]]>The post 555 Circuits Part 1 appeared first on Basic Electronics Tutorials.

]]>As we have seen previously, the 555 timer comes as a single device within an 8-pin dual-in-line package (DIP) or as the 556 device which has two 555 chips in a single 14-pin dual-in-line package. The two 555 timers within the 556 operate independently of each other but share a common V_{CC} supply and ground (0V) connection.

The standard TTL 555 can operate from a supply voltage between 4.5 volts and 18 volts, with its output voltage approximately 2 volts lower than its supply voltage V_{CC}. The 555 can source or sink a maximum output current of 200mA, (but it may get hot at this level), so the circuit variations are unlimited. Note that the CMOS versions of the 555, the 7555 and the 7556 may have different voltage and current ratings.

But first let us remind ourselves of some of the basic formulas we can use to calculate the oscillation frequency.

Where: t_{1} is the output high duration, t_{2} is the output low duration, T is the periodic time of the output waveform, ƒ is the frequency of the output waveform, and 0.693 = ln(2)

When connected as an astable oscillator, capacitor C charges through R_{A} and R_{B} but discharges only through R_{B}. Thus the duty cycle D is determined by the ratio of these two resistors. With the proper selection of resistors R_{A} and R_{B}, duty cycles of between 50 and 100% can be easily set.

The total time period T is given as the capacitor charging time, t_{1} (Output High) plus the discharging time, t_{2} (Output Low) as the capacitor charges and discharges between 1/3Vcc and 2/3Vcc respectively. In this mode of operation the charging and discharging times and therefore the frequency, ƒ which is given as: 1/T, is independent of the supply voltage.

The basic 555 oscillator circuit is very versatile, and we can create a number of interesting variations from it. The simplest 555 free-running astable oscillator circuit connects pin 3 (output) directly to the timing capacitor via a single resistor as shown.

When the output at pin 3 is HIGH, the capacitor charges up through the resistor. When the voltage across the capacitor reaches 2/3Vcc, pin 6 causes the output at pin 3 to change state and goes LOW. The capacitor now discharges back through the same resistor until pin 2 reaches 1/3Vcc causing the output to change state once again. The capacitor continually charges and discharges between 2/3Vcc and 1/3Vcc back and forth through the same resistor creating a HIGH and LOW state at the output, pin 3.

As the capacitor charges and discharges through the same resistor, the duty cycle of this basic arrangement is very close to 50% or 1:1. The series of square wave output pulses produced have a cycle time (T) equal to approximately 2(0.693)*RC or 2lin(2)*RC. The output waveform frequency (ƒ) is therefore equal to: 0.722/RC.

So for example, if we want to generate a 1kHz output square-wave waveform, then R = 3.3kΩ and C = 220nF using preferred component values.

By varying the value of either R or C the 555 astable multivibrator circuit can be made to oscillate at any desired output frequency. But what is the maximum frequency of oscillations we can produce from a single 555 timer chip.

To get the 555 to operate at its highest frequency, it is necessary to continuously retrigger it the instant the output changes state, from high to low, or low to high. The fastest switching speed can be obtained by removing both the R and C timing components and feeding the output signal directly back the trigger inputs.

By connecting the output, pin 3 to both the trigger input, pin 2 and the threshold input, pin 6, every time the output changes state it re-triggers the 555 to change state again. However, the output waveform will not be symmetrical or a square wave but a series of negative pulses.

The highest oscillation frequency obtained using this arrangement will depend on the supply voltage, the type of 555 chip used, TTL or CMOS and the manufacturer as the internal circuitry differs from manufacturer to manufacturer. But it is possible to produce an output frequency as high as 350kHz at 5 volts.

If we go back to the original 555 oscillator circuit and replace the timing capacitor with a large value electrolytic, for example, 220uF, 470uF capacitors, by selecting the appropriate timing resistor or resistors, the frequency of oscillation can be reduced to less than 1Hz. If this is the case, then the 555 circuit stops becoming an oscillator and becomes a timer or delay circuit.

In the time delay circuit, the output remains LOW until the 555 is triggered on pin 2 then goes HIGH for some pre-calculated time after triggering is received. Here the threshold, pin 6 and the discharge, pin 7 are tied together at the junction of the RC timing components.

The trigger pin 7, is held HIGH via resistor R_{1} until the pushbutton switch, S_{1} is closed. Operation of S_{1} momentarily shorts pin 7 to ground and therefore below 1/3Vcc initiating the delay. Once triggered, the 555 timer circuit shown will not respond to any additional triggering by the switch until after the timed delay period has been reached. This makes the circuit useful in switch debounce applications as a single pulse is created no matter how many times the switch is depressed.

The time delay period in which the output is HIGH is given as: 1.1RC in *seconds*, where R is in *Ohms* and C is in *Farads*.

So for our simple 555 time delay circuit, the output delay in which the output is in a HIGH state is calculated as: 1.1*9100*10*10^{-6} = 100ms. By selecting appropriate values of R and C output delays of a few micro-seconds to many hours can be obtained but with long delays, the timing is generally not accurate as the capacitor tolerance becomes large.

This can be overcome by changing the timing resistor to a potentiometer to compensate for the capacitor’s tolerances, or by selecting low leakage electrolytic capacitors. In practice, the timing resistor should not exceed about 10MΩ or a timing capacitor greater than 470uF as both of these combined would give a delay pulse of about 5170 seconds or about 1.5 hours.

We said previously that the duty cycle, that is the ratio of ON time to total cycle time, is limited to between 50% and 100% for the standard 555 oscillator circuit. But some applications may require a specific duty cycle to be set below 50%, that is the t_{1} (HIGH) time is less or shorter than the t_{2} (LOW) time which are set by the ratios of R_{A} and R_{B}.

As the resistance of R_{A} becomes much larger than R_{B}, the duty cycle increases towards unity (100%) as R_{B} approaches zero. Likewise, as the resistance of R_{B} increases with respect to R_{A}, the duty cycle approaches 50% (or 1:1) giving the output waveform a more square-wave appearance. However to get a full 50% duty cycle, R_{A} would need to be zero Ohms which is not allowed as this would short out V_{CC} to ground through the discharge pin 7.

One way of achieving a lower than 50% duty cycle is to include a diode within the RC timing circuit as shown.

The addition of diode, D_{1} across pins 6 and 7 of the basic 555 oscillator circuit, shorts out resistor R_{B} during the charging cycle.

The diode, which can be any general purpose silicon diode, allows the capacitor to charge directly from R_{A}, as R_{A} and D_{1} are effectively in series removing resistor R_{B} from the charging cycle, although a very small leakage current will still flow through R_{B}.

During the discharge cycle when the output at pin 3 is LOW, diode D_{1} is reverse biased so the circuit functions the same as before discharging through resistor R_{B} and into pin 7 of the 555.

Thus during the charging cycle when the output is HIGH, R_{A} and C control the t_{1} timing period, while during the discharging cycle when the output is LOW, R_{B} and C control the t_{2} timing period.

Note that because of the presence of diode, D_{1} across R_{B}, the diodes 0.7 volt forward voltage drop makes the circuit more sensitive to variations in supply voltage, Vcc. Thus the t_{1} timing expression is modified to approximately 0.8RC to account for this diode drop.

We can improve on the previous circuit by adding a second diode, D_{2} in series with the discharging resistor, R_{B} as shown.

With the inclusion of D_{2}, any parallel leakage current flowing through R_{B} during the charging cycle is completely blocked as diode, D_{2} is reverse biased during this timing period.

During the discharging period, the capacitor discharges back through the series connection of D_{2} and R_{B} as diode D_{1} is reverse biased during this cycle.

Thus both the charging and discharging paths for the timing capacitor become identical as the timing capacitor charges through R_{A} and D_{1} and discharges through R_{B} and D_{2} allowing for either timing period to be adjusted without affecting the other.

One interesting version of the improved duty cycle circuit using diodes, is that if you make the two timing resistors, R_{A} and R_{B} identical, that is R_{A} = R_{B}, the duty cycle will be exactly 50% producing a square wave output waveform.

Again the standard 555 astable oscillator equations are modified slightly to account for the inclusion of the diodes, and as before, due to the forward diode voltage drops, the timing periods are sensitive to supply voltage variations.

We can improve once again on the above circuit by using one or two potentiometers is series with the two diodes giving us fully independent variations in the charging and discharging timing periods as shown.

The timing circuit on the left shows the use of two potentiometers within the oscillator design. Using two potentiometers, VR_{1} and VR_{2}, one each in series with the diodes, the timing period for both the charging cycle (output high) and the discharging cycle (output low) can be independently adjusted allowing full control over the duty cycle without affecting the output frequency.

A simpler alternative variation on the previous circuit is by using a single potentiometer to control the two output timing periods at the same time as shown on the right hand circuit. With the potentiometers wiper arm at its center position, the resistive value between point A and the wiper is equal to the resistive value between point B and the wiper, so the duty cycle will be 50%, producing a square wave output waveform.

As the potentiometers wiper arm is varied from the center to point A, the duty cycle decreases. Likewise, as the potentiometers wiper arm is varied in the reverse direction from the center to point B, the duty cycle increases. Thus the duty cycle of the output waveform can be varied from low to high, without changing the output frequency. One very good use of this effect is in controlling the speed of DC motors using *pulse width modulation*.

Pulse width modulation or PWM, is a way of controlling the average voltage value applied to a load by constantly switching it ON and OFF at different duty cycles. Rather than control the rotational speed of a motor by carefully applying less and less voltage to it, we can control its speed by alternatively switching the voltage fully ON and OFF in such a way that the average ON time produces the same effect as a varying the supply voltage.

In effect the control voltage applied across the terminals of the motor is controlled by the duty cycle of the 555’s output waveform which in turn controls the speed of rotation. We could also use this pulse width modulation method to control the brightness of a lamp or LED.

The speed of rotation of the DC motor is controlled using the potentiometer which inturn varies the duty cycle of the output waveform from about 5% to 95%. Resistor R_{1} limits current flow into the base of the switching transistor, and diode D_{3} is used in parallel with the motor to suppression and voltage transients as the motor is switched ON and OFF.

The switching transistor given in the example is a BD220 NPN Power transistor, rated at 70 volts, 4 amps, but any equivalent transistor would do provided it can safely handle the motor load current. The switching transistor may require a heatsink to dissipate the heat.

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]]>The post Sallen and Key Filter appeared first on Basic Electronics Tutorials.

]]>As we have seen in this filters section, electronic filters, either passive or active, are used in circuits where a signals amplitude is only required over a limited range of frequencies. The advantage of using *Sallen-Key Filter* designs is that they are simple to implement and understand.

The Sallen and Key topology is an active filter design based around a single non-inverting operational amplifier and two resistors, thus creating a voltage-controlled voltage-source (VCVS) design with filter characteristics of, high input impedance, low output impedance and good stability, and as such allows individual Sallen-key filter sections to be cascaded together to produce much higher order filters.

But before we look at the design and operation of the *Sallen-key filter*, let’s first remind ourselves of the characteristics of a single resistor-capacitor, or RC network when subjected to a range of input frequencies.

When two (or more) resistors are connected together across a DC supply voltage, different voltage values will be developed across each resistor creating what is basically called a voltage divider or potential divider network.

The basic circuit shown consists of two resistors in series connected across an input voltage, V_{IN}.

*Ohm’s Law* tells us that the voltage dropped across a resistor is the sum of the current flowing through it multiplied by its resistive value, V = I*R, so if the two resistors are equal, then the voltage dropped across both resistors, R1 and R2 will also be equal and is split equally between them.

The voltage developed or dropped across resistor R2 represents the output voltage, V_{OUT} and is given by the ratio of the two resistors and the input voltage. Thus the transfer function for this simple voltage divider network is given as:

But what would happen to the output voltage, V_{OUT} if we changed the input voltage to an AC supply or signal, and varied its frequency range. Well actually nothing, as resistors are generally not affected by changes in frequency (wirewounds excluded) so their frequency response is zero, allowing AC, Irms^{2}*R voltages to be developed or dropped across the resistors just the same as it would be for steady state DC voltages.

If we change resistor R1 above to a capacitor, C as shown, how would that affect our previous transfer function. We know from our tutorials about Capacitors that a capacitor behaves like an open circuit once charged when connected to a DC voltage supply.

Thus when a steady state DC supply is connected to V_{IN}, the capacitor will be fully charged after 5 time constants (5T = 5RC) and in which time it draws no current from the supply. Therefore there is no current flowing through the resistor, R and no voltage drop developed across it, so no output voltage. In other words, capacitors block steady state DC voltages once charged.

If we now change the input supply to an AC sinusoidal voltage, the characteristics of this simple RC circuit completely changes as the DC or constant part of the signal is blocked. So now we are analysing the RC circuit in the frequency domain, that is the part of the signal that depends on time.

In an AC circuit, a capacitor has the property of **capacitive reactance**, **X _{C}** but we can still analyse the RC circuit in the same way as we did with the resistor only circuits, the difference is that the impedance of the capacitor now depends on frequency.

For AC circuits and signals, capacitive reactance (X_{C}), is the opposition to alternating current flow through a capacitor measured in Ohm’s. Capacitive reactance is frequency dependant, that is at low frequencies (ƒ ≅ 0) the capacitor behaves like an open circuit and blocks them

At very high frequencies (ƒ ≅ ∞) the capacitor behaves like a short circuit and pass the signals directly to the output as V_{OUT} = V_{IN}. However, somewhere in between these two frequency extremes the capacitor has an impedance given by X_{C}. So our voltage divider transfer function from above becomes:

Thus changes in frequency, causes changes in X_{C}, which causes changes in the magnitude of the output voltage. Consider the circuit below.

The graph shows the frequency response of this simple 1^{st}-order RC circuit. At low frequencies the voltage gain is extremely low, as the input signal is being block by the reactance of the capacitor. At high frequencies the voltage gain is high (unity) as the reactance is causes the capacitor to effectively become a short-circuit to these high frequencies, so V_{OUT} = V_{IN}

However, there becomes a frequency point where the reactance of the capacitor is equal to the resistance of the resistor, that is: X_{C} = R and this is called the “critical frequency” point, or more commonly called the **cut-off frequency**, or **corner frequency** **ƒ _{C}**.

As the cut-off frequency occurs when X_{C} = R the standard equation used to calculate this critical frequency point is given as:

The cut-off frequency, ƒ_{C} defines where the circuit, in this example, changes from attenuating or blocking all frequencies below, ƒ_{C} and starts to pass all the frequencies above this ƒ_{C} point. Thus the circuit is called a “high pass filter”.

The cut-off frequency is where the ratio of the input-to-output signal has a magnitude of 0.707 and when converted to decibels is equal to –3dB. This is often referred to as a filters 3dB down point.

As the reactance of the capacitor is related to frequency, that is capacitive reactance (X_{C}) varies inversely with applied frequency, we can modify the above voltage divider equation to obtain the transfer function of this simple RC high pass filter circuit as shown.

One of the main disadvantages of an RC filter is that the output amplitude will always be less than the input so it can never be greater than unity. Also the external loading of the output by more RC stages or circuits will have an affect on the filters characteristics. One way to overcome this problem is to convert the passive RC filter into an “Active RC Filter” by adding an operational amplifier to the basic RC configuration.

By adding an operational amplifier, the basic RC filter can be designed to provide a required amount of voltage gain at its output, thus changing the filter from an attenuator to an amplifier. Also due to the high input impedance and low output impedance of an operational amplifier prevents external loading of the filter allowing it to be easily adjusted over a wide frequency range without altering the designed frequency response.

Consider the simple active RC high-pass filter below.

The RC filter part of the circuit responds the same as above, that is passing high frequencies but blocking low frequencies, with the cut-off frequency set by the values of R and C. The operational amplifier, or op-amp for short, is configured as a non-inverting amplifier whose voltage gain is set by the ratio of the two resistors, R_{1} and R_{2}.

Then the closed loop voltage gain, A_{V} in the passband of a *non-inverting operational amplifier* is given as:

A simple 1^{st}-order active high-pass filter is require to have a cut-off frequency of 500Hz and a passband gain of 9dB. Calculate the required components assuming a standard 741 operational amplifier is used.

From above we have seen that the cut-off frequency, ƒ_{C} is determined by the values of R and C in the frequency-selective RC circuit. If we assume a value for R of 5kΩ (any reasonable value would do), then the value of C is calculated as:

The calculated value of C is 63.65nF, so the nearest preferred value used is 62nF.

The gain of the high pass filter in the passband region is to be +9dB which equates to a voltage gain, A_{V} of 2.83. Assume an arbitrary value for feedback resistor, R_{1} of 15kΩ, this gives a value for resistor R_{1} of:

Again the calculated value of R_{2} is 8197Ω. The nearest preferred value would be 8200Ω or 8.2kΩ. This then gives us the final circuit for our active high-pass filter example of:

We have seen that a simple first-order high-pass filters can be made using a single resistor and capacitor producing a cut-off frequency, ƒ_{C} point where the output amplitude is –3dB down from the input amplitude. By adding a second RC filter stage to the first, we can convert the circuit into a second-order high-pass filter.

The simplest second order RC filter consists of two RC sections cascade together as shown. However, for this basic configuration to operate correctly, input and output impedances of the the two RC stages should not affect each others operation, that is they should be non-interacting.

Cascading one RC filter stage with another (identical or different RC values), does not work very well because each successive stage loads the previous one and when more RC stages are added, the cut-off frequency point moves further away from the designed or required frequency.

One way to overcome this problem for a passive filter design is to have the input impedance of the second RC stage at least 10 times greater than the output impedance of the first RC stage. That is R_{B} = 10*R_{1} and C_{B} = C_{A}/10 at the cut-off frequency.

The advantage of increasing the component values by a factor of 10 is that the resulting second-order filter produces a steeper roll-off of 40dB/decade than cascaded RC stages. But what if you wanted to design a 4^{th} or a 6^{th}-order filter, then the calculation of ten times the value of the previous components can be time consuming and complicated.

One simple way to cascade together RC filter stages which do not interact or load each other to create higher-order filters (individual filter sections need not be identical) which can be easily tuned and designed to provide required voltage gain is to use *Sallen-key Filter* stages.

**Sallen-Key** is one of the most common filter configurations for designing first-order (1^{st}-order) and second-order (2^{nd}-order) filters and as such is used as the basic building blocks for creating much higher order filters.

The main advantages of the Sallen-key filter design are:

- Simplicity and Understanding of their Basic Design
- The use of a Non-inverting Amplifier to Increase Voltage Gain
- First and Second-order Filter Designs can be Easily Cascaded Together
- Low-pass and High-pass stages can be Cascaded Together
- Each RC stage can have a different Voltage Gain
- Replication of RC Components and Amplifiers
- Second-order Sallen-key Stages have Steep 40dB/decade roll-off than cascaded RC

However, there are some limitations to the basic Sallen-key filter design in that the voltage gain, A_{V} and magnification factor, Q are closely related due to the use of an operational amplifier within the Sallen-key design. Almost any Q value greater than 0.5 can be realised since using a non-inverting configuration, the voltage gain, A_{V} will always be greater than 1, (unity) but must be less than 3 otherwise it will become unstable.

The simplest form of Sallen-key filter design is to use equal capacitor and resistor values (but the C’s and R’s don’t have to be equal), with the operational amplifier configured as a unity-gain buffer as shown. Note that capacitor R_{A} is no longer connected to ground but instead provides a positive feedback path to the amplifier.

The passive components C_{A}, R_{A}, C_{B} and R_{B} form the second-order frequency-selective circuit.Thus at low frequencies, capacitors C_{A} and C_{B} appear as open circuits, so the input signal is blocked resulting in no output. At higher frequencies, C_{A} and C_{B} appear to the sinusoidal input signal as short circuits, so the signal is buffered directly to the output.

However, around the cut-off frequency point, the impedance of C_{A} and C_{B} will be the same value as R_{A} and R_{B}, as noted above, so the positive feedback produced through C_{B} provides voltage gain and and increase in output signal magnification, Q.

Since we now have two sets of RC networks, the above equation for the cut-off frequency for a Sallen-Key filter is modified too:

If the two series capacitors C_{A} and C_{B} are made equal (C_{A} = C_{B} = C) and the two resistors R_{A} and R_{B} are also made equal (R_{A} = R_{B} = R), then the above equation simplifies to the original cut-off frequency equation of:

As the operational amplifier is configured as a unity gain buffer, that is A = 1, the cut-off frequency, ƒ_{C} and Q are completely independent of each other making for a simpler filter design. Then the magnification factor, Q is calculated as:

Therefore for the unity-gain buffer configuration, the voltage gain (A_{V}) of the filter circuit is equal to 0.5, or -6dB (over damped) at the cut-off frequency point, and we would expect to see this because its a second-order filter response, as 0.7071*0.7071 = 0.5. That is -3dB*-3dB = -6dB.

However, as the value of Q determines the response characteristics of the filter, the proper selection of the operational amplifiers two feedback resistors, R_{1} and R_{2}, allows us to select the required passband gain A for the chosen magnification factor, Q.

Note that for a Sallen-key filter topology, selecting the value of A to be very close to the maximum value of 3, will result in high Q values. A high Q will make the filter design sensitive to tolerance variations in the values of feedback resistors R_{1} and R_{2}. For example, setting the voltage gain to 2.9 (A = 2.9) will result in the value of Q being 10 (1/(3-2.9)), thus the filter becomes extremely sensitive around ƒ_{C}.

Then we can see that the lower the value of Q the more stable will be the Sallen and Key filter design. While high values of Q can make the design unstable, with very high gains producing a negative Q would lead to oscillations.

Design a second-order high-pass *Sallen and Key Filter* circuit with the following characteristics: ƒ_{C} = 200Hz, and Q = 3

To simplify the math’s a little, we will assume that the two series capacitors C_{A} and C_{B} are equal (C_{A} = C_{B} = C) and also the two resistors R_{A} and R_{B} are equal (R_{A} = R_{B} = R).

The calculated value of R is 7957Ω, so the nearest preferred value used is 8kΩ.

For Q = 3, the gain is calculated as:

If A = 2.667, then the ratio of R_{1}/R_{2} = 1.667 as shown.

The calculated value of R_{2} is 5998Ω, so the nearest preferred value used 6000Ω or 6kΩ. This then gives us the final circuit for our Sallen and Key high-pass filter example of:

Then with a cut-off or corner frequency of 200Hz, a passband gain of 2.667, and a maximum voltage gain at the cut-off frequency of 8 (2.667*3) due to Q = 3, we can show the characteristics of this second-order high-pass Sallen and Key filter in the following Bode plot.

We have seen here in this tutorial that the Sallen-Key configuration, also known as a *voltage-controlled, voltage-source (VCVS)* circuit is the most widely used filter topologies due mainly to the fact that the operational amplifier used within its design can be configured as a unity gain buffer or as a non-inverting amplifier.

The basic Sallen-key filter configuration can be used to implement different filter responses such as, Butterworth, Chebyshev, or Bessel with the correct selection of RC filter network. Most practical values of R and C can be used remembering that for a specific cut-off frequency point, the values of R and R are inversely proportional. That is as the value of R is made smaller, C becomes larger, and vice versa.

The Sallen-key is a 2^{nd}-order filter design which can be cascaded together with other RC stages to create higher-order filters. Multiple filter stages need not be the same but can each have different cut-off frequency or gain characteristics. For instance, putting together a low-pass stage and a high-pass stage to create a Sallen and Key band-pass filter.

Here we have looked at designing a Sallen-key high-pass filter, but the same rules apply equally for a low-pass design.The voltage gain, A_{V} of the op-amp determines its response and is set by the voltage divider resistors, R_{1} and R_{2} remembering that the voltage gain must be less than **3** otherwise, the filter circuit will become unstable.

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]]>*Schottky diodes* have many useful applications from rectification, signal conditioning and switching, through to TTL and CMOS logic gates due mainly to their low power and fast switching speeds. TTL Schottky logic gates are identified by the letters LS appearing somewhere in their logic gate circuit code, e.g. 74LS00.

PN-junction diodes are formed by joining together a p-type and an n-type semiconductor material allowing it to be used as a rectifying device, and we have seen that when *Forward Biased* the depletion region is greatly reduced allowing current to flow through it in the forward direction, and when *Reverse Biased* the depletion region is increased blocking current flow.

The action of biasing the pn-junction using an external voltage to either forward or reverse bias it, decreases or increases respectively the resistance of the junction barrier. Thus the voltage-current relationship (characteristic curve) of a typical pn-junction diode is influenced by the resistance value of the junction. Remember that the pn-junction diode is a nonlinear device so its DC resistance will vary with both the biasing voltage and the current through it.

When forward biased, conduction through the junction does not start until the external biasing voltage reaches the “knee voltage” at which point current increases rapidly and for silicon diodes the voltage required for forward conduction to occur is around 0.65 to 0.7 volts as shown.

For practical silicon junction diodes, this knee voltage can be anywhere between 0.6 and 0.9 volts depending upon how it was doped during manufacture, and whether the device is a small signal diode or a much larger rectifying diode. The knee voltage for a standard *germanium diode* is, however much lower at approximately 0.3 volts, making it more suited to small signal applications.

But there is another type of rectifying diode which has a small knee voltage as well as a fast switching speed called a **Schottky Barrier Diode**, or just simply “Schottky Diode”. Schottky diodes can be used in many of the same applications as conventional pn-junction diodes and have many different uses, especially in digital logic, renewable energy and solar panel applications.

Unlike a conventional pn-junction diode which is formed from a piece of P-type material and a piece of N-type material, Schottky Diodes are constructed using a metal electrode bonded to an N-type semiconductor. Since they are constructed using a metal compound on one side of their junction and doped silicon on the other side, the Schottky diode therefore has no depletion layer and are classed as unipolar devices unlike typical pn-junction diodes which are bipolar devices.

The most common contact metal used for Schottky diode construction is “Silicide” which is a highly conductive silicon and metal compound. This silicide metal-silicon contact has a reasonably low ohmic resistance value allowing more current to flow producing a smaller forward voltage drop of around Vƒ<0.4V when conducting. Different metal compounds will produce different forward voltage drops, typically between 0.3 to 0.5 volts.

Above shows the simplified construction and symbol of a Schottky diode in which a lightly doped n-type silicon semiconductor is joined with a metal electrode to produce what is called a “metal-semiconductor junction”. The width of the ms-junction will depend on the type of metal and semiconductor material used, but when forward-biased, electrons move from the n-type material to the metal electrode allowing current to flow. Thus current through the Schottky diode is the result of the drift of majority carriers.

Since there is no p-type semiconductor material and therefore no minority carriers (holes), when reverse biased, the diodes conduction stops very quickly and changes to blocking current flow, as for a conventional pn-junction diode. Thus for a Schottky diode there is a very rapid response to changes in bias and demonstrating the characteristics of a rectifying diode.

As discussed previously, the knee voltage at which a Schottky diode turns “ON” and starts conducting is at a much lower voltage level than its pn-junction equivalent as shown in the following I-V characteristics.

As we can see, the general shape of the metal-semiconductor Schottky diode I-V characteristics is very similar to that of a standard pn-junction diode, except the corner or knee voltage at which the ms-junction diode starts to conduct is much lower at around 0.4 volts.

Due to this lower value, the forward current of a silicon Schottky diode can be many times larger than that of a typical pn-junction diode, depending on the metal electrode used. Remember that Ohms law tells us that power equals volts times amps, (P = V*I) so a smaller forward voltage drop for a given diode current, I_{D} will produce lower forward power dissipation in the form of heat across the junction.

This lower power loss makes the Schottky diode a good choice in low-voltage and high-current applications such as solar photovoltaic panels where the forward-voltage, (V_{F}) drop across a standard pn-junction diode would produce an excessive heating effect. However, it must be noted that the reverse leakage current, (I_{R}) for a Schottky diode is generally much larger than for a pn-junction diode.

Note however that if the I-V characteristics curve shows a more linear non-rectifying characteristic, then it is an *Ohmic contact*. Ohmic contacts are commonly used to connect semiconductor wafers and chips with external connecting pins or circuitry of a system. For example, connecting the semiconductor wafer of a typical logic gate to the pins of its plastic dual-in-line (DIL) package.

Also due to the Schottky diode being fabricated with a metal-to-semiconductor junction, it tends to be slightly more expensive than standard pn-junction silicon diodes which have similar voltage and current specifications. For example, the 1.0 Ampere 1N58xx Schottky series compared to the general purpose 1N400x series.

The Schottky diode also has many uses in digital circuits and are extensively used in Schottky transistor–transistor logic (TTL) digital logic gates and circuits due to their higher frequency response, decreased switching times and lower power consumption. Where high speed switching is required, Schottky based TTL is the obvious choice.

There are different versions of Schottky TTL all with differing speeds and power consumption. The three main TTL logic series which use the Schottky diode in its construction are given as:

- Schottky Diode Clamped TTL (S series) – Schottky “S” series TTL (74SXX) is an improved version of the original diode-transistor DTL, and transistor-transistor 74 series TTL logic gates and circuits. Schottky diodes are placed across the base-collector junction of the switching transistors to prevent them from saturating and creating propagation delays allowing for faster operation.
- Low-Power Schottky (LS series) – The transistor switching speed, stability and power dissipation of the 74LSXX series TTL is better than the previous 74SXX series. As well as a higher switching speed, the low-power Schottky TTL family consumes less power making the 74LSXX TTL series a good choice for many applications.
- Advanced Low-Power Schottky (ALS series) – Additional improvements in the materials used to fabricate the ms-junctions of the diodes means that the 74LSXX series has reduced propagation delay time and much lower power dissipation compared to the 74ALSXX and the 74LS series. However, being a newer technology and inherently more complex design internally than standard TTL, the ALS series is slightly more expensive.

All the previous Schottky TTL gates and circuits use a Schottky clamped transistor to prevent them from being driven hard into saturation.

As shown, a Schottky clamped transistor is basically a standard bipolar junction transistor with a Schottky diode connected in parallel across its base-collector junction.

When the transistor conducts normally in the active region of its characteristics curves, the base–collector junction is reverse biased and so the diode is reverse biased allowing the transistor to operate as a normal npn transistor. However, when the transistor starts to saturate, the Schottky diode becomes forward biased and clamps the collector-base junction to its 0.4 volt knee value, keeping the transistor out of hard saturation as any excess base current is shunted through the diode.

Preventing the logic circuits switching transistors from saturating decreases greatly their propagation delay time making Schottky TTL circuits ideal for use in flip-flops, oscillators and memory chips.

We have seen here that the **Schottky Diode** also known as a **Schottky Barrier Diode** is a solid-state semiconductor diode in which a metal electrode and an n-type semiconductor form the diodes ms-junction giving it two major advantages over traditional pn-junction diodes, a faster switching speed, and a low forward bias voltage.

The metal–to-semiconductor or ms-junction provides a much lower knee voltage of typically 0.3 to 0.4 volts compared against a value of 0.6 to 0.9 volts seen in a standard silicon base pn-junction diode for the same value of forward current. Variations in the metal and semiconductor materials used for their construction means that silicon carbide (SiC) Schottky diodes are able to turn “ON” with with a forward voltage drop as little as 0.2 volts with the Schottky diode replacing the less used germanium diode in many applications requiring a low knee voltage.

Schottky diodes are quickly becoming the preferred rectification device in low voltage, high current applications for use in renewable energy and solar panel applications. However, compared to pn-junction equivalents Schottky diode reverse leakage currents are greater and their reverse breakdown voltage lower at around 50 volts.

A lower turn-on voltage, faster switching time and reduced power consumption makes the Schottky diode extremely useful in many integrated-circuit applications with the 74LSXX TTL series of logic gates being the most common.

Metal–semiconductor junctions can also be made to operate as “Ohmic contacts” as well as rectifying diodes by depositing the metal electrode onto heavily doped (and thus low-resistivity) semiconductor regions. Ohmic contacts conduct current equally in both directions allowing semiconductor wafers and circuits to connect an to external terminals.

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