FPGA Blog

Actel Receives ISO/TS 16949:2002 Certification for ProASIC3

Ken Cheung — Tue, 15 Jul 2008 17:04:13 +0000

Actel Corporation (Nasdaq: ACTL) has received ISO/TS 16949:2002 certification. When combined with AEC-Q100 Grade 1 and Grade 2 qualification of its ProASIC(R)3 devices and the company's Production Part Approval Process (PPAP) documentation, the new certification ensures that customers can deploy Actel's automotive grade, low-power field-programmable gate array (FPGA) and confirms that the company's design, development and production procedures meet the standard's strict guidelines.

Actel's flash-based FPGA devices offer the industry's lowest power and critical firm error immunity levels not achieved by SRAM-based solutions. This enables a wide variety of transportation vehicles — from standard automobiles to trucks and locomotives — to leverage the flexibility, performance and overall lower program costs of using FPGAs in high-reliability applications. To date, more than 70% of the Actel's automotive-grade, flash-based devices are used in "under-the-hood" applications such as powertrain, safety and transmission control modules.

The ProASIC3 family also offers on-chip flash memory for FPGA switch control, making them immune to neutron-induced firm errors which can cause configuration upsets — a mandatory requirement in an industry driving toward zero defects. Actel's automotive-grade products provide the first viable alternative to complex and costly application-specific integrated circuit (ASIC) technology in under-the-hood applications.

More info: Actel

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Using HDL Simulation for Xilinx Virtex-5 FPGAs

Ken Cheung — Mon, 14 Jul 2008 21:01:33 +0000

Nu Horizons Electronics is offering a seminar titled "Using HDL Simulation for Xilinx Virtex-5 FPGAs." The event will take place from 9:00am to 1:30pm on July 22nd, 2008 in San Jose, CA. Lunch and refreshments will be provided. The seminar features hands-on labs and is intended for Design Engineers, Verification Engineers, and EDA Tool Managers.

Blurb:

Designers of modern FPGAs face large variety of challenges while working on their projects: they require speed tget results quickly, but high-end debugging features and good visibility of design elements is alsin demand. The ability toptimize your tool performance and set debugging options properly is critical, letting you get better results faster and increasing your job security.

The workshop (lecture with labs using Xilinx design as a vehicle) will show the attendees how tfine-tune simulations for maximal speed / most efficient debugging and present the latest, advanced verification techniques in action. The topics covered in presentation include: managing projects in Aldec Riviera-PRO, optimizing compilation and simulation, debugging techniques (smart waveform comparison, various flavors of coverage, etc.) and design analysis (design profiling and linting).

Topics

Overview
Getting Started with Riviera-PRO
Lab1
High Performance Xilinx Simulation
Lab2
Debugging the Design
Lab3
Waveform Compare
Lab4
Automatic Testbench Generation
Lab5
Coverage Tools
Lab6
Profiling and Linting
Lab7

More info: Using HDL Simulation for Xilinx Virtex-5 FPGAs Seminar

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Xilinx at Nuclear and Space Radiation Effects Conference

Ken Cheung — Thu, 10 Jul 2008 17:02:09 +0000

Xilinx, Inc. (Nasdaq: XLNX) will showcase its space enabling solutions at the IEEE Nuclear and Space Radiation Effects Conference (NSREC). The vent will take place July 14-18, 2008 in Tucson, Arizona. NSREC is an annual meeting of engineers and scientists presents the latest techniques for enhancing the performance of microelectronic devices and circuits that are used in radiation environments.

Xilinx will demonstrate and present the following at NSREC:

Fault-Injection Upset Simulator
Demonstration of a beam upset simulator based on fault injection and uses the same hardware as in-beam testing. The system, developed by the Radiation Test Consortium (XRTC), leverages the reconfigurability of Xilinx FPGAs and is capable of injecting simulated upsets at a rate of over 3 million per minute while verifying design functionality.

An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs
Heather Quinn, Paul Graham, Los Alamos National Laboratory
Tuesday, July 15
Session C-2, 3:40 p.m.

Xilinx Virtex-5 Field Programmable Gate Array Dose Rate Upset Investigations
Alonzo Vera, Daniel Llamocca, University of New Mexico; Joe Fabula, Xilinx; William Kemp, SES Consultants; Walter Shedd, David Alexander, Air Force Research Lab
Thursday, July 17
Session W-16, 2:30 - 4:30 p.m.

Static Upset Characteristics of the 90 nm Virtex-4QV FPGAs
Gary M. Swift, Carl Carmichael, Chen Wei Tseng, Greg Miller, Xilinx, Inc.; Gregory R. Allen, JPL; Jeffrey S. George, The Aerospace Corporation
Thursday, July 17
Session W-18, 2:30 - 4:30 p.m.

Neutron Soft Errors in Xilinx FPGAs at Lawrence Berkeley National Laboratory
Jeffrey George, Rocky Koga, The Aerospace Corporation; Margaret A. McMahan, Lawrence Berkeley National Laboratory
Thursday, July 17
Session W-21, 2:30 - 4:30 p.m.

Upset-Induced Failure Signatures, Recovery Methods, and Mitigation Techniques in a High-Speed Serial Data Link for Space Applications
Keith Morgan, Michael Caffrey, Mark Dunham, Paul Graham, Heather Quinn, LANL; Carl Carmichael, Tony Duong, Austin Lesea, Greg Miller, Gary Swift, Chen Wei Tseng, Yiding Wu, Xilinx; Roberto Monreal, SEAKR; Greg Allen, JPL
Thursday, July 17
Session PF-9

More info: NSREC | Xilinx Aerospace and Defense

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Enterpoint Craignell Modules Feature Xilinx Spartan-3E FPGA

Ken Cheung — Wed, 09 Jul 2008 23:46:34 +0000

The Craignell modules, from Enterpoint, offer alternative procurement solutions for hard to find components in DIL28, DIL32, DIL36 and DIL40 packages. The heart of the Craignell modules is a Xilinx Spartan-3E FPGA, which performs the logic or memory function of the obsolete component being replaced. The high density of the FPGA solution allows functions of up to 500,000 gates to be implemented. This allows logic functions as complicated as a 8088 microprocessor or memory devices as large as 16Mbit to be replicated in a single Craignell module. The Craignell modules are available now and are priced from GBP£25, US$50, in 100 off quantities.

In addition to the FPGA, Craignell modules contain power regulators and I/O buffering to allow operation from a single supply between 3V and 5.5V and can tolerate and drive CMOS levels on all I/Os making the module highly adaptable.

Enterpoint offers the Craignell modules in either raw un-programmed format for customers to implement their own logic functions or as turnkey solutions with design of replacement logic functions already implemented. Typical replacement, or enhancement, functions replicated in Craignells include Microprocessors, UARTs, PIOs, Counter Timers, Clock Generators SRAM, Eprom, Flash, FIFOs and Dual Port Memories.

More info: Enterpoint

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Ambric University Research Program

Ken Cheung — Wed, 09 Jul 2008 16:41:07 +0000

Ambric's University Program has now reached 13 members worldwide. All of the program members use Ambric's Massively Parallel Processor Array (MPPA) chips and aDesigner software development tools to tackle leading-edge research projects more effectively than with the traditional architectures and development tools of digital signal processors (DSPs) and field-programmable gate arrays (FPGAs). The 1.2 TeraOPS performance and highly scalable architecture of Ambric MPPA chips are ideal for high-performance parallel processing applications — such as medical imaging, video, wireless, image recognition, and defense.

Ambric University Program Members and their applications:

U.S.A.	International
Boston University Protein Docking Simulation	Imperial College London, U.K. Financial Market Simulation
Brigham Young University Computer Vision, Image Processing	Halmstad University, Sweden LTE software-defined radio
Lawrence Livermore National Labs Image Recognition, Signal Processing	University of British Columbia, Canada Computer architecture
Portland State University Machine Learning	University of Santiago, Spain Video encoding
University of Southern California Medical Ultrasound	University of Toronto, Canada Image processing
University of South Carolina Medical Image Processing
Virginia Tech Software-defined Radio
University of Washington Video Encoding, Computer Architecture

More info: Ambric's University Progam

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Evatronix C80186XL and C6502 Soft IP Cores

Ken Cheung — Tue, 08 Jul 2008 17:24:14 +0000

Evatronix SA introduced their C80186XL and C6502 soft IP cores. The cores are aimed at original chip replacement applications. Significant effort was undertaken to achieve the degree of reliability that guarantees trouble-free porting of the existing software to FPGA or ASIC based core implementations. C6502 and C80186XL IP cores are available for licensing immediately. Netlist or full source code, single or multiple use licences are available. Other versions of the 80186 architecture might be developed under Evatronix' design services contract according to customer needs.

The C6502 IP core features extreme efficiency - it takes as little as 2.4K gates at 79MHz when area optimized and 3.2K gates at 177MHz when speed optimized for ASIC technology. FPGA speed optimized implementations of the C6502 require no more than 390 slices in Xilinx FPGAs, while area optimized ones require slightly more than 300 slices.

The C80186XL is a high performance 16-bit microprocessor IP core designed to be a pin replacement of Intel[tm] 80c186xl chip. The core implements the same widely known instruction set as its chip predecessor, as well as an identical set of peripherals - Timer and Refresh Control Units, two independent DMA channels. The architecture, which derives from the speed-optimized C80186TX design, allows fast development of other 80186-compliant IP cores that would replace the following chips: 80c186ea, 80c186ec by Intel[tm] or AM186ER, AM186ED, AM186ES by AMD[tm].

Both designs are strictly synchronous with a synchronous reset and no internal tri-states. The provided set of functional inputs, outputs and control signals make creation of a pin compatible device a straightforward task. The cores are also an appealing solution for low volume applications; the C80186XL can be easily implemented into the inexpensive Altera device (Cyclone III EP3C16).

More info: Evatronix

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eASIC Nextreme Zero Mask-Charge ASIC Powers Nexus Chips

Ken Cheung — Tue, 08 Jul 2008 17:18:28 +0000

eASIC Corporation announced that Nexus Chips used eASIC's Nextreme zero mask-charge ASIC in its latest 3D graphics acceleration system. By using Nextreme, Nexus Chips was able to obtain twice the performance while reducing power consumption by 80% compared to the FPGA that was previously being used. Nexus Chips graphic acceleration devices are targeted at 3D gaming applications for cellular phones and mobile instruments. Nextreme's fast logic fabric and dedicated memories were ideal for implementing fast video datapaths required in Nexus Chips' latest acceleration system.

Nexus Chips selected eASIC's zero-mask charge, fast turnaround ASICs for they offer the flexibility and rapid time-to-market of FPGAs, but with significantly higher performance, lower cost and lower power per device. Nextreme devices provide a greener, lower power alternative to FPGAs. Nextreme devices replace millions of SRAM cells used for interconnect in FPGAs with a single via layer interconnect to dramatically reduce the die size and power consumption.

More info: eASIC

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QuickLogic PolarPro Platform Offers Flexible Upgrade for Smartphones

Ken Cheung — Mon, 07 Jul 2008 17:32:22 +0000

QuickLogic® Corporation's (NASDAQ:QUIK) addition of high-speed UARTs to the library of functions for its low-power, configurable Customer Specific Standard Product (CSSP) logic platforms for consumer electronics, offers a power-efficient single-chip solution to expand the interfacing capability of a mobile application processor to support high-data rate Bluetooth, as well as the integration of further high-desirability peripherals such as GPS.

The PolarPro platform, which is one of QuickLogic's CSSPs, provides smart phone developers with a means of expanding the native host controller resources of the phone's mobile application processor. PolarPro devices consume less than 10 microamps in standby mode and comes in TFBGA packages as compact as 5×5 mm, can easily integrate two high speed UARTs and an additional SDIO port, as well as the processor interface required.

The CSSP approach provides a low power, single-chip solution that contrasts well against alternative implementation strategies. There are commercial devices available for additional SDIO host controllers, or devices offering multiple high-speed UARTs, but using both would eat up valuable real estate on an already densely packed PCB. Migrating to another state-of-the-art processor is always an alternative, but this demands a major investment in software porting effort, as well as time. Conventional logic could also implement the functionality required, but this technology is generally viewed as too power hungry and costly for consumer applications such as this.

The first platform in QuickLogic's latest PolarPro II family offers a capacity of 27 Customizable Building Blocks (CBBs), a measure of the level of functionality that can be integrated. A high-speed UART from QuickLogic's library requires 5 CBBs, and an SDIO port, 15. Together with the logic required to implement an application processor interface, this device provides a cost effective solution for the smartphone configuration discussed. Other, larger PolarPro platforms are available for OEMs and ODMs that require more functionality, as well as devices that combine hard-wired functions with a programmable fabric.

More info: QuickLogic

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Webcast: Designing Multiservice Access Nodes

Ken Cheung — Tue, 01 Jul 2008 16:58:40 +0000

Altera has an On-Demand webcast entitled, Designing Multiservice Access Nodes for Cost, Power, and Features. The event presents some FPGA-based solutions for multiservice access nodes (MSAN). The webinar is intended for system architects, engineering management, and MSAN engineers. After viewing the on-demand seminar, you will:

Understand how to meet cost, power, and feature objectives for your MSAN application
Be aware of the pre-built and building-block solutions that can accelerate your design process
Learn about the cost advantages programmable logic can bring to an MSAN architecture

More info: Designing Multiservice Access Nodes for Cost, Power, and Features

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533 Mbps DDR2 SDRAM Solution for eASIC Nextreme

Ken Cheung — Mon, 30 Jun 2008 21:03:28 +0000

eASIC Corporation and Northwest Logic introduced a silicon-proven 533 Mbps DDR2 SDRAM solution for eASIC's low-cost Nextreme family of devices. The combination of eASIC's Nextreme and Northwest Logic's DDR2 SDRAM Memory Interface Solution provides 60% higher performance than mainstream low-density FPGAs, which are typically limited to 333 Mbps or less performance. The solution utilizes Northwest Logic's high-performance DDR2 SDRAM Controller Core and eASIC-specific DDR PHY to provide an easy-to-use, one-stop-shop solution for eASIC's Nextreme devices.

Northwest Logic's DDR2 SDRAM Memory Interface Solution combines Northwest Logic's high-performance, fully featured DDR2 SDRAM Controller with its eASIC-specific DDR PHY. This DDR PHY leverages the built-in DDR I/Os and DLLs of eASIC's Nextreme devices. The solution includes a variety of add-on peripherals including AHB/AXI Interface, Multi-Port Front-End and ECC Cores, which make it straightforward to integrate with other sub-systems. Northwest Logic's eASIC-based DDR2 SDRAM Interface Solution has been fully characterized to support robust 533 Mbps DDR2 SDRAM operation. Contact Northwest Logic for a detailed characterization report.

More info: eASIC | Northwest Logic

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