FPGA Blog http://fpgablog.com FPGA (field programmable gate array) and structured ASIC information Tue, 30 Jun 2009 20:51:45 +0000 http://wordpress.org/?v=2.7 en hourly 1 http://creativecommons.org/licenses/by-nc-sa/2.0/fpgabloghttp://feedburner.google.comSubscribe with My Yahoo!Subscribe with NewsGatorSubscribe with My AOLSubscribe with BloglinesSubscribe with NetvibesSubscribe with GoogleSubscribe with Pageflakes Rapid FPGA Development for Wireless Applications Workshop http://fpgablog.com/posts/sdr-forum-ip-cores/ http://fpgablog.com/posts/sdr-forum-ip-cores/#comments Tue, 30 Jun 2009 20:51:45 +0000 Ken Cheung http://fpgablog.com/?p=1359 The SDR Forum will hold its 64th General Meeting September 14-17 in San Jose, California. The meeting will feature a workshop, “Rapid FPGA Development for Wireless Applications – IP Cores, Tools and Standards.” The FPGA workshop will provide communications systems engineers with the knowledge they need to implement software defined and cognitive radio systems that utilize FPGA-based processing. Speakers at this workshop will include representatives of The MathWorks, Mercury Computer, Open Cores Protocol – International Partnership, Objective Interface Systems, PrismTech, Synopsis, and Xilinx.

More information: SDR Forum Meeting Registration Form

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]]> http://fpgablog.com/posts/sdr-forum-ip-cores/feed/ Pentek Model 4996A-207 VxWorks Board Support Package for Model 4207 http://fpgablog.com/posts/wind-river-powerpc-fpga/ http://fpgablog.com/posts/wind-river-powerpc-fpga/#comments Tue, 30 Jun 2009 18:28:26 +0000 Ken Cheung http://fpgablog.com/?p=1355 Pentek announced the VxWorks Board Support Package (BSP) for their Model 4207 processor board. The Model 4207 PowerPC and FPGA platform now supports the Wind River’s VxWorks real-time operating system (RTOS). The VxWorks BSP provides software developers with a complete library of hardware-initialization, control, and application functions fully compatible with Wind River’s Workbench development environment. Pentek Model 4996A-207 VxWorks Board Support Package for Model 4207 is available immediately with prices starting at $3,000 USD.

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]]> http://fpgablog.com/posts/wind-river-powerpc-fpga/feed/ OptNgn FFT WFTA Kernels Library for Mentor Precision RTL Synthesis http://fpgablog.com/posts/winograd-fourier-transform/ http://fpgablog.com/posts/winograd-fourier-transform/#comments Tue, 30 Jun 2009 17:00:15 +0000 Ken Cheung http://fpgablog.com/?p=1351 OptNgn has validated their FFT WFTA Kernels Library of streaming IP cores for use with Mentor Graphics Precision RTL Synthesis. The Winograd Fourier Transform (WFTA) kernels, along with their derivative 1D and 2D libraries, represent a vendor independent and high throughput way to use the cache-free FFT power available in FPGA coprocessors. Designers can now use libraries of cost effective RTL FFT elements in both their FPGAs and ASICs, knowing that they can be highly optimized by the Mentor Precision RTL Synthesis toolset. The FFT libraries are ideal for applications in wireless (3/4GPP LTE OFDM/MIMO) and convolution flow based signal filtering and object recognition in the audio, video, and scientific areas.

More information: OptNgn Software

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]]> http://fpgablog.com/posts/winograd-fourier-transform/feed/ Altera Cyclone III LS FPGA Family http://fpgablog.com/posts/cyclone-3-ls-fpgas/ http://fpgablog.com/posts/cyclone-3-ls-fpgas/#comments Mon, 29 Jun 2009 18:46:58 +0000 Ken Cheung http://fpgablog.com/?p=1347 Altera introduced the Cyclone III LS low-power FPGA family. The devices offer the highest logic, memory, and DSP density per board area. The Cyclone III LS are the lowest power FPGAs at less than 0.25W of static power for 200K logic elements (LEs). The Cyclone III LS FPGAs are ideal for power and board-space-sensitive applications in all market segments including military and industrial. Cyclone III LS devices are shipping now.

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]]> http://fpgablog.com/posts/cyclone-3-ls-fpgas/feed/ Lattice MachXO PLD .8mm Pitch Chip Array BGA Package http://fpgablog.com/posts/cabga256-xo640-xo1200-xo2280/ http://fpgablog.com/posts/cabga256-xo640-xo1200-xo2280/#comments Mon, 29 Jun 2009 16:00:49 +0000 Ken Cheung http://fpgablog.com/?p=1343 Lattice Semiconductor introduced a 0.8-mm pitch 256-pin Chip-Array BGA (caBGA256) package for its MachXO PLD family. The Mach XO640, XO1200, and XO2280 devices are now available in the 14 x 14 mm, caBGA256 package with up to 211 user I/O. The new packages provide designers with 10% lower cost and 30% reduction in board area than previously available on 1.0-mm pitch 256-pin Fine-Pitch Thin BGA (ftBGA256) packages. The new MachXO640, XO1200 and XO2280 caBGA256 device packages are supported in Lattice’s ispLEVER version 7.2, Service Pack 2 software. Production devices of the Mach XO640, XO1200, and XO2280 in the caBGA256 package are available now. Volume pricing for the Mach XO640 caBGA256 is $2.75 in 250,000 unit volumes.

More information: Lattice MachXO Reconfigurable Programmable Logic Devices

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]]> http://fpgablog.com/posts/cabga256-xo640-xo1200-xo2280/feed/ Mentor Graphics Precision RTL Supports Xilinx Virtex-6, Spartan-6 FPGAs http://fpgablog.com/posts/logic-physical-synthesis/ http://fpgablog.com/posts/logic-physical-synthesis/#comments Wed, 24 Jun 2009 22:10:53 +0000 Ken Cheung http://fpgablog.com/?p=1339 Support for the Xilinx Virtex-6 and Spartan-6 Field Programmable Gate Arrays (FPGAs) is available now in the Mentor Graphics Precision RTL and Precision RTL Plus products. The new support delivers logic and physical synthesis for quickly implementing complex designs that meet target specifications. Mentor is the first EDA synthesis provider to offer physical synthesis support for Virtex-6 and Spartan-6 designs. Its push-button physical synthesis capability works in conjunction with the new Xilinx ISE Design Suite 11.2 to provide superior Quality-of-Results (QoR). Designers can also leverage Precision’s industry-leading SystemVerilog and mixed language support to implement their designs for Virtex-6 and Spartan-6 FPGAs. During the implementation cycle, customers with large designs can reduce run time by utilizing Precision’s unique automatic incremental synthesis and its integration with Xilinx SmartCompile technology.

More information: Mentor Graphics

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]]> http://fpgablog.com/posts/logic-physical-synthesis/feed/ Xilinx Virtex-6 FPGA ML605 and Spartan-6 FPGA SP601 Evaluation Kits http://fpgablog.com/posts/xilinx-base-targeted-design-platform/ http://fpgablog.com/posts/xilinx-base-targeted-design-platform/#comments Wed, 24 Jun 2009 20:56:57 +0000 Ken Cheung http://fpgablog.com/?p=1335 The Xilinx Base Targeted Design Platform accelerates the development of system-on-chip (SoC) solutions with Xilinx Virtex-6 and Spartan-6 field programmable gate arrays (FPGAs). The Xilinx Base Targeted Design Platform consists of evaluation kits that contain the basic building blocks common in virtually all system designs to address a broad set of markets and applications. Designers are able to slash development time by as much as half compared to traditional design methodologies. Reference designs then guide designers on best practices for integrating custom elements into the base design and implementing advanced features, such as DDR2 and DDR3 memory interfaces, high-speed serial I/O, and on-chip clocking resources. Board schematics and layout files further streamline the design process.

Read more Xilinx Virtex-6 FPGA ML605 and Spartan-6 FPGA SP601 Evaluation Kits

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]]> http://fpgablog.com/posts/xilinx-base-targeted-design-platform/feed/ Prototyping and Functional Verification for Radiation Tolerant Designs http://fpgablog.com/posts/space-flight-systems-2/ http://fpgablog.com/posts/space-flight-systems-2/#comments Wed, 24 Jun 2009 16:47:23 +0000 Ken Cheung http://fpgablog.com/?p=1331 Actel will conduct an educational webinar from 3:00 to 4:00 pm CEST (11:00 am - 12:00 pm PDT) on Thursday, June 25, 2009. The online event is titled, Prototyping & Functional Verification for Radiation Tolerant Space-Flight Systems Designs. The webcast will introduce a prototyping solution for RTAX-S/SL and RTSX-SU devices, using ProASIC 3 FPGA technology with Aldec prototyping boards. The webinar presents a new complimentary reprogrammable prototyping design flow from Aldec. The presentation features a case study, from design to prototype, and includes development ROI and the benefits of using the Aldec prototyping solution for space-flight systems design.

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]]> http://fpgablog.com/posts/space-flight-systems-2/feed/ Cryptography Research DPA Workstation v6.16 with SASEBO-G Support http://fpgablog.com/posts/cri-fpga-images/ http://fpgablog.com/posts/cri-fpga-images/#comments Tue, 23 Jun 2009 17:01:59 +0000 Ken Cheung http://fpgablog.com/?p=1327 Cryptography Research (CRI) has integrated the SASEBO-G board with their DPA Workstation software to enable testing of FPGA images against side channel attacks such as Simple Power Analysis (SPA) and Differential Power Analysis (DPA). DPA Workstation v6.16 includes the capability to test FPGAs using the SASEBO-G board developed by the National Institute of Advanced Industrial Science and Technology (AIST). The release also adds improved visualization tools for interpretation and manipulation of power analysis waveforms.

Read more Cryptography Research DPA Workstation v6.16 with SASEBO-G Support

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]]> http://fpgablog.com/posts/cri-fpga-images/feed/ Actel RTAX FPGA Family Enhancements http://fpgablog.com/posts/space-flight-fpgas/ http://fpgablog.com/posts/space-flight-fpgas/#comments Wed, 17 Jun 2009 15:49:30 +0000 Ken Cheung http://fpgablog.com/?p=1321 Actel has made enhancements to their radiation-tolerant RTAX-S and RTAX-SL space-flight FPGAs. The RTAX-S/SL FPGA family is ideal for space-flight applications requiring built-in protection from radiation-induced single-event upset (SEU) events. RTAX-S/SL offers high performance at densities of up to 4 million equivalent system gates and 840 user I/Os for space-based applications. The RTAX-S/SL family features SEU-hardened flip-flops implemented without any user intervention, and offers the benefits of user-implemented triple module redundancy (TMR) without the associated overhead.

Read more Actel RTAX FPGA Family Enhancements

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