si-list

[SI-LIST] Re: PCB thin dielectrics (Istvan Novak)

Hi Ivor, To answer your base question, yes, thin laminates offer a practical way to increase PCB layer count if you want to keep overall thickness fixed. As others pointed out, you will need to look at all important aspects: among others cost, manufacturing concerns, availability and other practical limitations, such as in larger rigid boards you probably will need to limit the thin laminates to power-ground sandwiches. If a 2-mil laminate thickness buys you enough vertical room, the ...

[SI-LIST] Re: PCB thin dielectrics (steve weir)

Lee, the DuPont HK04 polyimide and Oak Mitsui BC24 are fairly interchangeable. Best Regards, Steve. Lee Ritchey wrote: Problem with most of these materials is they are single source with all that entails. I do just fine with standard laminates by using thin ...

[SI-LIST] Re: Vectra LCP-335 (Scott McMorrow)

Leonard Use 3.3 with a loss tangent of .008 @ 10 GHz as a good average. LCP is all over the place and actual local Er depends on how much glass is contained in any section of the extrusion. Thiner sections contain less glass. Thicker sections are closer to the 30% average loading for this material. You'll find that loss tangent for these connectors does not much matter. Scott ...

[SI-LIST] Re: PCB thin dielectrics (Andresakis, John)

Gentlemen, As Lee points out, it is an engineer's job to avoid single sourcing when possible. But as Steve indicated, there are 2 sources of 1 mil material. The HK04 (DuPont) and BC24 (Oak-Mitsui) products are used by a number of companies as interchangeable. Ivor, for what it sounds like what you are trying to do, either material would be acceptable. Let me know if you further information on our BC24 or other materials. ...

[SI-LIST] Re: Vectra LCP-335 (Kenneth W. Egan)

Hoechst Celanese Corp manufactures this material. Dielectric constant of 3.25 and a dissipation factor of 0.024 at 60 Hz. The polymer paper has a UL94-V0 rating and an in-plane CTE of less than 10 ppm/ C. The alleged advantages of this material over the aramid mat are the lower dielectric constant andvery low moisture absorption, less than 0.02%. Probably need to contact Hoechst to get material properties or a test lab to get the loss tan / Dk to 20G. ...

[SI-LIST] Re: XAUI/PCIe/SATA/HDMI simulations using HyperLynx (Beal, Weston)

Yes. You should update HyperLynx to 8.0, the latest release. -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [] On Behalf Of Rama Mohan Reddy Boreddy Sent: Friday, December 18, 2009 10:06 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] XAUI/PCIe/SATA/HDMI simulations using HyperLynx ...

[SI-LIST] Re: XAUI/PCIe/SATA/HDMI simulations using HyperLynx (Carrier, Patrick)

Hello Rama-- HyperLynx has quite extensive support for SERDES interfaces such as XAUI/PCIe/SATA/HDMI. In fact, we have design kits available on SupportNet for those busses. These are available with your SupportNet login and can be found at: ndex.cfm Also, a recorded webinar on SERDES analysis can be found online at: ...

[SI-LIST] Re: PCB thin dielectrics (Lee Ritchey)

Problem with most of these materials is they are single source with all that entails. I do just fine with standard laminates by using thin prepregs between the power planes. This does not result in single sourcing. I know that puts a crimp in those companies that offer special materials, but an engineer's job is to do what he can to avoid single sources when doing designs. Sorry Steve! Didn't mean to step on you here. Lee Ritchey ...

[SI-LIST] XAUI/PCIe/SATA/HDMI simulations using HyperLynx (Rama Mohan Reddy Boreddy)

Hi, Previously I have used Hyper Lynx 7.7 for SI Analysis to simulate DDR2 SDRAM which operates at 133 MHz. For current project, i need to simulate high speed interfaces such as XAUI/PCIe/SATA/HDMI. Please let us know whether HyperLynx supports this high speed interfaces. Regards, Rama ...

[SI-LIST] Vectra LCP-335 (Leonard Dieguez)

I'm using a Samtec connector for a project that I'm on and the plastic they are using is Vectra LCP-335 or just LCP I believe does anyone have the basic electrical properties for this material so I can do the proper 3D EM simulations? I would need loss tangent and Dk to start with. I would be nice to have these values out to 20 / 25 Ghz. Leonard Dieguez High Speed IO Applications, Altera Corporation ...

[SI-LIST] Re: PCB thin dielectrics (Ray Anderson)

There are a number of papers on the subject on Istvan Novak's web pages () Most of the ones related to thin dielectrics are from the 2044-2007 time frame but I think most of the info is still relevant. -Ray Anderson Xilinx Inc. -----Original Message----- ...

[SI-LIST] Re: PCB thin dielectrics (wolfgang . maichen)

Hi Ivor, such thin dielectrics are mostly used for power/ground plane pairs and possibly for low-speed (thus not impedance controlled) signal layers. They aren't as good for controlled-impedance signal layers because the trace widths necessary to achieve e.g. 50 Ohm characteristic impedance become impractically narrow, which results in very poor impedance control and high skin loss. For power/gnd pairs though they are great since they greatly cut down the supply inductance and add embedded capacitance (the former effect is the more important one). As you already noticed a nice side effect is they reduce the overall board thicknedd (or allow you to ...

[SI-LIST] Re: PCB thin dielectrics (steve weir)

Ivor, there are about four materials to know about: Except for exotic applications the big thrill in thin dielectrics is reduction in inductance. This lets you get rid of a bunch of bypass caps, and/or yield lower impedance to the power attachment of your IC package, and in a number of cases do things like reduce layer counts depending on the specifics of your power distribution scheme. With proper design a thin dielectric lets you use far fewer bypass capacitors to cover the frequency ranges from about 5MHz up to around 100MHz - 300MHz where the bypass network impedance crosses over into the ...

[SI-LIST] PCB thin dielectrics (Bowden, Ivor)

Hi SI people, Could I get some comments on the use of thin (0.0035) dielectrics in PCBs, in terms of available materials, cost, reliability, dielectric strength, trace width vs dielectric constant, power plane capacitance, stories, studies, useful web links, any other pertinent issues? Base question is, could this be a practical way to increase PCB layer count while maintaining overall PCB thickness? ...

[SI-LIST] Job opportunity at the Center for Remote Sensing of Ice Sheets (Sarah A . Seguin)

All, We have an opening at CReSIS, please see below for details. The Center for Remote Sensing of Ice Sheets (CReSIS) at the University of Kansas seeks an Electrical Engineer to work with faculty, staff, and students to develop, procure, install, and bring to operational status a new anechoic chamber and antenna test facility. The candidate will support development and deployment of radar systems to investigate polar ...

[SI-LIST] Signal Integrity openings in China? (Avtaar Singh)

Dear SI-List members: Does anyone have or know of any Signal Integrity openings in China? My friend is looking for jobs, and can join at a short notice. Regards, Avtaar ------------------------------------------------------------------ To unsubscribe from si-list: ...

[SI-LIST] Two job opportunities in Cisco Systems: Senior Signal Integrity Engineer (full-time) and Signal Integrity consultant (Zhiping Yang (zhiping))

Dear SI-list members, Please find job description for both positions at the end of this e-mail. Please submit your resume to zhiping@xxxxxxxxx if you are interested. ...

[SI-LIST] DesignCon early register deadline, Saturday, Dec. 18 (Barry Sullivan)

Greetings, For those of a certain age, my salutation may evoke memories of the opening used by the Selective Service Administration in notifying you that your number was up. Please relax, and rest assured that my message today is nothing so dire, but more in line with the seasonal spirit of holiday greetings. DesignCon will return to the Santa Clara Convention Center on February 1 - 4, 2010. During this season of giving, reward yourself for a job well done with the gift of continuing education and plentiful networking by ...

[SI-LIST] Re: AW: AW: Effect of temperature on at 200C for DDR3/4 boards (Loyer, Jeff)

One thing that will probably happen at this temperature is any humidity in the board will be baked out, decreasing loss, especially in the outer layers. I would be sure you're margining the system in your expected environmental conditions, after giving it enough time to dry out. Jeff Loyer -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [] On Behalf Of Havermann, Gert ...

[SI-LIST] Re: AW: Effect of temperature on at 200C for DDR3/4 boards (Bill Martin)

Barthi, A few more items: For cold temps, you will find the fastestICs (which might cause timing issues in your design) and also the highest current consumption. For cold temps, you will find the slowestICs (which might cause timing issues). Make sure you do purchase the right ICs for the environment you need your ...

[SI-LIST] AW: AW: Effect of temperature on at 200C for DDR3/4 boards (Havermann, Gert)

Hi Alexander, thanks for the datasheet, maybe it was the wrong file you attached, but Chart 2 shows Dk over frequency. Anyhow, the Dk over temperature is quite stable even for PTFE (1% doesn't worry me). I don't know if the Df will also change. If it does, that just adds more losses to the copper losses I mentioned, but doesn't affect the characteristic impedance. ...

[SI-LIST] Re: AW: Effect of temperature on at 200C for DDR3/4 boards (Alexander Ippich)

Hi Gert, Barthi, some base material suppliers are showing the changes of dielectric constant and dissipation factor over frequency in their data sheets. I have attached one example (please delete the string delete in front of the web link, but w/o, the list server will mangle the long adress). delete Charts #1 and #2 show the variation of Dk and Df over temperatures normalized ...

[SI-LIST] Re: AW: Effect of temperature on at 200C for DDR3/4 boards (Hermann Ruckerbauer)

Hi, I would agree with the previous answers ... don't worry on the PCB performance to much, the degradation of the silicon is what you need to take care. On DRAM side it is not only the change in the OCD (output drivers), but also the refresh timings are getting quite short for 100C. So you really need to do worst case corner simulations over the whole temperature range. ...

[SI-LIST] AW: Effect of temperature on at 200C for DDR3/4 boards (Havermann, Gert)

Hi Barthi, Your question is how the characteristic impedance of the PCB is affected by high temperatures (100C)? The Temperature shouldn't have a big influence on impedance. The series resistance will increase, but the result will just be higher losses. The board sice will increase with temperature, but each differential pair will just see fractions of this extra size, in my eyes not enough to worry about impedance changes. ...

[SI-LIST] Re: Effect of temperature on at 100C for DDR3/4 boards (wcmartin1)

Barthi, IC parts are rated consumer (0 to 70C), industrial (-40 to 85C) and military (-55 to 125C) on ensure the ICs can withstand the environment they will be used in. Typically the performance degrades at higher temps and is reflected in an IC's data sheet. So if you are truly at 100C, I hope you are purchasing military grade ICs for your board. Regards, ...

[SI-LIST] Re: Effect of temperature on at 100C for DDR3/4 boards (Barthi das)

Steve, Thanks for correcting me. Its 100C Regards Barthi --- On Wed, 12/16/09, steve weir weirsi@xxxxxxxxxx wrote: From: steve weir weirsi@xxxxxxxxxx ...

[SI-LIST] Re: Effect of temperature on at 200C for DDR3/4 boards (steve weir)

Did you mistype? Do you mean 100C? 200C is way beyond any DDR chip spec, controller or memory, and way beyond the safety classification for any conventional FR4 type PCB. Steve. Barthi das wrote: Hi, What is the effect of temperature (200C) on characteristic impedance at DDR3/4 speeds and what the best way to control the impedance because of the ...

[SI-LIST] Effect of temperature on at 200C for DDR3/4 boards (Barthi das)

Hi, What is the effect of temperature (200C) on characteristic impedance at DDR3/4 speeds and what the best way to control the impedance because of the temp effect? Appreciate if anyone sends the literature related to the topic Thanks Barthi ...

[SI-LIST] Cisco Job - Technical Lead - Signal and Power Integrity (SI) Engineering (Sadakathullah Mohamed Ali (mohamali))

Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Hi Members, =20 Cisco's gigabit Systems Business Unit is actively looking to hire a Technical lead with SI experience. =20 If anyone is interested please feel free to email me at mohamali AT cisco DOT com ...

[SI-LIST] Re: ESD protectioin at a Digital Input (steve weir)

Follow the current. Observe the voltage. Steve. Vinod Kumar wrote: Hi All, For handheld battery operated devices, we don't have a GND EARTH normally. So in this case how should we connect the ESD device? We generally have a separate noise GND and all the ESD devices are ...

[SI-LIST] Re: ESD protectioin at a Digital Input (Pommerenke, David)

Vinod, In general, I do not suggest to use the term ground, neither in grounded equipment, nor in hand held equipment. It just leads to confusion. It is better to think about current, return current and field control. For a hand held device it is worth to distinguish four types of ESD failure types: ...

[SI-LIST] Re: ESD protectioin at a Digital Input (Vinod Kumar)

Hi All, For handheld battery operated devices, we don't have a GND EARTH normally. So in this case how should we connect the ESD device? We generally have a separate noise GND and all the ESD devices are terminated to this. This GND is connected to signal GND at one point. But as explained at , if the common GND point is far away from ESD device, it can render the protection ineffective. ...

[SI-LIST] IBIS Summit at DesignCon 2010: First Call for Participation and Presentations (Lance Wang)

To All: This is the first announcement for the DesignCon 2010 IBIS Summit meeting to be held at the Santa Clara Convention Center in Santa Clara, California. ...

[SI-LIST] Re: Kramers-Kronig in Pictures (colin_warwick)

Ack! Sorry, that was my second bad link today. Try this instead: -- Colin -----Original Message----- From: WARWICK,COLIN (A-Americas,ex1) ...

[SI-LIST] Re: Kramers-Kronig in Pictures (colin_warwick)

Hi Peter, Thanks! Kramers-Kronig goes back to the 1920s of course. You can see the more recent Hall and Heck treatment that got my creative juices flowing in the preview at Google books: ...or you could buy their book of course :-) ...

[SI-LIST] Re: Kramers-Kronig in Pictures (Peter . Pupalaikis)

Colin: I'm not sure how much of your material or presentation style is original, but the material you presented was the clearest I've seen and it has sparked some further thinking and experimentation with these concepts. I've thought and read about this before, but it's the first time that I feel like I have a handle. Thanks for sharing this and I recommend it. ...

[SI-LIST] Re: Kramers-Kronig in Pictures (colin_warwick)

Hi, Sorry, I meant to put in the direct link. Here it is: -- Colin Warwick Signal Integrity Product Marketing Manager, Agilent EEsof EDA ...

[SI-LIST] AW: relation between rise time and trace length (Havermann, Gert)

Hi Mohammed, if your thinking would be correct, then how could anyone possibly send 10GBps signals over a 19 Backplane? I think you mixed something up. As long as your tracelength is shorter than the risetime, you don't have to think too much about impedance controlled traces. Traces longer than the risetime do need the right impedance to avoid reflections and other nasty effects. The return path length is not added to the tracelength of this rule of thumb. ...

[SI-LIST] Re: relation between rise time and trace length (steve weir)

Your question is very fundamental. What have you done to try and learn about the subject? Steve. Mohamed Ali Gazi wrote: Dear Experts, I understood from some of the materials that the trace length between the driver to receiver ( signal path + return path) should be less than the rise time. Is my understanding correct? ...

[SI-LIST] relation between rise time and trace length (Mohamed Ali Gazi)

Dear Experts, I understood from some of the materials that the trace length between the driver to receiver ( signal path + return path) should be less than the rise time. Is my understanding correct? For example if the rise time of a signal is 1ns then the signal trace length should be less than 3 inches( signal trace length 3 inches and return path 3 inches totally 6 inches = 1 ns of signal travel delay which is equal to rise time of the signal) ...

[SI-LIST] Looking for IBIS model for Qimonda GDDR3 device (Nick Langston)

Gurus, I am looking for a Hyperlynx IBIS model for the Qimonda HY18H1G321AF 1Gbit GDDR3 device. Of course Qimonda is gone and I haven't been able to get anything from Elpida. Any help would be appreciated. Nick Langston nick@xxxxxxxxxxxxxxxxxxxx ...

[SI-LIST] Kramers-Kronig in Pictures (colin_warwick)

Hi, Thanks to Eric Bogatin for pointing out a neat proof of the Kramers-Kronig relation in his excellent book review: ...of Hall and Heck's excellent book. After some reading and doodling, a little light bulb lit up, and the result was my latest blog posting Kramers-Kronig in Pictures here: The Kramers-Kronig relation is very useful in SI because it enables you to determine time-domain causality (or lack thereof) of a frequency domain model ...

[SI-LIST] Looking for IBIS model for Qimonda GDDR3 device (Nick Langston)

Gurus, I am looking for a Hyperlynx IBIS model for the Qimonda HY18H1G321AF 1Gbit GDDR3 device. Of course Qimonda is gone and I haven't been able to get anything from Elpida. Nick Langston, Liberty Research Test Sockets, ATE Boards, Connectors ...

[SI-LIST] Re: SERDES CDR with asynchronous reference clock? (steve weir)

Ivor, yes that is pretty much it. When the channel detects data loss, the VCO locks to the local clock in order to reduce lock time when data reappears. As long as each transmitter operates within the absolute clock tolerance the channel works. Ethernet has worked this way for a long time. The disadvantage of distributing clocks through trees is jitter accumulation. Steve. Bowden, Ivor wrote: Thank you Steve! Please let me reiterate to make sure I understand you. ...

[SI-LIST] Re: SERDES CDR with asynchronous reference clock? (Bowden, Ivor)

Thank you Steve! Please let me reiterate to make sure I understand you. The Rx clock controls data transfer AFTER buffered CDR is the key thing I was missing, the CDR will always have a PLL or some other type of clock regeneration recovered from the RX data stream. In addition, to quote an off list reply I received (thanks Leonard) When there is no data or no lock the internal PLL will normally frequency/ phase lock onto the reference clock. ...

[SI-LIST] Re: SERDES CDR with asynchronous reference clock? (Leonard Dieguez)

Ivor, In the SERDES there is a PLL that will adjust the internal sampling clock frequency. When there is no data or no lock the internal PLL will normally frequency/ phase lock onto the reference clock. This frequency is typically very close to the actual data rate. Once the receiver of the SERDES receives data that data and the PLL clock is compared in frequency and phase in a separate phase-frequency dectector (PFD) the error signal is then used to adjust the PLL in such a way to sample the incoming data. In an analog system quadrature PFD/sampling is used to align the data edge and the sampling edge to ...

[SI-LIST] Re: ODT Impedance on DDR2 (Cusanelli, Tony)

Disclaimer: I WORK FOR MENTOR GRAPHICS however, below is the header from the DDR report. It is quite long, so it wraps in this email, but you can see that we do compensate for derating. The eye diagram does not use AC DC rules, it just shows the waveforms. However, the timing measurements that are used in the spread sheet do follow the DDR spec and use AC and DC thresholds when appropriate. The wizard allows you to experiment with different ODT configurations. Here is the header row for data bit simulation: ...

[SI-LIST] Re: AW: changing Frequency Response! (Aubrey Sparkman)

Peter, Are you using a separate simulator to simulate the voltage source and probes? Which one? Are you doing a linear or decade sweep? What edge rate did you use in Siwave? Aubrey Sparkman Aubrey.K.Sparkman@xxxxxxxx ...

[SI-LIST] Re: ODT Impedance on DDR2 (Hermann Ruckerbauer)

Hi, usually just looking at a single trace or simulating just a view bits gives only a qualitative answer, but no quantitative answer. To decide on pass or fail you need to Calculate a timing budget. This can be done by doing a (long enough) PRBS simulation with at least 3 (better 5) Signals (1 Victim and 4 Aggressors) and evaluate the resulting dataeye according the spec. in DDR Case you would evaluate the eye with AC/DC based setupHold times and adding the slew rate dependent ...

[SI-LIST] Re: ODT Impedance on DDR2 (Mashook Ahamed Usman)

Hi Sudarshan, Our usual practice is to simulate with these three configuration(usually various models comes with the IBIS model of the same chipset) and see which has the least shoot and proper rise time in run interactive window of the tool. If possible use the DDR2 wizard(Hyperlynx8.0)and see the overall result in the excel sheet which tells you how many cases passed and failed. All the best, M Usman -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [] On ...