VLSI QnA

Verilog Timing Checks

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 17 Jun 2014 17:12:00 +0000

Verilog provides system tasks to do timing checks. There are many timing check system tasks available in Verilog. We will discuss the timing check system tasks one by one. All timing checks must be inside the specify block only. Before starting with the timing check system tasks, let us first see the description of all arguments

Timing check system tasks arguments

Please go through the the posts on setup and hold timing for better understanding of these tasks.

$setup

Checks setup time violation.

Syntax : $setup(data_event, reference_event, limit[, notifier]);

Violation is reported if, (T_{reference_event} – T_{data_event}) < limit

Example :$setup(data, posedge clock, 3);

$hold

Checks hold time violation.
Syntax : $hold(reference_event, data_event, limit[, notifier]);
Violation is reported if, (T_{data_event} – T_{reference_event}) < limit
Example :$hold(posedge clear, data, 5);

$width

Check that the width of a pulse meets the minimum width requirement.
Syntax : $width(reference_event, limit[, notifier]);
Violation is reported if, (T_{data_event} – T_{reference_event}) < limit
The data_event is explicitly specified for this system task. The data_event is the next opposite edge of the reference_event signal.
Example :$width(posedge clock, 6);

$recovery

Usually it is applied for checking reset recovery violation.
Syntax : $recovery(reference_event, data_event, limit[, notifier]);
Violation is reported if, (T_{data_event} – T_{reference_event}) < limit
Example :$recovery(posedge clock, reset, 5);

$skew

Used to check synchronicity of clocks inside a circuit.
Syntax : $skew(reference_event, data_event, limit[, notifier]);
Violation is reported if, (T_{data_event} – T_{reference_event}) > limit
Example : $skew(posedge clock1, posedge clock2, 5);

$setuphold

Checks setup and hold timing violations. It is a combination of $setup and $hold system tasks.
Syntax : $setuphold(reference_event, data_event, setup_limit, hold_limit[, notifier]);
Violation is reported if, (T_{data_event} – T_{reference_event}) < hold_limit
(T_{reference_event} – T_{data_event}) < setup_limit
Example :$setuphold(posedge clock, data, 5, 10);

Edge Sensitive Paths, Conditional Path Delay and specparam statements

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 15 Jun 2014 15:30:00 +0000

Edge-Sensitive Paths

An edge-sensitive path construct is used to model the timing of input to output delays, which occurs only when a specified edge occurs at the signal.

Parallel Connection:
([edge_identifier] input_terminal => output_terminal [polarity]:data_source) = delays;

Full Connection :
([edge_identifier] input_terminal *> output_terminal [polarity]:data_source) = delays;

Edge identifier : posedge, negedge

Polarity : '+', '-'

For more about parallel and full connection, please go through this post.

Example :

(posedge clock => (q +: d)) = (10 : 8)

At a positive edge on a 'clock' signal the value of 'q' will change, using the rising delay of 10 and the falling delay of 8 time unit. The data path travels from 'd' to 'q' and data 'd' is not inverted.

Rising : 0 -> 1, x -> 1, z -> 1
Falling : 1 -> 0, x -> 0, z -> 0
Turn off : 0 -> z, 1 -> z, x -> z

Conditional path delays

Sometimes, the pin-to-pin delay might change on the basis of the states of input signals to a circuit. Verilog allows path delays to be assigned conditionally, based on the value of the signals in the circuit.

Conditional path delays are also known as state dependent path delays (SDPD).

Example :

module foo (out, a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

specify
//Parallel connection for different pin-to-pin timing on the basis of state of input signal
if (a)
(a => out) = 9;
if (~a)
(a => out) = 10;

//Full connection for different pin-to-pin timing on the basis of state of input signal
if ({c,d}) == 2'b01)
(c,d *> out) = 11;
else
(c,d *> out) = 13;
endspecify

and a1 (e, a, b);
and a2 (f, c, d);
and a3 (out, e, f);
endmodule

specparam statements

Special parameters can be declared for use inside a specify block. These parameters are declared by the keyword specparam. The specparam values can only be used inside their specify block and not elsewhere. The specify parameters are helpful while assigning delays as these values only need to be changed in case of new timing parameters, instead of changing the hardcoded values for each connection.

Example :
specify
specparam d_to_q = 8;
specparam clk_to_q = 10;

(d => q) = d_to_q;
(clk => q) = clk_to_q;
endspecify

Specify Block

noreply@blogger.com (Kamlesh Bhesaniya) — Mon, 09 Jun 2014 15:29:00 +0000

Specify Blocks :

As we discussed in our last post, a delay between a source (input or inout) pin and a destination (output or inout) pin of a module is called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify. A specify block constitutes all the statements between the keyword specify and endspecify.

Placement of Specify Block :

A specify block is a separate block in the module, which neither comes under initial or always block.

Inside Specify Blocks :

Parallel connection

Usage : ( <source_field> => <destination_field>) = <delay_value>);

Examples :

//bit-to-bit connection. both i and out are single-bit. i is the 'source field' and out is the 'destination field'.

(i => out) = 6;

//vector connection. both i and out are 4-bit vectors.

(i => out) = 6;

The above statement can be expanded as follows :

(i[0] => out[0]) = 6;
(i[1] => out[1]) = 6;
(i[2] => out[2]) = 6;
(i[3] => out[3]) = 6;

//illegal connection i[4:0] is a 5-bit vector, out[3:0] is a 4-bit. Gives error; mismatch between bit width of source and destination fields.

Full connection

Usage : ( <source_field> *> <destination field>) = <delay_value>);

In a full connection, each bit in the source field connects to every bit in the destination field. The full connection overcomes the limitation of parallel connection in which the widths of source and destination field need to be same. The main use of the full connection is in in-fact, specifying delays between different source and destination fields' width.

Examples :

//i[31:0] is a 32-bit vector and out[15:0] is a 16-bit vector

//Delay of 6 between each bit of i and every bit of out is given as

specify
(i *> out) = 6;
endspecify
//The expression would require 352 (16*32) parallel connections to specify the delays.

In our coming post , we will have a look at conditional path delays, specparam statements and how do you model edge sensitive delays.

Delay Models in Verilog

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 08 Jun 2014 15:30:00 +0000

Why delays are required in Verilog simulation?

Functional verification of hardware only tells whether the functionality of design is correct or not. However, in real hardware, logic elements and path have delays associated with them. Therefore, it is also required that design meets timing requirements.

There are three types of delay models used in Verilog simulation - distributed, lumped and pin-to-pin (path) delays. We'll look into each delay model one by one.

Distributed Delay

Distributed delays are specified on a per element basis. Each individual logic element is assigned a specific delay value. In the two code examples below, it is shown that how delays are specified to individual gates (primitives) and assign statements.

Distributed Delay

Example 1: Distributed Delay applied to individual gates.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay is applied to each gate.
and #4 a1(e, a, b);
and #3 a2(f, c, d);
and #5 a3(out, e, f);
endmodule

Example 2: Distributed Delay applied using assign statement.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay is applied to each assign statement.
assign #4 e = a & b;
assign #3 f = c & d;
assign #5 out = e & f;
endmodule

Lumped Delay

Lumped delays are specified on a per module basis. They are specified as a single delay on the output gate of the module. The lumped delay takes into consideration the maximum delay from an input to output. From the above, example we can see the maximum delay from input to output is 9 time units (delay from input a to output out), so this delay is mapped to the output gate of the module.

Lumped Delay

Example 3:Lumped Delay Model

module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay only applied to output gate.
and a1(e, a, b);
and a2(f, c, d);
and #9 a3(out, e, f);
endmodule

Pin-to-Pin Delays

In the pin-to-pin delay model, delays are assigned individually to paths from each input to output. Although pin-to-pin delays may look very detailed, but they are easier for designer, as it requires no knowledge of internals of module. The module may be coded in behavioral statements, data flow, gates, or mixed design. These delays are also known as path delays.

Pin-to-Pin Delay

For the above figure, pin-to-pin delay are specified as follows :

path a-e-out delay = 9

path b-e-out delay = 9

path c-f-out delay = 8

path d-f-out delay = 8

In our next post, we will see how the path delays are specified in Verilog.

Digital Design Interview Questions - v1.3

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 03 Jun 2014 16:37:00 +0000

Q.1) Explain metastability.

Answer) A flip flop enters into meta-stable state, when the hold or setup window is violated. At this time, the output of flip flop is unpredictable.

If you want to read more about setup and hold violations, go through this post.

Q.2) What are the probable ways to avoid metastability?

Answer) Ways to avoid metastability :

Lowering clock frequency - Gives setup slack
Lowering data speed - Gives hold slack.
Faster flip flop - The setup and hold values are very less, hence chances for violation decreases.

Q.3) In a system with

(a) Insufficient hold time , will slowing the clock frequency will help?

Answer) No, it doesn't help. Making the data path slower will help with hold time ,but could violate setup time.

(b) Insufficient setup time ,will slowing the clock frequency will help?

Answer) Yes, making data path faster will help setup time, but will violate in hold time.

Q.4) Design a clock divider circuit which divides the clock by an odd number and has 50% duty cycle. (o/p clk = i/p clk/N, where N is an odd number).

Answer) We will first examine an example where the input clock is divided by 3. After, which we will generalize the steps for any odd number.

Step I :

Design a odd number counter (in this case, counter which counts up-to 2)

2-bit counter

Truth table for divide by 3 counter

D0 = q1

D1 = not(q1).not(q0)

From the above simplifications, we can draw the circuit for divide by 3 counter.

Circuit for divide by 3 counter.

Divide by 3 counter waveform

Step II : 50% duty cycle

Now, we have divided the input clock by 3, but the duty cycle is still not 50%. To get 50% duty cycle, we shift the Q0 output by 90 degrees and add a gate to OR the two flip flops' output.

Divide by 3 with 50% duty cycle

Please note that in above figure, the last flop has negated clock at its clock input terminal.

Divide by 3 with 50% duty cycle waveform

The above method can be extended to other odd larger by divide "N" numbers by following the same design flow :

Design a Up or Down divide by "N" counter.
Add a flip flop to follow one of the flip flops in the counter 1/2 clock cycle.
OR the output of added flip flop with the one that is driving it to achieve 50% duty cycle.

VLSI Glossary

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 25 May 2014 15:36:00 +0000

VLSI Glossary

ASIC	Application Specific Integrated Circuit
ATPG	Automatic Test Pattern Generation
AOCV	Advance On Chip Variation
BC	Best Case
CCS	Composite Current Source
CG	Composite Grain
CMP	Chemical Mechanical Planarization
CTS	Clock Tree Synthesis
CAD	Computer Aided Design
DDC	Synopsys Database Format (Synopsys specific)
DEF	Design Exchange Format
DFM	Design For Manufacture
DRC	Design Rule Check
DFT	Design For Test
DSPF	Detailed Standard Parasitic Format
ECO	Engineering Change Order
EM	Electro magnetic
ESD	Electro-Static Discharge
EDA	Electronic Design automation
EDIF	Electronic Design Interchange Format
FPGA	Field Programmable Gate Array
GDSII	Graphic Data System II
HVT	High Vt
HDLs	Hardware Descriptive language
IMD	Inter-Metal Dielectric
ILD	Inter Layer Dielectric
IO	Input Output
ITF	Interconnect Technology File
IC	Integrated Circuit
LEF	Library Exchange Format
LIB	Library
LVS	Layout Vs Schematic
LSI	Large Scale Integration
MCMM	Multi-Corner Multi-Mode
NDR	Non default Rule
NLDM	Non-Linear Delay models
OPC	Optical Proximity Correction
PG pin	Power and Ground Pin
PLIB	Physical Library
PLL	Phase Lock Loop
PVT	Process Voltage Temperature
PDEF	Physical Design Exchange Format
QOR	Quality Of Result
RAM	Random Access memory
ROM	Read Only Memory
RDL	Re-Distribution layer
RTL	Register Transfer Level
RSPF	Reduced Standard Parasitic Format
SAIF	Switching Activity Interchange Format
SDF	Standard Delay Format
SOC	System On Chip
SOI	Silicon On Insulator
SPEF	Standard Parasitic Exchange Format.
SPICE	Simulation Program for Integrated Circuits Emphasis
SSI	Small Scale Integration
SPF	Standard Parasitic Format
SBPF	Synopsys Binary Parasitic Format
SDC	Synopsys Design Constraint
TLF	Timing Library Format
TTL	Transistor-Transistor Logic
TF	Technology File
UPF	Unified Power Format
ULSI	Ultra Large Scale Integration
VCD	Value Change Dump
VHDL	VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language
VLSI	Very large Scale Integration

Interview Questions on Blocking and Nonblocking Assignments

noreply@blogger.com (Kamlesh Bhesaniya) — Fri, 23 May 2014 17:24:00 +0000

This post is continuation to our previous post on blocking and non-blocking assignments. For better understanding of how the blocking and nonblocking assignments are scheduled in Verilog, please go through this post.

Q.1) What will be the output of following code?

module seq;
reg clk, rst, d;
initial
begin
$monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d);
#1 clk = 0;
#10 rst = 0;
#5 d = 0;
#10 $finish;
end
endmodule

Answer) 0 clk = x rst = x d = x
1 clk = 0 rst = x d = x
11 clk = 0 rst = 0 d = x
16 clk = 0 rst = 0 d = 0

Q.2) What will be the output of following code?

module parallel;
reg clk, rst, d;
initial
begin
$monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d);
fork
#1 clk = 0;
#10 rst = 0;
#5 d = 0;
join
#1 display("%t Terminating simulation", $time);
end
endmodule
(Note : fork-join block causes the statements to be evaluated in parallel, i.e. all at the same time.)

Answer) 0 clk = x rst = x d = x

1 clk = 0 rst = x d = x

5 clk = 0 rst = x d = 0

10 clk = 0 rst = 0 d = 0

11 Terminating simulation

Q.3) What will be the output of the following code ?

blocking nonblocking

always @(i1 or i2) always @(i1 or i2)

begin begin

i1 = 1; i1 = 1;

i2 = 2; i2 = 2;

#10; #10;

i1 = i2; i1 <= i2;

i2 = i1; i2 <= i1;

end end

(a) (b)

Answer) In the case of (a), i.e. blocking the values of i1 and i2 will be both '2', whereas in the case of (b) (nonblocking) the values of i1 and i2 will be '2' and '1' respectively.

Q.4) What will be the output of the following code ?

module tp;
reg i1;
initial

$monitor("\$monitor: i1 = %b", i1);
initial

begin
$strobe ("\$strobe : i1 = %b", i1);
i1 = 0;
i1 <= 1;
$display ("\$display: i1 = %b", i1);
#1 $finish;

end
endmodule

Answer) $display: i1 = 0
$monitor: i1 = 1
$strobe : i1 = 1

Q.5) What will be the output of the following code?

module tp;

reg i1, i2;

initial

begin

i1 = 0;

i2 = 1;

i1 <= i2;

i2 <= i1;

$monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);

$display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);

$strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);

#0 $display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);

#1 $monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);

$display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);

$strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);

$display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);

#1 $finish;

end

endmodule

Answer) 0ns: $display: i1=0 i2=1

0ns: #0 : i1=0 i2=1

0ns: $monitor: i1=1 i2=0

0ns: $strobe : i1=1 i2=0

1ns: $display: i1=1 i2=0

1ns: #0 : i1=1 i2=0

1ns: $monitor: i1=1 i2=0

1ns: $strobe : i1=1 i2=0

In case of any doubt regarding the above solutions, feel free to leave a comment.

Verilog "Stratified Event Queue"

noreply@blogger.com (Kamlesh Bhesaniya) — Thu, 22 May 2014 16:40:00 +0000

Verilog "Stratified Event Queue"

The Verilog event queue is a conceptual model, which helps us understand how various events like blocking assignments, nonblocking assignments function.

According to the Verilog IEEE standard, the Verilog event queue is logically segmented into five different regions.

1) Active Events :

Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions.

2) Inactive Events.

Events which are processed after the processing of active events. In this queue, #0 delay assignments are scheduled.

3) Nonblocking assign update events

Events that were evaluated during previous simulation time, but are assigned at this simulation time after the processing of active and inactive events. It is these queue where the LHS of nonblocking assignment is updated.

4) Monitor Events

Events that are processed after all the active, inactive and nonblocking assign update events have been processed. This queue contains $monitor and $strobe assignments.

5) Future Events
Events to occur at future simulation time.

Verilog Event Queue model

Example :
What will be the output of following piece of code?
initial
begin
a = 1'b0;
a <= 1'b1;
$display("\nValue of a is :%b", a);
end

Many of us think that the the value of a displayed will be '1', but it is not correct. Using the Verilog event queue,
I) a = 1'b0;
This will be placed in the active events, so the assignment will take place immediately. Hence, at this time , the value of a is '0'.

II) a <= 1'b1;
As you remember from our previous post on nonblocking assignments, the nonblocking assignment is a two step process, so only RHS evaluation will be scheduled in active event. At this point the LHS will not be updated, so the value of a still remains '0'.

III) $display("\nValue of a is :%b",a);
Since, it is a display statement the statement will be placed in active events and processed immediately, so we get the value of a printed as '0'.

IV) In this step, the LHS of nonblocking statement in II will be updated, at this time the value of a will change from '0' to '1'.

Blocking, Nonblocking Assignments and Verilog Race Condition

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 20 May 2014 16:04:00 +0000

Blocking Assignment

The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the RHS arguments and complete its assignment without interrupt from any other Verilog statement.

Execution of blocking assignments can be seen as a one-step process:

Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.

The problem occurs, when the RHS side of one assignment in one procedural block is same as the LHS side of another assignment in another procedural block and both the assignments are scheduled to be executed in the same simulation time step, then in this case there is no sure way to predict which assignment will occur first. This condition is known as Verilog race condition. The race condition is shown using the below example

module tp ( output reg o1,
output reg o2,
input clk,
input rst
);

always @(posedge clk or posedge rst)
if (rst)
o1 = 1;
else
o1 = o2; //------> I

always @(posedge clk or posedge rst)
if (rst)
o2 = 0;
else
o2 = o1; //-------> II
endmodule

In this case, when the design gets out of reset, we cannot predict whether statement I will be executed first or statement II. If statement I is executed first, then values of o1 = 0, o2 = 0 ; if statement II is executed first, then o1 = 1; o2 = 1, hence this is a Verilog race condition.

Nonblocking Assignment

The nonblocking assignment operator is denoted by "<=". A nonblocking assignment evaluates the RHS side of a nonblocking statement at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled.

Execution of nonblocking assignments can be seen as a two-step process:

Evaluate the RHS of nonblocking statements at the beginning of the time step.
Update the LHS of nonblocking statements at the end of the time step.

module tp ( output reg o1,
output reg o2,
input clk,
input rst
);

always @(posedge clk or posedge rst)
if (rst)
o1 <= 1;
else
o1 <= o2; //------> I

always @(posedge clk or posedge rst)
if (rst)
o2 <= 0;
else
o2 <= o1; //-------> II
endmodule

In this case, when reset is applied, o1 = '1' and o2 = '0', when the reset is de-asserted, the RHS side of both the statements are updated at the start of time step, but the assignment takes place only at the end of the time step, hence there is no race condition. At the end of time step , o1 = '0' and o2 = '1'.

Finite State Machine (FSM)

noreply@blogger.com (Kamlesh Bhesaniya) — Mon, 19 May 2014 16:50:00 +0000

Ways to design clocked sequential circuits :

Mealy Machine
Moore Machine

Mealy Machine

In a Mealy machine, the outputs are a function of the present state and the value of inputs. Due to this, outputs may change asynchronously with change in inputs.

Output = f(Present State, Input)

Moore Machine

In a Moore machine, the outputs depend only on the present state. In the case of Moore Machine, the next state is calculated using the inputs and the current state. The outputs are computed by a combinatorial logic circuit whose inputs are the state variables.

Output = f(Present State)

Please go through the excitation table for D - flip flop for better understanding.

Q) Design a circuit that detects three consecutive '1's using Mealy and Moore FSM.

Answer)
I) Mealy FSM

Mealy FSM

State truth table

Y = In.q1

Q1 = In.q1 + In.q0

Q0 = In.not(q1).not(q0)

Mealy FSM circuit implementation

II) Moore FSM

Moore FSM

State truth table

Output truth table

Y = q0.q1

Q1 = In.q0 + In.q1

Q0 = In.q1 + In.not(q0)

Moore FSM circuit implementation

Synchronous and Asynchronous resets

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 18 May 2014 12:45:00 +0000

Reset

Reset is needed for:

Forcing the digital circuit into a sane state for simulation
Initializing hardware, as circuits have no way to initialize themselves.
For simulation purpose, it is advantageous to have reset applied to all elements that have states.

Synchronous Resets :

Based on the fact that the reset will be sampled on the active edge of the clock. Reset is treated as any other input to the state machine.

Synchronous Resets

Advantages :

As there is no reset pin in the flop, the size is smaller.
The circuit becomes completely synchronous.
It provides filtering for the reset line so that it is not affected by glitches, unless they occur right at clock edge.

Disadvantages :

Since the reset input is added to combinatorial logic, hence the combinatorial logic becomes complex.
May require a pulse stretch circuit to guarantee that a reset pulse is wide enough to be seen at the rising clock edge.
Reset buffer tree may be required to ensure that all resets occur in the same clock cycle.
Require a free running clock to ensure reset takes place.

Asynchronous Resets :

Based on the fact that the reset has priority over other signals, when asserted, reset occurs. The main problem when dealing with the asynchronous resets is their removal; the asynchronous resets need to be de-asserted synchronously.

Asynchronous Resets

Advantages :

No clock is required for assertion of reset.
Data path is clear of reset signals.

Disadvantages :

The flop becomes sensitive to the glitches or noise present in the reset line.
The deactivation of reset of all flip flops must be synchronous.

Asynchronous Reset Problem

Problems with asynchronous de-assertion of asynchronous reset :

Violation of reset recovery time
Reset removal happening in different clock cycles for different sequential elements.

Reset Recovery Time :

Reset recovery time refers to the time between when reset is de-asserted and the time that the clock signal goes high again. Missing a recovery time can cause signal integrity or metastability problems with the registered data outputs.

Reset removal traversing different clock cycles :

When reset removal is asynchronous to the rising clock edge, slight differences in propagation delays in either or both the reset signal and the clock signal can cause some registers or flip-flops to exit the reset state before others.

Reset Synchronizer

Without a reset synchronizer, the usefulness of the asynchronous reset in the final system is void even if the reset works during simulation.

Reset Synchronizer

An external reset signal asynchronously resets a pair of master reset flip-flops, which then drives the master reset signal asynchronously through the reset buffer tree to the rest of the flip flops in the design. The entire design will be asynchronously reset.

Reset removal is done by de-asserting the reset signal, which in turn allows the d-input of the first master reset flip flop to pass through the reset synchronizer. The reason for using two flip flops is to remove any metastability that might be caused by the reset signal being removed asynchronously and too close to the rising clock edge. As two flip flops are used , it typically takes two active clock edges after reset removal to synchronize removal of master reset.

Timing Parameters related to Asynchronous Reset :

Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.

Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.

Reset Recovery time and Reset Removal time

T Flip Flop

noreply@blogger.com (Kamlesh Bhesaniya) — Sat, 17 May 2014 07:40:00 +0000

Q.1) Explain T flip flop.

Answer) Toggle flip flop is basically a J_K flip flop with its inputs tied together.

Analyzing the circuit,
I) When CLK = ↓ , T = '0' / '1',
There is no change in the output.

II) When CLK = '0' , T = '0' / '1',
There is no change in the output.

III) When CLK = '1' , T = '0' / '1',
There is no change in the output.

IV) When CLK = ↑ , T = '0',
There is no change in the output ,as J = '0' and K = '0' .

READ : J-K Flip Flop

V) When CLK = ↑ , T = '1',
The output gets toggled, as J = '1' and K = '1'.

Truth table for T flip flop

Q.2) Draw the excitation table for T flip flop.

Answer) From the truth table, we can infer the following points.
When Q retains its state either from '0' to '0' or '1' to '1', T = '0'
When Q changes its state from '1' to '0' or '0' to '1', T ='1'.

Excitation table for T flip flop

Q.3) Convert J-K flip flip to T flip flop.

Answer) Given flop : J-K flip flop (Output)

Flop to be derived : T flip flop (Input)

Combined truth table for converting J-K flip flop into T flip flop.

K-Map Simplification

T flip flop using J-K flip flop

Q.4) Convert S-R flip flop into T flip-flop.

Answer) Given flip flop : S-R flip flop (Output)

Flop to be derived : T flip flop (Input)

Combined truth table for converting S-R flip flop into T flip-flop

K-Map Simplification

T flip flop using S-R flip flop.

Q.5) Convert D flip flop to T flip flop.

Answer) Given flop : D flip flop. (Output)

Flop to be derived : T flip flop (Input)

Combined truth table for converting D flip into T flip flop

K-Map Simplification

T flip flop using D flip flop

Q.6) Convert T flip flop to D flip flop

Answer) Given flop : T flip flop

Flop to be derived : D flip flop.

Combined truth table for converting T flip flop into D flip flop

K-Map Simplification

D flip flop using T flip flop.

READ : D Flip Flop

Q.7) Convert T flip flop to S-R flip flop.

Answer) Given flop : T flip flop (Output)

Flop to be derived : S-R flip flop (Input)

Combined truth table for converting T flip flop into S-R flip flop.

K-Map Simplification

S-R flip flop using T flip-flop.

Q.8) Convert T flip flop into J-K flip flop.

Answer) Given flop : T flip flop (Output).

Flop to be derived : J-K flip flop (Input)

Combined truth table for converting T flip flop into J-K flip flop.

K-Map Simplification

J-K flip flop using T flip flop.

Interesting Fact : Full form of JK in J-K flip flop is Jack Kilby.

Verilog Interview Questions - v1.5

noreply@blogger.com (Kamlesh Bhesaniya) — Mon, 12 May 2014 17:08:00 +0000

Q.1) If a pure combinational circuit is coded inside always block, is it necessary to mention all of the inputs in the sensitivity list?

Answer) Yes, in a pure combinational circuit it is advisable to mention all of the inputs in the sensitivity list, as not doing so may create different result in pre-synthesis and post-synthesis simulation, as during the synthesis, the tool considers all the input in the sensitivity list, whereas, simulation tool only considers the given inputs in the sensitivity list.

Q.2) If in1= 4'b011 and in2= 4'b0011, then the result of in1**in2 will be
A) 6
B) 9
C) 27
D) Invalid expression

Answer) C

Q.3) Give three methods to generate clock in Verilog.

Answer)

I) initial

begin

clk = 0;

end

always

begin

#(CLK_PERIOD/2) clk = ~clk;

end

II) initial

begin

clk = 0;

forever

begin

#(CLK_PERIOD/2) clk = ~clk;

end

III) initial

begin

clk = 0;

end

always

begin

#(CLK_PERIOD/2) clk = 0;

#(CLK_PERIOD/2) clk = 1;

end

Q.4) What will be the output of the following case statement?
wire [3:0] temp;
always @(...)
begin
case (1'b1)
temp[0] : Block 1;
temp[1] : Block 2;
temp[2] : Block 3;
temp[3] : Block 4;
endcase
end

Answer) The case statement walks down the list of options and executes the first one that matches. So, for example if, the MSB of temp is the only '1' in temp, then Block 4 statements will be executed.

Q.5) Why the statement "if (2'b10 & 2'b01)." doesn't behave as expected, i.e. return true case?

Answer) This is one of the most common coding error. In this case, the operator that is used is the bitwise AND(&) operator, whereas the correct operator that should have been used is the logical AND operator(&&).

For more Verilog Interview Questions, click here.

J-K Flip Flop

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 11 May 2014 14:32:00 +0000

Q.1) Explain J-K flip flop.

Answer) The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K.

S = not(K.Q)

R = not(J.not(Q))

Analyzing the above circuit :

I) When CLK = ↓, J = 0, K = 1,

The output of the flip-flop does not change, i.e. Q and not(Q) retain their state.

II) When CLK = ↑ , J = 0, K = 0

S = 1; R = 1,

Outputs will be retained.

III) When CLK = ↑ , J = 0, K = 1

S = not(Q) ; R = 1, hence according to the operation of S-R latch,

Q = 0 and not(Q) = 1.

IV) When CLK = ↑ , J = 1, K = 0

S = 1; R = Q, hence according to the operation of S-R latch,

Q = 1 and not(Q) = 0.

V) When CLK = ↑ , J = 1, K = 1

S = not(Q), R = Q

a) If Q = 0 and not(Q) = 1,

S = 1 and R = 0, hence output Q = 1 and not(Q) = 0.

b) If Q = 1 and not(Q) = 0,

S = 0 and R = 1, hence output Q = 0 and not(Q) = 1.

Hence, we conclude that for J=K=1, the outputs get toggled.

Truth Table for J-K Flip Flop.

Q.2) Draw the excitation table for J-K flip flop.

Answer) From the truth table, we can infer the following points :
a) When Q retains state '0' ,
J = K = 0 and J = 0 , K =1 => J = '0' , K = 'x'

b) When Q changes from '0' to '1' ,
J = K = 1 and J = 1 , K =0 => J = '1' , K = 'x'

c) When Q changes from '1' to '0' ,
J = K = 1 and J = 0 , K =1 => J = 'x' , K = '1'

d) When Q retains state '1' ,
J = K = 0 and J = 1 , K =0 => J = 'x' , K = '0'

Excitation Table for J-K Flip Flop.

Q.3) Convert S-R flip flop into J-K flip flop.

Answer) Given flop : S-R flip flop (Output)
Flop to be derived : J-K flip flop (Input)

MUST READ : S-R flip flop

Combined truth table for converting S-R flip flop into J-K flip flop.

K-Map Simplification

J-K flip flop using S-R flip flop.

Q.4) Convert J-K flip flop into D flip flop.

Answer) Given flop : J-K flip flop (Output)
Flop to be derived : D flip flop (Input)

MUST READ : D flip flop

Combined truth table for converting J-K flip flop into D flip flop.

K-Map Simplification

D flip flop using J-K flip flop.

Q.5) Convert J-K flip flop into S-R flip flop.

Answer) Given flop : J-K flip flop (Output)

Flop to be derived : S-R flip flop (Input)

Combined truth table for conversion of J-K flip flop into S-R flip flop.

K-Map Simplification

S-R flip flop using J-K flip flop.

Q.6) Convert D flip-flop into J-K flip flop.

Answer) Given flop : D flip flop (Output)

Flop to be derived : J-K flip flop (Input)

Combined truth table for conversion of D flip flop into J-K flip flop.

K-Map Simplification

J-K flip flop using D flip flop.

D Flip flop

noreply@blogger.com (Kamlesh Bhesaniya) — Sat, 10 May 2014 19:42:00 +0000

Q.1) What is D type flip-flop?

Answer) The D type flip-flop has one data input 'D' and a clock input. The circuit edge triggers on.the clock input. The flip-flop also has two outputs Q and not(Q). The operation of the D type flip-flop is as follows:

Any input appearing (present state) at the input D, will be produced at the output Q in next clock cycle

Example : If in the current time D = 0 and Q = 1, the next state will be D = (0/1) and Q = 0.

Truth Table for D Flip Flop.

Q.2) Draw the excitation table for D - flip flop.

Answer) From the truth table, we can see that,

When Q retains it state from '0' to '0' or changes from '1' to '0', the value of D is '0'.

When Q retains it state from '1' to '1' or changes from '0' to '1' , the value of D is '1'.

Excitation table for D flip flop.

Q.3) Draw the circuit diagram of D - flip flop.

Answer) The circuit diagram for D flip flop can be easily drawn by converting the S-R flip flop into D flip flop. For converting one flip flop to another, a truth table is prepared by combining the excitation tables for both the flops. The given flop (in this case S-R flip flop) acts as outputs and flop to be derived (in this case D flip flop) along with current output and next state output acts as inputs.

READ : S-R Flip Flop

Combined truth table for converting S-R flip flop into D flip flop.

K-Map Simplification

D Flip Flop using S-R Flip Flop.

Q.4) Convert D flip flop into S-R flip flop.

Answer) In this case,

Given flop : D flip flop (output)

Flop to be derived : S-R flip flop (input)

Combined truth table for converting D flip flop into S-R flip flop.

K-Map Simplification

S-R Flip Flop using D Flip Flop.

S-R latch and flip-flop

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 06 May 2014 18:45:00 +0000

Q.1) Explain S-R Latch using NAND gates.

Answer) Latch is a sequential logic circuit which checks all its inputs continuously and will change its output as soon as the input changes without waiting for the clock signal. Generally an enable signal is provided for a latch. When the enable signal is active, the output will change as soon as there is change in input.

It has two outputs Q and not(Q) which are complements of each other.

The boolean equation for the outputs can be expressed as follows :

Q = not(R.not(Q))

not(Q) = not(S.Q)

I) S = 0, R = 0 (Race Condition)

Substituting the value of S and R in the above equations, we get both Q and not(Q) as 1. This is an indeterminate state and should be avoided.

II) S = 0, R = 1 (Reset Condition)

Since, S = 0, it forces not(Q) to be 1 and R = 1 forces Q = 0.

III) S = 1, R = 0 (Set Condition)

In this case, R = 0 forces the Q = 1 and S = 1 forces not(Q) = 0.

IV) S = 1, R = 1 (No change)

Substituting the values of S and R in the above equation, we get,

Q = Q and not(Q) = not(Q), hence there is no change in the outputs.

Q.2) Explain positive edge triggered S-R flip flop.

Answer) The S-R flip flop consists of a differentiator circuit and a S-R gated latch. C-R₁acts as a differentiator and converts the rectangular clock pulses into positive and negative spikes. The diode acts as a rectifying diode and allows only the positive spikes to pass through, blocking the negative spikes.

Q.3) Draw the excitation table for S-R flip flop.

Answer) From the above truth table, we can infer following points :

When Q retains state '0', we have two conditions S = R = '0' and S = '0'; R = '1', hence to retain state '1', S = '0' and R = 'x'
When Q changes from 0' to '1', S = '1' ; R = '0'
When Q changes from '1' to '0', S = '0' ; R = '1'.
When Q retains state '1' , we have two conditions S = R = '0' and S = '1'; R = '0', hence to retain state '1' , S='x' and R = '0'.

Q.4) Explain race condition.

Answer) Race condition occurs when both S and R input of latch becomes '0'. When any one input to a NAND gate is '0', its output becomes '1'. Thus both the outputs will try to become '1', hence it is called race condition.

Verilog Interview Questions - v1.4

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 06 May 2014 02:08:00 +0000

Q.1) If a net has no driver, it gets the value
A) 0
B) X
C) Z
D) U

Answer) C

Q.2) What is the default value of reg?
A) 0
B) X
C) Z
D) U

Answer) B

Q.3) The task $stop is provided to
A) End simulation
B) Suspend simulation
C) Exit simulator
D) None of the above

Answer) B

Q.4) If A= 4`1xxz and B= 4`b1xxx, then A= = =B will return
A) 1
B) X
C) Z
D) 0

Hint

Answer) D

Q.5) Externally, a output port must always connected to a
A) net only
B) a reg only
C) either net or reg
D) None of the above

Answer) A

Verilog Interview Questions - v1.3

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 04 May 2014 15:17:00 +0000

Q.1) Explain inter-assignment and intra-assignment delay.

Answer) Inter-assignment delay is used when a delay is specified to the left of a procedural assignment.

reg a, b;
initial
begin
a = 0;
#10 b = 1;
end

The execution of the procedural assignment is delayed by the number specified by the delay control. Therefore, the 'b' assignment is delayed by the 10 time units.

Intra-assignment delay is used when a delay is specified to the right of a procedural assignment.

reg a, b, c;

initial

begin

a = 0; b = 0;

c = #10 a + b;

end

The execution of above statement takes as follows :

Take the value of a and b at the time = 0, evaluate a + b and then wait 10 time units to assign value to c.

Q.2) What will be the output/effect of the following statements?
a) a = 4'd12;
$display("Value of a = %b\n", a);
b) b = 3'd2;
$monitor($time, "Value of b = %b\n", b[2:0]);
c) `define SIZE 1024
$display(" Size is %h", SIZE);

Answer)

a) Value of a = 1100

b) 0Value of b = 010

c) Size is 00000400

Q.3) What will be the output of following code?
reg a,b,c;
reg [2:0] d;
initial
begin
a = 1'b0;
$display("Time %t a %b b %b c %c d %d",$time,a,b,c,d);
b = #10 1'b1;
$display("Time %t a %b b %b c %c d %d",$time,a,b,c,d);
c = #5 1'b0;
$display("Time %t a %b b %b c %c d %d",$time,a,b,c,d);
d = #20 {a,b,c};
$display("Time %t a %b b %b c %c d %d",$time,a,b,c,d);
end

Answer)

Time 0 a 0 b x c x d x

Time 10 a 0 b 1 c x d x

Time 15 a 0 b 1 c 0 d x

Time 35 a 0 b 1 c 0 d 010

Q.4) What will be the output of the below initial block?
initial
begin
a = 1'b0;
$display("Initial 1 a %b b %b c %b d %b\n",a,b,c,d);
#0 c = b;
$display("Initial 2 a %b b %b c %b d %b\n",a,b,c,d);
end
initial
begin
b = 1'b1;
$display("Initial 3 a %b b %b c %b d %b\n",a,b,c,d);
#0 d = a;
$display("Initial 4 a %b b %b c %b d %b\n",a,b,c,d);
end

Answer) Initial 1 a 0 b x c x d x

Initial 3 a 0 b 1 c x d x

Initial 2 a 0 b 1 c 1 d x

Initial 4 a 0 b 1 c 1 d 0

Q.5) What is the final value of d?
initial
begin
b = 1'b1; c = 1'b0;
#10 b = 1'b0;
end
initial
begin
d = #25 (b|c);
end

Answer) In the above example, both the initial blocks will be executed at the same time. Since, in the second initial block, there is an intra assignment delay, so the value of d will be calculated at 0 time, but will be assigned after 25 time units. So, the final value of d will be 1.

CMOS Interview Questions - v1.2

noreply@blogger.com (Kamlesh Bhesaniya) — Sat, 03 May 2014 17:35:00 +0000

Q.1) Draw the CMOS layout of tristate buffer.

Answer) When En = 0,
The PMOS part of the circuit as well as NMOS part of the circuit doesn't conduct, so therefore no one drives the output, resulting in high impedance circuit.

When En = 1; In = 0,
The PMOS part of the circuit conducts resulting in '1' at the output.

When En = 1; In = 1,
The NMOS part of the circuit conducts resulting in '0' at the output.

Q.2) Draw the CMOS layout for the following function :
z = [a.b +c.(d + e)]

Answer) From CMOS Interview Questions - v1.1 post, the key to solving such problems is that first derive the PMOS part (pullup circuit) and NMOS part (pulldown circuit) circuit and then draw the complete CMOS layout.

PMOS Part = not([a.b + c.(d+e)]
= not(a.b).not(c.(d+e))
= (not(a) + not(b)).(not(c) + not(d).not(e))

NMOS Part = (a.b + c.(d+e))

Q.3) Explain transmission gate.

Answer) A transmission gate, or analog switch, is defined as an electronic element that will selectively block or pass a signal level from the input to the output. This switch is comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner so that both transistors are either on or off.

When the voltage on node X is a '1', the complementary '0' is applied to node active-low X, allowing both transistors to conduct and pass the signal at A to B. Similarly, when the voltage on node active-low X is a '0', the complementary '1' is applied to node A, turning both transistors off and forcing a high-impedance condition on both the A and B nodes.

The labels A and B can be reversed.

Q.4) Draw 2-to-1 mux using transmission gate.

Answer)

Q.5) Draw the layout of XOR gate using transmission gate.

Answer)

VHDL Interview Questions - v1.0

noreply@blogger.com (Kamlesh Bhesaniya) — Fri, 02 May 2014 16:54:00 +0000

Q.1) What is VHDL?

Answer) VHDL stands for "VHSIC Hardware Description Language." VHSIC, in turn, stands for "Very High Speed Integrated Circuit," which was a U.S. Department of Defense program.

Q.2) Difference between VHDL and VERILOG?

Answer)

	VHDL	Verilog
Compilation	Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in its own system file in which case separate compilation should not be an issue.	Care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.
Data Types	VHDL may be preferred because it allows a multitude of language or user defined data types to be used.	Verilog data types are very simple, easy to use and very much geared towards modeling hardware structure. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user
Design reusability	VHDL. Procedures and functions may be placed in a package so that they are available to any design-unit that wishes to use them.	There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.
	VHDL is strongly typed.	Verilog is loosely typed.
	VHDL is case insensitive.	Verilog is case sensitive.
	Supports library management.	No support for librariers.

Q.3) Difference between SIGNAL and VARIABLE ?

Answer)

	Signal	Variable
Assignment	<=	:=
Utility	Represents circuit interconnects (wires)	Represents local information.
Scope	Can be global (seen by entire code)	Local (visible only inside the corresponding PROCESS, FUNCTION or PROCEDURE)
Behaviour	Update is not immediate n sequential code(new value generally available at the end of PROCESS, FUNCTION or PROCEDURE)	Updated immediately (new value can be used in next line of code)
Usage	In a PACKAGE, ENTITY or ARCHITECTURE. In an ENTITY, all PORTS are SIGNALS by default.	Only in sequential code, that is in PROCESS, FUNCTION or PROCEDURE

Q.4) Are Verilog/VHDL concurrent or sequential language in nature?

Answer)

Verilog and VHDL both are concurrent languages.
Any hardware descriptive language is concurrent in nature.

Q.5) Describe the logic system introduced by the IEEE 1164 standard.

Answer) IEEE 1164 standard describes a 9-value logic system.

'U' : unresolved
'X' : Forcing unknown
'0' : Forcing low.
'1' : Forcing high.
'Z' : High impedance.
'W' : Weak unknown.
'L' : Weak low.
'H' : Weak high.
'-' : Don't care.

CMOS Interview Questions - v1.1

noreply@blogger.com (Kamlesh Bhesaniya) — Thu, 01 May 2014 07:56:00 +0000

Q.1) Explain the difference between PMOS and NMOS.

Answer) A NMOS transistor is made up of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows forming an n-type channel between the source and the drain and a current is carried by electrons from source to the drain through an induced n-type channel.

A PMOS transistor is made up of p-type source and drain and a n-type substrate. When a positive voltage is applied between the source and the gate (negative voltage between gate and source), a p-type channel is formed between the source and the drain with opposite polarities. A current is carried by holes from source to the drain through an induced p-type channel.

n-channel MOSFETs have some performance advantages over p-channel MOSFET’s. The mobility of electrons, which are carriers in the case of an n-channel device, is about two times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel device is faster than a p-channel device.

Advantages of PMOS :

PMOS technology is highly controllable.
It is a low cost process.
It has good yield and high noise immunity.

Advantages of NMOS :

Since electron mobility is twice (say) that of hole mobility, an n-channel device will have one-half the on-resistance or impedance of an equivalent p-channel device with the same geometry and under the same operating conditions. Thus n-channel transistors need only halt the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs can be smaller for the same complexity or, even more important, they can be more complex with no increase in silicon area.

NMOS circuits offer a speed advantage over PMOS due to smaller junction areas. Since the operating speed of an MOS IC is largely limited by internal RC time constants and capacitance of diode is directly proportional to its size, an n-channel junction can have smaller capacitance. This, in turn, improves its speed.

Disadvantages of NMOS :

The n-channel device has following problems in the device processing. Most of the mobile contaminants are positively charged. Since NMOS operates with the gate positively based with respect to the substrate, these ions collect along the oxide-silicon interface. This charge causes a shift in VTh. Also, there is fixed positive charge at the Si-SiO2 interface resulting from various steps of the manufacturing process. This also shifts the threshold voltage. Both these charges have tendency to make the device normally on. These two charges exist in PMOS device too, but the positive ions are pulled to the AI-S1O2 interlace by the negative bias applied to gate. There, they cannot affect the device threshold severely.

Another problem with NMOS device occurs during the oxidation of silicon which takes place at the Si-SiO2 interface. No real abrupt change occurs between silicon and Si02; rather there is a transition zone. This transition zone contains positively charged Silicon atoms which increase the absolute magnitude of the threshold voltage for a p-channel device and decrease the absolute magnitude of the threshold voltage for an n-channel device. This means it is difficult to make an n-channel device that is off at zero gate voltage. This is why it is more difficult to make an n-channel device than a p-channel device.

Q.2) Draw the CMOS layout of NAND gate.

Answer) NAND gate equation : output = not(A.B)

output = not(A) + not(B)

The CMOS layout consists of PMOS and NMOS. For drawing PMOS layout use the given equation. For NMOS take the complement of the equation and draw it.

+ -> in parallel.

. -> in series.

So, the PMOS equation comes as :

PMOS equation : not(A) + not(B)

and the NMOS equation as follows :

NMOS equation : A.B

Q.3) Draw the CMOS layout of NOR gate.

Answer) NOR gate equation : output = not(A+B)

output = not(A).not(B)

PMOS equation : not(A).not(B)

NMOS equation : A + B

Q.4) Why are NAND gates preferred over NOR gates?

Answer) NAND gate is better gate for design than NOR because at the transistor level, the mobility of electrons is higher than the mobility of holes. Inorder to make the rise and fall times of a gates equal usually the width of PMOS transistor is made higher, so the resistance of it would be less and can attain equal rise and fall times.

In NAND gates the PMOS transistors are connected in parallel and there by its effective resistance decreases. So now one can achieve the same rise and fall times at lower widths of the PMOS, whereas in NOR gate, the PMOS transistors are connected in series, thereby increasing the resistance and also the rise time.

Q.5) Draw the CMOS, PMOS and NMOS layout of inverter.

Answer) NOT gate equation : output = not(A)

PMOS equation : not(A)

NMOS equation : A

Synthesis Interview Questions - v1.0

noreply@blogger.com (Kamlesh Bhesaniya) — Tue, 29 Apr 2014 17:40:00 +0000

Synthesis is the stage in the design flow which is concerned with translating the HDL code into gates - and that's putting it very simply! First of all, the HDL code must be written in a particular way for the synthesis tool that you are using to infer required hardware. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Q.1)What value is inferred when multiple procedural assignments are made to the same reg variable in an always block?

Answer) When there are multiple non-blocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example

always @ (posedge clk)

begin

q <= a^b;

q <= a & b;

q <= a|b;

end

Q.2) List out some synthesizable and non-synthesizable constructs.

Answer)

Synthesizable	Non-Synthesizable
Assign	Initial block
For loop	Delay statements
Gate level primitives	Events
Repeat with constant value	Real data types
	Time data type
	Fork, Join

Q.3) What is the hardware that is inferred by the conditional operator?

Answer) Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexor. For example, the following is the code for a simple multiplexor.

assign y = (s == 1'b1) ? a1 : a0;

Q.4) What logic is inferred when there are multiple assign statements targeting the same wire?

Answer) It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source. However, it is legal to drive a three-state wire by multiple assign statements

Q.5) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Answer) Slow the clock down on the one with setup violations, as by slowing the clock the data will reach before the setup time window and will not violate the setup time.

For removing hold violations, add redundant logic in the path where there are hold violations, as it will slow down the data path, and the data will not change in the hold window, thereby avoiding hold violation.

CMOS Interview Questions - v1.0

noreply@blogger.com (Kamlesh Bhesaniya) — Mon, 28 Apr 2014 16:29:00 +0000

Q.1) What do you understand by UPF?

Answer) Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process — RTL (register transfer level) or earlier.

UPF provides a consistent format to specify power-aware design information that cannot be specified in HDL code or when it is undesirable to directly specify within the HDL logic, as doing so would tie the logic specification directly to a constrained power implementation.

Q.2) Explain different approaches of state retention.

Answer) Given a power switching fabric and an isolation strategy, it is possible to power gate a block of logic, but unless a retention strategy is employed, all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. The following three approaches can be used.

A software approach based on reading and writing registers.
A scan-based approach based on the re-use of scan chains to store state off chip.
A register-based approach that uses retention registers.

Q.3) Explain glitching power dissipation and ways to minimize it.

Answer) In digital circuits glitch is an undesired transition that occurs before the signal settles to its intended value. In other words, glitch is an electrical pulse of short duration that is usually the result of a fault or design error. As shown in the adjacent diagram, there is some delay at the output O₁, which results in a glitch at output O2. As there is some capacitance associated with the output O2, it leads to switching power dissipation. This switching power dissipation arising out of a glitch is known as glitching power dissipation. ( The inverter delay implies the delay taken by gate to reflect the output after change in inputs.)

These “extra” transitions can be minimized by

Balancing all signal paths
Reducing logic depth

Realization of A.B.C.D in cascaded form where there is possibility of glitch.

Balanced realization of the same function with lesser possibility of glitch

Q.4) Which is better - sign-magnitude form of number representation or 2’s complement form in terms of power dissipation?

Answer) In most of the signal processing applications, 2’s complement is typically chosen to represent numbers. Sign extension causes MSB sign-bits to switch when a signal transitions from positive to negative or vice versa; 2’s complement can result in significant switching activity when the signals being processed switch frequently around zero. Switching in MSBs can be minimized by using sign-magnitude representation.

Q.5) Why low power has become an important issue in the present day VLSI circuit realization?

Answer) In deep sub-micron technology the power has become as one of the most important issue because of :

Increasing transistor count; the number of transistors is getting doubled in every 18 months based on Moore,s Law.
Higher speed of operation; the power dissipation is proportional to the clock frequency.
Greater device leakage currents; In nanometer technology the leakage component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power in technology generations

Clock Jitter

noreply@blogger.com (Kamlesh Bhesaniya) — Sun, 27 Apr 2014 15:52:00 +0000

Jitter

Jitter is the short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge.

Clock jitter refers to temporal variation of clock period at a given point-that is, the clock period can reduce or expand on cycle by cycle basis. it is strictly a temporal uncertainty measure and is often specified at a given point on the chip.

From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. Jitter can also be generated from PLL known as PLL jitter. Possible jitter values should be considered for proper PLL design.

Jitter can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform

Sources of Jitter Common sources of jitter include:

Internal circuitry of the phase-locked loop (PLL)
Random thermal noise from a crystal
Other resonating devices
Random mechanical noise from crystal vibration
Signal transmitters
Traces and cables
Connectors
Receivers

Impact of Jitter on sequential system

Jitter directly impacts the performance of a sequential system. Ideally, the clock period starts at edge 2 and ends at edge 5 and with a nominal clock period of TCLK. However as a result of jitter, the worst case scenario happens when the leading edge of the current clock period is delayed (edge 3), and the leading edge of the next clock period occurs early (edge 4). As a result, the total time available to complete the operation is reduced by twice t_{jitter in the worst case.}

Clock Skew

noreply@blogger.com (Kamlesh Bhesaniya) — Sat, 26 Apr 2014 12:53:00 +0000

Clock skew

The operation of most digital circuit systems, such as computer systems, is synchronized by a "clock" that dictates the sequence and pacing of the devices on the circuit. Ideally, the input to each element has reached its final value before the next clock movement occurs so that the behaviour of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at the registers is zero.

Reasons for clock skew:

This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Two types of skews are defined: Local skew and Global skew.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This is also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Why clock skew is a problem?

Two types of violation can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.

Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, because the new data was not set up and stable before the next clock tick arrived.

A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Positive Skew

When the source flop is clocked first than the destination flop, the clock skew is called as positive skew.

From the below waveform, we can see that the hold slack reduces, when there is a positive skew. Hence, we can infer that the positive skew increases the chances of hold violation.

Negative Skew
When the destination is clocked before the source, the clock skew is called as negative skew.

From the waveform below, we can see that the setup slack decreases in case of negative skew. So, the negative skew increases the chances of setup violation.

Uncertainty
Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

ALSO READ : Clock Jiiter

VLSI QnA

Verilog Timing Checks

$setup

$hold

$width

$recovery

$skew

$setuphold

Edge Sensitive Paths, Conditional Path Delay and specparam statements

Edge-Sensitive Paths

Conditional path delays

specparam statements

Specify Block

Specify Blocks :

Placement of Specify Block :

Inside Specify Blocks :

Parallel connection

Full connection

Delay Models in Verilog

Why delays are required in Verilog simulation?

Distributed Delay

Lumped Delay

Pin-to-Pin Delays

Digital Design Interview Questions - v1.3

Q.1) Explain metastability.

Q.2) What are the probable ways to avoid metastability?

Q.3) In a system with

(a) Insufficient hold time , will slowing the clock frequency will help?

(b) Insufficient setup time ,will slowing the clock frequency will help?

Q.4) Design a clock divider circuit which divides the clock by an odd number and has 50% duty cycle. (o/p clk = i/p clk/N, where N is an odd number).

VLSI Glossary

VLSI Glossary

Interview Questions on Blocking and Nonblocking Assignments

Q.1) What will be the output of following code?

Q.2) What will be the output of following code?

Q.3) What will be the output of the following code ?

Q.4) What will be the output of the following code ?

Q.5) What will be the output of the following code?

Verilog "Stratified Event Queue"

Verilog "Stratified Event Queue"

Blocking, Nonblocking Assignments and Verilog Race Condition

Blocking Assignment

Nonblocking Assignment

Finite State Machine (FSM)

Ways to design clocked sequential circuits :

Mealy Machine

Moore Machine

Q) Design a circuit that detects three consecutive '1's using Mealy and Moore FSM.

Synchronous and Asynchronous resets

Reset

Synchronous Resets :

Asynchronous Resets :

Asynchronous Reset Problem

Reset Synchronizer

Timing Parameters related to Asynchronous Reset :

T Flip Flop

Q.1) Explain T flip flop.

Q.2) Draw the excitation table for T flip flop.

Q.3) Convert J-K flip flip to T flip flop.

Q.4) Convert S-R flip flop into T flip-flop.

Q.5) Convert D flip flop to T flip flop.

Q.6) Convert T flip flop to D flip flop

Q.7) Convert T flip flop to S-R flip flop.

Q.8) Convert T flip flop into J-K flip flop.

Verilog Interview Questions - v1.5

Q.1) If a pure combinational circuit is coded inside always block, is it necessary to mention all of the inputs in the sensitivity list?

Q.2) If in1= 4'b011 and in2= 4'b0011, then the result of in1**in2 will be A) 6 B) 9 C) 27 D) Invalid expression

Q.3) Give three methods to generate clock in Verilog.

Q.4) What will be the output of the following case statement? wire [3:0] temp; always @(...) begin case (1'b1) temp[0] : Block 1; temp[1] : Block 2; temp[2] : Block 3; temp[3] : Block 4; endcase end

Q.5) Why the statement "if (2'b10 & 2'b01)." doesn't behave as expected, i.e. return true case?

J-K Flip Flop

Q.1) Explain J-K flip flop.

Q.2) Draw the excitation table for J-K flip flop.

Q.3) Convert S-R flip flop into J-K flip flop.

Q.4) Convert J-K flip flop into D flip flop.

Q.5) Convert J-K flip flop into S-R flip flop.

Q.6) Convert D flip-flop into J-K flip flop.

D Flip flop

Q.1) What is D type flip-flop?

Q.2) Draw the excitation table for D - flip flop.

Q.2) If in1= 4'b011 and in2= 4'b0011, then the result of in1**in2 will be
A) 6
B) 9
C) 27
D) Invalid expression

Q.4) What will be the output of the following case statement?
wire [3:0] temp;
always @(...)
begin
case (1'b1)
temp[0] : Block 1;
temp[1] : Block 2;
temp[2] : Block 3;
temp[3] : Block 4;
endcase
end

Q.1) If a net has no driver, it gets the value
A) 0
B) X
C) Z
D) U

Q.2) What is the default value of reg?
A) 0
B) X
C) Z
D) U

Q.3) The task $stop is provided to
A) End simulation
B) Suspend simulation
C) Exit simulator
D) None of the above

Q.4) If A= 4`1xxz and B= 4`b1xxx, then A= = =B will return
A) 1
B) X
C) Z
D) 0

Q.5) Externally, a output port must always connected to a
A) net only
B) a reg only
C) either net or reg
D) None of the above

Q.2) What will be the output/effect of the following statements?
a) a = 4'd12;
$display("Value of a = %b\n", a);
b) b = 3'd2;
$monitor($time, "Value of b = %b\n", b[2:0]);
c) `define SIZE 1024
$display(" Size is %h", SIZE);

Q.5) What is the final value of d?
initial
begin
b = 1'b1; c = 1'b0;
#10 b = 1'b0;
end
initial
begin
d = #25 (b|c);
end

Q.2) Draw the CMOS layout for the following function :
z = [a.b +c.(d + e)]