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scaling.&lt;/p&gt;&quot;]}],[0,{&quot;heading&quot;:[0,&quot;Increasing engineering effort&quot;],&quot;alphaNumeric&quot;:[0,&quot;55%&quot;],&quot;svgRefIcon&quot;:[0,&quot;&quot;],&quot;linkText&quot;:[0,&quot;&quot;],&quot;linkData&quot;:[0,&quot;&quot;],&quot;tileImage&quot;:[0,&quot;&quot;],&quot;tileImageAlt&quot;:[0,&quot;&quot;],&quot;description&quot;:[0,&quot;&lt;p&gt;The engineering effort for AI chips has more than doubled, increasing from ~10,000 to ~24,000 engineering-months. (&lt;a target=\&quot;_blank\&quot; rel=\&quot;noopener noreferrer\&quot; href=\&quot;https://www.ibs-inc.net/\&quot;&gt;IBS Global Semiconductor Industry Service, March 2026&lt;/a&gt;)&lt;/p&gt;&quot;]}],[0,{&quot;heading&quot;:[0,&quot;Skyrocketing costs&quot;],&quot;alphaNumeric&quot;:[0,&quot;120%&quot;],&quot;svgRefIcon&quot;:[0,&quot;&quot;],&quot;linkText&quot;:[0,&quot;&quot;],&quot;linkData&quot;:[0,&quot;&quot;],&quot;tileImage&quot;:[0,&quot;&quot;],&quot;tileImageAlt&quot;:[0,&quot;&quot;],&quot;description&quot;:[0,&quot;&lt;p&gt;The cost of advanced chip design has increased by over 120%, climbing from $245M to $539M (&lt;a target=\&quot;_blank\&quot; rel=\&quot;noopener noreferrer\&quot; href=\&quot;https://www.ibs-inc.net/\&quot;&gt;IBS Design Cost Report, AI, Chiplets, Sep 2024&lt;/a&gt;)&lt;/p&gt;&quot;]}],[0,{&quot;heading&quot;:[0,&quot;Constrained talent-pool&quot;],&quot;alphaNumeric&quot;:[0,&quot;1M&quot;],&quot;svgRefIcon&quot;:[0,&quot;&quot;],&quot;linkText&quot;:[0,&quot;&quot;],&quot;linkData&quot;:[0,&quot;&quot;],&quot;tileImage&quot;:[0,&quot;&quot;],&quot;tileImageAlt&quot;:[0,&quot;&quot;],&quot;description&quot;:[0,&quot;&lt;p&gt;We will see a global shortage of 1 million semiconductor workers by 2030 (&lt;a target=\&quot;_blank\&quot; rel=\&quot;noopener noreferrer\&quot; href=\&quot;https://www.deloitte.com/us/en/industries/tmt/articles/global-semiconductor-talent-shortage.html\&quot;&gt;Deloitte, 2022, the global semiconductor talent shortage&lt;/a&gt;).&lt;/p&gt;&quot;]}]]],&quot;isTwoColsInTab&quot;:[0,false],&quot;ctaButtonData&quot;:[0],&quot;layoutColumns&quot;:[0,4]}" ssr client="scroll-owner" before-hydration-url="/_astro/astro_scripts/before-hydration.js.D0rOOQXB.js" opts="{&quot;name&quot;:&quot;ContentfulIsland&quot;,&quot;value&quot;:{&quot;ownerId&quot;:&quot;contentful-sitesThreeColTiles-1oTFADuv8Rbq3y6fwjrbJO&quot;,&quot;strategy&quot;:&quot;visible&quot;,&quot;targetIds&quot;:[&quot;1oTFADuv8Rbq3y6fwjrbJO&quot;]}}" await-children><div><div class="container three-column-tile"><div class="row"><div data-ste-element="teaser" data-ste-teaser-type="tile" data-ste-teaser-title="Accelerating complexity:" class="col-12 col-sm-12 col-md-6 col-lg-3 tileHeightAdjust"><div class="tile-flex-wrapper"><strong aria-hidden="true" class="tileAlphaNumericField tile-alphaNumeric text-interactive-cyan">2X</strong><h3 class="strong tileHeading"><span class="visually-hidden">2X<!-- --> </span>Accelerating complexity: </h3><div class="tileDescription"><p>Software demands are doubling every four months, outpacing Moore’s Law scaling.</p></div></div></div><div data-ste-element="teaser" data-ste-teaser-type="tile" data-ste-teaser-title="Increasing engineering effort" class="col-12 col-sm-12 col-md-6 col-lg-3 tileHeightAdjust"><div class="tile-flex-wrapper"><strong aria-hidden="true" class="tileAlphaNumericField tile-alphaNumeric text-interactive-cyan">55%</strong><h3 class="strong tileHeading"><span class="visually-hidden">55%<!-- --> </span>Increasing engineering effort</h3><div class="tileDescription"><p>The engineering effort for AI chips has more than doubled, increasing from ~10,000 to ~24,000 engineering-months. (<a target="_blank" rel="noopener noreferrer" href="https://www.ibs-inc.net/">IBS Global Semiconductor Industry Service, March 2026</a>)</p></div></div></div><div data-ste-element="teaser" data-ste-teaser-type="tile" data-ste-teaser-title="Skyrocketing costs" class="col-12 col-sm-12 col-md-6 col-lg-3 tileHeightAdjust"><div class="tile-flex-wrapper"><strong aria-hidden="true" class="tileAlphaNumericField tile-alphaNumeric text-interactive-cyan">120%</strong><h3 class="strong tileHeading"><span class="visually-hidden">120%<!-- --> </span>Skyrocketing costs</h3><div class="tileDescription"><p>The cost of advanced chip design has increased by over 120%, climbing from $245M to $539M (<a target="_blank" rel="noopener noreferrer" href="https://www.ibs-inc.net/">IBS Design Cost Report, AI, Chiplets, Sep 2024</a>)</p></div></div></div><div data-ste-element="teaser" data-ste-teaser-type="tile" data-ste-teaser-title="Constrained talent-pool" class="col-12 col-sm-12 col-md-6 col-lg-3 tileHeightAdjust"><div class="tile-flex-wrapper"><strong aria-hidden="true" class="tileAlphaNumericField tile-alphaNumeric text-interactive-cyan">1M</strong><h3 class="strong tileHeading"><span class="visually-hidden">1M<!-- --> </span>Constrained talent-pool</h3><div class="tileDescription"><p>We will see a global shortage of 1 million semiconductor workers by 2030 (<a target="_blank" rel="noopener noreferrer" href="https://www.deloitte.com/us/en/industries/tmt/articles/global-semiconductor-talent-shortage.html">Deloitte, 2022, the global semiconductor talent shortage</a>).</p></div></div></div></div></div></div><!--astro:end--></astro-island></div></div></div><div class="theme-group theme-sand"><div id="UFGAZ0nM2Fohbel13sGBN" class="sitesCardsContainer themed-component-wrapper" data-ste-section="Sites: Cards Container" data-ste-section-id="UFGAZ0nM2Fohbel13sGBN"><div data-disw-scroll-owner="contentful-sitesCardsContainer-UFGAZ0nM2Fohbel13sGBN" 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opts="{&quot;name&quot;:&quot;ContentfulIsland&quot;,&quot;value&quot;:{&quot;ownerId&quot;:&quot;contentful-sitesCardsContainer-UFGAZ0nM2Fohbel13sGBN&quot;,&quot;strategy&quot;:&quot;visible&quot;,&quot;targetIds&quot;:[&quot;UFGAZ0nM2Fohbel13sGBN&quot;]}}" await-children><section id="UFGAZ0nM2Fohbel13sGBN" class="bg-sand-light theme-sand" role="region" aria-labelledby="section-heading-UFGAZ0nM2Fohbel13sGBN"><div class="section-heading mb-4 container text-start" data-ste-element="Sites: Section Heading"><div class="group-focus"><div class="row text-start"><div class="col col-md-8"><strong class="text-kicker">trending technologies</strong><h2><span>Our strategic imperatives </span></h2></div></div></div><div class="row text-start"><div class="col col-md-8"><p>We are pioneering EDA&#x27;s future through purpose-built solutions that address today&#x27;s trending technologies and accelerate semiconductor and PCB design.</p></div></div></div><div class="container"><div class="cards-profile cards-profile-single-column-adaptive-image-size"><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="AI-first design methodology" class="card-image-left " role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc" tabindex="0"><div><div class="card-image-left-wrapper"><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/22SnNVVELpgAXbScRkbxFJ/en-US/siemens-fuse-eda-ai-agent-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/22SnNVVELpgAXbScRkbxFJ/en-US/siemens-fuse-eda-ai-agent-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/22SnNVVELpgAXbScRkbxFJ/en-US/siemens-fuse-eda-ai-agent-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="siemens-fuse-eda-ai-agent-newsroom-01-1280x720" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">AI-first design methodology</h3><div id="undefined-desc" class="card-image-left-text"><p>We must embed context and domain-aware AI throughout the EDA workflow to shift from reactive to predictive semiconductor design.</p></div></div></div></div></div></div><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="3D IC implementation" class="card-image-left card-image-left-hovered" role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc"><a class="card-image-left-link" href="https://eda.sw.siemens.com/en-US/ic-packaging/3d-ic-design/" target="_self" rel="noopener noreferrer"><div class="card-image-left-wrapper"><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="3D IC" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">3D IC implementation</h3><div id="undefined-desc" class="card-image-left-text"><p>3D IC enables post-Moore&#x27;s Law scaling through vertical chiplet integration while introducing new challenges like thermal hotspots, multi-layer complexity, testing difficulties and design verification bottlenecks.</p></div></div></div></div></a></div><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="Hardware-software co-design" class="card-image-left card-image-left-hovered" role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc"><a class="card-image-left-link" href="/en-us/products/pave360/" target="_self" rel="noopener noreferrer"><div class="card-image-left-wrapper"><picture><img src="https://assets.new.siemens.com/dam-asset/445ed3e9-d02f-4f84-84bf-03b56b547836/Automotive--Digital-Twin-2023--Red-car-split-screen--3840x2160--V2.png?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://assets.new.siemens.com/dam-asset/445ed3e9-d02f-4f84-84bf-03b56b547836/Automotive--Digital-Twin-2023--Red-car-split-screen--3840x2160--V2.png?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://assets.new.siemens.com/dam-asset/445ed3e9-d02f-4f84-84bf-03b56b547836/Automotive--Digital-Twin-2023--Red-car-split-screen--3840x2160--V2.png?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="Digital twin of a car" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">Hardware-software co-design </h3><div id="undefined-desc" class="card-image-left-text"><p>Hardware, as an abstraction of software, requires shift-left simultaneous optimization before you can commit to silicon, delivering superior performance and efficiency through unified design flows.</p></div></div></div></div></a></div><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="Advanced-node readiness" class="card-image-left card-image-left-hovered" role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc"><a class="card-image-left-link" href="/en-us/products/ic/calibre-manufacturing/" target="_self" rel="noopener noreferrer"><div class="card-image-left-wrapper"><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="Close-up of a computer chip on a circuit board with digital overlay graphics" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">Advanced-node readiness</h3><div id="undefined-desc" class="card-image-left-text"><p>Industry acceleration toward 3nm, 2nm and future nodes, demands advanced-node readiness spanning tools, design methodologies and process expertise to navigate escalating complexity and cost pressures.</p></div></div></div></div></a></div><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="Shift-left verification" class="card-image-left card-image-left-hovered" role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc"><a class="card-image-left-link" href="/en-us/products/ic/calibre-design/shift-left-calibre/" target="_self" rel="noopener noreferrer"><div class="card-image-left-wrapper"><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/4o4WYKBF2CSiMuS76m7fgd/en-US/siemens-questa-one-agentic-ai-toolkit-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/4o4WYKBF2CSiMuS76m7fgd/en-US/siemens-questa-one-agentic-ai-toolkit-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/4o4WYKBF2CSiMuS76m7fgd/en-US/siemens-questa-one-agentic-ai-toolkit-newsroom-01-1280x720.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="siemens-questa-one-agentic-ai-toolkit-newsroom-01-1280x720" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">Shift-left verification</h3><div id="undefined-desc" class="card-image-left-text"><p>Shift-left verification is a critical chip design strategy, with AI accelerating early defect detection through intelligent pattern recognition, automated testing, yield prediction and optimized coverage.</p></div></div></div></div></a></div><div data-ste-element="teaser" data-ste-teaser-type="card-image-left" data-ste-teaser-title="Ecosystem integration" class="card-image-left card-image-left-hovered" role="article" aria-labelledby="undefined-title" aria-describedby="undefined-desc"><a class="card-image-left-link" href="/en-us/partners/eda-ecosystem-solutions/" target="_self" rel="noopener noreferrer"><div class="card-image-left-wrapper"><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/7Co00hxgsdgybzdhMg2wJn/en-US/calibre-rv-card-image-640x360.png?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/7Co00hxgsdgybzdhMg2wJn/en-US/calibre-rv-card-image-640x360.png?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/7Co00hxgsdgybzdhMg2wJn/en-US/calibre-rv-card-image-640x360.png?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="ECA CPU brand evolution - hand holding microchip" loading="lazy"/></picture><div class="card-image-left-content"><div><h3 id="undefined-title" class="card-image-left-title">Ecosystem integration</h3><div id="undefined-desc" class="card-image-left-text"><p>Ecosystem integration unifies design flows, leverages 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opts="{&quot;name&quot;:&quot;ContentfulIsland&quot;,&quot;value&quot;:{&quot;ownerId&quot;:&quot;contentful-sitesCardsContainer-3EmiSeFBuxl18kcS6ywyV0&quot;,&quot;strategy&quot;:&quot;visible&quot;,&quot;targetIds&quot;:[&quot;3EmiSeFBuxl18kcS6ywyV0&quot;]}}" await-children><section id="3EmiSeFBuxl18kcS6ywyV0" class="cards-defaultBackground" role="region" aria-labelledby="section-heading-3EmiSeFBuxl18kcS6ywyV0"><div class="section-heading mb-4 container text-start" data-ste-element="Sites: Section Heading"><div><div class="row text-start"><div class="col col-md-8"><h2 class="header-focus"><span>Explore our EDA solutions </span></h2></div></div></div><div class="row text-start"><div class="col col-md-8"><p>Learn more about our EDA products, solutions and services.</p></div></div></div><div class="container"><div class="row cards-container-row"><div class="siemens-cards col-md-4"><a href="/en-us/products/ic/" target="_self"><div data-ste-element="teaser" data-ste-teaser-type="card" data-ste-teaser-title="IC design, verification and manufacturing" id="G_%20IC%20design%2C%20verification%20and%20manufacturing%20-0" class="card blogWrap rounded-0 card-hover" role="article" aria-labelledby="G_%20IC%20design%2C%20verification%20and%20manufacturing%20-0-title" aria-describedby="G_%20IC%20design%2C%20verification%20and%20manufacturing%20-0-desc"><div class="imageWrapper"><picture><source type="image/webp"/><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3db3urC1cvz8QZEVtAa5Vs/en-US/questa-one-main-chip-digital-twin-feature-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="Close-up of a computer chip on a circuit board with digital overlay graphics" class="cardImgTop lazy" loading="lazy"/></picture></picture></div><div class="card-body d-flex flex-column p-3"><strong class="text-kicker pb-2 mb-0 text-color"></strong><div class="category d-none">all</div><h3 id="G_%20IC%20design%2C%20verification%20and%20manufacturing%20-0-title" class="pb-4 mb-0"> IC design, verification and manufacturing </h3><div id="G_%20IC%20design%2C%20verification%20and%20manufacturing%20-0-desc" class="text-black card-text pb-3 mb-0"><div><p>A comprehensive portfolio of tools for the design, verification and manufacturing of integrated circuits.</p></div></div><div data-area="card-info-section" class="d-flex flex-column justify-content-end h-100"></div></div></div></a></div><div class="siemens-cards col-md-4"><div data-ste-element="teaser" data-ste-teaser-type="card" data-ste-teaser-title="2.5/3D semiconductor heterogeneous integration" id="G_2.5%2F3D%20semiconductor%20heterogeneous%20integration-1" class="card blogWrapNoLink rounded-0" role="article" aria-labelledby="G_2.5%2F3D%20semiconductor%20heterogeneous%20integration-1-title" aria-describedby="G_2.5%2F3D%20semiconductor%20heterogeneous%20integration-1-desc" tabindex="0"><div class="imageWrapper"><picture><source type="image/webp"/><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6ZiT22BfSZKYzOaAEIfbn6/en-US/3diccard640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="3D IC" class="cardImgTop lazy" loading="lazy"/></picture></picture></div><div class="card-body d-flex flex-column p-3"><strong class="text-kicker pb-2 mb-0 text-color"></strong><div class="category d-none">all</div><h3 id="G_2.5%2F3D%20semiconductor%20heterogeneous%20integration-1-title" class="pb-4 mb-0">2.5/3D semiconductor heterogeneous integration</h3><div id="G_2.5%2F3D%20semiconductor%20heterogeneous%20integration-1-desc" class="text-black card-text pb-3 mb-0"><div><p>Solutions for the prototyping, planning, design and verification of advanced IC packaging platforms.</p></div></div><div data-area="card-info-section" class="d-flex flex-column justify-content-end h-100"></div></div></div></div><div class="siemens-cards col-md-4"><a href="/en-us/products/pcb/" target="_self"><div data-ste-element="teaser" data-ste-teaser-type="card" data-ste-teaser-title="Electronic Systems design and manufacturing" id="G_Electronic%20Systems%20design%20and%20manufacturing-2" class="card blogWrap rounded-0 card-hover" role="article" aria-labelledby="G_Electronic%20Systems%20design%20and%20manufacturing-2-title" aria-describedby="G_Electronic%20Systems%20design%20and%20manufacturing-2-desc"><div class="imageWrapper"><picture><source type="image/webp"/><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3mDgp7h2psk0sxHYgoBYAV/en-US/pcb-hero-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3mDgp7h2psk0sxHYgoBYAV/en-US/pcb-hero-640x360.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3mDgp7h2psk0sxHYgoBYAV/en-US/pcb-hero-640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="Digital twin of a printed circuit board (PCB)" class="cardImgTop lazy" loading="lazy"/></picture></picture></div><div class="card-body d-flex flex-column p-3"><strong class="text-kicker pb-2 mb-0 text-color"></strong><div class="category d-none">all</div><h3 id="G_Electronic%20Systems%20design%20and%20manufacturing-2-title" class="pb-4 mb-0">Electronic Systems design and manufacturing</h3><div id="G_Electronic%20Systems%20design%20and%20manufacturing-2-desc" class="text-black card-text pb-3 mb-0"><div><p>All aspects of electronic product development, including mechanical, electrical, PCB design, simulation, verification and manufacturing.</p></div></div><div data-area="card-info-section" class="d-flex flex-column justify-content-end h-100"></div></div></div></a></div><div class="siemens-cards col-md-4"><a href="https://eda.sw.siemens.com/en-US/consulting-services/" target="_self"><div data-ste-element="teaser" data-ste-teaser-type="card" data-ste-teaser-title="EDA consulting services" id="G_EDA%20consulting%20services-3" class="card blogWrap rounded-0 card-hover" role="article" aria-labelledby="G_EDA%20consulting%20services-3-title" aria-describedby="G_EDA%20consulting%20services-3-desc"><div class="imageWrapper"><picture><source type="image/webp"/><picture><img src="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/4h58ucsM1TEoadGYJkTYzF/en-US/AdobeStock_191904862_cr_640x360.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60" 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srcSet="https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3ajOv4flADoOxflfIh0D1S/en-US/cloud-server-640x480.jpg?auto=format%2Ccompress&amp;w=320&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 320w, https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3ajOv4flADoOxflfIh0D1S/en-US/cloud-server-640x480.jpg?auto=format%2Ccompress&amp;w=640&amp;h=360&amp;fit=crop&amp;crop=faces%2Cedges&amp;q=60 640w" sizes="100vw" alt="An array of cloud servers." class="cardImgTop lazy" loading="lazy"/></picture></picture></div><div class="card-body d-flex flex-column p-3"><strong class="text-kicker pb-2 mb-0 text-color"></strong><div class="category d-none">all</div><h3 id="G_EDA%20cloud%20offerings-4-title" class="pb-4 mb-0">EDA cloud offerings</h3><div id="G_EDA%20cloud%20offerings-4-desc" class="text-black card-text pb-3 mb-0"><div><p>We provide market-leading, best-in-class EDA tools and managed services for use in your cloud environment.</p></div></div><div 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