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    <title>RRAM-Info - The RRAM Experts</title>
    <link>https://www.rram-info.com/</link>
    <description>The RRAM Experts</description>
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<pubDate>Fri, 23 Oct 26 07:45:00 +0300</pubDate>
<item>
  <title>Weebit Nano reports a strong quarter as two customers test ReRAM silicon ahead of 2027 production</title>
  <link>https://www.rram-info.com/weebit-nano-reports-strong-quarter-two-customers-test-reram-silicon-ahead-2027-production</link>
  <description>&lt;p&gt;ReRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; reported its results for the first quarter of its 2027 fiscal year (the quarter ended September 30, 2026). Weebit reports in Australian dollars - the US dollar figures below are converted at the current exchange rate. The company keeps moving its ReRAM technology closer to mass production: two product customers are now testing working silicon with embedded Weebit ReRAM, onsemi started qualifying the technology, and two new AI customers signed on to explore ReRAM-based in-memory computing.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2026-10/Weebit-Nano-Q1-FY27-financials-infographic-USD.png" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2026-10/Weebit-Nano-Q1-FY27-financials-infographic-USD.png.webp?itok=iH07OIek" width="600" height="413" alt="Weebit Nano Q1 FY27 financials" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p class="text-align-center"&gt;&lt;em&gt;Weebit Nano Q1 FY27 at a glance (infographic: RRAM-Info)&lt;/em&gt;&lt;/p&gt;&lt;p&gt;Customer cash receipts reached US$4.3 million in the quarter (from licensing and NRE fees), and Weebit also received a US$2.6 million R&amp;amp;D tax rebate in France. Net cash used in the quarter was only US$2.3 million, and Weebit ended September with US$115.5 million in the bank. The company reaffirmed its guidance for revenue of at least US$5 million in the first half of FY27, up 26% from the same period last year. This follows a record FY26, in which revenue grew 246% to US$10.7 million.&lt;/p&gt;</description>
  <guid isPermaLink="false">366 at https://www.rram-info.com</guid>
          <pubDate>Fri, 23 Oct 2026 07:45:00 +0300
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          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>RRAM-Info-Editor</dc:creator>
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<item>
  <title>Researchers develop ReCross, an RRAM crossbar in-memory computing scheme that accelerates AI recommendation models</title>
  <link>https://www.rram-info.com/researchers-develop-recross-rram-crossbar-memory-computing-scheme-accelerates-ai-recommendation</link>
  <description>&lt;p&gt;Researchers from National Taiwan University and Taiwan's Macronix have developed ReCross, an in-memory computing (IMC) scheme that uses RRAM crossbar arrays to accelerate deep learning recommendation models (DLRMs) - the AI models used by online retailers, streaming services and advertising platforms to personalize content. The embedding layers in these models are a major memory bottleneck: Meta's data center DLRMs require up to 4 terabytes of embedding tables, and embedding lookups alone account for 50-75% of the inference runtime.&lt;/p&gt;&lt;img class="align-center align-center" src="https://www.rram-info.com/sites/default/files/mcp-uploads/ReCross-ReRAM-crossbar-embedding-reduction-2026.png" alt="The ReCross system architecture: correlation-aware embedding grouping, access-aware crossbar allocation and energy-aware dynamic switching" width="625" height="649" loading="lazy"&gt;&lt;p class="text-align-center"&gt;&lt;em&gt;The ReCross architecture (image: Lai et al., SAC '26)&lt;/em&gt;&lt;/p&gt;&lt;p&gt;In an RRAM crossbar, embedding reduction (the summing of several embedding vectors into one) can be performed as a single analog multiply-and-accumulate (MAC) operation, directly in memory. But simply mapping embeddings onto the crossbars leads to poor utilization. ReCross uses three techniques to solve this. First, it groups embeddings that are frequently accessed together onto the same crossbar, based on a co-occurrence graph built from the access history. Second, it duplicates frequently accessed embeddings across several crossbars, using logarithmic scaling to decide how many copies each one gets. Finally, a new dynamic-switch flash ADC uses a low-power read mode when only a single embedding is accessed - which the researchers found to be the case in 26-54% of crossbar activations - and switches to full MAC mode only when needed.&lt;/p&gt;</description>
  <guid isPermaLink="false">365 at https://www.rram-info.com</guid>
          <pubDate>Tue, 20 Oct 2026 12:09:23 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>RRAM-Info-Editor</dc:creator>
          </item>
<item>
  <title>Researchers combine HfO2 RRAM with stochastic MTJs to create a hybrid Ising machine for optimization problems</title>
  <link>https://www.rram-info.com/researchers-combine-hfo2-rram-stochastic-mtjs-create-hybrid-ising-machine-optimization-problems</link>
  <description>&lt;p&gt;Researchers from CEA-Leti, Spintec and C2N (Université Paris-Saclay) have developed a hybrid nanoelectronic Ising machine that combines hafnium-oxide RRAM with stochastic magnetic tunnel junctions (SMTJs). Such a machine searches for the lowest-energy state of a network of interacting binary variables, which makes it a good fit for hard combinatorial optimization problems such as vehicle routing, power-grid balancing and chip layout.&lt;/p&gt;&lt;p&gt;&lt;img class="align-center" src="https://www.rram-info.com/sites/default/files/mcp-uploads/cea-leti-reram-smtj-ising-machine.jpg" alt="The CEA-Leti / Spintec / C2N hybrid RRAM-SMTJ Ising machine prototype" width="800" height="450" loading="lazy"&gt;&lt;/p&gt;&lt;p&gt;In the new system, an RRAM crossbar array encodes the graph of the problem, while the SMTJs, whose magnetization flips randomly under ordinary thermal noise, act as probabilistic bits. The two are connected in a single loop, so the system moves toward better solutions without a digital controller managing every update. The researchers also found that tuning the read voltage across the RRAM array gradually suppresses the randomness of the SMTJs as the search progresses, which provides the annealing behavior intrinsically, without extra circuitry.&lt;/p&gt;</description>
  <guid isPermaLink="false">363 at https://www.rram-info.com</guid>
          <pubDate>Wed, 23 Sep 2026 11:58:56 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>RRAM-Info-Editor</dc:creator>
          </item>
<item>
  <title>dorsaVi begins testing its first RRAM structure, to measure the energy required to update memory states</title>
  <link>https://www.rram-info.com/dorsavi-begins-testing-its-first-rram-structure-measure-energy-required-update-memory-states</link>
  <description>&lt;p&gt;Australia-based RRAM developer &lt;a href="https://www.rram-info.com/companies/dorsavi"&gt;dorsaVi&lt;/a&gt; announced that it has begun to test its first RRAM structure, to measure the energy required to update memory states. The company says that this work is intended to establish an initial energy-performance benchmark for dorsaVi’s low-power hardware pathway before more comprehensive testing with its RRAM Validation Chip.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2026-07/DorsaVi-logo.png" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2026-07/DorsaVi-logo.png.webp?itok=0WOKDkW5" width="369" height="65" alt="DorsaVi logo" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;dorsaVi says that it sees physical AI, including advanced robotics, autonomous systems and adaptive wearables, as a potential application area where local memory and processing could reduce the need to send all raw sensor data to a distant processor.&lt;/p&gt;</description>
  <guid isPermaLink="false">362 at https://www.rram-info.com</guid>
          <pubDate>Sat, 19 Sep 2026 11:20:25 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Researchers fabricate a high-performance lead-free perovskite RRAM device, using low-temperature sputtering</title>
  <link>https://www.rram-info.com/researchers-fabricate-high-performance-lead-free-perovskite-rram-device-using-low-temperature</link>
  <description>&lt;p&gt;Researchers from Taiwan's National Cheng Kung University developed RRAM memory based on lead-free Na0.5K0.5NbO&lt;sub&gt;3&lt;/sub&gt;/HfO perovskite materials. The researchers fabricated a device using low-temperature sputtering, and report high performance and excellent process compatibility.&amp;nbsp;&lt;/p&gt;&lt;div&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2026-09/Lead-free-perovskite-RRAM-National-Cheng-Kung-University.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2026-09/Lead-free-perovskite-RRAM-National-Cheng-Kung-University.jpg.webp?itok=qygtl2YA" width="600" height="274" alt="Lead-free perovskite RRAM, National Cheng Kung University" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;The researchers say that the new device exhibits forming-free switching, low operating voltages (−1 V/1.5 V), a high ON/OFF ratio of ∼200, and endurance exceeding 105 cycles.&lt;/p&gt;</description>
  <guid isPermaLink="false">361 at https://www.rram-info.com</guid>
          <pubDate>Fri, 04 Sep 2026 15:16:16 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>4DS acquires drone swarm software startup Jenesys</title>
  <link>https://www.rram-info.com/4ds-acquires-drone-swarm-software-startup-jenesys</link>
  <description>&lt;p&gt;&lt;a href="https://www.rram-info.com/4ds-memory"&gt;4DS Memory&lt;/a&gt; announced that it plans to acquire a new an edge-AI and autonomous systems software developer called Jenesys Pty Ltd. The company seeks to raise $5 million AUD to fund this acquisition, which also includes performance rights.&amp;nbsp;&lt;/p&gt;&lt;img data-entity-uuid="3b9773e5-4329-417e-8bbb-7aee528036de" data-entity-type="file" alt="4DS Jenesys logos" data-image-style="600_width" loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/inline-images/4DS-Jenesys-logos.jpg.webp?itok=e3G7UCys" width="600" height="156" typeof="Image" class="image-style-_00-width"&gt;&lt;p&gt;Jenesys Pty was established in November 2025, and it seeks to build coordination software for drone swarms. that need to keep working when GPS and communications drop out. 4DS will pay A$5 million in shares at A$0.01 plus performance rights tied to revenue milestones.&lt;/p&gt;</description>
  <guid isPermaLink="false">360 at https://www.rram-info.com</guid>
          <pubDate>Wed, 02 Sep 2026 14:06:51 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>4DS Memory announced a lower loss in Q2 2026 following its cost reduction drive and its focus on mature-node markets</title>
  <link>https://www.rram-info.com/4ds-memory-announced-lower-loss-q2-2026-following-its-cost-reduction-drive-and-its-focus-mature</link>
  <description>&lt;p&gt;&lt;a href="https://www.rram-info.com/4ds-memory"&gt;4DS Memory&lt;/a&gt; announced its financial results for Q2 2026, with a 11% increase in revenue to $243,000 USD, and a net loss of $1.14 million USD - down 85% from last year.&lt;/p&gt;&lt;img data-entity-uuid="514266c1-7e8a-49ed-ba98-e630bd000fea" data-entity-type="file" alt="4DS Memory logo" data-image-style="600_width" loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/inline-images/4DS-memory.png.webp?itok=lpl3Zchp" width="600" height="268" typeof="Image" class="image-style-_00-width"&gt;&lt;p&gt;The company says that the improved earnings reflect the company's improved cost control and its new strategic shift toward commercialization of the 60nm RRAM platform with a focus on India's mature-node semiconductor market.&lt;/p&gt;</description>
  <guid isPermaLink="false">359 at https://www.rram-info.com</guid>
          <pubDate>Sat, 29 Aug 2026 08:15:56 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>dorsaVi starts silicon fabrication of its first RRAM-CMOS validation chip</title>
  <link>https://www.rram-info.com/dorsavi-starts-silicon-fabrication-its-first-rram-cmos-validation-chip</link>
  <description>&lt;p&gt;Australia-based RRAM developer &lt;a href="https://www.rram-info.com/companies/dorsavi"&gt;dorsaVi&lt;/a&gt; announced that it has commenced physical manufacturing of its first RRAM-CMOS validation chip. The company's manufacturing data package has passed foundry intake, the wafer lot has been committed to fabrication, and processing is now underway on the front-end CMOS base.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2026-07/DorsaVi-logo.png" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2026-07/DorsaVi-logo.png.webp?itok=0WOKDkW5" width="369" height="65" alt="DorsaVi logo" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;The chip began its tape-out process in July 2026, and the current run will produce the transistor and circuit-level structures needed to support the RRAM memory array, the peripheral circuits and various evaluation features - before the RRAM-specific layers are added. Once the CMOS base is complete, the wafers will move on to partner-led back-end-of-line processing and RRAM stack integration, followed by electrical testing and characterisation.&lt;/p&gt;</description>
  <guid isPermaLink="false">356 at https://www.rram-info.com</guid>
          <pubDate>Wed, 12 Aug 2026 21:31:20 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Peking University researchers develop OmniGuard, a two-level security framework for RRAM-based AI accelerators</title>
  <link>https://www.rram-info.com/peking-university-researchers-develop-omniguard-two-level-security-framework-rram-based-ai</link>
  <description>&lt;p&gt;Researchers from Peking University in Beijing, China, working with the Beijing Advanced Innovation Center for Integrated Circuits, have proposed a protection framework for RRAM-based deep neural network (DNN) accelerators. In this framework, the researchers split accelerator security into two distinct levels. The framework, called OmniGuard, achieves a 1.33x to 4.38x speedup and 1.26x to 2.65x power savings, with a reported 5% energy overhead and 3% area overhead.&lt;/p&gt;&lt;p&gt;RRAM-based computing-in-memory (CIM) accelerators have become one of the mainstream options for running neural network inference on edge devices, as performing the multiply-accumulate operation inside the memory array itself avoids the data movement that dominates the energy budget of conventional von Neumann designs. But edge hardware sits in the field, physically accessible to whoever holds it, and the trained model weights programmed into the RRAM array are usually the most valuable asset on the chip. The researchers note that these security vulnerabilities are a real obstacle to deploying RRAM-based accelerators commercially.&lt;/p&gt;</description>
  <guid isPermaLink="false">355 at https://www.rram-info.com</guid>
          <pubDate>Sun, 02 Aug 2026 06:37:28 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>DorsaVi</title>
  <link>https://www.rram-info.com/companies/dorsavi</link>
  <description>&lt;p&gt;DorsaVi Limited develops RRAM-based memory and neuromorphic processing technologies aimed at edge-intelligence applications in robotics, exoskeletons, prosthetics and smart sensing.&lt;/p&gt;&lt;p&gt;DorsaVi works with researchers at ITRI Taiwan and NTU Singapore to advance its technology. The company also offers a wireless movement sensor platform.&lt;/p&gt;</description>
  <guid isPermaLink="false">354 at https://www.rram-info.com</guid>
          <pubDate>Thu, 30 Jul 2026 09:02:22 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Researchers demonstrate a non-volatile RRAM-based RF switch covering DC-Ku band</title>
  <link>https://www.rram-info.com/researchers-demonstrate-non-volatile-rram-based-rf-switch-covering-dc-ku-band</link>
  <description>&lt;p&gt;Researchers from the College of Electronic and Optical Engineering at Nanjing University of Posts and Telecommunications (NJUPT) in Nanjing, China, have designed, fabricated and measured a single-pole single-throw (SPST) RF switch built on an RRAM process. The switch operates across the DC-Ku band with a measured insertion loss below 1 dB, and it holds its state without any standing bias.&lt;/p&gt;&lt;p&gt;RF switches sit in the front-end of nearly every wireless system, routing signals between transmit and receive paths. The standard options used today, field-effect transistors, PIN diodes and RF MEMS, all share a drawback: they need a continuous bias voltage or drive current to stay in either the ON or the OFF state. Over long operating periods that translates into meaningful static power draw and thermal management headaches, which is exactly the wrong trade-off for battery-powered IoT nodes and wearables.&lt;/p&gt;</description>
  <guid isPermaLink="false">353 at https://www.rram-info.com</guid>
          <pubDate>Wed, 29 Jul 2026 07:55:37 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>InnoMem Technologies and Tsinghua University present 16Mb RRAM suitable for automotive OTA applications</title>
  <link>https://www.rram-info.com/innomem-technologies-and-tsinghua-university-present-16mb-rram-suitable-automotive-ota-applications</link>
  <description>&lt;p&gt;Researchers at China's Tsinghua University, together with &lt;a href="https://www.rram-info.com/companies/innomem-technologies"&gt;InnoMem Technologies&lt;/a&gt;, have developed a 16Mb embedded RRAM device with a hybrid array structure, built on a 28 nm process, that is highly suited for automotive OTA update applications.&lt;/p&gt;&lt;img data-entity-uuid="d172160e-a8ee-4a1e-bae3-535ac815eb64" data-entity-type="file" data-image-style="600_width" loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/inline-images/Innovation-Memory-logo_0.png.webp?itok=Ek_2B00f" width="326" height="85" alt typeof="Image" class="image-style-_00-width"&gt;&lt;p&gt;The researchers say that the new 1T1R/2T2R hybrid array structure design enhances the reliability and system compatibility. The researcher used several technologies to increase performance - a load balancing approach to address the IR-drop issue and improve cell uniformity, and a hierarchical column selection strategy to suppress the leakage current in the write path, optimizing write operations at high temperature.&lt;/p&gt;</description>
  <guid isPermaLink="false">346 at https://www.rram-info.com</guid>
          <pubDate>Mon, 20 Jul 2026 10:41:28 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit Nano raises $60 million USD to support its RRAM R&amp;D and commercial expansion</title>
  <link>https://www.rram-info.com/weebit-nano-raises-60-million-usd-support-its-rram-rd-and-commercial-expansion</link>
  <description>&lt;p&gt;RRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced that it has successfully raised $87 million AUD (about $60 million USD) through placements with institutional investors and a separate offering in Israel.&lt;/p&gt;&lt;img data-entity-uuid="8c5dede6-4b88-490f-a9c5-0212d8fc52d8" data-entity-type="file" alt="Weebit Nano, the next NVM is here, logo" data-image-style="600_width" loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/inline-images/Weebit-Nano-logo.png.webp?itok=Y9Mvih8T" width="600" height="114" typeof="Image" class="image-style-_00-width"&gt;&lt;p&gt;The company will use the funds to support both technical advancements and commercial expansion.&lt;/p&gt;</description>
  <guid isPermaLink="false">344 at https://www.rram-info.com</guid>
          <pubDate>Fri, 03 Apr 2026 08:46:01 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit Nano licenses its RRAM technology to Texas Instruments</title>
  <link>https://www.rram-info.com/weebit-nano-licenses-its-rram-technology-texas-instruments</link>
  <description>&lt;p&gt;RRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced that it has licensed its RRAM technology to Texas Instruments.&lt;/p&gt;&lt;a href="https://www.rram-info.com/sites/default/files/2024-07/Weebitnano-chip.jpg"&gt;&lt;img class="image-style-large align-center" src="https://www.rram-info.com/sites/default/files/styles/large/public/2024-07/Weebitnano-chip.jpg?itok=fNRAkJr4" alt="Weebit Nano chip photo" width="400" height="220" loading="lazy" typeof="Image"&gt;&lt;/a&gt;&lt;p&gt;Under the agreement, Weebit's technology will be integrated into TI's advanced process nodes for embedded processing semiconductors. The collaboration covers IP licensing, technology transfer, design, and qualification of Weebit RRAM within TI's process technologies.&lt;/p&gt;</description>
  <guid isPermaLink="false">343 at https://www.rram-info.com</guid>
          <pubDate>Tue, 30 Dec 2025 11:28:38 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>YF Capital acquires a 2.1% stake in China-based RRAM maker InnoStar</title>
  <link>https://www.rram-info.com/yf-capital-acquires-21-stake-china-based-rram-maker-innostar</link>
  <description>&lt;p&gt;YF Capital has acquired a 2.1% stake in &lt;a href="https://www.rram-info.com/companies/innostar-semiconductor"&gt;InnoStar&lt;/a&gt;, a Shanghai-based RRAM developer established in 2019. YF Capital is a private equity firm, linked to Alibaba's Jack Ma. This follows an investment by Ant Group (also founded by Jack Ma) in August 2025.&amp;nbsp;&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2024-03/Innostar-Semi-HQ-Shanghai.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2024-03/Innostar-Semi-HQ-Shanghai.jpg.webp?itok=4fsQUodo" width="600" height="346" alt="InnoStar Semi HQ building, Shanghai" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;Last year ByteDance (owner of TikTok) &lt;a href="https://www.rram-info.com/bytedance-invests-shanghai-based-rram-developer-innostar-aiming-use-its-technology-future-vr"&gt;also investment in InnoSTar, and holds a ~9% stake&lt;/a&gt;. InnoStar uses a 28-nm process and is said to be China's first RRAM developer.&lt;/p&gt;</description>
  <guid isPermaLink="false">342 at https://www.rram-info.com</guid>
          <pubDate>Wed, 24 Dec 2025 13:26:22 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>4DS announced it is pausing its operations for 3 months for a strategic review, CTO and CSO resign</title>
  <link>https://www.rram-info.com/4ds-announced-it-pausing-its-operations-3-months-strategic-review-cto-and-cso-resign</link>
  <description>&lt;p&gt;&lt;a href="https://www.rram-info.com/4ds-memory"&gt;4DS Memory&lt;/a&gt; announced that it has decided to take a strategic three-month pause to decide its future direction after an extensive analysis of its Sixth Platform Lot memory technology.&amp;nbsp;&lt;/p&gt;&lt;p&gt;4DS also said that it will disengage from active collaborations with imec and Infineon Technologies. Following these decisions, 4DS announced that CTO Dr Ting Yen and chief strategy officer Peter Himes had tendered their resignations.&lt;/p&gt;</description>
  <guid isPermaLink="false">341 at https://www.rram-info.com</guid>
          <pubDate>Fri, 05 Sep 2025 15:32:29 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>GlobalFoundries announced that its 22FDX+ with RRAM technology is now available, with volume production coming in 2026</title>
  <link>https://www.rram-info.com/globalfoundries-announced-its-22fdx-rram-technology-now-available-volume-production-coming-2026</link>
  <description>&lt;p&gt;GlobalFoundries announced the availability of its 22FDX+ with RRAM technology. The new RRAM technology, according to GlobalFoundires, delivers secure, low-latency, high-density embedded memory for code storage for wireless microcontrollers and AI IoT applications.&lt;/p&gt;&lt;p&gt;GF’s embedded RRAM offers cost-effective memory with low power read/write, high endurance and excellent retention. On-chip integration with GF’s enhanced 22FDX platform delivers improved data retention, reliability, security and power efficiency, creating compact and versatile system-on-chip (SoC) solutions for intelligent, connected devices.&amp;nbsp;&lt;/p&gt;</description>
  <guid isPermaLink="false">340 at https://www.rram-info.com</guid>
          <pubDate>Fri, 29 Aug 2025 18:06:47 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>TSMC to start developing 6 nm RRAM technology targeting automotive AI applications</title>
  <link>https://www.rram-info.com/tsmc-start-developing-6-nm-rram-technology-targeting-automotive-ai-applications</link>
  <description>&lt;p&gt;TSMC is launching its first design center in Europe, with a focus on memory technologies for automotive applications.&amp;nbsp;&lt;/p&gt;&lt;p&gt;The company announced that it will start developing 6-nm embedded RRAM technologies, to complement its 28-nm (already qualified), 12-nm (planned). TSMC is targeting high-end automotive applications, specifically AI chips and technologies. It will also &lt;a href="https://www.mram-info.com/tsmc-develop-5-nm-mram-technology-europe-targeting-automotive-ai-applications"&gt;start developing 5-nm MRAM chips&lt;/a&gt;.&lt;/p&gt;</description>
  <guid isPermaLink="false">339 at https://www.rram-info.com</guid>
          <pubDate>Wed, 28 May 2025 13:21:21 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit and EMASS to demonstrate RRAM technology for edge AI applications</title>
  <link>https://www.rram-info.com/weebit-and-emass-demonstrate-rram-technology-edge-ai-applications</link>
  <description>&lt;p&gt;RRAM Developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced a partnership with Embedded AI Systems (EMASS), a pioneer in ultra-low-power AI computing. The two companies are collaborating to demonstrate the advantages of RRAM technology for edge AI applications.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2025-03/Weebit-EMASS-Demo-Board-EW25.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2025-03/Weebit-EMASS-Demo-Board-EW25.jpg.webp?itok=xHdQKsoX" width="600" height="450" alt="Weebit and EMASS demonstration board, EW25" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;Weebit says that the combination of its RRAM technology with EMASS’ ultra-low power AI SoC, at a 22nm process node, aims to enhance energy efficiency, reduce power consumption, and enable instant system wake-up for AI-driven applications, unlocking new capabilities in edge computing.&lt;/p&gt;</description>
  <guid isPermaLink="false">338 at https://www.rram-info.com</guid>
          <pubDate>Thu, 06 Mar 2025 11:46:16 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit Nano licenses its RRAM technology to onsemi</title>
  <link>https://www.rram-info.com/weebit-nano-licenses-its-rram-technology-onsemi</link>
  <description>&lt;p&gt;RRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced that it has licensed its RRAM memory technology to onsemi, a tier-1 semiconductor supplier.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2025-01/Weebit-Nano-Onsemi-RRAM-license.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2025-01/Weebit-Nano-Onsemi-RRAM-license.jpg.webp?itok=A9OmWDPW" width="600" height="360" alt="Weebit Nano licenses its RRAM technology to onsemi poster" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;Under the terms of the agreement, Weebit ReRAM IP will be integrated into onsemi’s Treo platform, to provide embedded non-volatile memory (NVM). Weebit ReRAM integration into a Bipolar CMOS, DMOS (BCD) process provides a low-power, cost-effective NVM that has proven excellent retention at high temperatures.&lt;/p&gt;</description>
  <guid isPermaLink="false">337 at https://www.rram-info.com</guid>
          <pubDate>Thu, 02 Jan 2025 06:36:56 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>4DS Memory signs up Infineon to develop an RRAM memory test chip</title>
  <link>https://www.rram-info.com/4ds-memory-signs-infineon-develop-rram-memory-test-chip</link>
  <description>&lt;p&gt;&lt;a href="https://www.rram-info.com/4ds-memory"&gt;4DS Memory&lt;/a&gt; announced that it has entered into a significant design agreement with Infineon Technologies to develop a custom RRAM memory test chip. 4DS says that this is a crucial step in its technology advancement.&lt;/p&gt;&lt;p&gt;Under the terms of the agreement, Infineon will provide technical expertise and resources to design the custom RRAM memory test chip based on 4DS's requirements. 4DS will pay a total of $4.5 million USD for the initial 15-month scope of work. 4DS will announce plans to raise new capital to support this agreement.&lt;/p&gt;</description>
  <guid isPermaLink="false">336 at https://www.rram-info.com</guid>
          <pubDate>Wed, 18 Dec 2024 15:24:59 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit Nano raises $32.4 million to advance its RRAM memory technology</title>
  <link>https://www.rram-info.com/weebit-nano-raises-324-million-advance-its-rram-memory-technology</link>
  <description>&lt;p&gt;RRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced that it has raised $50 million AUD (about $32.4 million USD) through a strongly supported underwritten placement to institutional investors.&lt;/p&gt;&lt;a href="https://www.rram-info.com/sites/default/files/2024-07/Weebitnano-chip.jpg"&gt;&lt;img class="image-style-large align-center" src="https://www.rram-info.com/sites/default/files/styles/large/public/2024-07/Weebitnano-chip.jpg?itok=fNRAkJr4" alt="Weebit Nano chip photo" width="400" height="220" loading="lazy" typeof="Image"&gt;&lt;/a&gt;&lt;p&gt;The company says that funds will be used to expand the company’s commercialization activities, support new customer and partner agreements, and accelerate the development of its cutting-edge RRAM technology.&lt;/p&gt;</description>
  <guid isPermaLink="false">335 at https://www.rram-info.com</guid>
          <pubDate>Tue, 03 Dec 2024 14:24:12 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Qualcomm introduces new IOT chipsets with embedded RRAM memory</title>
  <link>https://www.rram-info.com/qualcomm-introduces-new-iot-chipsets-embedded-rram-memory</link>
  <description>&lt;p&gt;Qualcomm Technologies has announced two new IOT chipsets, the Qualcomm QCC730M and Qualcomm QCC74xM modules. The company says that these modules are perfectly suited for IoT applications in the smart home, smart appliances and more.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2024-11/Qualcomm-QCC730M-features.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2024-11/Qualcomm-QCC730M-features.jpg.webp?itok=QFhOVczq" width="600" height="290" alt="Qualcomm QCC730M RRAM and features slides" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;The QCC730M chip is is a dual-band, micro-power Wi-Fi 4 module. Offering a dedicated 60Mhz MCU units, 640kB of SRAM and 1.5Mb &amp;nbsp;RRAM memory. The QCC730M also integrates hardware crypto accelerator, and secure boot, debug, and storage.&lt;/p&gt;</description>
  <guid isPermaLink="false">334 at https://www.rram-info.com</guid>
          <pubDate>Thu, 14 Nov 2024 12:14:12 +0200
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Xianxim Technology starts producing the world's first 28 nm image quality driver IC for miniLED LCD TV makers</title>
  <link>https://www.rram-info.com/xianxim-technology-starts-producing-worlds-first-28-nm-image-quality-driver-ic-miniled-lcd-tv</link>
  <description>&lt;p&gt;China-based Xianxin Technology, in collaboration with several research institutes in China, have developed the world's first 28 nm image quality adjustment chip that is powered by embedded RRAM memory.&lt;/p&gt;&lt;p&gt;The company says it is now mass producing the new driver IC, which will be supplied to high-end miniLED LCD TV makers. The company says that by adopting RRAM rather than the mainstream external Flash memory, it enables faster read operations, and lower cost production.&amp;nbsp;&lt;/p&gt;</description>
  <guid isPermaLink="false">333 at https://www.rram-info.com</guid>
          <pubDate>Thu, 12 Sep 2024 15:28:51 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Researchers from the University of Michigan explain the role of phase separation in RRAM mechanism</title>
  <link>https://www.rram-info.com/researchers-university-michigan-explain-role-phase-separation-rram-mechanism</link>
  <description>&lt;p&gt;Researchers from the University of Michigan have discovered the role of phase separation in memristor mechanism, thus paving the way to improving RRAM memory.&amp;nbsp;&lt;/p&gt;&lt;p&gt;Up until now, researchers were not sure why memristors retain their memory for a long time, as current models did not explain this fully. The new researchers explain that in memristors, oxygen ions prefer to be away from the filament and will never diffuse back, even after an indefinite period of time.&lt;/p&gt;</description>
  <guid isPermaLink="false">332 at https://www.rram-info.com</guid>
          <pubDate>Wed, 11 Sep 2024 11:18:00 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>New Radio Tech launches an RRAM-powered ultra-wideband chip</title>
  <link>https://www.rram-info.com/new-radio-tech-launches-rram-powered-ultra-wideband-chip</link>
  <description>&lt;p&gt;China-based wireless IC designer New Radio Tech (NRT) introduced a new Ultra-WideBand (UWB) chip, the URSAMAJOR 82660, that integrates RRAM. We assume that the embedded RRAM technology was provided by &lt;a href="https://www.rram-info.com/companies/reliance-memory"&gt;Hefei Reliance Memory&lt;/a&gt;, but we're not certain.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2024-09/New-Radio-Tech-URSAMAJOR%2082660.png" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2024-09/New-Radio-Tech-URSAMAJOR%2082660.png.webp?itok=ImrkB9lI" width="600" height="317" alt="New Radio Tech URSAMAJOR 82660 UWB Chip poster" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;The company says that integrating the RRAM into their chip is a major achievements, and it allows them to reduce the chip's footprint by 40%, while being highly cost effective compared to conventional chips that are based on external Flash or integrated eFlash solutions.&lt;/p&gt;</description>
  <guid isPermaLink="false">331 at https://www.rram-info.com</guid>
          <pubDate>Fri, 06 Sep 2024 09:18:02 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Weebit Nano and DB HiTek tape out their first 130nm RRAM demonstration chip</title>
  <link>https://www.rram-info.com/weebit-nano-and-db-hitek-tape-out-their-first-130nm-rram-demonstration-chip</link>
  <description>&lt;p&gt;In October 2023 RRAM developer &lt;a href="https://www.rram-info.com/weebit-nano"&gt;Weebit Nano&lt;/a&gt; announced that it has signed a licensing agreement with DB HiTek, a Korean-based foundry (said to be one of the world's top 10 foundries). The commercial agreement includes technology transfer, qualification and licensing.&lt;/p&gt;&lt;div class="align-center"&gt;&lt;div class="field field--name-field-media-image field--type-image field--label-hidden field__item" data-quickedit-field-id="media/23/field_media_image/en/default" data-once="quickedit"&gt;&lt;a href="https://www.rram-info.com/sites/default/files/2024-07/Weebitnano-chip.jpg" target="_blank"&gt;&lt;img class="image-style-large" src="https://www.rram-info.com/sites/default/files/styles/large/public/2024-07/Weebitnano-chip.jpg?itok=fNRAkJr4" alt="Weebit Nano chip photo" width="400" height="220" loading="lazy" typeof="Image"&gt;&lt;/a&gt;&lt;/div&gt;&lt;/div&gt;&lt;p&gt;Yesterday Weebit announced together with DB HiTek that it has taped-out (released to manufacturing) a demonstration chip integrating Weebit’s embedded RRAM module in DB HiTek’s 130nm Bipolar-CMOS-DMOS (BCD) process. The highly integrated demo chips will be used for testing and qualification ahead of customer production, while demonstrating the performance and robustness of Weebit’s technology.&lt;/p&gt;</description>
  <guid isPermaLink="false">330 at https://www.rram-info.com</guid>
          <pubDate>Wed, 31 Jul 2024 11:14:32 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Visionox, Sunrise Display Microelectronics and Hefei Reliance Memory develop the world's first AMOLED driver with RRAM memory</title>
  <link>https://www.rram-info.com/visionox-sunrise-display-microelectronics-and-hefei-reliance-memory-develop-worlds-first-amoled</link>
  <description>&lt;p&gt;China-based &lt;a href="https://www.oled-info.com/"&gt;OLED&lt;/a&gt; producer Visionox, together with Sunrise Display Microelectronics and &lt;a href="https://www.rram-info.com/companies/reliance-memory"&gt;Hefei Reliance Memory&lt;/a&gt;, developed the world's firs AMOLED device driver that is powered by RRAM memory.&amp;nbsp;&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2024-07/RRAM-AMOLED-design-Visionox-Sheng-Sage.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2024-07/RRAM-AMOLED-design-Visionox-Sheng-Sage.jpg.webp?itok=h4FNz-xa" width="600" height="240" alt="AMOLED driver IC with RRAM, vs classic design, by Visionox Sheng and Sage" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;All AMOLED drivers on the market use a combination of SRAM memory, OTP (one-time programmable memory) and external Flash memory (for non-volatile memory), mostly to perform the Demura compensation function. The RRAM memory enables lower cost of production, higher efficiency - and smaller area.&lt;/p&gt;</description>
  <guid isPermaLink="false">329 at https://www.rram-info.com</guid>
          <pubDate>Mon, 29 Jul 2024 10:12:54 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Researchers design a versatile compact RRAM model that can model different types of RRAM devices</title>
  <link>https://www.rram-info.com/researchers-design-versatile-compact-rram-model-can-model-different-types-rram-devices</link>
  <description>&lt;p&gt;Researchers from The University of California, Berkeley, designed a new versatile compact RRAM model that can model different types of RRAM devices such as oxide-RRAM (OxRAM) and conducting-bridge-RRAM (CBRAM).&amp;nbsp;&lt;/p&gt;&lt;p&gt;The researchers say that their new model unifies the switching mechanisms of these RRAMs into a single framework. The researchers showcase the model’s accuracy in reproducing published experimental device DC and transient characteristics of various RRAM structures. They also demonstrated the model’s efficacy in capturing RRAM variability and conducting 1T1R circuit simulations.&lt;/p&gt;</description>
  <guid isPermaLink="false">328 at https://www.rram-info.com</guid>
          <pubDate>Thu, 18 Jul 2024 15:56:49 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
<item>
  <title>Nuvoton launches an energy-efficient microcontroller that features 512Kb RRAM</title>
  <link>https://www.rram-info.com/nuvoton-launches-energy-efficient-microcontroller-features-512kb-rram</link>
  <description>&lt;p&gt;Nuvoton Technology launched the M2L31, a new energy-efficient microcontroller, that features up to 512Kb of high-performance low-power non-volatile RRAM.&lt;/p&gt;&lt;div class="align-center"&gt;
  
  &lt;a href="https://www.rram-info.com/sites/default/files/2024-06/nuvoTon-NuMicro-M2L31.jpg" target="_blank"&gt;
    
    &lt;img loading="lazy" src="https://www.rram-info.com/sites/default/files/styles/600_width/public/2024-06/nuvoTon-NuMicro-M2L31.jpg.webp?itok=3jdsVSCC" width="600" height="338" alt="NuvoTon NuMicro M2L31 photo" typeof="Image" class="image-style-_00-width"&gt;




  &lt;/a&gt;
&lt;/div&gt;
&lt;p&gt;The M2L31 is based on an Arm Cortex-M23 core (up to 72Mhz), and is designed to meet the growing demand for sustainable high-performance embedded computing power. Nuvoton explains that a main contributor to the high efficiency of the new chip is its choice of memory, an on-chip RRAM instead of flash memory that draws less power and can be written to without an erase cycle beforehand.&lt;/p&gt;</description>
  <guid isPermaLink="false">325 at https://www.rram-info.com</guid>
          <pubDate>Sun, 23 Jun 2024 14:08:26 +0300
</pubDate>
          <source url="https://www.rram-info.com/rss.xml">RRAM-Info - The RRAM Experts</source>
          <dc:creator>Ron Mertens</dc:creator>
          </item>
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