Lithography

Semiconductor-grade flow sensor measures photoresist, solvent supply

Mon, 14 May 2012 13:02:00 GMT

May 14, 2012 -- SENSIRION introduced the SLQ-QT105 semiconductor-grade flow sensor for flow rates below 2cc/sec (120ml/min) of hydrocarbon-based liquids, such as photoresists and solvents.

The flow sensor targets high-purity fluid handling applications for semiconductor, flat panel display (FPD), and photovoltaics manufacturing. Flow is measured without moving parts and non-invasively through the wall of a straight flow channel.

The SLQ-QT105 sensor features a 40msec measurement response time and very high sensitivity for flow rates down to 0.05cc/sec (3ml/min). Detection of air bubbles in the microliter range is also possible.

A smart digital interface and robust RS485 communications enable remote deployment and provide bus capability.

SENSIRION supplies humidity sensors and flow sensors. Learn more at www.sensirion.com

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Nanostructured polymer lithography platform established by CEA-Leti and Arkema

Fri, 11 May 2012 21:14:00 GMT

May 11, 2012 -- Research organization CEA-Leti, chemical company Arkema, and LCPO (Laboratoire de Chimie des Polymères Organiques), all based in France, are demonstrating the resolution potential of lithography based on nanostructured polymers. These initial results meet the requirements of the next 4 generations of electronic chips -- ranging from 20nm to sub-10nm. Building on this success, CEA-Leti and Arkema -- which first announced their partnership in microelectronics research earlier this month -- have created a development platform dedicated to this technology.

As part of their joint laboratory, Arkema and CEA-Leti, with the help of Professor Hadziioannou’s team of LCPO, have successfully patterned a 20nm pitch and reduced the diameter of contacts down to 7nm with nanostructured polymers.

Arkema and CEA-Leti have created IDEAL (Insertion of directed self assembly [DSA] lithography for CMOS application), a collaborative research platform dedicated to the development and industrialization of lithography based on nanostructured polymers. This platform relies on CEA-Leti’s expertise in process and electronic component integration, and on Arkema’s know-how in the development and industrialization of nanostructured polymers. These complementary capabilities will help adapt materials and processes to achieve optimum results for the semiconductor industry.

The self-assembly (or nanostructuring) of polymers is an alternative to conventional optical and the new extreme ultra violet (EUV) lithography technologies. DSA lithography boasts low manufacturing costs and straightforward integration in existing processes for microelectronics manufacturers. Also read: EUV, DSA ready at 11nm

Arkema has developed a block copolymer technology that yields innovative nanostructured materials with a wide range of properties, some of which are particularly suited to self-assembled lithography. CEA-Leti is using its advanced 300mm pilot line for the collaboration.

Leti (Laboratoire d'Électronique de Technologie de l'Information) is an institute of CEA, a French research and technology organization with activities in energy, IT, healthcare, defense and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in micro- and nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics, as well as in Micro-Nano Systems (MNS). For more information, visit www.leti.fr.

Arkema is a global chemical company. Learn more at http://www.arkema.com/.

President Obama speaks at Albany Nano-Tech Complex today

Tue, 08 May 2012 15:11:00 GMT

May 8, 2012 -- US President Barack Obama toured the University at Albany - State University of New York (SUNY) - Albany Nano-Tech Complex at 12EST today, speaking about the economy in the College of Nanoscale Science and Engineering’s (CNSE) NanoFab Extension Building.

Semiconductor foundry GLOBALFOUNDRIES will help host the presidential visit, which had to move from GLOBALFOUNDRIES’ new Fab 8 to the college for logistical reasons. CNSE is a global education, research, development and technology deployment resource dedicated to preparing the next generation of scientists and researchers in nanotechnology. It hosts myriad private-public partnerships with academia and research organizations partnering with global semiconductor equipment and materials suppliers, as well as chip makers. Also read: A day at Albany CNSE: Leading-edge techs, innovation vs. efficiency

GLOBALFOUNDRIES CEO Ajit Manocha will speak during the event as well. Since breaking ground on Fab 8 in 2009, GLOBALFOUNDRIES has created more than 1,300 new direct jobs with the project, drawn from local talent in the region and national and international sources. In addition, the project has created an additional 4,300 construction related jobs and established the largest private Project Labor Agreement in history, generating hundreds of millions of dollars of economic development throughout upstate New York. Fab 8 began production in January 2012, and should ramp to volume production this year.

In January, President Obama visited Intel’s Ocotillo semiconductor manufacturing location in Chandler, AZ, touring Fab 42, which is under construction. The visit carried a similar theme as today’s -- advanced manufacturing jobs in America, and improving education to develop future technological leaders from America. Obama is emphasizing the connection between education, innovation, and manufacturing in supporting investment and bringing jobs back to the US, which the administration touts as "insourcing."

"The true engine of job creation in this country is the private sector. There are steps we can take as a nation to make it easier for companies to grow and to hire -- to create platforms of success," said Obama at CNSE (via @Obama2012 on twitter). He listed ways to accelerate the US economy, including tax breaks for clean-energy companies and small business owners, support for veterans in the job market, and encouraging US-based manufacturing and exports. "American manufacturers are creating new jobs for the first time since the 1990s," he said, and asserted that half of America's largest companies are considering moving manufacturing operations from China to the US. "Even when we can't make things cheaper than other countries, we can always make them better."

From the White House: "The President’s visit to the College of Nanoscale Science and Engineering at SUNY-Albany demonstrates the important role that partnerships between universities and companies can play in accelerating education, innovation and U.S. manufacturing investment."

The President has proposed a $1 billion investment for a "National Network for Manufacturing Innovation consisting of up to fifteen institutes, each serving as a hub that will help to make US manufacturing facilities and enterprises more competitive and encourage investment in the United States." The White House says that these "hubs," like CNSE, will bring large companies, small and medium enterprises, research organizations and universities, federal agencies, and states together to advance key manufacturing technologies with broad applications. In March, the Administration announced that it "will invest $45 million in existing resources to launch a single pilot institute through a competitive award to be announced later this year."

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Lithography challenges for leading edge 3D packaging applications

Mon, 07 May 2012 18:00:00 GMT

Warren W. Flack, Manish Ranjan, Gareth Kenyon and Robert Hsieh, Ultratech, Inc., San Jose, CA. John Slabbekoorn, Andy Miller, imec, Leuven, Belgium

The lithography challenges associated with TSV fabrication for various devices structures are investigated.

The use of though-silicon via (TSV) technology was first commercialized by CMOS image sensor manufactures for use in high-end mobile phones [1]. It is expected that memory companies will start utilizing TSV technology for stacking memory chips to meet the high data rate transfer requirements within the next few years [2, 3]. Lithography is one of the critical process steps that affect the final device performance and associated yield for TSV manufacturing. One of the unique lithography challenges during TSV process step is the need for back-to-front side alignment solution. This challenge arises from the fact that the 3D devices have active metallization levels on both sides of the device and when patterning the back side, the front side alignment targets are not visible using conventional alignment approaches. This paper investigates the lithography challenges associated with TSV fabrication for various devices structures.

Silicon test wafers were fabricated with a variety of films to evaluate the back-to-front side wafer alignment. The reference layer is defined in a standard damascene copper process and protected with a passivation layer. Next the wafers are flipped, bonded, and thinned to various thicknesses. Images of the embedded alignment target are shown for various silicon thicknesses and wafer surface quality. Experimental back-to-front alignment metrology data is shown as a function of silicon thickness for various film stacks.

The embedded lithography alignment target can be viewed using three different techniques as shown in Fig. 1. The lithography system used in this investigation implements a topside IR illumination configuration for back-to-front side alignment which provides flexibility in target number and placement on a 300mm wafer [4].

FIGURE 1. Three different techniques for viewing an embedded target for back-to-front side alignment.

The lithography system used for back-to-front side alignment is an Ultratech AP300 DSA. The stepper has a 0.16 NA, 1X Wynne-Dyson projection lens design, illuminated by broadband, three-wavelength ghi-line illumination. In this investigation two types of overlay tests were run on 200 mm wafers.

Single pass topside overlay test

The single pass topside overlay has alignment and metrology features etched in the top silicon surface. The base pattern wafers were created using an ASML PAS5500/750 deep UV scanner with a specially designed mix-and-match test reticle containing alignment targets and various metrology structures. These patterns were then etched 500 nm into the silicon surface to make artifact wafers. A complementary mix-and-match test reticle was used on the AP300 for single pass testing. Alignment of targets at the top surface of the wafer was performed using the off axis DSA camera. The photoresist was 1800nm thick IX845 exposed at 250mJ/cm² in i-line mode. The resulting exposure wafers can be measured using conventional overlay metrology tools.

Double pass embedded overlay test

This technique measures overlay from embedded target alignment by forming structures at the top surface that can be measured using conventional topside metrology [4]. The double pass test wafers were prepared using a copper damascene process. A dielectric layer consisting of 250 nm of SiO2 was deposited followed by an etch-stop layer and 600 nm of SiO2. Then a PAS5500/750 scanner was used to image a base pattern using a specially designed mix-and-match test reticle. After etching the 600 nm SiO2 layer, 1000 nm of copper was deposited to fill the trenches and Chemical Mechanical Polish (CMP) was used to expose the underlying oxide, leaving a flat surface with copper filled trenches. This was covered by a SiO2 passivation layer.

The copper damascene wafers were inverted and glued to a quartz carrier. The wafers were thinned using a grinding system to three Si thicknesses (100, 200, and 300 mm). The last step was polishing the surface by CMP to remove surface damage leaving an optically smooth surface. The resulting wafer cross section is shown in Fig. 2.

FIGURE 2. Cross section of test wafers with embedded damascene Cu targets.

A mix-and-match test reticle designed to match the PAS 5500/750 patterns was used on the AP300 for double pass testing. Two layers are sequentially aligned and exposed: the first layer is aligned to the embedded reference target and with the wafer oriented at 0° rotation, and the second layer is aligned and exposed with the wafer oriented at 180° rotation. Alignment of the embedded targets was performed using the off axis DSA camera.

Metrology

Combining the two tests (single pass, and double pass) gives an effective method to calibrate back-to-front side overlay. The single pass test provides a means to monitor the full set of linear overlay terms, and the double pass test gives the relative mean bias between embedded target alignment and topside alignment.

Both single pass and double pass methods create overlay structures at the surface which can then be measured by a metrology tool or measured on the stepper using SSM. The SSM method was specifically designed to perform stepper-to-itself overlay testing for which both layers are produced in photoresist. All wafers in this study were measured using SSM per the overlay sampling plan shown in Fig. 3.

FIGURE 3. Overlay sampling plan on 200 mm diameter wafer consists of 21 measurements per field at 11 fields.

All metrology tools can introduce apparent errors known as tool induced shift (TIS) [5]. These errors include asymmetries in the measurement tool interacting with the metrology mark , the materials contrast difference between layer 1 and 2 marks, and the algorithm for localizing mark features. A standard TIS calculation involves averaging two measurements taken at 0 and 180 degrees orientation.

For the single pass topside overlay test the TIS for SSM metrology was measured to be 113 nm and 39 nm for X and Y respectively. This error is primarily attributed to the SSM measurement construction which uses a single image model to capture layer 1 in etched silicon and layer 2 targets in photoresist. The materials contrast and the CD difference between the two layers affect the TIS error measurement for single pass testing. TIS errors in single pass testing with SSM can be minimized by matching layer 1 and layer 2 dimensions in process optimization. For the double pass embedded overlay test, the material contrast and CD error sources for TIS are avoided since both layers are patterned in the same photoresist.

Results and Discussion

Example image capture for embedded targets is shown in Fig. 4. It is clear that the non-CMP wafers in 4a have prominent scratch mark that could interfere with pattern recognition. To minimize this risk, the choice of target design should be composed of a variety of angles to make the target less sensitive to texture direction such as the split circle in 4b.

FIGURE 4. DSA camera view of (a) wafer after grinding, (b) wafer after grinding and CMP polish.

In cases where the appearance of a target is obscured, the use of a synthetically created target model helps the pattern recognition to disregard features that are non productive for pattern capture (Fig. 6).

FIGURE 5. Images of DSA targets through three thicknesses of Si. At 300 µm the image gets grainier, but capture and overlay remain quite acceptable. Overall dimension of this target is 68 µm.

Fig. 5 shows a metal target viewed through 100, 200, and 300 µm silicon. Even at the thickest 300 µm thick film the target image quality was good and no problems were observed for alignment capture or overlay performance.

FIGURE 6. Plot of mean error versus silicon thickness for double pass overlay.

In Fig. 6, overlay means in X and Y from the double pass embedded overlay test are plotted as a function of silicon thickness. The error bars denote ±1 standard deviation calculated from single pass topside data.

Conclusions

Test wafers with embedded Cu targets were fabricated in a variety of silicon thicknesses to evaluate the back-to-front side wafer alignment. Single pass topside overlay testing over an extended period of time shows that consistent overlay can be achieved well within the DSA specification of 2.0 µm. More detailed double pass embedded target overlay testing shows that the effect of silicon thickness does not significantly impact the mean results relative to the single pass calibration. The results show that the simpler single pass topside test can provide reasonable accuracy for monitoring processes that align to embedded targets.

References

1. Clark, P., "CMOS Image Sensor Market Set for Steady Growth," EE Times, May 13, 2011.

2. Doe, P., "Elpida Looks to TSV," 3D Packaging, 14, February 2010.

3. TechSearch International, "Through Silicon Via Technology," January 2008.

4. Flack, W. et. al, " Development and Characterization of a 300mm Dual-Side Alignment Stepper," Optical Lithography XX Proceedings, SPIE 6520 (2007).

5. Coleman, D. et. al, "On the Accuracy of Overlay Measurements: Tools and Mark Asymmetry Effects," Integrated Circuit Metrology, Inspection, and process Control IV Proceedings, SPIE 1261 (1990).

Manish Ranjan (lead author) is Vice President, Advanced Packaging and Nanotechnology Markets at Ultratech, Inc., 3050 Zanker Road, San Jose, CA 95124 USA; ph.: (800) 222-1213; email: mranjan@ultratech.com.

Solid State Technology, Volume 55, Issue 4, May 2012

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Organic complementary logic aim of 2 European research projects

Fri, 04 May 2012 17:53:00 GMT

May 4, 2012 -- The Heterogeneous Technology Alliance (HTA), a team of European technology institutes, is focusing on high-performance organic electronic circuits through 2 projects: COSMIC to develop p- and n-type organic thin film transistors (OTFTs) for complementary logic, and POLARIC for shrinking critical dimensions (CD) of OTFTs.

OTFTs face limited device performance and volume production methods. Recent progress has enabled air-stable, printable, n-type semiconductor materials, making it possible to combine p- and n-type thin film transistors into complementary logic. This could enable breakthrough application of printed electronic circuits that perform comparably to silicon-based complementary metal-oxide semiconductors (CMOS).

Also read: Organic Electronics Workshop: TFTs, FETs, and a seeing microphone by Michael A. Fury

The COSMIC (Complementary Organic Semiconductor and Metal Integrated Circuits) project will develop p- and n-type OTFTs and integrate them into complementary logic, aiming for processing tolerances in organic integrated circuits (ICs): better noise margins, higher complexity, improved yield, and lower supply voltage demand. The researchers will demonstrate an analog-to-digital converter coupled to a temperature sensor, introducing OTFTs in the sensors and actuator market. They will also build a silent authentication tag, comprising an organic RF receiver, with potential for item-level, secure tracking of goods using realistic protocols.

Schematic from COSMIC.

Also read: High interest in low-end printable electronics by Katherine Derbyshire

The POLARIC (Printable, Organic and Large-Area Realisation of Integrated Circuits) project is mainly focused on increasing organic electronics’ performance by shrinking the CD of the OTFTs. Small critical dimensions make organic ICs compatible with high-throughput transistor fabrication methods, like roll-to-roll (R2R) nanoimprint lithography. This high-resolution patterning technique produces transistor channel lengths below 1µm, increasing organic electronics’ performance. Researchers plan to demonstrate an active-matrix liquid display and RFID tag.

VTT's vision for a flexible display backplane, POLARIC project.

The organic electronic building blocks and manufacturing platforms gained from COSMIC and POLARIC will be propagated to all areas of printed electronics -- sensors, memories, batteries, photovoltaics, lighting, etc.

The HTA is a novel approach to creating and developing micro technologies, nano electronics, and smart systems. It combines the capabilities and facilities of CEA-Leti and CEA-Liten, CSEM, Fraunhofer Group for Microelectronics, and VTT, structured to facilitate technology transfer to European and international companies. Visit www.hta-online.eu for more information.

Participants in the COSMIC project: Fraunhofer EMFT (coordinator, Germany), Commissariat à l'Energie Atomique (France), IMEC (Belgium), STMicroelectronics SRL (Italy), TNO (Netherlands), Technische Universiteit Eindhoven (Netherlands), Technische Universitat Berlin (Germany), Friendly Technologies LTD (UK), Consiglio Nazionale Delle Ricerche (Italy), Universita di Catania (Italy), and Flexink (UK), Polymervision B.V. Learn more at www.project-cosmic.eu.

Participants in the POLARIC project: VTT Technical Research Centre of Finland (coordinator, Finland), 3D-Micromac (Germany), AMO (Germany), BASF (Switzerland), CSEM (Switzerland), Cardiff University (UK), Fraunhofer EMFT (Germany), IMEC (Belgium), Imperial College London (UK), Joanneum Research (Austria), micro resist technology (Germany), Obducat Technologies (Sweden), and Asulab, a division of The Swatch Group Research and Development Ltd. (Switzerland). Learn more at www.polaricproject.eu.

Ion beam optimization to reduce EUV mask blank defects

Fri, 04 May 2012 17:00:00 GMT

PATRICK KEARNEY and FRANK GOODWIN, SEMATECH, Albany, NY

A likely cause of many of the defects seen on EUV mask blanks is the ion beam missing the target of the mask blank deposition system. This analysis provides a possible solution.

Extreme ultraviolet lithography (EUVL) is currently scheduled for high volume manufacturing starting in 2015. One of the top remaining hurdles to its implementation is the defect level of mask blanks. SEMATECH is working to accelerate progress in defect reduction by partnering with mask blank suppliers to improve the mask deposition technology at the Mask Blank Development Center (MBDC) in Albany, NY.

EUVL masks are composed of a substrate coated with a reflective molybdenum/silicon multilayer. The multilayer consists of 80 alternating layers of 4nm silicon and 3nm molybdenum. EUVL mask blanks are produced by ion beam sputtering in Veeco Nexus tools [1]. Figure 1 shows the inside of one of our mask blank deposition tools. From left to right are the target turret, the ion source, and the mask holder. The ion beam leaves the ion gun and ideally strikes a small spot (~4" diameter) on the 12" target. The ions that strike the target knock off atoms of target material, which are then launched away from the target. Some of these atoms are caught on the mask substrate, forming a film. When a layer has been deposited, the ion beam is turned off and the alternate target is moved into the ion beam position. The ion beam is turned on, and the subsequent layer is deposited. Layer thicknesses are controlled by controlling the beam voltage and current and by adjusting the deposition time of each layer. This deposition technique can meet the stringent uniformity and reflectivity specifications of EUVL masks and has the lowest proven defect level of any deposition technique for such masks.

FIGURE 1. Veeco Nexus ion beam deposition tool used in this work.

Tool shield interaction

One source of mask blank defects added during deposition is the interaction of the ion beam with the tool shields. Figure 2 shows a stainless steel defect embedded inside the multilayer that we believe came from the shields. The defect was imaged using high angle annular dark field (HAADF) imaging, and the chemical analysis was performed using energy dispersive X-ray mapping by a scanning transmission electron microscope (STEM-EDS). The defect, which clearly contains iron and chrome, reached the substrate during the deposition of the multilayer. The shields are stainless steel that have been texturized by alumina grit blasting. They are subsequently cleaned to remove the residual alumina. This allows the surface to handle thick coatings without flaking, but leaves the surface fragile under ion irradiation. Ions that hit the shield will sputter away the shield material and can eventually liberate particles of the shield material. Understanding why the ion beam strikes these shields is crucial to being able to reduce this defect source.

FIGURE 2. STEM HAADF cross sections and STEM-EDX compositional analysis of an embedded stainless steel defect.

Ion beam formation

Ion source operation involves setting many input parameters including the beam voltage that determines the ion energy, the suppressor voltage that influences beam divergence and electron backstreaming into the source, the RF power that supplies the plasma, the flow and type of gas that forms the ions, and the chamber pumping speed. Complex limits on the input parameters determine when the beam is stable enough to use for production. These input parameters also interact to influence the divergence of the beam. The theory of ion beam formation for these sources is based on the work of Kaufmann et al. [2], which predicts a beam that is well confined on the target for normal beam parameters. Because experiments have shown evidence of etching outside the target, we decided to further investigate the beam and this etching.

A simple way to measure the beam profile was to attach oxide-coated silicon wafers to the target and etch them with the ion beam. As the oxide layer is etched away, the wafer changes color. Qualitatively, the beam erosion profile can be estimated by observing the color pattern on the etched wafer; quantitatively, data can be extracted from analysis of photographs of the wafers. Charging of the oxide wafer was prevented by over-neutralizing the ion beam. The influence of the ion source parameters on the beam profile was studied with the goal of confining more of the beam to the target. The beam focus was found to improve as the suppressor voltage was lowered, the beam voltage raised, and the RF power adjusted to maintain the beam current at an optimum level that depended on both the gas type and voltages that were used. Importantly, the behavior of the optimum beam current with ion mass and the improvement in beam focus with beam energy were different from what the theory predicted, which would have led us to operate the ion source with a wider beam than necessary. Figure 3 compares images of the etch patterns under previous ion source conditions and under the optimum conditions found in this work. On the left is an image of a wafer etched at our initial operating point (600V beam voltage and 500V suppressor voltage). On the right is an image of a wafer etched at our optimized operating point (1500V beam voltage and 200V suppressor voltage). In both cases, the time was set to etch approximately 50 microns of material from the wafer at the point of maximum etch. The outer teal ring on each sample represents a contour of a constant etch rate of approximately 0.25% of the maximum etch intensity. The figure indicates that for the initial operating point this contour extends beyond the edge of the target, while under the optimized condition the contour is contained on the target. The optimized beam parameters should result in less beam missing the target, leading to fewer shield defects on the mask.

FIGURE 3. Target beam profiles for initial and optimized source parameters showing much better beam containment on the target when parameters are optimized.

Finding the source of defects

To obtain more information about the mechanisms behind the etching, we measured where in the chamber the etching species originated using a pinhole camera with an oxide wafer as the recording medium (Fig. 4). Initial measurements with an Impedans Semion [3] retarding field analyzer failed to show any ions striking the shields in the area of the etch. This suggests that the etching species are neutrals, not ions. The obvious sources for neutral atoms with enough energy to etch the shields are charge exchange collisions either in the ion beam or inside the source. A high energy ion comes close to a neutral atom with a thermal velocity. An electron from the atom crosses over to the high energy ion, resulting in an ion and a high energy neutral. Cross sections for charge exchange collisions can be larger than for physical collisions between ions and atoms.

FIGURE 4. Pinhole camera image of ion source, ion beam and target and an optical image of the same locations.

We are currently improving the model of the ion source/ion beam in collaboration with Tech-X Corporation [4]. The plan is to use their VORPAL software to model the plasma within each beamlet of the ion beam, including gas scattering and charge exchange collisions. The model should be able to more realistically predict the ion beam profile throughout the chamber as the source parameters are varied. We are also using the pinhole camera technique to quantify the amount of etch from both the ion source and ion beam as the beam parameters are varied. This data should help us keep the ion beam on the target and reduce ion beam-induced shield defects.

References

1. Veeco Instruments, Plainview, NY, USA. www.veeco.com

2. Kaufman, H., R., Cuomo, J., J., Harper, J. M., E., "Technology and applications of broad-beam ion sources used in sputtering. Part 1. Ion source technology," J. Vac. Sci. Technol., 21(3), 725-736 (1982).

3. Impedans, Dublin, Ireland, www.impedans.com

4. Tech-X Corporation, Boulder, CO, USA, www.txcorp.com

Patrick Kearney is an EUV Technical Expert and FRANK GOODWIN is the program manager for SEMATECH's EUV Mask Blank Defect Reduction Program and Mask Blank Development Center., Albany, NY. e-mail: Patrick.Kearney@sematech.org.

Solid State Technology, Volume 55, Issue 4, May 2012

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CEA-Leti unveils wide-reaching silicon research scope

Wed, 02 May 2012 20:51:00 GMT

May 2, 2012 -- CEA-Leti has introduced the “LETI-3S” concept, for “Silicon Specialty Solutions.” The research is oriented to start-ups, component integrators, fabless or fablite chip companies, and equipment/consumable suppliers. Other potential partners include foundries, research centers with a limited processes offer, micro and nanotechnologies companies that do not want low-volume activities, and high-value silicon wafer suppliers.

3S addresses deposition; front side/back side clean, wet etch, and strip; lithography with dual side alignment capability; etching, implant, epitaxy, diffusion; chemical mechanical polishing (CMP), bonding, grinding, dicing; and advanced in-line metrology.

LETI-3S will operate on the Minatec Campus in Grenoble on 24/7 200mm and 300mm wafer platforms in its 8,000-m² state-of-the-art clean rooms. Smaller wafer sizes will also be available thanks to an innovative holder technology. LETI-3S can provide substrates or work on customer wafers, pre-processed or not, under stringent contamination protocols.

LETI-3S ensures a full traceability from process flow conception to product delivery. SPC, FMEA, audits or conformance certificates to specifications are available according to the type of inquiry.

Laurent Malier, CEO of CEA-Leti, said LETI-3S offers “simple access to [CEA-Leti’s] resources.” He expects the program will significantly enlarge Leti’s panel of industrial partners in different sectors. CEA-Leti currently hosts 200 assignees from partner companies.

CEA is a French research and technology organization, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies in order to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. Visit www.leti.fr.

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Become the Best of West at SEMICON West

Tue, 01 May 2012 21:08:00 GMT

May 1, 2012 -- Solid State Technology and SEMI will present the 2012 Best of West product awards at SEMICON West 2012, July 10-12 in San Francisco. Best of West recognizes important product and technology developments in the microelectronics industries.

This is the second year that Solid State Technology has co-hosted the awards program. Check out last year's winner: SigmaTech's UltraMap-TSV system.

All SEMICON West exhibitors are eligible to participate. Consideration for the Best of West awards will be limited to all products, services and technologies publicly introduced from August 1, 2011 to SEMICON West 2012. Entries are limited to two per exhibitor, and the submitting company cannot be representative firms or other third-parties.

Winners will be selected by an independent panel of highly qualified judges from academia and the industry. Entries are judged on their financial impact on the industry, engineering or scientific achievement, or societal impact and benefits. SEMI reserves the right to make all final decisions on eligibility.

Deadline for submissions is extended to May 21, 2012! Submit a Best of West entry.

To enter the Best of West competition, submit company name and contact information, a maximum 750-word description of the new product /technology, and a maximum 300-word summary of why it’s important, in Microsoft Word. Supporting charts, graphs and illustrations must be submitted as part of the Microsoft Word document. Entries that are not submitted in Microsoft Word or otherwise do not follow instructions will be rejected.

Finalists will receive recognition for their achievement through press releases, on the SEMICON West website, through online exhibitor directories, and special booth displays.

Winners will be announced during SEMICON West and will be selected from the pool of finalists. Judges may visit exhibitors during SEMICON West to obtain further information on the submission.

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Arkema enters microelectronics manufacturing research area with CEA

Tue, 01 May 2012 19:32:00 GMT

May 1, 2012 -- French research organization CEA will extend its collaboration with chemical company Arkema beyond photovoltaics into microelectronics and organic electronics, setting up two joint public-private research projects in CEA-Leti and CEA-Liten.

The partners will develop ultra-high-performance materials and manufacturing processes to grow the leading-edge electronics sector in France. Arkema will nanostructure polymers to produce new materials that optimize performance and cost of next-generation silicon components. CEA researchers will share expertise in microelectronics development processes. The CEA-Leti (Laboratoire d'Electronique et de Technologie de l'Information) will focus on microelectronics and information technologies. CEA-Liten (Laboratoire d’Innovation pour les Technologies des Energies Nouvelles et les nanomatériaux) will study new energy technologies.

Also read: CEA-Leti Annual Review: The heart of Europe's semiconductor industry challenges

Arkema will bring a group of technical polymers (fluorinated, piezoelectric, nanostructured thermoplastic polymers) to Liten to meet the technological challenges of the large-area printed electronics sector (flexible screens, intelligent packaging and textiles, photovoltaic panels). The aim is to improve system lifetimes, manufacturing costs, and integration of several functions onto a single support. The use of organic materials opens up a new field of printable, transparent and flexible components that can be integrated into large-area printed electronic products.

The partnership will help develop new materials for lithography and organic electronics manufacturing, said Christian Collette, VP of research & development at Arkema. Microelectronics are a new focus of research for Arkema.

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defense and security. Leti specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. For more information, visit www.leti.fr.

Arkema is a global chemical company. Learn more at http://www.arkema.com/.

A fresh perspective on 450mm

Tue, 01 May 2012 05:00:00 GMT

I recently had the good fortune to moderate the SEMI Northeast Forum on 450mm in Albany. Presenters were Michael Liehr, vice president of research for CNSE and general manager of the G450C Consortium; Bruce Kellerman, Senior Director, Product Marketing, MEMC; Gary Gallagher, VP, 300mm and 450mm /On-site Services; and Akihisa "Aki" Sekiguchi, SPE Corporate Marketing, Tokyo Electron Ltd. (Aki was a last minute stand-in for IBM's Paul Farrar who was called away on business).

The forum was held in one of the auditoriums at the CNSE Albany Nanotech campus, which has rapidly become the focal point of semiconductor R&D in North America.

Liehr led things off with what was really the first public glimpse into the new G450C. He said their goal was to install about 100 450mm tools in a large cleanroom at CNSE (in the $365 million NanoFab Xtension building under construction). These would represent 50 different tool types, with two competing suppliers of each type of tool. Request for quotes (RFQs) have already been sent out, and he expects tools to start arriving in the second half of 2013, with the remainder of the tools coming in over the subsequent one and a half years. The pilot line, if you want to call it that, would then be operational around the end of 2014 or the beginning of 2015.

The G450C was part of a huge investment of $4.4 billion was announced last year, with $400 million coming from New York State, for R&D in Albany and other NY sites (2500 new high tech jobs!).

Despite this noteworthy progress, many challenges remain before 450mm can become a reality. "It's a real challenge for us," Kellerman of MEMC said. "We're basically going to be losing money until this reaches maturity. It's an ugly scenario." He said he saw no significant technical hurdles, noting that mechanical wafes are readily available and test wafers are being made available. However, he said, many issues were unclear: the timing, the transistor architecture, the starting material and the tool availability, to name a few. G450C is off to a great start, but it is still early.

Solid State Technology, Volume 55, Issue 4, May 2012

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What have we done for you lately?

Tue, 01 May 2012 05:00:00 GMT

This page is usually reserved for a guest editorial by someone in the industry that wants to rant a little bit about the lack of standards in any given area, the need to get young students interested in engineering and the sciences, why fab safety is so important, or answering the call to innovate, to give a few examples.

This month, I'd like to put on my Associate Publisher hat and tell you about some of the changes Solid State Technology has recently made, and what we can do for you.

For starters, you may have noticed a change to our logo on the front of the magazine and on our website, with a bit more empahsis on the "Solid State" part of it. We did this in part to call attention to our roots, going back 54 years to 1958. The magazine actually started out as "Semiconductor Products" and then became "Semcionductor Products and Solid State Technology" in 1962, and then "Solid State Technology" in 1968. It was cool then, and it's still cool today!

Another reason for the change is that we have broadened our focus beyond mainstream semiconductor manufacturing to include more on advanced packaging, MEMS, LEDs, displays and other types of electronics such as biomedical devices, sensors and power electronics. Each of these has evolved to the point where new and unique process technologies and materials are required, and our goal is to keep you informed of the latest advances.

Most of you are reading this magazine in a digital format, perhaps on a mobile device. In October of last year, we launched a new design tailored for easy readability in the digital format.

We also made substantial improvements to our website, www.solid-state.com, to provide easier navigation, better search, faster load times, better SEO and greater ease-of-use with mobile devices. Five channels (each with topic centers) focus on Semiconductors, Packaging, MEMS, LEDs and Displays.

We have a strong line-up of Solid State Technology newsletters now including: WaferNEWS, LED Manufacturing News, Displays Digest, Advanced Packaging News, MEMS Direct and, every weekday, The Daily Pulse (sign up on the web).

Each month, we deliver this magazine to 40,000 people around the world. If you include SST China and SST Taiwan, each of which includes translated and original content, that number is well over 57,000 (57,301 to be exact).

What's important to note here is that the people reached by the magazine is a very different audience than that of our website (about 100,000 unique visitors/month) and newsletter subscribers (45,000). This gives us a total worldwide reach of 233,286 people.

In addition to the magazine and the website, we produce The ConFab, an exclusive invitation-only event coming up next month in Las Vegas (I'm the conference chair), webcasts, technology guides, videos, and an online Buyer's Guide. On our website, you'll also find white papers, podcasts, blogs and a bunch of other stuff (whew, if you're tired of reading this, think about me!).

Industry Forum columns conclude with a call to action, so here it is: Think about how you might contribute material. We're always looking for good feature content – you'll find our "roadmap" in our editorial calendar – as well as business and technology news, blogs, columns, book reviews, conference reports, case studies, how-to articles, new products.. you name it. We're happy to work with you to see what makes the most sense.

Any questions? Contact me for editorial matters, at peters@pennwell.com, and, for advertising and sponsorships, contact Kerry Hoffman at kerryh@pennwell.com.

Solid State Technology, Volume 55, Issue 4, May 2012

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Reducing mask write-time—which strategy is best?

Tue, 01 May 2012 05:00:00 GMT

Steffen Schulze and Tim Lin, Mentor Graphics, Wilsonville, OR

A number of techniques have been developed to control mask write time by reducing shot count. This article describes and compares several techniques, and the merits versus cost of each.

An upcoming challenge of advanced-node design is the expected mask write time increase associated with the continued use of 193nm wavelength lithography. If nothing is done, then shot count, the major predictor of mask write time, will increase more than 10x. A number of techniques have been developed by electronic design automation (EDA) software suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing. These approaches promise a reduction in shot counts anywhere between 10% and 40%. This article describes and compares several techniques, and the merits versus cost of each[1].

Mask write time increase has a number of dimensions. One is the increase in shot count: the number of shots directly correlates to mask write time. The addition of more shapes from OPC contributes as well. Another dimension is the introduction of litho techniques like multi-patterning, which adds more masks to the set and hence increases the overall mask writing time. The growth in mask counts can be countered with capacity and won't be addressed here.

Increased mask write time leads to increased mask cost that detracts from the benefit of moving to advanced nodes, so taking steps to mitigate or reduce this cost is attractive. However, these additional steps also impose some news cost on the overall process. We introduce a number of techniques that mitigate the impact on mask write time and offer a benefit versus effort of deployment assessment [2].

Shot count reduction approaches

We analyzed the following shot count reduction approaches:

• Optimized fracture

• Pre-fracture jog alignment

• L-shot

• Multi-resolution writing (MRW)

• Optimization-based fracture

• Optimized OPC output

Optimizing fracture

The baseline shot count is defined by the fracture step – a general polygon can be fractured into elementary figures in a variety of ways – hence the fracture algorithm can be tuned to achieve the minimum shot count.

The fracture step is driven by three metrics:

• Smallest total shot count

• Smallest number of outside small figures (shots exceeding the vendor recommended smallest shot size)

• Smallest number of dual shot splits for critical cd features

Tuning the heuristic to the node-driven changes in design style and RET/OPC methodology can lead to a reduced shot count. In a recent test on an M1 22nm design, roughly a 2% shot count reduction was achieved. While the reduction is not large in itself, such improvements have a large cumulative effect over time, and other algorithm improvements, such as small-outside figure reduction, also indirectly improve the shot count. This method is also easy to adopt with minimal cost to the user.

Jog alignment

One source of small figures is misaligned vertices on opposing sides of polygons, a.k.a jogs. Misaligned jogs can occur in OPC during fragmentation, when different data levels are merged prior to fracture, or during biasing. When jogs are misaligned even by a small amount, a small trapezoid is required between them. Jog alignment suppresses the small figures by identifying jogs on opposing sides of polygons and aligning them based on user-defined parameters[3]. The principle is shown in Fig. 1.

FIGURE 1. Reduction of shot count by jog alignment using Calibre MASKopt.

Jog alignment is an additional processing step that is inserted into the workflow prior to the fracture. It is conducted with the same tools as in the current flow. Because the mask target is modified, a verification step to assess the mask edge placement error (EPE) is recommended. The downstream processes on the mask writer are not impacted by this method, including the onboard proximity effect correction (PEC) algorithms.

FIGURE 2. Jog alignment results (Calibre MASKopt) showing shot count and EPE range versus max. jog alignment at mask scale.

Jog alignment can yield significant shot count reduction, as illustrated in Fig. 2. In an experiment, we applied jog alignment, varying the jog movement distance over a range of 0nm up to 100nm at mask scale. A 34% shot count reduction was achieved without any degradation of the mask (based on the EPE range).

L-shot

L-shot fracture reduces shot count by expanding the range of geometries that can be written in a single shot [4]. Current e-beam mask writing tools allow triangles or rectangles. The concept of L-shot fracture is to let the write tools make a single shot in the shape of an "L". Overall, a shot count reduction of between 20% and 40% was achieved.

To create an L-shaped shot, an additional aperture is required in the write tools. Today, two rectangular apertures are used to create rectangular shots of different sizes, but a cross-shaped aperture is needed for L-shot. This requires significant development by the e-beam write tool manufacturers. This method does not change other fundamentals of the mask writing process.

Multi-resolution writing

Photomasks are conventionally written in two or more passes in which the same data is exposed multiple times with a shifted placement. Each identical exposure integrally multiplies the mask write time.

The objective of multi-resolution writing (MRW) is to jointly customize the shot patterns in both passes. In particular, one may decompose the exposure into one "detail" pass with about as many shots as the conventional pass and one "coarse" pass with many fewer shots such that the desired image is obtained. The coarse pass deposits an "average" image and the detail pass "refines" it [5].

We used a prototype model-based MRW software on a 22nm active layer, and the results are shown in Figure 3. The maxDist parameter controls the aggressiveness of MRW, with maxDist = 0, meaning that no MRW is applied. The shot count reduction was up to 33%.

FIGURE 3. MRW results showing shot count and EPE range versus maxDist at mask scale. Noteworthy is that the EPE range is reduced over the base-line, owing to the application of mask process correction as part of the algorithm to secure the mask target.

The deployment of this method requires adjustments both to data preparation and to the mask writing equipment. The MRW software is used before fracture, then the two different data layers are fractured.

Optimized-based fracture

Optimization-based fracture is one method for writing curvilinear masks within a reasonable shot count [6]. In traditional fracture, trapezoids are created to exactly cover the input polygons submitted to the fracture algorithm; shots are abutting and non-overlapping. Optimization-based fracture relaxes those constraints.

Shots can be placed such that they can overlap or be non-abutting so that sub-resolution gaps exist. The optimization problem is formulated to minimize the number of shots while maintaining the intended post-OPC pattern on the mask. The solution incorporates an e-beam blur (forward scattering + resist blur) model to properly simulate the overlapping and non-abutting shapes. Allowing for overlapping shots and non-abutting shots expands the solution space and provides the optimization engine more opportunity to reduce the shot count. Experiments demonstrate up to 28% reduction with a limited impact on wafer process window and max EPE. However, it does require an update to the workflow on the current mask writer equipment.

Optimized OPC output

The complexity of the OASIS layout presented to the mask manufacturing process is largely driven by the RET and OPC processes. The insertion of assist features, the decoration of layout shapes and the simplification of smooth target mask contours as obtained by inverse lithography methods with tight tolerances increase the shot count of the output. A number of techniques to reduce the complexity and hence reduce the mask writing time can be applied during the application of OPC. In this case, any changes to the output layout are intrinsically verified against the tolerances required by the litho process. The OPC tools referenced in this study (Calibre OPCproTM and Calibre nmOPCTM) offer two main user-controlled options to reduce shot count [7,8].

• Jog-smoothing – the alignment of adjacent fragments to eliminate vertices prior to the final iterations

• Jog-alignment – vertex alignment across the shapes during the fragmentation step

Assessment of mask write time solutions

Deployment of mask write time reduction techniques in a running mask manufacturing line requires changes that will impact the current technology, workflows, and equipment to varying degrees. We aimed for maximum write time reduction at the lowest cost and with the smallest impact to the running operation.

We associated a cost indicator as a relative rating of the effort for the implementation and execution of each technique. Benefit indicators are associated with the potential for shot count reduction. The results of the assessment are displayed in Fig. 4.

FIGURE 4. Benefit and effort assessment for various mask write time reduction techniques.

A few observations are noteworthy. The biggest benefit is obtained from optimized OPC output, which also incurs one of the lowest costs of adoption. Optimization-based fracture with dose modulation ranks highest on the cost scale. All methods modifying the mask shapes impose increasing effort depending on the complexity of the changes.

Optimized OPC output wins

We reviewed several mask write time reduction techniques designed to contain the increase in mask shot count while preserving the results quality. Multiple factors impact the cost associated with shot count reduction – CD control on mask and wafer, hardware and software changes, and data preparation effort. The goal is to get maximum write time reduction at the lowest cost and with smallest impact to the running operation. The technique of optimized OPC output was the clear winner. Post-OPC data simplification techniques of varying complexity follow a steep deployment cost curve and require careful consideration.

Acknowledgements

The authors would like to thank their colleagues from Mentor Graphics – A. Elayat, E. Sahouria, P. Thwaite, J. Mellmann, N. Akkiraju, Y. Granik, U. Hollerbach.

References

1. A. Elayat, T. Lin, E. Sahouria, S.F. Schulze, "Assessment and comparison of different approaches for mask write time reduction", Proc SPIE 8166, 816634 (2011) http://go.mentor.com/23bmz

2. James Word, Keisuke Mizuuchi, Sai Fu, William Brown, Emile Sahouria, "Mask shot count reduction strategies in the OPC flow", Proc. SPIE 7028, 70283F (2008) http://dx.doi.org/10.1117/12.799410

3. Steffen Schulze, Emile Sahouria, Eugene Miloslavsky, "High-performance fracturing for variable shaped beam mask writing machines", Proc. SPIE 5130, 648 (2003) http://go.mentor.com/236y3

4. Emile Sahouria and Amanda Bowhill, "Generalization of shot definition for variable shaped e-beam machines for write time reduction", Proc. SPIE 7823, 78230T (2010) http://go.mentor.com/236y4

5. Emile Sahouria, "Multiresolution mask writing", Proc. SPIE 7985, 798503 (2011) http://dx.doi.org/10.1117/12.881929

6. Timothy Lin, Emile Sahouria, Nataraj Akkiraju, Steffen Schulze, "Reducing shot count through optimization-based fracture", Proc. SPIE 8166, 81660T (2011) http://dx.doi.org/10.1117/12.897779

7. Sean Hannon, Travis Lewis, Scott Goad, Kenneth Jantzen, Jianlin Wang, Hien T. Vu, Emile Sahouria, Steffen Schulze, "Reduction of layout complexity for shorter mask write-time", Proc. SPIE 6730, 67303K (2007) http://go.mentor.com/236y5

8. Ayman Yehia, "Mask-friendly OPC for a reduced mask cost and writing time", Proc. SPIE 6520, 65203Y (2007) http://go.mentor.com/236y6

Steffen Schulze is product marketing director for Calibre mask data preparation products at Mentor Graphics Corp., 8005 S.W. Boeckman Rd., Wilsonville, OR 97070; ph 800/547-3000, e-mail steffen_schulze@mentor.com. Tim Lin is technical marketing engineer for Calibre mask data preparation products at Mentor Graphics Corp., 46871 Bayside Parkway, Fremont, CA 94538; ph ph 800/547-3000, e-mail tim_lin@mentor.com.

Solid State Technology, Volume 55, Issue 4, May 2012

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Vistec delivers electron-beam lithography system to ITME researchers in Poland

Thu, 26 Apr 2012 15:42:00 GMT

April 26, 2012 -- Vistec Electron Beam GmbH, electron-beam (ebeam) lithography system supplier, sold a Variable Shaped Beam system SB251 to the Institute of Electronic Materials Technology (ITME) in Warsaw, Poland, for R&D on micro-optical and diffractive elements, new materials, and masks for optical lithography.

The purchase decision was made as a result of a European tendering procedure.

Vistec's electron-beam writer offers high performance and flexibility, said Dr. Zygmunt Luczynski, director of ITME. The Vistec SB251 is a universal system, designed for direct write and mask making exposures. It handles and exposes transparent & non-transparent materials for semiconductor and optics applications. The tool features 50kV electron optics, an address grid of 1nm, and an exposure platform with a stage travel range of 210mm². Lithography below 50nm is achieved on various substrates, from pieces to 200mm wafers and 7” masks. It also boasts a graphical user interface (GUI), fully automated cassette-to-cassette substrate handling, and the data preparation software package ePLACE (provided by EQUIcon GmbH).

The collaboration between ITME and Vistec began more than 20 years ago, noted Wolfgang Dorl, general manager of Vistec Electron Beam.

As a leading research institute in Poland, ITME is working in the multidisciplinary area of research, development and manufacturing of materials, innovative devices and components for application in electronics, micromechanics and optoelectronics. ITME manufacturing technologies are being developed for single crystals of semiconductor materials, oxide crystals (optical, piezoelectric), super-pure metals, and active glass. Nanotechnologies are widely used in studies of new materials. The Institute develops epitaxial structures for electronic and optoelectronic devices, innovative lasers, photo detectors, sensors, filters, piezoelectrics, and diffractive lenses. The single-crystal growth method invented by Prof. Jan Czochralski is continued at the Institute. Development of this method leads to the subsequent development of highly advanced technologies in a field of semiconductor and oxide single crystals. For more information see: http://www.itme.edu.pl/home-page.html.

The Vistec Electron Beam Lithography Group is a global manufacturer and supplier of electron-beam lithography systems with applications ranging from nano and bio-technology to photonics and industrial environments like mask making or direct writing for fast prototype development and design evaluation. The Vistec Electron Beam Lithography Group combines Vistec Lithography and Vistec Electron Beam. Website: www.vistec-semi.com.

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Major semiconductor makers order EUV lithography metrology tool from Carl Zeiss

Wed, 25 Apr 2012 14:14:00 GMT

April 25, 2012 -- Carl Zeiss Semiconductor Metrology Systems (SMS) Division won orders for its extreme ultraviolet lithography (EUVL) actinic aerial image metrology system, AIMS EUV, from 2 of the 4 members of SEMATECH’s EMI partnership (GLOBALFOUNDRIES, Intel, Samsung Electronics, TSMC). The tool allows semiconductor makers to review defects in advanced masks needed for EUVL.

The remaining 2 EMI members are expected to place orders in accordance with their agreed-upon slot assignments, noted Dr. Oliver Kienzle, managing director of Carl Zeiss SMS.

Carl Zeiss SMS developed the AIMS EUV tool in cooperation with the scanner optics department of Carl Zeiss SMT, Lithography Optics (LIT), and external partners.

Kienzle notes that the metrology tool wins “confirm the relevance of EUV technology for the industry.” Metrology tools for EUVL are an industry need that could benefit from governments' support, asserted Dan Armbrust, president & CEO of SEMATECH, at the SEMI Industry Strategy Symposium (ISS) 2011.

The AIMS EUV platform enables development and manufacturing of defect-free EUVL masks supporting the 22nm half-pitch (hp) technology node, with extendibility to 16nm hp. A first production-ready platform is scheduled for delivery in Q3 2014.

SEMATECH’s EMI project, begun in 2010, tackles the infrastructure gap for EUV mask manufacturing, by funding development of critical metrology tools. EMI is administered by SEMATECH’s Lithography Program, based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. At SEMICON West 2011, Stefan Wurm, SEMATECH, discussed EUV lithography's infrastructure, saying the SEMATECH EMI initiative was successful in developing commercial tools through a joint development agreement with Carl Zeiss, and commercial actinic blank inspection that meets memory manufacturer needs through EIDEC. SEMATECH is now working to extend inspection to meet all industry needs (memory, logic, and foundry).

Recent news from the SEMATECH Lithography program: SEMATECH adds Inpria resists to EUV lithography work

EMI’s first major project involved SEMATECH and Carl Zeiss collaborating on the development and manufacturing of the first actinic aerial image metrology EUV system targeted for EUVL volume production.

Learn more at http://www.zeiss.de.

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SEMATECH adds Inpria resists to EUV lithography work

Tue, 24 Apr 2012 21:02:00 GMT

April 24, 2012 -- Inpria, chemical materials supplier for thin-film deposition, joined the consortium SEMATECH’s Resist Materials and Development Center (RMDC) in its Lithography Program. Inpria and SEMATECH will tackle on critical issues for resist in extreme ultraviolet (EUV) lithography. The partnership will rely on SEMATECH’s hardware and research expertise and semiconductor experience, and Inpria’s advanced semiconductor patterning materials and processes.

The RMDC is hosted at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany.

Inpria’s inorganic resists have resolved 11nm line/space features and exhibit high etch resistance. Inpria and SEMATECH will extend resists to qualify the 0.5 NA EUV imaging optics, which support resist research for 11nm half-pitch (hp) and smaller nodes in the RMDC facilities. Inpria will also work to increase the photosensitivity of its resist materials, meeting productivity requirements for future semiconductor manufacturing applications.

Also read: EUVL resist and materials development for the 22nm node and beyond

This partnership will “rapidly increase the rate of development” for Inpria’s EUV lithography materials, said Andrew Grenville, CEO of Inpria. It will also “help strengthen the RMDC’s ability to address critical resist issues in advanced materials,” said Stefan Wurm, director of Lithography, SEMATECH.

SEMATECH’s RMDC will provide access to 2 micro-exposure tools (METs) as well as several metrology tools located at the College of Nanoscale Science and Engineering of the University at Albany and the University of California, Berkeley. At the RMDC, leading resist and materials suppliers participate in focused, cooperative R&D with SEMATECH member companies. Together, the RMDC provides the hardware and research expertise required by materials suppliers and member companies to develop EUV resist processes that meet the stringent resolution, linewidth roughness, and sensitivity specifications needed for EUV insertion at member companies.

SEMATECH is an international consortium of leading semiconductor device, equipment, and materials manufacturers. Learn more at this year celebrates 25 years of excellence in accelerating the commercialization of technology innovations into manufacturing solutions. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at www.sematech.org..

Inpria designs and synthesizes solution precursors for the deposition of high-performance inorganic thin films, addressing critical needs in device fabrication and patterning across multiple industries. Information about Inpria Corporation can be found at www.inpria.com.

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Semiconductor subsystems see record revenues thanks to 32nm and below

Mon, 23 Apr 2012 19:08:00 GMT

April 23, 2012 -- Strong lithography spending, as well as several acquisitions and divestures in the space, brought changes to the critical subsystems of semiconductor/related markets sector, says VLSIresearch.

2011 was a record year for critical semiconductor manufacturing subsystem suppliers, with 9.3% revenue growth to $7.88 billion for the industry segment. Semiconductor manufacturing at 32nm and smaller nodes drove capital expenditures, stimulating demand for high-value critical subsystems. Weakening demand was seen from the flat panel display (FPD), data storage, light-emitting diode (LED) and photovoltaic industries. Another record year is on the horizon, VLSIresearch estimates, with 2012 set to beat the $8 billion mark for the first time.

Table. Top 10 suppliers of critical subsystems 2011. Copyright © 2012 VLSI Research Inc. All rights reserved.
Company	Rank 2010	Rank 2011	Critical subsystems revenues 2011, $M
Carl Zeiss SMT	1	1	1545
Edwards	3	2	585
MKS Instruments	2	3	530
Brooks Automation	4	4	425
Pfeiffer Vacuum Technology	21	5	310
Horiba Ltd	6	6	250
Advanced Energy Industries	5	7	235
Cymer Inc.	8	8	235
EBARA Corporation	9	9	190
Hirata	13	10	180

Carl Zeiss SMT continued to gain market share as the top supplier, coming out of 2011 with record lenses sales at $1,545 million.

Edwards recaptured the #2 ranking from MKS Instruments, which dropped to #3.

Brooks Automation performed well, retaining #4.

The big gainer was Pfeiffer Vacuum Technology, which acquired Alcatel-Lucent’s Vacuum Technology Unit, Adixen, at the end of 2010. Pfeiffer Vacuum jumped sixteen places to #5.

Horiba consolidated its #6 position, while Advanced Energy Industries lost 2 places as the sale of its Aera mass flow business to Hitachi Metals took effect.

Cymer (#8) and EBARA (#9) posted steady growth.

A surge in Q1 2011 sales propelled Hirata into the Top 10 for the first time.

VLSIresearch inc provides market research and economic analysis on the technical, business, and economic aspects within nanotechnology and related industries. VLSIresearch’s primary databases and reports cover the semiconductor, flat panel display, PV cell and module manufacturing industries, and the market for critical subsystems and components within these and associated high technology industries. Website: www.vlsiresearch.com.

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North American semiconductor fab tool makers see March book-to-bill hike

Fri, 20 Apr 2012 11:39:00 GMT

April 20, 2012 -- With a book-to-bill ratio of 1.13, North America-based manufacturers of semiconductor equipment saw a sixth climb in the ratio, which has steadily improved since it hit 0.71 in September 2011, according to SEMI's March Book-to-Bill Report.

The three-month average of worldwide bookings in March 2012 was $1.48 billion, the highest reported value since July 2011, said Denny McGuirk, president and CEO, SEMI. The bookings figure is 10.7% higher than the final February 2012 level of $1.34 billion, and 6.4% below the $1.58 billion in orders posted in March 2011.

The three-month average of worldwide billings in March 2012 was $1.31 billion. The billings figure is 0.9% less than the final February 2012 level of $1.32 billion, and is 20.9% less than the March 2011 billings level of $1.66 billion.

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. A book-to-bill of 1.13 means that $113 worth of orders were received for every $100 of product billed for the month.

Figure. Billings and bookings figures are in millions of U.S. dollars. Source: SEMI April 2012

	Billings (3-mo. avg)	Bookings (3-mo. avg)	Book-to-bill

Oct 2011	1,258.3	926.8	0.74
Nov 2011	1,176.7	977.2	0.83
Dec 2011	1,300.0	1,102.9	0.85
Jan 2012	1,239.9	1,187.5	0.96
Feb 2012 (final)	1,322.8	1,336.9	1.01
March 2012 (prelim)	1,310.9	1,479.3	1.13

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is a global industry association serving the nano- and micro-electronic manufacturing supply chains. For more information, visit www.semi.org.

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Ultratech brings former member back to Board

Thu, 19 Apr 2012 12:39:00 GMT

April 19, 2012 - BUSINESS WIRE -- Ultratech Inc. (UTEK), lithography and laser-processing system supplier to semiconductor manufacturers and packaging providers, added Michael C. Child to its Board of Directors. Child served on Ultratech’s Board of Directors from 1993 to 1997.

Child has been with TA Associates Inc., a Boston-based private equity firm that manages over $16 billion in capital, since 1982, and is currently a senior advisor. He sits on the boards of Finisar Corporation, IPG Photonics, and FreeWave Technologies. While at TA, he has served as a director of 16 public companies including AST Research, Cadence Design Systems, DH Technology, Eagle Test Systems, Fargo Electronics, Network General Corporation, Novellus Systems, and Sonic Solutions. Prior to joining TA, Child worked for Rolm Corporation as a product manager, The Boston Consulting Group as a consultant, and Hewlett-Packard as a production engineer.

Child holds a bachelors of science in electrical engineering from the University of California at Davis and an M.B.A. from the Stanford Graduate School of Business.

Child combines extensive knowledge of this industry and of Ultratech itself, noted Ultratech chairman and CEO Arthur W. Zafiropoulo.

Ultratech Inc. (UTEK) designs, manufactures and markets photolithography and laser processing equipment for bump packaging of integrated circuits and high-brightness LEDs (HBLEDs). Ultratech developed laser spike anneal technology, which increases device yield, improves transistor performance and enables the progression of Moore's Law for 45-nm and below production of state-of-the-art consumer electronics. Visit Ultratech online at www.ultratech.com.

ASMC will focus on productivity and technology challenges

Wed, 18 Apr 2012 20:13:00 GMT

The 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2012) will be held May 15-17 in Saratoga Springs, New York. The conference will feature presentations of more than 85 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features a panel discussion on “Competing for R&D Dollars,” moderated by Solid State Technology Editor-in-Chief Pete Singer, and 15 technical sessions on advanced semiconductor manufacturing, as well as a tutorial on Advanced Device Design offered by IBM Research.

For over 20 years, ASMC has provided a premier venue for industry professionals to learn and share knowledge on new and “best practice” semiconductor manufacturing issues and concepts. ASMC provides a valuable source of cost-effective, hands-on solutions to address real-world manufacturing challenges. It is acknowledged as a leading technical conference that enables collaboration and sharing of technical breakthroughs. This year’s conference features keynotes delivered by industry leaders, including: Michael Campbell, senior vice president, Engineering, Qualcomm, and Andrea Lati, principal analyst, VLSI Research.

As advances in materials and process technology continue, the semiconductor manufacturing industry is faced with difficult challenges as it balances costs and critical technology issues. Limited R&D dollars is the reality, and it is unclear how wafer size transition, next node scaling, new transistor technology, 450mm EUV, and 3D-IC will be funded. To address this issue, ASMC offers a panel discussion this year on “Competing for R&D Dollars: Funding the Future” with panelists from Applied Materials, ASML, GLOBALFOUNDRIES and IBM addressing 450mm, EUV and 3D.

ASMC 2012 sessions include:

Factory Optimization: Semiconductor equipment and manufacturing are increasingly complex with strict economic constraints. The sessions discuss novel solutions to improve equipment/factory productivity and performance.
Advanced Metrology: Advanced semiconductor manufacturing demands advanced metrology techniques. This session details new technologies and improvements.
3D/Through Silicon Via (TSV): Very Large Scale Integration motivates 3D integrated circuit architectures. This session presents complexities of TSV techniques supporting 3D designs.
Equipment, Materials & Processes: Advanced memory and logic manufacturers face daunting challenges as the next generation device nodes come on line. Innovations in equipment, materials, and processes help meet those challenges.
Emerging Technologies and Innovative Devices: Innovative integrated circuit functionalities continue to be integrated in semiconductor manufacturing. This session presents analysis of the effects of enabling technologies, and innovative integrated circuit designs.
Equipment and Materials Productivity: Optimizing equipment and performance will help improve fab metrics, minimize wafer costs and maximize competitiveness— how to help optimize equipment utilization, improve predictive modeling of fab operations, and tool performance.
Advanced Patterning and Design for Manufacturability: IC production today requires innovative lithography design and manufacturing techniques, including collaborative efforts between chip makers and equipment suppliers discussing leading-edge solutions
Process Development and Control: The demand for high quality and product yields is a constant driver for advanced process development and control techniques. Session covers improvements in processes, tool controls and predictive process performance analysis.
Defect Inspection and Yield Optimization: Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices

ASMC also holds an interactive poster session and reception, which provides an ideal opportunity for networking between authors and conference attendees. During this session, participants can engage authors in in-depth discussion of a wide range of issues.

ASMC 2012 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT). Corporate sponsors include: Applied Materials, ATMI, ChemTrace, CNW Courier Network, Edwards, KLA-Tencor, Mentor Graphics, Nikon, NY Loves Nanotech, and Valqua. Additional sponsors include: Saratoga Convention & Tourism Bureau, Saratoga Economic Development Corporation, and the city of Saratoga Springs, New York.

Laser lithography tool uses piezo stage to construct submicron features

Tue, 17 Apr 2012 16:20:00 GMT

April 17, 2012 -- The new laser lithography tool from Nanoscribe GmbH produces complex 3D submicron structures up to 1mm with 150nm widths, boasting full automation and precise repeatability. It is based on a 3-axis piezo nano-positioning stage from PI (Physik Instrumente).

The PImars P-563 flexure-guided, piezo-driven nanopositioning XYZ stage provides positioning ranges to 300 x 300 x 300µm and nanometer-range repeatability. A parallel-metrology position feedback system based on highly linear capacitive sensors allows the sample to be moved precisely and repeatedly in relation to the laser focus. A digital piezo motion controller provides path control.

The tool can be used to construct biometric characteristics or to create microstructures for small pumps and needles.

More information on XYZ piezo nano-positioning systems is available at http://www.nanopositioning.net/XYZ_nanopositioning_stage.php#P563

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