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2012-02-09T17:29:00.002-08:00

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MICROPROCESSOR BASED IMPEDANCE RELAY

2012-02-09T17:22:00.000-08:00

MICROPROCESSOR BASED IMPEDANCE RELAY

ABSTRACT

With growing complexity of modern power systems, faster, more accurate and reliable than existing protection schemes have become essential. Microprocessor based protective schemes are the latest development in this area.

These micro processor based schemes generally deliver better performance at relatively lower cost and with simpler construction because the operation of the scheme depends largely on programming the micro processor and little on the actual hardware connections.

In this paper the implementation of an impedance relay using 8085 microprocessor is described. That kit used for this purpose is Vinytics VMC 8506 which has an inbuilt ADC interface based on ADC0809 chip and also some relays which can be turned on or off by providing simple 8085 instructions. The relay is operated in three zones with the required delay based on impedance.

INTRODUCTION

In some applications it is necessary that the relay protecting a part of the power system operate for faults within a certain distance of the location on any one of the lines. The protecting scheme accordingly uses distance relays and is divided into three zones. The zones are classified based on the impedance seen by the relay and the relays are hence called impedance relays.

OPERRATING PRICIPLE OF THE IMPEDANCE RELAY

The operation of an impedance relay can best be understood by examining the complex plane impedance locus which is shown in figs.1 If the fault impedance is Z then the relay operates instantaneously when

| Z | < |Z 1| that is if it lies in the zone 1. If |Z 1| < | Z | < | Z 2|, then the fault is in second zone and thus the relay operates after some delay. For | Z | lying between | Z 2 | and | Z 3 | a greater delay is introduced before the operation of the relay because the fault is in the third zone of operation. If | Z | exceeds | Z 3 | then the relay will not operate as the fault impedance is outside the operating zone of the impedance relay.

TORQUE PRODUCED IN AN ELECTROMECHANICAL IMPEDANCE RELAY

In an impedance relay, the torque produced by a current element is balanced against the torque of a voltage element. The current element produces positive (pick up) torque proportional to I² whereas voltage element produces negative torque proportional to V². the torque equation is

T=K’I² - K’’ V² + K’’’

Where K’ and K’’ are torque constants and K’’’ is spring constant and is generally neglected. At balance point T=0, from this equation we get impedance V/I = Sq. root of (K’/K’’)

DISADVANTAGES OF ELECTROMECHANICAL IMPEDANCE RELAYS

It has poor mechanical stability.

Operates rather slowly.

Possibility of incorrect operation because of the mechanical constraints.

Very tough to change the zones of protection.

MICROPROCESSOR BASED IMPEDANCE RELAY

The disadvantages of a conventional impedance relay arte overcome by using microprocessors for realizing the operation of the relays. Microprocessor based relays perform very well and their cost is relatively low.

ADVANTAGES OF MICROPROCESSOR BASED RELAYS

v Flexibility

v Highly reliable

v Fast operation

IMPEDANCE RELAY

To realize an impedance relay, the voltage and current are supplied to the microprocessor via an A/D converter which supplies the corresponding digital values to the processor. The microprocessor then finds the fault impedance by dividing the voltage count with the current count. Based on this fault impedance the microprocessor decides the zone in which the relay has to be operated and sets the delay time accordingly.

HARDWARE

INTRODUCTION

The hardware required for realizing an impedance relay using microprocessors is dealt in this paper. The basic block diagram of the scheme is shown in Fig.2.

The fault current and voltage are fed to the ADC through channel 1 and channel 0. The channel selection is done by the microprocessor and the information is carried on to the ADC through the chip 74LS144. Start of conversion pulse is also given through this decoder chip to the ADC. The EOC line from the ADC chip is passed on to the 8085 microprocessor through a latch 74LS367.

The digital readout is given to the microprocessor via an octal tristate buffer 74LS244. Depending on the fault impedance calculated by the microprocessor it issues a trip signal after some delay to the relay. This relay is directly interfaced with the microprocessor

VOLTAGE INPUT

The analog voltage is fed to the ADC through a bridge circuit containing a C-filter as shown in Fig.3.

The supply voltage is stepped down to 3V rms and then fed to the bridge rectifier circuit. Thus the dc output voltage available after rectification is 4.2V. A high value capacitor is connected from the output to ground to smoothen out the ripple present after rectification. This dc voltage is fed to channel 0 of ADC.

CURRENT INPUT

Since the ADC can sense only voltage levels a proportional voltage to the fault current is generated by passing the fault current through a low resistance of 0.1 ohms and measuring the voltage drop is the resistance. Since the drop is of the order of fraction of a volt and the ADC cannot sense voltage variations in that order, the drop is amplified using an op-amp inverting amplifier whose gain is fixed at 10. Since the output voltage of the inverting amplifier is negative, it is connected to the ground pin of the ADC and the op-amp ground is connected to channel 1 to take care of the polarities. The circuit for current input is shown in Fig4.

ADC INTERFACE

VMC 8506 provides an onboard for ADC 0809 chip which is based on successive approximation type analog to digital conversion. It allows the user to have 8 analog input channels from channel-0 to channel-7. These input points are brought out at the connector J9 in the VMC 8506 kit.

PROCEDURE FOLLOWED FOR USING ADC 0809

The input channel is selected by out putting the code 00 to 07 at input port of ADC 0809 whose active range port addresses range from 98 to 9F for channel select and start of conversion signals. The program uses the port address 98H for this purpose. After the start of conversion pulse is sent by outputting 08 at this port address, the EOC signal is checked at port No.A8. Digital data is read from port no38.

ADC 0809

The interfacing of ADC with microprocessor is shown in the basic block diagram in Figure 5.

RELAYS

VMC-8506 provides facility of DIP relays on its board. These DIP relays have an address (80-87) and are used in I/O mapped mode. The address (80-87) here means that any of the addresses from 80 to 87 can be used. These relays provide one N/O contact which closes on energizing the relay. The DIP relays used are O/E/N make and are 52-71A-05-0 and have nominal coil voltage of 5V DC. The full specifications of these relays are specified by the manufacturer are:

SPECIFICATIONS

CONTACT FORM NORMALLY OPEN

CONTACT RATING : MAX.POWER-10 WATTS

MAX VOLTAGE-100 VOLT D.C.

MAX. CURRENT-0.25 (SWITCHING)

-1.00 (CARRYING)

CONTACT RESISTANCE : 150 MILLIONS (INITIAL)

DIELECTRIC WITHSTANDING ACROSS CONTACTS-200V DC

CONTACTS TO COIL-1000V RMS.

OPERATE TIME : 0.5 MILLI SECONDS (MAX.)

(INCLUDING BOUNCE)

RELEASE TIME : 0.35 MILLI SECONDS (MAX)

(0.50 MILLI SECONDS WHEN SUPPRESSOR DIODE IS USED)

THE PROCEDURE FOLLOWED FOR ENERGIZING THE RELAYS

The relays onboard can be energized as follows:

1. The accumulator is loaded with 01, 02, 04 or 08 depending upon which relay 1, 2, 3 or 4 has to be energized.

2. This data is outputted at address 80.

In our program only relay 1 is used. Thus the accumulator is loaded with 01.

The tripping signal is issued at port 80.

The relay is directly interfaced with the microprocessor.

SOFTWARE

INTRODUCTION

The program for realizing the impedance relay characteristic is divided into four modules. This paper gives a description of the individual modules and their flow charts along with combining the modules for effective operation.

MODULE-1: MAIN ROUTINE

The flow chart for this routine is shown in figure 5. first channel 0 of ADC is selected and the digital equivalent of the voltage input at channel 0 is read. It is stored in memory. Similarly, the digital equivalent of the voltage signal which is proportional to the fault current is read from channel 1 and it is placed in another memory location.

Next, the fault impedance is calculated by calling a division routine that performs the V/I calculation. The result is stored in another memory location.

Then the fault impedance is compared with the three zone impedances which are placed in successive memory locations as input data. If Z < Z1 then the control is transferred to the instruction labeled TRIP1 in the delay subroutine. If Z < Z2 then it is given to TRIP2 and if Z < Z3 then to TRIP3. for values of Z exceeding this limit, no trip signal is issued and the control is transferred back to the reading of channel 1.

Channel 0 need not be read again as it is fed from constant voltage source.

After the trip signal is issued the control automatically gets transferred from the delay routine to again the reading of channel 1 in the main program.

MODULE-2:ADC SUBROUTINE

The flow chart for this routine is shown in figure 6. After getting the number of channel that has to be read from the main routine, a start of conversion pulse is applied to the ADC chip along with the channel number. The end of conversion signal from the ADC is checked continuously until it is high. Then the digital data which is available at the ADC output port is read by the microprocessor and is stored in the accumulator for further processing.

MODULE-3:DIVISION SUBROUTINE

The flow chart for this subroutine is shown in fig 7. The division here is performed by trial subtractions. The divisor is subtracted from the 8 MSBs of the dividend. If there is no borrow, the bit of the quotient is set to 1: otherwise 0. to line up the dividend and quotient properly the dividend is shifted lift by one bit before each trial of subtraction. The dividence and quotient share a 16-bit register. Due to shift of dividend one bit of the register falls vacant in each step. The quotient is stored in vacant bit positions.

MODULE-4: DELAY CUM TRIP SUBROUTINE

The flow chart for this module is shown in fig 8. It has three entry points TRIP1, TRIP2 and TRIP3 which are accessed, from the main program. The register C is given a count depending on the trop status decided by the main program for zone 2 and zone 3 operations. For zone 1, TRIP 1 entry is accessed and no delay is evoked.

After executing the delay part the instruction for sending a trip signal to the relay are executed making the relay operate.

Then control is transferred to the main module at the channel-1 selection instruction

CONCLUSION

Microprocessor based relays are becoming rapidly popular because of the advantages they offer. But they also suffer from some drawbacks. They offer high initial cost and it is not economical to replace the existing electromechanical relays with microprocessor relays.

The microprocessor based impedance relay is implemented using the available hardware on VMC-8506 microcomputer board and with necessary external hardware. The microprocessor based relays are invading the power system network since they are flexible and reliable. The same board can be used for over current and directional over current protection and hence cost of the relay will be less compared to conventional type

LATEST TITLES OF PROJECTS FOR COMPUTER SCIENCE (IEEE) STANDARD

2012-02-09T04:37:00.000-08:00

LATEST TITLES OF PROJECTS FOR COMPUTER SCIENCE (IEEE) STANDARD

CONFERENCE-IEEE INFOCOM

DOUBLE-COVERED BROADCAST (DCB): A SIMPLE RELIABLE BROADCAST ALGORITHM IN MANETS:--JAVA--2004

Mobile ad hoc networks (MANETs) suffer from high transmission error rate because of the nature of radio communications. The broadcast operation, as a fundamental service in MANETs, is prone to the broadcast storm problem if forward nodes are not carefully designated. The objective of reducing the broadcast redundancy while still providing high delivery ratio for each broadcast packet is a major challenge in a dynamic environment. In this paper, we propose a simple, reliable broadcast algorithm, called double-covered broadcast (DCB), that takes advantage of broadcast redundancy to improve the delivery ratio in the environment that has rather high transmission error rate. Among 1-hop neighbors of the sender, only selected forward nodes retransmit the broadcast message. Forward nodes are selected in such a way that (1) the sender’s 2-hop neighbors are covered and (2) the sender’s 1-hop neighbors are either a forward node, or a non-forward node but covered by at least two forwarding neighbors. The retransmissions of the forward nodes are received by the sender as confirmation of their receiving the packet. The non-forward 1-hop neighbors of the sender do not acknowledge the reception of the broadcast. If the sender does not detect all its forward nodes’ retransmissions, it will resend the packet until the maximum times of retry is reached. Simulation results show that the algorithm provides good performance for a broadcast operation under high transmission error rate environment

COMBINATORIAL APPROACH FOR PREVENTING SQL INJECTION ATTACKS:--J2EE--2009

A combinatorial approach for protecting Web applications against SQL injection is discussed in this paper, which is a novel idea of incorporating the uniqueness of Signature based method and auditing method. The major issue of web application security is the SQL Injection, which can give the attackers unrestricted access to the database that underlie Web applications and has become increasingly frequent and serious. From signature based method standpoint of view, it presents a detection mode for SQL injection using pair wise sequence alignment of amino acid code formulated from web application form parameter sent via web server. On the other hand from the Auditing based method standpoint of view, it analyzes the transaction to find out the malicious access. In signature based method It uses an approach called Hirschberg algorithm, it is a divide and conquer approach to reduce the time and space complexity. This system was able to stop all of the successful attacks and did not generate any false positives.

INTERNATIONAL CONFERENCE ON INTELLIGENT AND ADVANCED SYSTEMS

PREDICTIVE JOB SCHEDULING IN A CONNECTION LIMITED SYSTEM USING PARALLEL GENETIC ALGORITHM:--JAVA--2005

Job scheduling is the key feature of any computing environment and the efficiency of computing depends largely on the scheduling technique used. Intelligence is the key factor which is lacking in the job scheduling techniques of today. Genetic algorithms are powerful search techniques based on the mechanisms of natural selection and natural genetics. Multiple jobs are handled by the scheduler and the resource the job needs are in remote locations. Here we assume that the resource a job needs are in a location and not split over nodes and each node that has a resource runs a fixed number of jobs. The existing algorithms used are non predictive and employs greedy based algorithms or a variant of it. The efficiency of the job scheduling process would increase if previous experience and the genetic algorithms are used. In this paper, we propose a model of the scheduling algorithm where the scheduler can learn from previous experiences and an effective job scheduling is achieved as time progresses.

CONFERENCE-IEEE INFOCOM

DOUBLE-COVERED BROADCAST (DCB): A SIMPLE RELIABLE BROADCAST ALGORITHM IN MANETS:--JAVA--2004

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How to make all links open in new windows

2012-02-08T00:21:00.000-08:00

How to make all links open in new windows :

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complete guide to select in tcs

2012-01-25T07:41:00.000-08:00

complete guide to select in tcs

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COMPLETE GUIDE TO FACE TCS

JNTU-ANANTAPUR : B.Tech 1,2,3,4 Years (I & II Semester) April/May/June-2011 Regular/Supple Exams Question Papers

2012-01-20T02:20:00.000-08:00

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2012-01-19T04:57:00.000-08:00

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2nd Semester(2-1,2-2) Syllabus for R09 Regulations (B.tech & B.Pharmacy)

Student guide

GATE 2009 QUESTION PAPERS WITH KEY&SOLUTIONS ALL BRANCHESGATE 2009 QUESTION PAPERS WITH KEY&SOLUTIONS ALL BRANCHES

GATE 2009 QUESTION PAPERS KEY&SOLUTIONS ALL BRANCHES

CLICK HERE TO DOWNLOAD

MICROPROCESSOR BASED IMPEDANCE RELAY

LATEST TITLES OF PROJECTS FOR COMPUTER SCIENCE (IEEE) STANDARD

How to make all links open in new windows

complete guide to select in tcs

JNTU-ANANTAPUR : B.Tech 1,2,3,4 Years (I & II Semester) April/May/June-2011 Regular/Supple Exams Question Papers

JNTU Syllabus Books For All Years & All Branches (R09,R07 & R05)

JNTU ANANTAPUR (JNTUA)

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