The GP5080 reference platform, provides developers with a low power, high data system throughput of more than 120 MB/s in sequential read and over 80 MB/s in sequential write with 4-channel NAND Flash access.

Translated into layman’s language this is bags faster than hard disk drives during booting.

Below is a block diagram of the reference platform

As well as the SATA interface, the GP5080 features a 32-bit ARM7 processor.  This provides firmware capability to improve the SSD’s performance in terms of lifetime and reliability by providing higher computing capability such as a flash translation layer, bad block management, wear leveling algorithm and power fail recycling.

There were compatibility issues with standard polysilicon gates that prevented transistors from switching properly at low threshold voltages, therefore high-k gate dielectrics are paired with a metal gate electrodes, hence the term high-k gate metal gate (HKMG). 

Two commercial manufacturing methods have emerged to integrate these materials namely “gate-first” and “gate-last” and are offered by GLOBALFOUNDRIES and TSMC respectively. Eager to capture 28 nm design starts both methods have been compared for both their merits and potential disadvantages. So which one does a design team choose for their 28 nm SoC?

HKMG Gate First, Gate Last

Dr Hoffmann articulates these differences in the above table. Essentially for low power applications gate-first is the better choice. However, for high performance applications the gate-last process with the faster transistors is more appropriate.

The synergies between cloud computing and I/O Virtulization (IOV) are pretty straight forward: cloud computing assumes a complete decoupling of applications from platforms (any application can run on any platform). For that to happen – efficiently – you have to be able to provide an application with just the right mix of CPU performance, connectivity, I/O bandwidth (QoS to be more precise) to clients, storage or other processors as required. That is hard to do with the existing PC-derived server architecture where the I/O capabilities of a server (HBAs, NICs, DAS…) are defined at data center build-time rather than at application run-time. IOV effectively separates all the I/O from the compute part of the servers and allows the above “mix” to be dynamically tuned on demand.

Why PCI Express? It’s the default I/O interconnect in servers today. It in effect defines the boundary between the compute and I/O subsystems in a server. So why would you use anything else? Putting anything else in the way (eg., Infiniband) just adds cost, power, complexity and a bandwidth bottleneck.

Another characteristic of using PCI Express is that we can make the IOV technology completely transparent to the server software. The servers still see standard PCIe NICs and HBAs (albeit those are now virtual rather than physical) and run the same standard I/O vendors’ driver and management utilities. This makes minimises the potential disruption caused introducing IOV (never a good thing in the real world) and also accounts to some extent why you don’t see a “bandwagon” effect. PCIe IOV does not require an “ecosystem” because of this “transparency”. It also makes it a very horizontal technology. It doesn’t just apply to clouds but to all computing platforms today. It is certainly a key enabler for clouds, but I wouldn’t want associated only with clouds.

There’s a much bigger market out there.

Serial ATA (SATA) is a high-speed serial bus interface used to transfer data from motherboards to peripheral storage devices, such as optical disk drives, HDDs and solid state disk drives. The SATA interface is being integrated into SoCs for consumer electronic products and enterprise class storage systems.  According to IDC, more than 1.1 billion SATA hard drives have shipped from 2001 to 2008. Last year, SATA captured more than 98% of internal hard disk drive shipments, demonstrating that SATA technology is now used in the vast majority of desktop and mobile personal computers.  

So - there is a lot of SATA out there and it makes sense to develop it as IP.  

Due to this demand, the SATA interface is increasingly becoming available as third party intellectual property (IP) in leading edge deep sub-micron CMOS technologies (65/55 nm and 40/45 nm) to help speed development time and lower costs. The quality, completeness and interoperability of this IP become the key considerations to the SoC integrator.   

Interoperability is a key part of the standardization of SATA interface and a program managed by the SATA-IO http://www.serialata.org/, ensures interoperability across SATA products. The interoperability task is becoming complex and is not only a consideration on the system side but also on the IP developer.   

During testing in our Hillsboro, Oregon labs., we discovered two electrical specifications related to wake-up from sleep mode and out of band signaling that did not reflect the current performance of today’s leading edge CMOS technologies. The SATA testing requirements and specifications for partial exit latency for host applications with spread spectrum-enabled only and the burst and gap width tolerances for out of band signals needed to be updated. The bottom-line was that  the speed and on-chip variations of the low power, low leakage deep sub-micron CMOS technologies posed certain challenges to SATA logo certification for these two specifications. The good news was that having completed silicon evaluation of over hundreds of devices, our SATA experts saw no impact on functionality or interoperability. Therefore our proposal, that was successfully received, to the SATA-IO Working Group was to update the the logo testing requirements.    

Together with the SATA IO Working Group, Synopsys helped to resolve these two issues. The specific details are available to SATA-IO members in the latest version of the Universal Test Document (UTD) 1.4.1. 

SATA Disk Drives That Passed Interoperability

The key highlight of the event was the rapid appearance of 3D equipment only months after the Consumer Electronics Show in Las Vegas (CES).  At CES, LG, Samsung, Toshiba and Panasonic all presented their 3D TV line-up, with Samsung and Toshiba also indicating that some select 3D TVs will also incorporate real-time 2D to 3D conversion processors. 

To ensure that our HDMI 1.4a IP core interoperated with the latest 3D equipment, our engineering team made the trek from Portugal to Milpitas and using the HAPS platform, we tested the 3D modes with key RX platforms from various vendors. Our TX solution was flexible enough to provide the experience of 3D movies with RX platforms in less than 30 minute de-bug sessions. This is pretty amazing! In fact we tested our TX core with 28 RX cores during the 5 days of plugfest.

Here’s some background. There are a total of 68 video modes which can be used in 2D or in 8 different 3D formats. However, most televisions today only support about 10 out of the 68 video modes and 3 out of 8 3D formats. Half side-by-side seems to be the most popular 3D format since it requires the same bandwidth as the 2D format (with 50% compression). The 720p and 1080i HD formats continue to be the most popular in North America.

If you’ve been following HDMI you may remember the Ethernet over HDMI hype. This feature did not even show up in any of the multimedia devices at this plugfest. It seems the market is still questioning the real world use cases and feasibility of Ethernet over HDMI.

3D HD broadcasting with Direct TV to your home