Harold Joseph (Cypress) showed that analog interfaces, “sensor” & general purpose data converters are finding their way into mainstream micro-controllers and other generic digital processing chips. From my perspective we will see more of this as applications ramp-up and mature, for example smart-grid metering and automotive requirements. As these data converters (ADC, DAC) move into the micro-controller, the process nodes required will get smaller. The key is robustness and flexibility in these applications.

Jeff Miller from Tanner EDA presented a good summary of the deep-submicron challenges the impact analog design causing a bottleneck, similar to the points on the first slide below. Solutions to some of these challenges are presented in my slide two.

Warren Savage contradicted the panel by highlighting the OMAP5: complex general purpose digital functions rely on raw performance to differentiate. They start in very advanced nodes to keep power dissipation down and increase functionality.

Although the initial iterations are really general purpose and do not integrate pure analog content, I would say that as the product life-cycle evolves, differentiation is achieved by adding more periphery analog functions. A good example is the application processor that is being merged with the baseband or with the digital TV reception to reduce costs. These ASSPs derivatives include analog in these additional functions.

My panel contribution is captured in the two slides below – there are new challenges in developing analog/mixed-signal in 28-nm and 20-nm but these can be solved with improvements in power, area and performace. The ADC on slide 2 highlights this point.

Next generation HDMI: Synopsys believes that for its continued success, HDMI should evolve to address the specific needs of each of the three broad segments discussed above.

1. Digital Home – HDMI dominates this market segment with close to 100% penetration in applications like DTVs, Blu Ray Players, AVRs, and Game Consoles. Hence HDMI should continue to future-proof itself, further enhance the user experience, and integrate some of the digital home connectivity standards. Some specific ideas include:
   1. Increasing bandwidth from 10.2Gbps à ~18Gbps to support deep-color 4K resolution mode
   2. Offer cinema video formats (21:9 aspect ratio as defined in CEA-861-F  specification)
   3. Offer a transparent remote control with the goal to control the source remotely
2. Mobile Multimedia (battery powered applications) – HDMI has experienced a rapid penetration in the mobile multimedia applications. The top 7 tablets in the world are now supporting HDMI connectivity (either directly or through a dongle). HDMI competes with MHL in mobile applications and should offer the following enhancements to succeed in this segment:
   1. Power consumption is a key factor in mobile applications. Hence HDMI should target to reduce the overall power consumption by Muxing some of the TMDS channels, offering reduced range differential amplitude and low resolution video modes. HDMI should also eliminate some of the legacy requirements such as 5V protection to save area, pin count and power.
   2. Battery charging capability is also extremely important to penetrate into mobile market. HDMI should offer battery charging functionality (just like USB) by using its HPD (hot plug detect) and NC (no connect) pins.
3. PC Applications – HDMI clearly competes with Displayport in this segment and should offer PC-specific features to penetrate into this eco-system. Some specific ideas to successfully compete with Displayport are:
   1. Increasing bandwidth from 10.2Gbps à ~18Gbps to support resolution up to WQXGA (2560×1600) at 120Hz frame rate. This would require using the TMDS clock lane as a 4th TMDS data channel + embedded clock.
   2. Transporting up to 4 video frames to support daisy chaining for multi-display mode.
   3. Transport USB2.0 traffic within the HDMI cable (similar to HEAC) by mapping D+ and D- from USB2.0 into HDMI NC and HPD pins. Extent CEC to declare USB traffic.

While we are recommending all these new features, Synopsys is mindful that one of the underlying requirements is backwards compatibility to previous generations of the specification. We will always take this into account as we work with other forum members to define the future of HDMI. 

Finally, Synopsys is glad to be a part of the HDMI forum and given our deep understanding of connectivity IPs, we will help enhance HDMI specification and enable it to successfully compete with other standards like DisplayPort, MHL and V-by-One.

From an analog/mixed-signal  design perspective the most interesting challenge was to support the scaling trends that the digital circuits benefit. The challenges can be summarised as: 

• Meeting 28 nm process design rules for manufacturability
• SoC integrators expect analog/mixed-signal IP to follow digital scaling trends – the IP cannot grow in size
• System specs have not changed to reflect lower  (1.8 V) I/O voltages

In order to meet these challenges, new analog/mixed-signal design techniques need to be developed  in order to benefit from technology scaling. Below is an example of an analog to digital converter where, through new design techniques the design has scaled ten times since the original architecture. Calibration techniques (“digitally enhanced analog”) were used to reduce demand on analog features: gain, offset, matching and increase robustness to PVT. And analog techniques such as clock boosting switches to circumvent low supply voltage, while internally processing signals with large voltage swings were used. All of these techniques are applicable to 28 nm.

ADC Scaling Using Design Techniques

 From a system specification perspective, if USB and HDMI are to be integrated on a 28 nm SoC, 5 V compliance requirements must be met – the challenge for the design engineer is to do this using 1.8 V transistors.

Scaling analog/mixed-signal circuits and meeting the “high voltage” system requirements are two of the challenges that must be met in order to support successful implementation of these new 28 nm technologies. That is, the IP needs to work not only on the prototype test-chip but also in production.

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

iSupply is forecasting ~55% CAGR in NFC for mobile phones between now and 2015.

NFC enabled handsets will create new opportunities for marketing, payment, and data interactions for consumers. At the most basic level, smart posters with embedded NFC tags will allow a passerby to download information on local restaurants, movie trailers, or upcoming events by simply tapping their phone on the poster. Maxim Integrated Circuits recently announced that they will be demonstrating smart poster technology at upcoming conferences and for a period of 4 hours recently, there was an NFC enabled sign demonstration in Times Square.

Moving beyond smart posters is full mobile payment. One of the keys to enabling mobile payment is the creation and implementation of a secure element to provide the necessary encryption technology to satisfy the requirements of the entire ecosystem, including consumers, network operators, and financial institutions. The need for secure elements is being served in two main ways. First, a number of companies, such as Verayo, have taken their proprietary technology and used it to create discrete ICs that can be incorporated into systems such as a SIM card to provide security function. Other companies, including IntrinsicID and Invia among others, are developing their technology to be delivered as IP for integration into larger SoCs.

One common requirement for both smart posters as well as mobile payments is the need for embedded nonvolatile memory. Synopsys DesignWare portfolio offers a range of nonvolatile memory options optimized for NFC requirements for both discrete tags and secure elements (normally developed in analog focused process nodes) and fully integrated secure elements that require implementation in an advanced process node.

To learn more http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_oct0511

You can also down load the preliminary DFI3.0 specification at http://www.ddr-phy.org/

Synopsys is a proponent and a driver of the DFI specification because it provides a level of certainty for our IP users when it comes to integration of the DDR subsystem, especially if the user is using the Synopsys DDR controller with another PHY or a Synopsys DDR PHY with a DDR controller IP from another source. 

Synopsys DesignWare DDR protocol controller showing DFI.

Well, actually the concept is not new. Different protocols, or standards pushed by many companies, have fought for predominance in the home networking arena. Each uses its own media. For example, the power grid for Power Line Communications, the telephone network for HPNA and the coaxial cable network for MoCA. The figure below shows the home network (G.hn) implementation.

In a typical home several of these networks co- exist, however they are not necessarily physically placed where they are more useful. Everybody has gone through the frustration of finding that the plug in the wall is not where it would be most convenient. This has, in fact, been a major limitation of the adoption of home networking, when compared to wireless.

G.hn, which is being standardized by the ITU, achieves this goal by defining a unified Physical Layer and Data Link Layer that can operate over multiple wire types. Furthermore, this PHY (and other critical blocks in the system) are defined for each wire type, resulting in the ability to outperform the specialized standards for each wire. In other words G.hn unites coax, phone lines and mains (electrical) cabling into a single network capable of hosting multiple HD streams over gigabit bandwidths around the home.

In parallel, the IEEE standardization body is already looking into ways of converging wireline home networking and wireless (WiFi, Power Line and Coax), from the network management perspective. It’s still an open question if this standard (IEEE P1905.1 working group) will also cover G.hn or not.

Apart from convergence, the other key “selling factor” for G.hn is the increased bit rate supported. These two factors place severe requirements in terms of the PHY performance and specifically the data converters. For example, the high data rate (high bandwidth) requires high sampling rates: 200 to 400 MSPS and the harsh, unfriendly, nature of the power grid. This imposes high resolution: 12 to 14-bit while processing these very large bandwidth signals.

I’m happy that Synopsys is participating in these emerging standards, by offering a family of  data converters that addresses exactly the requirements for such systems. This portfolio is made of compact and ultra low power 12-bit 250 MSPS ADCs and 14-bit 400 MSPS DAC which are  ideally suited for broadband communication applications helping to bring intelligence to your home wall plug.

Now with hindsight, having completed our new DDR product roadmap, the integration of the engineering team; the challenge turned out to be great opportunity to bring in the DNA of a company that was making traction in high speed memory interfaces and combining it with our own expertise as an IP provider.

A new DDR controller was released http://synopsys.mediaroom.com/index.php?s=43&item=897 with improvements in latency, performance and lower gate count. The DDR memory controller is user configurable, which allows users to generate a single port DDR controller with all the required features for their particular application.  In addition to basic features, such as bus width, number of ranks and DRAM protocol selection, this release enables users to optimize data throughout and area, with the configurable look-ahead, as well as reduce latency with the optional priority bypass. Several software programmable options to tune the DDR memory controller are offered to meet the needs of the users particular application and traffic.

With respect to the DDR PHY, we were investigating methods to make it easier for our customers to configure, estimate power based on DDR user defined traffic and the result was the DDR PHY Compiler http://synopsys.mediaroom.com/index.php?s=43&item=888.  This is truly a first for DDR PHYs.  The PHY compiler allows customers to use a GUI interface to configure and automatically generate all required files to enable integration of the DDR PHY.  The PHY compiler not only will enable users to configure their DDR PHY, but offer power estimates based on user defined DDR traffic for each supported DDR protocol, a diagram of the PHY even wrapping a corners.  There are over 60 parameters that can be modified to optimize the DDR PHY integration. 

DDR PHY Compiler

In the next few months I’ll be posting more DDR product updates.

Today, the final version of the PCI Express 3.0 (Generation 3) specification was released by the PCI Express Special Interest Group (PCI-SIG). With almost 1000 members and backed by companies such as Intel, HP, Oracle, AMD, Dell and Nvidia, this 8 Gb/s high speed serial interface will open new market opportunities in enterprise, data center and storage applications.

Three Generations Of PCI Express

Board member and chairman, Ramin Neshati, said that the new 8 Gb/s architecture will allow companies to build low-cost and power-efficient components and systems, could also be used for on-board components such as co-processors. The new specification could boost data transfers in high-performance systems, and data will get to storage devices and memory faster. He continued by saying that if a system builder is on a budget and has certain power consumption restrictions, they could build a server based on the second generation. For faster servers you could go with the third generation.  Products designed around the latest specification will be able to achieve bandwidth near 1 GBps one direction on a single-lane configuration and scale to 32 GBps on a 16-lane configuration, Neshati said. He brought up an interesting point: that the new generation does not automatically replace the existing install base – it just targets a different market.

This begs the question on whether the previous generations will slowly disappear. From our market understanding, new opportunities are being created – especially driven by consumer connectivity in printers and wireless hubs. These applications only require the first PCI Express generation in a single lane, enabling the designer to trade off area, power and bandwidth. So, all three generations will survive – targetting specific markets. The above table provides a summary of the speed improvements.

In the enterprise market, at these high gen. 3.0 speeds, equalizers need to be used to counteract the effects of interference, cross-talk and high frequency noise. The type of equalization was a topic that was discussed extensively inside and outside the PCI-SIG. Power and area drove some of the decisions to include only a linear equalizer (CTLE) in the receiver for the PCI Express 3.0 PHY specifications. In evaluating the channel, that decision was re-thought, considering that there is a 10 mV eye-opening after the reference CTLE. In reality this means that the eye is closed. Under these conditions, decision feedback equalization DFE (either direct or unrolled) was a considered option. This will improve the PHY’s peformance but potentially impact power and area. In summary the CTLE  boosts signal plus the noise, so SNR gets worse. DFE uses previous data bits to determine equalization and improves SNR. 

Synopsys PCI Express Gen. 3 PHY Test-Chip

Further details on the complete solutions for all three generations of PCI Express can be found on http://www.synopsys.com/IP/InterfaceIP/PCIExpress/Pages/default.aspx

This was the first ever HDMI installer workshop with the goal of providing better insight into HDMI protocol and equipment connection sequences. We gained familiarity was various test instruments. We also learnt that most common problems in HDMI installations happen when an HDMI device (HDMI AVRs, HDMI switches, HDMI splitters, HDMI Cat6 Extenders etc) is inserted between 2 existing HDMI devices (set top box and digital TV). The device in the middle manipulates DTV’s EDID in various ways to reflect its limitations or improvements over DTV’s capabilities. Such daisy chaining does not work very well and troubleshooting the faulty component can be a night mare. We also saw some failures related to HDCP over poor quality cables. The bit errors during HDCP authentication corrupt the DDC channel and cause the authentication to fail.

Lessons learnt in such events are invaluable and our customers (and end consumers) reap the benefits of a robust interface that is a true “plug and play”.