The process engineers in the foundry need to figure out an extraction technique for obtaining a set of optimal model parameters for BSIM. This is usually achieved through a semi-manual fitting process using many current-voltage measurements. One of the critical models is the output conduction of the MOSFET. The output conduction has become worse with each process generation, a good analog CMOS circuit designer can cope with this as long as there is an accurate model. However, this parameter is very hard to model accurately – many measurements of different transistor aspect ratios need to be taken. It’s a double whammy.  With the number of different types of 28 nm, this is becoming a challenging and an expensive bottle-neck for the foundries. 

Ford’s genius was that he addressed the problem of the Model T assembly line bottle-neck by offering only the fastest drying paint. Black. Ultimately, what the analog CMOS analog circuit designer cares most about, regardless of the actual performance of the  technology, is the accuracy of the model.

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If you talk to analysts they will say that 3D TV is the next big wave in consumer electronic market. CES 2010 was dominated by 3D TVs. Sony, Toshiba and Hitachi will be releasing their 1^st models of 3D TVs later this year. Likewise content providers have begun talking about 3D content for kids. Next generation game consoles will definitely incorporate 3D capabilities. Synopsys’ announcement of HDMI 1.4 cores will help expedite the adoption of the 3D into the digital home theatre appliances.

HDMI will enjoy a 33% CAGR in the portable multimedia (camcorders, still cameras, PMPs) devices. Low power is the key to succeed in this market. Our HDMI 1.4 TX PHY core features sub 50mW power for such applications. Furthermore our HDMI IP comes with ATC reports, test results from plug fest events and with complete system validation on a HAPS-51 based platform.

There are conflicting opinions in the market about how far can HDMI evolve. Has it reached its saturation in terms of bandwidth, color formats & other features? Is law of diminishing returns kicking in? Most customers are still trying to get a good handle on the HEAC feature. Regardless, 3 out 4 customers in the digital home arena are seriously looking into incorporating 1.4 features into their next generation SOCs/systems.

Synopsys’ HDMI 1.4 cores will incorporate HEAC block to support bi-direction transfer of IP packets and audio packets, hence simplifying the home theatre system by eliminating additional connectors, wires and dongle cards on each appliance to connect to Ethernet/802.11. The SoC designer will be responsible for providing their own 100BASE-TX and S/PDIF blocks that will seamlessly connect with the Synopsys’ HDMI HEAC block. The SoC designer will need to incorporate higher layers of 100BASE-TX only if IP packets need to be processed in the end application. Likewise 100BASE-TX IOs are optional depending on whether the end application needs to connect to external router to obtain IP packets. A simplified block diagram of sink and source SoCs with HDMI HEAC block is shown below.

As an IP provider, Synopsys will play an important role in the commercialization of HDMI. The consumer electronic giants we have been working with have appreciated the reduction in their development costs and shortened time-to-market. Also we have applied all the valuable lessons learnt from the plugfest events and HDMI ATCs to reduce the interoperability problems recently seen in the HDMI appliances. For this reason, we believe that a growing number of SoC and system designers will choose to keep their development schedules and budgets on track and lower integration risk by buying their HDMI IP from us.

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Virtual resources act as proxies for physical resources (memories, disk drives and servers) that have the same external interfaces and functions composed from physical resources. A “virtualization intermediary” creates virtual resources and “maps” them to physical resources and provides isolation between virtual resources and this is accomplished through a combination of software, firmware, and hardware mechanisms.

So, imagine applying virtualized devices using PCI Express for a 10 Gb Ethernet backbone.

To keep things simple suppose that we tried to share this connection using physical deployment giving each physical machine access to 5Gb, or half of the available bandwidth, which we will implement with five 1Gig Ethernet adaptors in each machine feeding into a switch that has the actual 10Gig connection to the network.

Obviously this has introduced a considerable amount of additional HW, meaning added cost and, probably more importantly, space and power. But we have also statically partitioned the bandwidth.

Contrast that with an approach that uses virtual deployment of the bandwidth, as in the picture, and you can see that the management of that device can be very fluid and based on the dynamic requirements of each of the consumers of the bandwidth.

More about virtulization can be found on http://synopsysoc.org/theeyeshaveit/?p=33 and

http://www.pcisig.com/specifications/iov/single_root/

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At the this year’s CES, one of Synopsys’ USB 3.0 and HDMI customers, Displaylink demonstrated how the speed of USB 3.0 enables flawless transmission of uncompressed 1080P high definition video and 3D gaming over USB. 

Above is the tabletop demo showing a USB 3.0 Host PC connected to a Buffalo brand USB 3.0 external hard drive and FPGA board containing Displaylink’s proprietary display technology and USB 3.0 and HDMI connections.  Residing next to the blue USB 3.0 cable is a black HDMI cable connected to a 42 inch 1080P Samsung LED LCD.  A variety of high definition movies and display examples were displayed on the LCD TV.

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Wire bond packages are often preferred for their lower cost yet flip chip packaging offers higher performance from a signal integrity perspective due to the lower inductance in the chip connectivity. One of the greatest challenges in any SoC that utilizes one or more high speed DDR3 channels (e.g., above 1066Mbps data rate) is the connection that the high-speed, parallel data channel DDR brings to the packaging technology and printed circuit board (PCB) design. Cost and power being the critical factors in consumer devices means that the IP vendor:

• Must not limit the IP in terms of using low cost packages and regular printed circuit boards
• Figure out the best power delivery characteristics

DDR3 is an example where speeds in the 1 Gb/s region will start to become common place in low cost consumer devices. So the design optimization challenge is to meet the speed using the most inexpensive package and the lowest number of PCB layers. In the following example this translates to using wirebond packaging and four layer PCB using through hole vias http://techon.nikkeibp.co.jp/article/HONSHI/20091126/178048/ where Synopsys’ DDR IP is implemented and validated at 1 Gb/s speeds.

With respect to power, poor power delivery characteristics can lead to effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion. This is described in more detail in http://synopsysoc.org/theeyeshaveit/?p=66

So the low cost consumer requirements in terms of the package type, PCB material and number of layers will dictate the future designs of  DDR3 IP.

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