Output signal isolation method is usually a preferred choice than the input isolation method as former leads to fewer isolation cells and gives better control over how the enable signal can be  propagated to the isolation logic. 

Input isolation will be a better choice if there are very few independent domains. In such situation isolation enable signal management is very straight-forward.  Here number of power domain is not the main component, its the sequence in which they are powered down and up. In this case isolation cell is only required when the power island is active. During the power down period, the power island is no longer functional and no power is supplied to the island. Therefore, neither the floating inputs nor the input transient state matters to the power island, which is overall good from total power perspective.

For this method, probably regular standard cells (NAND and NOR) can be used as isolation cells rather than requiring a custom cell.

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I know we spend so much time in writing power intent of a design and validating whether its correct or not. In that process on a recent project, I did some analysis on how some of the intent generation can be pseudo automated.

Used the MV static checker, MVRC to auto generate some policies based on the xover analysis and it helped quite a bit and was amazed at how fast I was able to generate these constraints from MVRC.

For example, on one of the design, finding out what need to be isolated and excluded from isolation was not a trivial task due to multi-fanout nature of the ports/pins. Looked at the xover analysis within MVRC and used this feature to auto-generate some of the isolation policies. It was less than 30 lines of TCL code within MVRC, which made my life easier in generating some part of power intent.

just an example on what I did within MVRC

set f1 [open ${source_island}_${dest_island}.xover w]
set xs [get_crossovers -source $source_island -dest $dest_island]
foreach x $xs {
    set src_port  [get_crossover_info -object $x -boundary_source]
    set src_port [regsub -all {\{} $src_port {}]
    set src_port [regsub -all {\}} $src_port {}]
    lappend src_ports_list $src_port }}
}

if {$src_ports_list!=""} {puts $f1 "set_isolation ${source_island}_${dest_island}_ISO -domain ${source_island} -isolation_power_net $domain_vdd_net -isolation_ground_net VSS -clamp_value 0 -elements \"$src_ports_list\""}

This may not be complete, but idea is very similar to one given above.

We can debate on whether should a sign-off MV tool be used for this or not?

Happy Holidays.

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 (1) Output signal isolation is usually a better choice than the input isolation .

(2) Input isolation is reasonable on designs that have controllable independent power domains

(3) If custom isolation cells are not available, regular cells such as (AND/NOR) can be used, but we need to make sure that these cells are kept alive all the time.

(4) Isolation cells impacts timing and area and hence should be used and analyzed properly. It should be inserted as early as possible in the design cycle to account for area/timing penalty.

(5) If feed through paths exist in the power down domain, its not necessary to isolate these nets , but need to be kept alive

(6) Isolation cells should be placed close to boundary and interface nets should be protected all the time and should not be buffered if its residing in a domain, whose power characteristics is different from source/sink domain

(7) Some logic cells such as XOR gates, should be avoided at the interface logic so as to prevent any accidental sneak paths

(8) Check the isolation states to make sure, parking at one value “1” or “0” does not lead to any sneaky paths

(9) Its preferable to use enable level shifter instead of LS+ISO cells .

(10) Last but not the least, make sure to write the isolation policy in UPF at the right interface. Its not practical and reasonable to write isolation policy both at the sink/source simultaneously.

Lets discuss about the placement of these cells and AON’ness of these cells in the next post.

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My apologies for changing the title of my previous post. I realized that most of the optimization challenges are primarily due to the design requirements not UPF requirements. UPF is just a medium to define power intent, similar to verilog defining the logic intent of the design.

continuing on the same topic, few more reasons, which makes optimization challenging are

1. Isolation cells, isolating off/on blocks need to be placed closer to source if the isolation cell used is a single rail cell and its residing domain is different than the source/sink domain. This ensures that the signal is isolated properly to reach the sink. Scenario changes if the isolation cells used are dual rail isolation cell. 
2. During scan mode, all the special cells should be directly controllable and observable . This puts restriction on how tools can handle scan chain. This can also lead to scan chain re-ordering locally.
3. Global signal distribution need to be power aware.. This leads to proper usage of AON buffers and regular buffers depending on how the global signal traverses.
4. Physically each power domain/island/voltage area can restrict the routing of the signals, which might lead to taking  longer route to reach destination. Due to these longer routes, more buffers/inverters/logic may be required to fix transition/timing/si requirements.

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I quite often get this question, my design used to work fine , P&R tools did not have any issues and was routed clean and so was LVS . But the same design, targeted towards reducing power leads to undesirable results and not at all clean?

Now lets look at some of the challenges faced by the optimization tools, when power domains are introduced through UPF? Other thing to keep in mind is power is no longer an after thought process anymore, designs need to be well architected up-front to avoid certain issues stated above!

(1) Physical optimization during placement is constrained to ensure that cells in a power domain are placed inside the island(voltage area). This requires hard exclusive region constraints applied to the cells in the power domain during the placement and physical aware optimization process. It also requires tools to keep track of logical hierarchies as netlist is being modified, all the physical optimization need to align itself with the logical hierarchies and insert the new cells in the respective hierarchies, else we end up having AON cells in dead region and vice-versa

(2) New cells created during re-structuring logic or local buffering in a power domain must be assigned to the power island and constrained to ensure that they are placed inside the respective island.

(3) Short feed-through paths in a power island should be protected from buffer insertion during design optimization and design-rule fixing to maintain wire connection(inserting buffers and the entry point of the island and exit point of the island). Long feed-through paths that need repeaters must be buffered by always-on buffers so that the feed-through paths are functional while the island is powered down.

(4) Special cells such as Level Shifter/Isolation Cells….etc, have their respective places physically(pre-defined) to avoid electrical issues and should be honored through out the optimization process.

…more in my next post.

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