We’ll post a question – two each month – and the first person to post the correct answer will win a $40 Amazon gift card.

You can play two ways, on our Facebook page and through Twitter.

On our Facebook page:

• If you’re not already, become a fan (click “Like” on www.facebook.com/synopsys)
• Watch your Facebook feed for our trivia questions to be posted
• Post your answer in the comment area under the trivia question

Through Twitter:

• If you’re not already, follow us on Twitter (click “Follow” on www.twitter.com/synopsys)
• Watch your Twitter timeline for trivia questions posted by @synopsys
• Tweet your answer to @synopsys

The winner of each question will be announced right away via Facebook and Twitter.

Read the full contest rules here.

The contest is underway. The first question was, “What was Synopsys’ original name when the company was founded?” The answer is, “Optimal Solutions”. (Did you know that?)

For more trivia about Synopsys and our history, visit our timeline.

Play and enjoy the game! (Almost forgot, no Synopsys employees, please.)

A decade ago, I was part of the core team that brought VHDL International (VI) and Open Verilog International (OVI) to form Accellera. VI and OVI were successful in their own right in the promotion and adoption of their respective HDLs (VHDL and Verilog). One could say that the formation of Accellera was due to the industry’s desire that HDLs had to grow further to help address verification, test, and power issues. Part of the truth, though, is that we were duplicating efforts and paying too much for two organizations. I’ll never forget going to a VI board meeting one day and an OVI board meeting the day after. Many of the same people were in both meetings, but some of them switched their viewpoints. I called them out for arguing with themselves.

Accellera’s desire to provide much-needed standards was realized with SystemVerilog, Open Verification Library (OVL), Open Compression Interface (OCI), Unified Power Format (UPF) and Universal Verification Methodology (UVM). Accellera then merged with The SPIRIT Consortium to expand the scope of language-based standards activity to include IP standards. Today, IP-XACT efforts under Accellera are helping integrate use of IP and its meta-data into various standards such as UVM. This is a classic example of collaboration among adjacent standards that benefits the user community with improved productivity and provides business opportunities for tool and IP vendors.

Here is some trivia about the merger that you won’t find in the announcement:

- Most of the Board makeup is the same as before (7 of 9 OSCI board members were also Accellera board members). That should bring continuity and easier integration of things like Policies and Procedures.

- There is an increase in the number of associate members. This brings the opportunity for broader collaboration and participation in future standards work.

- Logistics and infrastructure will continue to be provided by the highly capable and experienced people who’ve worked for both organizations for decades.

- Kavi continues to provide the online platform.

- Members will save money on dues and get more benefits. There, I said it.

- There is a good balance between users and vendors. Accellera Systems Initiative is not dominated by EDA companies.

- Accellera Systems Initiative will not be called ASI. That would be confusing.

- The idea of merging the two organizations came up four years ago.

As the Accellera and OSCI communities come together under a single umbrella, I believe the new organization will remain focused on the fundamental premise of EDA standards – interoperability between tools to help build robust design and verification flows. Portability of a design across multiple tools may be desirable (e.g., switching from one functional simulator to another), but it’s often not practical. It’s the ability to take the design through successive stages of refinement and validation that makes the standards most valuable.

I would like to see Accellera Systems Initiative bring the industry even more collaboration and the platform for improved interoperability across system and chip design tools in coming years. And I’d like to invite you to participate.

Electronic design standards such as Hardware Description Languages (HDLs) have fueled innovation for decades in the semiconductor industry. These language standards raised the level of design abstraction to help enhance productivity – that was the benefit in the early days when the industry was migrating away from schematic-based design. Further, the HDLs – initially Verilog and VHDL – allowed designers to think in terms of functions rather than structures, thereby enabling design sizes to move from thousands of gates to millions of gates. The innovations that followed came in many forms – from design and analysis tools to new methodologies and global teams working around the clock on large projects. None of this would have been possible without a common, precise language to describe electronic circuits.

More recently, the SystemVerilog HDL has allowed us to think in terms of object-oriented verification environments for the ever-increasingly complex system-on-chip (SoC) designs. The success of a “reuse paradigm”, both for design and verification building blocks and the SoCs that are designed with them, is due in large part to the standardization of HDLs, HDL-based methodologies, and other technical standards.

From a different perspective, standards enable innovations to be developed on top of maturing technologies rather than reinventing the wheel. This increases the rate of innovation – a far cry from stagnation.

In addition to HDLs, Synopsys and our customers are also beneficiaries of technical standards such as the well-known USB, Wi-Fi, and PCI. and other communication protocols/interfaces. As a leader in the IP building block business, we are able to provide standards-based design and verification IP to help our customers accelerate their product schedules. Availability of standards-based, verified components allows the precious skilled engineering resources to be focused on building innovative and differentiated products instead of reinventing the wheel of implementing standard interfaces. Our participation in the groups that create and maintain these standards means we supply IPs that are compliant with the approved specifications, and we help enable interoperability between devices adhering to the corresponding standard.

From our very beginning, Synopsys’ business has benefited from using HDL standards as input to our tools, be it synthesis or simulation. Working with our customers and the entire semiconductor ecosystem, we have developed standards-based tools and methodologies to help ensure that each design moves from concept to silicon and then into a system (an end product) in the most efficient manner. We continue to invest in standardization efforts, lead with new and innovative technologies, and collaborate with customers, partners, and competitors alike to build strong platforms that enable the advancement of innovation.

Active participation in industry standardization activities requires a long-term vision and commitment, and the benefits are tangible. We have this, and that’s why we do it.

Whether our technology alone is being donated to be considered as part of a standard or it is one of several contributions, the goal is always to look for ways a new standard will help solve a wide range of problems. As a solutions provider, we certainly have insight into some of the use models that will benefit from the new standard. Often times, however, other participants in the standards development process bring additional requirements for the new standard to support use models that were previously not considered.

For example, Synopsys made the Liberty format for technology library modeling – originally known as .lib – an open standard more than a decade ago. Following that, some of the very first updates to Liberty came from recommendations by Cadence Design Systems. As process technology continued to move ahead from 180 nanometer to 90 nanometer towards 14 nanometer, many new features were added to the Liberty format to represent corresponding abstractions for design and analysis tools. Contributors to its upgrades included IC designers, EDA tool suppliers, and library developers.

Currently evolving under the IEEE’s Industry Standards & Technology Organization (IEEE-ISTO), the format continues to progress along with the technology it supports. Overseeing its evolution is the Liberty Technical Advisory Board (LTAB), a group of experts with a vested interest in maintaining the usefulness and robustness of the Liberty format.The group continues to tap into Synopsys’ – and others’ – expertise which is made readily available. Most recently, the group discussed and approved several new features to help model low-power cells, which are critical to the advancement and sales of mobile devices.

The collaborative effort among semiconductor foundries, fabless design houses, semiconductor IP providers, and EDA tool vendors (several in addition to Synopsys) is continuing to benefit the entire industry. It is also helping Synopsys maintain close ties with the entire semiconductor ecosystem to better understand upcoming requirements and challenges – giving us an opportunity to be the first to provide innovative solutions.

At my company, we collaborate with a wide range of players in the industry on standards issues. This includes competitors, partners, and customers – typically in a Standards Development Organization (SDO) such as the IEEE Standards Association or Standards-Setting Organization (SSO) like Accellera.

Through such participation, we often find that our endeavors to solve our customers’ problems are exactly the same as our competitors’. In fact, at times, the customers who are participating in standards activities are asking us to solve the same problem as they ask the other EDA tool suppliers. In many cases, standards-based collaborative efforts are far more efficient overall than having one vendor working directly with each customer.

The Universal Verification Methodology (UVM) and Unified Power Format (UPF) under Accellera (which is now IEEE Std. 1801) are great examples of standards helping solve much larger problems across the broad industry than what individual companies could do on their own.

These standards successes (and many others) led with technology donations from Synopsys, such as the core of SystemVerilog, the register package in UVM, and several low-power technologies for UPF. Donation (in standards parlance, “contribution”, to differentiate it from money) of production-proven technologies helps align the EDA  tool developers and IP providers with the customers in the most effective and expedient manner. As customers and non-customers become aware of the public standards based on our technology, not only does it continue to build Synopsys’ technical leadership and respect for our technologists, but it also provides the opportunity for adoption of our tools and methodologies because they are standards-compliant. This is yet another good reason why we at Synopsys continue to be actively involved in standards activities.