computer tutorial

Cloned Motherboards

noreply@blogger.com (jazz filling) — Fri, 15 Aug 2008 13:42:00 +0000

by : http://www.hardwaresecrets.com/article/65/1

Cloned Motherboards

There are several motherboards that are not manufactured, rather they are bought from another manufacturer and have their tag sticked to them, as it happens to those from Amptron, Alton, Aristo and Matsonic. Matsonic used to sell their board under the brand "Eurone. All those "manufacturers" buy boards from ECS (EliteGroup Systems), which is one of the largest motherboard manufacturers in the world and is also the owner of the brand PCChips, one of the most popular motherboard manufacturer in developing countries because of their low prices.

ECS says they use the brand PCChips for their boards for the low-end PC market, while the boards sold under the brand ECS have better quality control. However, several ECS and PCChips motherboards are simply identical.

For example, if you buy an ECS K7SOM+ motherboard in the belief you are making a better deal than buying one from PCChips you are mistaken, for that motherboard is actually the M810DLU from PCChips. Similarly, if you an MS9138E from Matsonic you will be really taking home an M925 from PCChips.

We compiled two tables showing the correspondence of the most popular cloned motherboards on the market today. Notice that that table is far from being thorough, being just a fast guide to be used when buying a low cost motherboard.

Socket 478 (Intel Processors)

ECS	PCChips	Matsonic	Amptron	Chipset
P4IBASD V3.X	M902LU v3.0	MS9047C		Intel 845D
P4S5A	M930LMR			SiS 645
P4S5A/DX	M930ALU v5.x			SiS 645DX
P4S5MG/651+	M935ALU v5.1B			SiS 651
P4S5MG/GL	M935LU v5.1B (M935DELR)			SiS 650GL
P4S5MG/GL+	M935MLU5			SiS 650GL
P4S8AG	M947			SiS 648
P4VMM2		MS9138D		VIA P4M266
P4VMM2 v3.1	M925 ALMU (M925LU v3.x)	MS9138E	XP4-925ALU	VIA P4M266
P4VXAS2 v2.X		MS9107C		VIA P4X266A
P4VXASD2 v5.X	M922 v5.0			VIA P4X333
P4VXASD2+	M922LU v5.0	MS9147C	XP4-922LU	VIA P4X333

Socket A (AMD Processors)

ECS	PCChips	Matsonic	Amptron	Chipset
	M825LU v3.x		K7-825LU v.3.1	VIA KM266
K7S7AG	M847			SiS 746
K7SEM v3.0	M810L v7.1C		K7-810CLM4	SiS 730S
K7SOM+	M810DLU		K7-810DLM4	SiS 730D
K7VMM	M825LMU			VIA KM266
K7VTA3 V2.X		MS8137C+		KT266A
K7VTA3 V7.0		MS8167C		KT333CF

Athlon 64

noreply@blogger.com (jazz filling) — Tue, 12 Aug 2008 05:51:00 +0000

by :www.hardwaresecrets.com/article/272

Athlon 64

In this tutorial we will list all Athlon 64, Athlon 64 FX and Athlon 64 X2 CPU models from AMD released to date and the main differences between them.
By the way, AMD has recently changed the name of those CPUs, dropping the number "64" from their name. So Athlon X2 and Athlon 64 X2 are the same CPU, and so on.
Those three CPUs are based on AMD64 architecture, where the main feature is the memory controller embedded in the processor itself and not located on the chipset like all other CPUs. Besides Athlon 64, Athlon 64 FX and Athlon 64 X2 we also have Sempron (models based on sockets 754 and AM2), Opteron and Turion 64 CPUs based on this architecture. Read our Inside AMD64 Architecture for an in-depth explanation on how these CPUs work.
Because of this architecture the communication between the CPU and the memory modules is done thru a dedicated memory bus, while the communication between the CPU and the chipset uses a separated bus, HyperTransport (click here to read our tutorial on HyperTransport).
AMD CPUs based on Athlon 64 architecture can be found with the following socket types:
Socket 754: Used by early Athlon 64, some Sempron models and Turion 64. Their memory controller is single channel, meaning that the CPU accesses memory at 64-bit rate.
Socket 939: Used by Athlon 64, Athlon 64 FX , Athlon 64 X2 and Opteron processors. Their memory controller is dual channel, meaning that the CPU accesses memory at 128-bit rate, if two memory modules are used.
Socket 940: Used by early Athlon 64 FX and Opteron processors. Their memory controller is dual channel, meaning that the CPU accesses memory at 128-bit rate, if two memory modules (or an even number of memory modules) are used. They require ECC memory type.
Socket AM2: Used by Athlon 64, Athlon 64 FX, Athlon 64 X2 and Sempron (some models) processors. On these models the embedded memory controller supports DDR2-533, DDR2-667 and DDR2-800 memories at dual channel configuration, meaning that the CPU accesses the memory at 128-bit rate if two modules (or an even number of memory modules) are used. Keep in mind that the memory controller of socket 754, 939 and 940 CPUs support only DDR memories.
Socket F: This 1,207-pin socket created for the latest Opteron models is also used by the Athlon 64 FX processors used on AMD’s Quad FX platform (Athlon 64 FX models 7x). CPUs based on this socket can operate under SMP (Symmetric Multiprocessing) mode, i.e. you can have more than one CPU working in parallel. Like socket AM2 processors, the memory controller found on socket F processors supports DDR2-533, DDR2-667 and DDR2-800 memories under dual channel configuration, meaning that the CPU can access the memory at a 128-bit rate if an even number of memory modules is used.
The memory controller integrated on socket AM2 and socket F CPUs can support DDR2-533, DDR2-667 and DDR2-800 memories. The problem, however, is how the memory bus clock is achieved. Instead of being generated thru the CPU base clock (HTT clock, which is of 200 MHz), it divides the CPU internal clock. The value of this divider is half the value of the CPU multiplier.
For example, an AMD64 CPU with a clock multiplier of 12x will have a memory bus divider of 6. So this CPU will work at 2.4 GHz (200 MHz x 12) and its memories will work at 400 MHz (DDR2-800, 2,400 MHz / 6). Keep in mind that DDR and DDR2 memories are rated with double their real clock rate.
The problem is when the CPU clock multiplier is an odd number. For an AM2 CPU with a clock multiplier of 13x, theoretically its memory bus divider would be of 6.5. Since the AMD64 memory bus doesn’t work with “broken” dividers, it is rounded up to the next higher number, seven in this case. So while this CPU will work at 2.6 GHz (200 MHz x 13), its memory bus will work at 371 MHz (742 MHz DDR) and not at 400 MHz (800 MHz DDR), making the CPU to not achieve the maximum bandwidth the DDR2 memory can provide.

Installing Frontal USB Ports

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 13:11:00 +0000

By : www.hardwaresecrets.com/article/90

Installing Frontal USB Ports

The most sophisticated cases have frontal USB ports. To use them, you need to connect them to the motherboard of your computer. In this tutorial we will show how this connection must be done.

Figure 1: Detail of a case with two USB ports on its front (this case has also two jacks from on-board audio).
Nowadays motherboards have four, six or eight USB ports, but normally only two or four of them are directly soldered to the motherboard, at its back. Due to that, we generally two USB ports left in the motherboard. These left ports are usually available in 9- or 10-pin connector, as you can see on Figures 2 and 3. It is in that connector that the USB ports of the front panel of the case should be installed.

Figure 2: 9-pin USB header on the motherboard where the frontal USB ports should be installed.

Figure 3: Another example of the 9-pin USB header where the frontal USB ports should be installed. In this case, where we have two connectors available, just one will be used.

The biggest problem is that there is no standardization among the several motherboards manufacturers for the functions of each pin, that is, pin 1 of a motherboard connector may have a different meaning from pin 1 of a motherboard connector from another manufacturer. Because of that, each wire of the USB ports of the front panel of the case use individual connectors. As each USB port uses four wires, your case will have eight wires coming from the front panel, in case your case has two USB ports, which is the most common number.

Figure 4: Wires from the frontal USB ports of the case.
On each wire connector you can read its meaning, which may be +5V (or VCC or Power), D+, D - and GND. Besides the meaning, in each connector you can read whether the wire belongs to port 1 (or A or X) or to port 2 (or B or Y) of the case. The first step for the installation is to separate the wires according to the port, that is, to separate the wires in two groups: port 1 and port 2.

Next you must install the wires in the motherboard connector. The biggest problem is to know the meaning of each motherboard pin, since this is usually not written on the motherboard. For this task, you will need to check the board manual. There you will find the meaning of each connector pin, as we show on Figure 6. All you have to do is to install each of the wires (+5V, D+, D - and GND) in the correct places as shown in the manual. In the motherboard of our example, the port 1 wires must be connected the following way: +5V to pin 1, D- to pin 3, D+ to pin 5, and GND to pin 7. The port 2 wires must be connected the following way: +5V to pin 2, D- to pin 4, D+ to pin 6, and GND to pin 8. Notice that the meaning of each pin of your motherboard may be different from this example, therefore you will need to check your board manual. Usually the wires of a door will be one side of the connector (odd pins) and the wires of the other port will be on the other side (even pins).

Figure 6: USB header pin-out, from the motherboard manual.

PC Assembling Problems

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:58:00 +0000

By :www.hardwaresecrets.com/article/42

Preventing Overheating

If you want to ensure that you won’t face overheating, random crashes (resets and the infamous “Blue Screen of Death”) and performance issues with your PC you should check whether it is assembled 100% correctly or not. In this tutorial we will show you where to look for assembling errors on your PC.
First, let’s start with the PC assembly itself. The errors describe on this page can overheat your PC thus causing random problems like random resets and crashes (PC “freezing”, “Blue Screen of Death”, etc).
Antistatic foam: Most motherboards come from factory with an antistatic foam (usually pink, white or black) in their packing. Many technicians, when installing the motherboard to the case, pinch this foam between motherboard and metallic chassis, thinking that this procedure will avoid that motherboard from touching the case metallic frame. It happens that this foam holds motherboard-generated heat, hindering the normal airflow that exists between motherboard and the case chassis. Therefore, it is quite common that a computer assembled using this foam crashes or issues random errors, due to the overheating.
Internal main power cord: In AT cases it is quite common to have the main power cord that connects the power supply to the power-on switch in front panel hanging loose over motherboard, often hindering the heat dissipation and even contacting the processor fan, causing it to stop running and PC to crash due to overheating. The ideal would be to lay this cable to the power supply switch by the right side of the case (facing front of case in upright position), in the upper part of the frame, and not hanging loose by left side, as it is common to find. Since AT cases are used only on very old PCs, you probably won’t face this issue, however we kept it listed here for historic purposes.

Other loose cables: The same idea applies to all other cables inside the PC, like the power supply cables and the flat cables used to connect the hard disk drives, optical drives and floppy disk drives. You should fasten these cables with a cable holder and put them inside an empty 5 ¼” bay in order to prevent these cables from blocking the airflow inside the PC and also preventing them to stuck the CPU fan.

Thermal grease: If you are facing overheating problems with your CPU, you should check whether thermal grease was correctly applied on the CPU or not.

Under dimensioned case: Cases look all the same, but they aren’t. Current Intel CPUs (Pentium 4 “Prescott” and beyond) require cases with a side duct in order to improve the airflow inside the case. If you don’t use a case with this side duct you may face overheating problems.

Extra fans wrongly installed: If your case has extra fans, you should check if they are installed on the right position, i.e. blowing the air in the right direction. Fans installed on the rear part of the case must be installed pulling the hot air from inside the PC case to the outside. Fans installed on the front part of the case must be installed pushing cold air from outside the case to the inside. Putting your hand near the fan should be enough for you to feel which way it is blowing air. If any extra fan is reversed, just remove it from your case and install it again, flipping it over.
The problems listed below are not directly related to overheating, but you should check them as well.
Loose motherboard: Your motherboard must be very well fastened to case's metallic frame. We've seen many cases where the computer gives random resets or crashes when the desk was rocked, just because the motherboard was practically loose inside the case. In other cases, it is very common for the PC to lose its machine setup when a new daughter board is installed, as motherboard bends (due to lack of padding points) and some of the motherboard soldering points contact the metallic frame. Therefore your motherboard must be very well fastened to case's frame, using the largest quantity of fastening points as possible.
Hard disk flat cable: If you still use a parallel IDE hard disk drive (e.g. ATA-100, ATA-133) instead of Serial ATA (SATA), you should check carefully how it is installed. Parallel IDE hard disk drives use a 40- or 80-wire flat cable that normally has three connectors, one in each cable end and one midway. The hard disk must be connected to one end of the cable and motherboard to the other end. The midway connector stays normally loose. It happens that some technicians connect the hard disk to the midway connector, is such a way that a cable end connector hangs loose. This is not good, as this stretch of the cable will actuate as an antenna, receiving and injecting noise in the data transmission, and as such hard disk transfer rate will be reduced. Also, if your hard disk cable is using a 40-wire flat cable, we recommend you to replace it with an 80-wire cable
Optical drive as hard disk slave: Also if you still use a parallel IDE hard disk drive, the optical drive (CD, DVD, etc) must be installed in the secondary IDE port of motherboard, configured as "master". Many people install the optical drive on the same cable as hard disk (using that midway connector that stays usually empty), as "slave". In that way the hard disk drive and the optical drive will have to strive for cable utilization, as they use same cable, and both devices can't change information with the system processor simultaneously, reducing computer performance. If your computer optical drive is sharing the same cable as the hard disk drive, undo this installation: install it on the motherboard secondary IDE port as “master” (you will need a 40- or 80-wire flat cable). Newer motherboards, however, are coming with just one parallel IDE port (see Figure 11), giving us no other option than installing the optical drive and the hard disk drive on the same cable. If this is your case, we highly recommend you to replace your hard disk drive with a Serial ATA one in order to leave the optical unit alone on the parallel IDE port, thus increasing system disk performance.

Next Pentium 4

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:51:00 +0000

http://www.hardwareanalysis.com/content/article/1686/

By: Dan Mepham

The next Pentium 4 processor, Prescott arrives

In 1965, just a few years after the first integrated circuits saw the light of day, a chemist by the name of Dr. Gordon Moore made an observation that would become a guiding rule for the next forty years. His prediction, affectionately dubbed 'Moore's Law' by the press, stated that the speed and number of transistors built into the latest integrated circuits would double every eighteen months. Three years later, in 1968, Moore would go on to co-found what is now the world’s largest semiconductor manufacturer, and would have a first-hand role in ensuring that his prediction would hold. And hold it has. Intel’s first processors in the early 1970’s consisted of just one or two thousand transistors. That increased to tens of thousands in the late seventies as Intel pushed its 8086 processor. Progress continued through the hundreds of thousands of transistors with the 80286 and 80386 families, and finally reached the million transistor mark with the 486DX and its integrated FPU. The nineties was the decade of the Pentium processor, from its 3-million transistor introduction in 1993 to the 25-million transistor Pentium III in the late nineties. Finally, the current Pentium 4 processors boast a modest 55-million transistor count. Key to increasing transistor count, and therefore performance, is the reduction of the size of those transistors. 55 million transistors as they were in 1970 would never have worked; the circuit would have been too huge and too hot to be practical. Decreasing the size of the transistors allows them to be made cheaper, switched faster, and run cooler. Over the decades we’ve seen transistors drop from several microns down to the current 0.13 micron technology.Today we see the introduction of Intel’s smallest mass-produced transistor at just 0.09 microns (90 nanometers). Welcome, ladies and gentlemen, to Prescott Country.
Caching In
The use of the 90nm transistor allows Intel to construct much larger (in terms of the number of transistors) processors, while keeping the physical size small. When processors are manufactured, the yield rates on those processors are directly related to how large, physically, the processors are. A processor that is twice the size of another is essentially twice as likely to contain manufacturing impurities, and therefore will be subject to much lower yield rates. We’ve seen this on a simple basis with respect to Intel’s server products. Later versions of the Pentium III Xeon, for example, incorporated huge on-die caches that bumped the transistor count into the hundreds of millions, and resulted in a die size two to three times the size of a typical desktop processor at the time. These huge Xeons were difficult to manufacture, and came with a corresponding price premium. The move to 90nm technology has allowed Intel to cram a comparatively huge amount of cache memory onto the Pentium 4 die. Prescott improves on the previous Northwood processor by boasting a huge 1MB L2 cache. Despite the larger cache, which helps to drive Prescott’s transistor count to over 125 million, the processor’s physical size remains manageable at only 112 square millimeters – roughly 50% smaller than Intel’s first Willamette Pentium 4 with its tiny 256kB L2 cache.In addition, Intel has also taken the opportunity to increase the size of the Pentium 4’s L1 cache as well. Prescott’s L1 data cache is now doubled to 16kB, while the L1 instruction cache (or Execution Trace Cache) remains at 12k micro-ops. The Pentium 4 was initially designed with a small 8kB L1 data cache as a tradeoff in order to maximize the speed of the cache. Set-associativity of the L1 data cache has also increased from 4-way to 8-way.

Figs. 1 & 2 - Color-enhanced photos of Intel's Pentium 4 processor dies. On the left is the 130nm Northwood core; the 90nm Prescott core is on the right. Notice the larger L2 area on the Prescott die.

As you'll see later in the benchmarks, however, there are tradeoffs necessary in order to implement such a large cache.

Branching Off
Intel has further made some subtle but important enhancements to the Pentium 4’s branch prediction systems. Mispredicted code branches result in pipeline stalls as the entire pipeline needs to be flushed to clear the bad branch. With the Pentium 4’s extremely deep pipeline (more on this later), stalls have a dramatic impact on performance.Despite the exemplary accuracy of the Pentium 4’s branch predictor units, there nevertheless exist situations in which the BPU simply cannot make a prediction. In this case, the Branch Target Buffer (BTB) contains no prediction information about the current branch, and so the processor defaults to a rather simple, static prediction algorithm. Intel has enhanced this simple static algorithm to be more accurate. Without excessive description, the new prediction algorithm examines the distance and other properties of the branch to attempt to ascertain whether the branch may be a loop-ending command, and thus whether or not it should be taken. Subtle enhancements have also been made to the dynamic brand prediction algorithms as well.Branch prediction success rate is often difficult to quantify, and changes to branch prediction schemes can show various outcomes, ranging from much better performance, to marginally better performance, or even to decreased performance in some situations. We have been given access to some in-house testing conducted by Intel, and while we cannot post actual numbers at this time, we can summarize the results as follows: Testing using the SPECint_base2000 software showed that Prescott’s mispredicted branch rate ranged from 54% lower to 10% higher than Northwood’s at the extremes, and the overall average branch misprediction rate was about 12% lower on the new Prescott core than Northwood; an impressive improvement.Again, these results are difficult to quantify in terms of real-world performance, but the effects should not be underestimated given the degree to which mispredicted branches impact the performance of Prescott’s deep pipeline.

Round 3, SSE Gets a Refresh
Prescott marks the introduction of Intel’s latest extensions to the IA-32 ISA, adding thirteen new instructions. Most of these new instructions make use of the Streaming SIMD Extension (SSE) registers, and as a result, Intel has named the new instructions SSE3. The majority of these instructions relate to graphics and complex arithmetic operations. Two of the instructions were designed to help software make better use of the processor’s Hyper-Threading capability by helping to indicate when a thread may no longer be engaged in useful work.Naturally the benefits of these added instructions will not become apparent until software developers begin to make use of them. As is generally the case with instruction set extensions, there will be particular pieces of software or particular operations that exhibit very tangible performance improvements, while others really have no use for the added instructions, and thus show no change.

Intel's 2004 Roadmap, Sock-et to Me!
Both Prescott and Northwood are introduced in 3.40 GHz versions today, and both are packaged in the current Socket-478 platform. 3.40 GHz will be the final stop for the Socket-478 platform at the high-end, however.When Intel introduces a 3.60 GHz variant of the Prescott processor in Q2 2004, it will be on the new Socket-775 platform only. Socket-775 boards will have much tougher power design specifications that will be necessary to feed these thirsty processors at 3.60 GHz and above. Subsequent versions of the Prescott processor, including the 3.80 GHz in Q3 2004, and the 4.00 GHz in Q4 2004, will appear on the Socket-775 platform only, as will Prescott’s successor, Tejas, in 2005. All Prescott Pentium 4 processors will operate with an 800 MHz FSB, and will feature Hyper-Threading Technology (excluding the 2.80A GHz model, which uses a 533 MHz bus and no Hyper-Threading).At the low-end, Intel will continue to use the Socket-478 platform for its Celeron processor through 2004. Over the year, the Celeron will slowly ramp up to 3.33 GHz using the 90nm process, and continue to use the Socket-478 platform. It will eventually migrate to the Socket-775 platform as well near the end of the year. All 90nm Celerons will get a bump to 256kB of L2 cache.

Fig. 3 - Intel's current 2004 roadmaps suggest the above processors will be introduced in the timeframes indicated. The last Socket-478 Pentium 4 processor is the 3.40 GHz parts introduced today.

As an aside, these 90nm Celerons may be of some interest to overclockers. A 2.53 GHz (533 MHz FSB) Celeron using the 90nm process will be introduced in Q2 2004, and depending on its price and the maturity of the process at that point, may prove to be a capable overclocker.
Incremental Improvements
Beyond the previously discussed items, Prescott also contains several incremental improvements versus the previous Northwood core. We won’t discuss these in great detail, but rather summarize them briefly below:
Automated functional block design & strained silicon technology
Shifter/Rotator block added to one of the core’s double-speed ALUs
More flexible trace cache
Added a dedicated integer multiplier, which results in lower integer multiply latency.
Increased micro-op scheduler capacity
Improved hardware and software prefetching capability
Additionally, to clear up any confusion that may be caused by the marketing, the following table summarizes current Intel Pentium 4 processors that are available as of today.
Fig. 4 - Intel's current desktop processor lineup. These processors are available at retail and OEM levels as of the time of publication of this article.

Something Rotten in Santa Clara
Despite what seems to be a largely improved processor, and one that should easily outperform a Northwood-core Pentium 4 at equivalent clock speed, this is not the case. Further, there are some strong indications that there is something very seriously wrong with Intel’s 90nm process. Firstly, Prescott was delayed. Earlier roadmaps showed Prescott arriving at the end of 2003, which clearly hasn't been the case. Secondly, Prescott’s pipeline has been deepened versus Northwood’s (probably related to the delays) from 20 stages up to a whopping 31 stages. More importantly, signs indicate that this wasn’t a previously planned change, and Intel seems much less inclined to discuss it than is typically the case when these types of changes are made. From a company that prides itself on adhering to its roadmaps religiously, and that typically talks about these changes openly, this is some rather alarming behavior. Typically a process shrink like this would allow an almost instant boost in clockspeed. The last drop, from the 180nm Willamette down to the 130nm Northwood allowed an almost instant 20% boost in clockspeed, which worked its way up to over 60% as the process was refined. The final Northwood at 3.40GHz is 70% faster than the fastest Willamette as a result of the success of the 130nm process.This time, on the other hand, the drop to 90nm seems not to be resulting in the usual improvements. So much so, in fact, that a rather last-minute change to the pipeline was necessary to produce decent yields at the promised speeds. The longer pipeline will lower Prescott’s IPC, and largely offset any gains as a result of the improvements discussed. See our benchmarks for direct comparison. Some would no doubt argue that Intel is simply taking its time, and preparing for the future, as there's no imminent danger from AMD at the moment (which also seems to be having trouble with its 130nm strained silicon process - coincidence?). There may be some validity to that argument. Unfortunately at this point we can’t offer anything more than speculation. Intel’s public position is that everything is just fine, a 31-stage pipeline was all part of the plan, and it still promises 4GHz by year end. Yet its actions seem to indicate behind-the-scenes scrambling. Usually when there's this much whispering about problems, and such a tight-lipped reaction from the company, there's at least some truth to the speculation. We leave you to form your own conclusions.

Benchmark Configuration
Intel Pentium 4 Processor 3.20E GHz (Prescott)
Intel Pentium 4 Processor 3.06 GHz (Northwood)
Intel Desktop Board D875PBZ, 875 Chipset
512 MB (2 x 256 MB) PC3200 DDR Memory in Dual-Channel Configuration
ATI Radeon 9700 Pro
Western Digital WD400BB 40 GB Hard Disk
Creative Labs SoundBlaster Live!
Enermax EG465P-VE 460W Power Supply
Microsoft Windows XP Professional w/ Service Pack 1
Microsoft DirexctX 9.0
Intel Chipset Drivers v/ 5.00.1012
Intel Application Accelerator v/ 3.5.0.2600
ATI Catalyst 4.1

Socket T

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:49:00 +0000

By : http://en.wikipedia.org/wiki/Socket_T

Socket T
Specifications
Type:LGA

Chip form factors:Flip-chip land grid array

Contacts:775

Bus Protocol

FSB:533 MT/s, 800 MT/s, 1066 MT/s, 1333MT/s

Voltage range

Processors:
Intel Pentium 4 (2.66 - 3.80 GHz)Intel Celeron D (2.53 - 3.6 GHz )Intel Pentium 4 Extreme Edition (3.20 - 3.73 GHz)Intel Pentium D (2.66 - 3.60 GHz)Intel Pentium Extreme Edition (3.20 - 3.73 GHz)Intel Core 2 Duo (1.60 - 2.67 GHz)Intel Core 2 Extreme (2.66 - 2.93 GHz)Intel Core 2 Quad (2.4 GHz)Intel Xeon (1.86-2.66 GHz)

Socket T, also known as LGA775, is Intel's latest desktop CPU socket. LGA stands for Land Grid Array. The word "socket" is now a misnomer, because an LGA775 motherboard has no socket holes, instead it has 775 protruding pins which touch contact points on the underside of the processor (CPU).
The Prescott and Cedar Mill Pentium 4 cores, as well as the Smithfield and Presler Pentium D cores, currently use the LGA775 socket type. In July 2006, Intel released the desktop version of the Core 2 Duo (codenamed Conroe), which also uses this socket, as does the subsequent Core 2 Quad. Intel changed from Socket 478 to LGA775 because the new pin type offers better power distribution to the processor, allowing the front side bus to be raised to 1333 MT/s. The 'T' in Socket T was derived from the now cancelled Tejas core, which was to replace the Prescott core.
As it is now the motherboard which has the pins, rather than the CPU, the risk of pins being bent is transferred from the CPU to the motherboard. The risk of bent pins is reduced because the pins are spring-loaded and locate onto a surface, rather than into a hole. Also, the CPU is pressed into place by a "load plate", rather than human fingers directly. The installing technician lifts the hinged "load plate", inserts the processor, closes the load plate over the top of the processor, and pushes down a locking lever. The pressure of the locking lever on the load plate clamps the processor's 775 gold contact points firmly down onto the motherboard's 775 pins, ensuring a good connection. The load plate only covers the edges of the top surface of the CPU; the center is free to make contact with the cooling mechanism placed on top of the CPU.

Improvements in Heat Dissipation
The force from the load plate ensures that the processor is completely level, giving the CPU's upper surface optimal contact with the heat sink or cold-water block fixed onto the top of the CPU to carry away the heat generated by the CPU. This socket also introduces a new method of connecting the heat dissipation interface to the chip surface and motherboard. With Socket T, the heat dissipation interface is connected directly to the motherboard on four points, compared with the two connections of the Socket 370 and the "clamshell" four-point connection of the Socket 478. This was done to avoid the reputed danger of the heatsinks/fans of pre-built computers falling off in transit. LGA775 was announced to have better heat dissipation properties than the Socket 478 it was designed to replace; but the Prescott core CPUs (in their early incarnations) ran much hotter than the previous Northwood-core Pentium 4 CPUs, and this initially neutralized the benefits of better heat transfer. However, modern Core 2 Duo processors run at lower temperatures than the Prescott CPUs they replace.

Socket T mechanical load limits
All socket T processors(Pentium 4, Celeron, Core 2 and Quad Xeon) have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits will crack the processor die and make it unusable.

The transition to the LGA packaging has lowered those load limits, which are smaller than the load limits of Socket 478 processors but they are bigger than socket 370 and socket A processors which were fragile. They are large enough to ensure that processors will not crack.

Socket P

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:47:00 +0000

By : http://en.wikipedia.org/wiki/Socket_P

Socket P

Socket P
Specifications
Type:PGA

Chip form factors:Flip-chip pin grid array

Contacts:478

Bus Protocol

FSB:400MT/s, 533 MT/s, 667 MT/s, 800MT/s

Voltage range

Processors:
Intel Core Solo,Intel Core Duo,Intel Dual-Core Xeon (1.67, 2.0),Intel Core 2 Duo, (T5x00, T7x00),Intel Celeron M (Penryn, Merom)

The Intel Socket P is the mobile processor socket replacement for the new Intel Core 2 chips. It has an 800 MT/s FSB, that is switchable on the fly to 400MT/s to save power. It launched on May 9, 2007, as part of the Santa Rosa platform. Socket P has 478 pins, but is not pin-compatible with Socket M.

Processors
Celeron M 540
Core 2 Duo T7100
Core 2 Duo T7300
Core 2 Duo T7500
Core 2 Duo T7700
Rumored to use this socket:
Core 2 Duo X7800 (2.6 GHz)
Core 2 Duo X7900 (2.8 GHz)

Socket 478

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:45:00 +0000

By :http://en.wikipedia.org/wiki/Socket_478

Socket 478
Specifications
Type :PGA-ZIF

Chip form factors:Flip-chip pin grid array (FC-PGA2 or FC-PGA4)

Contacts:478

Bus Protocol:AGTL+

FSB:400 MT/s533 MT/s800 MT/s

Voltage range

Processors :
Intel Pentium 4 (1.4 - 3.4 GHz)Intel Celeron (1.7 - 2.8 GHz)Celeron D (2.13 - 3.2 GHz)Intel Pentium 4 Extreme Edition (3.2, 3.4 GHz)

In computing, Socket 478 is a type of CPU socket used for Intel's Pentium 4 and Celeron series CPUs. Socket 478 was phased out with the launch of LGA775.
Socket 478 has been used for all of the Northwood Pentium 4s and Celerons, the first Prescott Pentium 4s, and some Willamette Celerons and Pentium 4s. Socket 478 also supports newer Prescott Celeron Ds, and early Pentium 4 Extreme Edition processors with 2MB of L3 cache and some Core Duos. The socket was launched with the Northwood core to compete with AMD's 462-pin Socket A and their Athlon XP processors. Socket 478, which accommodates high and low-end processors, was also the replacement for Socket 423, a Willamette processor socket which remained in the market for only a short time.
Motherboards that use this socket support DDR, RDRAM, and in some cases SDRAM. However, the majority of boards are DDR based. Initial motherboards only supported RDRAM, however RDRAM is quite expensive, compared to DDR and SDRAM, and consumers demanded an alternative, thus DDR and SDRAM boards were made. Later revisions to chipsets that support Socket 478 added higher FSB speeds, higher DDR speeds, and support for dual channel DDR.
Like the previous Socket 423, Socket 478 is based on Intel's Quad Data Rate technology, with data transferring at four times the clock rate of its Front Side Bus. As such, the 400 MT/s bus was based on a 100 MHz clock signal, but was still able to provide 3.2GB/s of data to the chipset. At its release, no SDRAM product was capable of supporting so high a data rate, so Intel pushed forward RDRAM technology, with two channels of PC800 providing synchronous data capability. Poor consumer acceptance of expensive RDRAM lead Intel to release low-performance PC133-supporting chipsets, and finally DDR chipsets.
While the original 400 MT/s bus matched the data rate of PC3200, this bus speed was already outdated by the time PC3200 became available. Dual-channel memory was introduced on later chipsets, so that a matched pair of PC3200 modules was able to match the final 800 MT/s FSB.
The Celeron D is also available for Socket 478 and they are now the only CPU's still made for the socket. They use a quad-pumped 133MHz Bus Giving A 533MT/s FSB. They are available with 256KB L2 Cache and are built on the 90nm manufacturing process, using the Prescott Core.
Socket 478 is officially known by Intel as FC-PGA2 [1]. While Core Duo is available in a 478-pin package, that socket is different: micro FC-PGA [2], which was also used for earlier Pentium M and Celeron M processors. Core Duo is also available in a 479-ball (not pin) package known as micro FC-BGA.
Socket 478 mechanical load limits
All socket 478 processors(Pentium 4 and Celeron) have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits will crack the processor die and make it unusable.

LocationDynamicStaticTransientIHS Surface

890 N(200 lbf)
445 N(100 lbf)
667 N(150 lbf)

Socket 423

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:44:00 +0000

By : http://en.wikipedia.org/wiki/Socket_423

SpecificationsTypePGA-ZIF

Chip form factorsOrganic Land Grid Array (OLGA) on Interposer (OOI) (INT2 and INT3)

Contacts
423
Bus ProtocolAGTL+

FSB100 MHz FSB(equivalent to FSB400 (Quad data rate))

Voltage range1.0 - 1.85 V

ProcessorsIntel Pentium 4 (1300 MHz - 2000 MHz)

Socket 423
Socket 423 was a CPU socket used for the first Pentium 4 processors, based on the Willamette core. The socket was short-lived, as it became apparent that its electrical design proved inadequate for raising clock speed beyond 2.0 GHz. Intel produced chips using this socket for less than a year, from November 2000 to August 2001. It was replaced by Socket 478.
The "PowerLeap PL-P4/N" is a device developed in the form of a socket adapter allowing the use of socket 478 processors on the socket 423.
Along with the socket these CPUs use (and therefore the motherboards), there is another short lived and odd piece of hardware: the RAM. The type of RAM used on some of these motherboards is RDRAM. This type of RAM is now very expensive, ranging from $US54 for 128MB to $US214 for 512MB. These sticks of RAM also must be used in pairs similar to modern dual channel memory.

Xeon

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:40:00 +0000

By : http://en.wikipedia.org

Xeon

The Xeon brand refers to Intel's x86 multiprocessing CPUs - for dual-processor (DP) and multi-processor (MP) configuration on a single motherboard (like AMD's Athlon MP and Opteron branded processors) - targeted at non-consumer markets of server and workstation computers, and also at blade servers and embedded systems. The Xeon brand has been maintained over several generations of x86 and x86-64 processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. Intel's (non-x86) IA-64 processors are called Itanium, not Xeon.

Pentium II Xeon
The first Xeon branded processor was released in 1998, named the Pentium II Xeon (codenamed "Drake"), as the replacement of the Pentium Pro. It was based on the 0.25 µm "Deschutes" core (P6 microarchitecture) branded Pentium II (sharing its 80523 product code), used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the Pentium II desktop CPU (Deschutes) in that its off-die L2 cache ran at full speed. It also used a larger slot known as slot 2. Cache sizes were 512 KB, 1 MB and 2 MB, and it used a 100 MT/s front side bus (FSB).

Pentium III Xeon
In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. The initial version, "Tanner", was just like its predecessor except for the addition of Streaming SIMD Extensions (SSE) and a few cache controller enhancements found in the "Katmai" Pentium III. The second version, the "Cascades", was based on the "Coppermine" core branded Pentium III. The Cascades had a 133 MT/s bus and only a 256 KB on-die L2 cache resulting in almost the same capabilities, as the Coppermine desktop Slot 1 versions (branded Pentium III) also capable of dual-processor operation, but not only quad-processor operation. To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. Product codes for Tanner and Cascades mirrored that of Katmai and Coppermine; 80525 and 80526 respectively.

Xeon (DP) & Xeon MP (32-bit)
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst architecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascade 2 MB core and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive.
At most two Foster processors could be accommodated in an SMP system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson Hyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions.
In 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 KB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache.
The Foster shared the 80528 product code with Willamette; The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.

Xeon (DP) & Xeon MP (64-bit)

Due to a lack of success with Intel's Itanium and Itanium 2 processors, the 90 nm version of the Pentium 4 (""Prescott") was built with support for 64-bit instructions (called Intel 64, Intel's implementation of x86-64), and a Xeon version codenamed "Nocona" was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with twice the L2 cache of Nocona and able to reduce its clockspeeds during low processor demand. However, independent tests showed that AMD's Opteron still outperformed Irwindale.
64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. All these Prescott-derived Xeons have the product code 80546.

Dual-Core Xeon

"Paxville DP"
The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. Paxville DP had NetBurst architecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield") with 4 MB of L2 Cache (2 MB per core). The only one Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.

7000-series "Paxville MP"
An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 and 3.0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.

LV (ULV), "Sossaman"
On 14 March 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Subsequently an ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like AMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e. targeted at the blade-server and embedded markets), and it was rated at a thermal design power (TDP) of 31 watts (LV: 1.66 and 2 GHz ) and 15 W (ULV: 1.66 GHz)[1]. As such, it supported most of the same features as earlier Xeons - Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but it did not support 64-bit operations, so it could not run 64-bit-only server software, such as Microsoft Exchange Server 2007, and - so - it was limited to only 16 GB of memory. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to allow Sossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favour of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no planned upgrades.

5000-series "Dempsey"
On 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst architecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.67 and 3.73 GHz (model numbers 5030-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771.

5100-series "Woodcrest"
On 26 June 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel Core microarchitecture processor to be launched on the market. It is a server and workstation version of the Intel Core 2 processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.

It has a 1333 MT/s FSB in most models, except for the 5110 and 5120, which have a 1066 MT/s FSB, with the fastest processor clocking in at 3.0 GHz. All Woodcrests use LGA 771 and all but the 5160 and 5148LV have a TDP of 65 W, which is much less than the previous generation of 130 W. The 5160 has a TDP of 80 W, still much less than 130 W, and the 5148LV, has a TDP of 40 W. All models support Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, with Demand-Based Switching only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MiB of shared L2 Cache.

7100-series "Tulsa"
Released on 29 August 2006 , the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MiB of L2 cache (1 MiB per core) and up to 16 MiB of L3 cache. It uses Socket 604 . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MiB to 16 MiB across the models.

7300-series "Tigerton"
The 7300 series, codenamed Tigerton will be a quad-core, MP-capable processor to be released in place of Whitefield. It is expected to ship in the second half of 2007.

3000-series "Conroe"
The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU, released at the end of September 2006, was just rebranded version of the Intel's mainstream Conroe otherwise branded as Core 2 Duo (for consumer desktops). Unlike most Xeon processors, they only support single-CPU operation. They use Socket T (LGA775), operate on a 1066 MHz front-side bus, and do not support Hyper-Threading. Processors with a number ending in "5" have a 1333 MT/s FSB.

Quad-Core Xeon

5300-series "Clovertown"

A quad-core successor of Woodcrest for DP segment, consisting of two Woodcrest chips in one package similar to the Pentium D Presler or quad-core Kentsfield. The Clovertown has been usually implemented with two Woodcrest dies on a multi-chip module, with 8 MiB of L2 cache (4 MiB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown, product code 80563, on 14 November 2006 [9] with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 to 2.66 GHz. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB. All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310 and L5320 (1.6 and 1.86 GHz respectively). The 3.0 GHz X5365 was expected in July 2007, and became available in the Apple Mac Pro [11] on 4 April 2007.

3200-series "Kentsfield"
Intel released relabeled versions of its quad-core Core 2 Quad processor as the Xeon 3200-series on 7 January 2007. The models are the X3210, X3220 and X3230, running at 2.13, 2.4 and 2.66 GHz, respectively. Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MHz front-side bus.

Future versions

Whitefield (cancelled)

A quad-core processor, partially based on Woodcrest, and would have used the new Common System Interface (CSI) bus, a bus shared with the Itanium 2 processors of its generation (beginning with the "Tukwila" core). Whitefield would have had 16 MiB of L2 cache, manufactured using the 65 nm process initially, and the 45 nm process later.
Whitefield was the first full processor being worked on at Whitefield, Bangalore, India. It was cancelled from the processor roadmap and replaced with Tigerton.

Aliceton

Aliceton was a successor to Tigerton. It has effectively been renamed Dunnington as the original Dunnington was based on the now cancelled Whitefield.

Dunnington

A 45 nm successor to Tigerton (formerly Aliceton), a four to eight (likely six) core processor [19] [20]. Dunnington was originally based on Whitefield, but with Whitefield cancelled, Dunnington's details are less clear.
Harpertown
Harpertown is said to be a 45 nm, eight-core processor with 12 MiB of L2 cache. An older rumour stated that it was simply the 45 nm shrink of Woodcrest, but that has since changed. Harpertown, which will succeed the current 65 nm Clovertown processors (Xeon 5300 series), will receive 5400 sequence number, with X, E, and L letters indicating performance, regular and low-power versions of the CPU.
The mainstream lineup (80 watts) will reach from the E5405 with a clock speed in the low 2 GHz range up to the E5450 with 3.0 GHz. The X5460 will clock in at 3.16 GHz and will be rated at a thermal design power of 120 watts. Intel also plans to introduce two low-power versions, rated at 50 watts, with 2.33 and 2.66 GHz speeds (L5410 and L5430). All Harpertown processors will include a 12 MB L2 cache, up from 8 MB in Clovertown. The front side bus is expected to be a FSB1333 version across the board, while the slide published by VR-Zone still indicates that the E5405 could run at a slower clock speed.
The dual-core version of the CPU, code-named Wolfdale, apparently will be available with processor speeds of 1.86 GHz and 3.33 GHz (both rated at 65 watt TDP). There will also be a 3.16 GHz low-power version of the processor, running at 40 watts.

Harpertown and Wolfdale are expected to launch late in Q4 of this year(2007).

Gainestown
Gainestown is a quad-core processor based on Intel's upcoming Nehalem microarchitecture.

Beckton
Nehalem-based MP-capable processor.

Supercomputers

Supercomputers based on Xeon processors in the top 10 of the Top500 fastest supercomputers in the world:
Thunderbird, at Sandia National Laboratories. Machine: Dell PowerEdge 1850 Cluster. CPU: 9,024 Xeons (3.6 GHz). Connection: InfiniBand. Rmax: 38.27 Teraflops. (number 5 as of November 2006, ahead of the fastest Itanium-based supercomputers but behind three PPC-based systems and one Opteron system.)

Intel Itanium

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:36:00 +0000

By : http://en.wikipedia.org

Itanium
Itanium 2

Produced:
From mid 2002 to present
Manufacturer:Intel
CPU Speeds:733 MHz to 1.6 GHz
FSB Speeds:200 MHz to 533 MHz
Instruction Set:Itanium
Socket:PAC611
Cores:
· McKinley
· Madison
· Hondo
· Deerfield
· Montecito

Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel has released two processor families using the brand: Itanium and Itanium 2. The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP) which was then later developed by HP and Intel together.
Itanium's architecture differs dramatically from the x86 and x86-64 architectures used in other Intel processors. The architecture is based on explicit instruction-level parallelism, with the compiler making the decisions about which instructions to execute in parallel. This approach allows the processor to execute up to six instructions per clock cycle. By contrast with other superscalar architectures, Itanium does not need elaborate hardware to keep track of instruction dependencies during parallel execution.
After a protracted development process, the first Itanium was released in 2001, and subsequently more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007, Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC. After a schedule slip of several years,Intel released its newest Itanium 2, codenamed Montecito, in July 2006.
Development: 1989–2001
In 1989, HP determined that reduced instruction set computer (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture called Explicitly Parallel Instruction Computing (EPIC) that allows the processor to execute multiple instructions in one clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, where one instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.
HP determined that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so HP partnered with Intel in 1994 to develop the IA-64 architecture, which derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of the enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, codenamed Merced, in 1998.
During development, Intel, HP, and industry analysts were predicting that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications. Several groups began to develop operating systems for the architecture, including Microsoft Windows variants, Linux variants, and UNIX variants. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of the Merced began slipping quarter by quarter.Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more unanticipated research was needed.
Intel announced the official name of the processor, Itanium, on October 4, 1999.Within hours observers referred to the processor as Itanic,a reference to Titanic, the "unsinkable" ocean liner which sank in 1912. Itanic has since often been used by The Register,Scott McNealy,and others It alludes to the perception that Itanium is a white elephant which cost Intel and HP many billions of dollars while failing to achieve expected performance and sales in the originally projected timeframe. Meanwhile, RISC and CISC architects were making steady improvements in superscalar implementations, allowing them to break the one-instruction-per-clock barrier without using EPIC.

Itanium processor: 2001–02

Intel Itanium processor
Produced:
From June 2001 to June 2002
Manufacturer:Intel
CPU Speeds:733 MHz to 800 MHz
FSB Speeds:266 MT/s to 266 MT/s
Instruction Set:Itanium
Socket:PAC418
Core Name:Merced

By the time Itanium was released in June, 2001, it was no longer superior to contemporaneous RISC and CISC processors. Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on x86 processors, and at the high end with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86's successful "horizontal" (i.e., single architecture, multiple systems vendors) market. Its success was limited to replacing PA-RISC and Alpha in HP systems and MIPS in SGI's HPC systems. POWER and SPARC remained strong, while the 32-bit x86 architecture grew into the enterprise space. With economies of scale fueled by its enormous installed base, x86 was the preeminent "horizontal" architecture in enterprise computing. HP and Intel recognized that Itanium was not competitive and replaced it with Itanium 2 a year later, as they had planned. Only a few thousand of the original Itaniums were sold, due to limited availability caused by poor yields, relatively poor performance, and high cost. However, these machines were useful for software development for the Itanium 2 processors that followed. IBM delivered a supercomputer based on this processor.[12]
Itanium 2 processors: 2002–present
The Itanium 2 was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The initial Itanium 2 was codenamed McKinley. McKinley used a 180 nm process, but it relieved many of the performance problems of the original Itanium. In 2003, AMD released the Opteron, which implemented its x86-64 64-bit architecture. Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004 Intel released a new Itanium 2 family member, codenamed Madison, in 2003. Madison used a 130 nm process and was the basis of all new Itaniums until Montecito was released in June 2006.
In March, 2005, Intel announced that it was working on a new Itanium device, codenamed Tukwila, to be released in 2007. Tukwila would have four processors and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon.Intel later said that Tukwila would be delivered in late 2008.
In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software portingThe Alliance announced that its members would invest $10 Billion in Itanium solutions by the end of the decade. As of June 2007, Intel has released seven additional versions of the Itanium 2, and another is expected in late 2007.
Architecture
the Itanium instruction set and microarchitecture, and the technical press has provided overviews.The architecture has been renamed several times during its history. HP called it EPIC and renamed it to PA-WideWord. Intel later called it IA-64, before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64. It is a 64-bit register-rich explicitly-parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 264 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.
The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.
Instruction execution
Each 128-bit instruction word contains three instructions, and the fetch mechanism can read up to two instruction words per clock from the L1 cache into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the instruction set, and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units. The groups are:
Six general-purpose ALUs, two integer units, one shift unit
Four data cache units
Six multimedia units, two parallel shift units, one parallel multiply, one population count
two floating-point multiply-accumulate units, two "miscellaneous" floating-point units
three branch units
Thus, the compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply-accumulate operation, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four FLOPs per cycle.
Memory architecture
From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KiB. The Level 3 cache was also unified and varied in size from 1.5 MiB to 24 MiB. The 256 Kib L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU).
Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to by Intel's official name: the Scalability Port. The speed of the bus has increased steadily with new processor releases. The bus transfers 2x128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s and the 533 MHz Montecito bus transfers 17.056 GB/s.
Architectural changes
Itaniums released prior to 2006 had hardware support for the IA-32 architecture to permit support for legacy server applications, but performance was much worse in comparison with native instruction performance and contemporaneous x86 processors. In 2005 Intel developed a software emulator that provided better performance. With Montecito, Intel removed IA-32 support from the hardware.
With Montecito, Intel made enhancements to the architecture in July 2006 The architecture now includes hardware multithreading: each processor maintains context for two threads of execution. When one thread stalls due to a memory access the other thread gains control. Intel calls this "coarse multithreading" to distinguish it from "hyperthreading technology" that was used in some x86 and x86-64 microprocessors. Coarse multithreading is well matched to the Intel Itanium Architecture and results in an appreciable performance gain. Intel also added hardware support for virtualization. Virtualization allows a software "hypervisor" to run multiple operating system instances on the processor concurrently. Montecito also features a split L2 cache, adding a dedicated 1 MiB L2 cache for instructions and converting the original 256 KiB L2 cache to a dedicated data cache.

As of 2007, several manufacturers offer Itanium 2 based systems, including HP, SGI, NEC, Fujitsu, Unisys, Hitachi, and Groupe Bull. In addition, Intel offers a chassis[20] that can be used by system integrators to build Itanium systems. HP, the only one of the industry's top four server manufacturers to offer Itanium-based systems today, manufactures at least 80% of all Itanium 2 systems. HP sold 7200 systems in the first quarter of 2006.[21] The bulk of the sales are of enterprise servers and machines for large-scale technical computing, with an average selling price per system in excess of US $200,000. A typical system uses eight or more Itanium processors.
Chipsets
The Itanium bus interfaces to the rest of the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. Currently, modern chipsets for Itanium are manufactured by HP, Fujitsu, SGI, NEC, Hitachi, and Unisys. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express.

Processors

The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt.The future of the Itanium family apparently lies in multi-core chips, based on available information about coming generations. The final products will most likely bear the Itanium 2 brand, or possibly Itanium 3. As of June 2007, some information is known for the following:
Montvale will be a revision of Montecito bringing slightly higher clock speeds (to 1.66Ghz), larger L3 caches (to 24MiB), and a faster FSB (to 667Mhz). The processor will implement a new power-saving system. Montvale will comprise a set of six variants called the Itanium 2 9100 series. Release is expected at the end of 2007. The processors were originally expected to be released in June 2007, a year after Montecito.
Tukwila, the first 65 nanometer design, is due in late 2008. Tukwila will include four cores, large on-die caches, Hyper-Threading technology and an integrated memory controller. A key feature of Tukwila is double-device data correction, which helps to fix memory errors. Poulson will use a 32 nm process and will feature four or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. For Kittson, few details are known other than the existence of the codename.

Intel Celeron

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:34:00 +0000

By : http://en.wikipedia.org/

Celeron

Produced:April 1998
Manufacturer:Intel
CPU Speeds:266 MHz to 3.60 GHz
FSB Speeds:66 MHz to 200 MHz
Process:(MOSFET channel length)0.25 µm to 0.065 µm
Instruction Set:x86, x86-64
Microarchitecture:P6, NetBurst, Core
Sockets:
· Slot 1
· Socket 370
· Socket 478
· LGA 775
Cores:
· Covington
· Mendocino
· Coppermine-128
· Tualatin-256
· Willamette-128
· Northwood-128
· Prescott-256

Celeron

Celeron is a brand name given by Intel Corp. to a large number of different x86 microprocessor models that they produced and marketed as a budget/value CPU line. The Celeron family complements Intel's higher-performance (and more expensive) product lines (currently Core 2 Duo and formerly Pentium). Introduced in April 1998, the first Celeron was based on the Pentium II core. Later versions were based on the Pentium III, Pentium 4,Pentium M, and Core 2 Duo. These processors are suitable for most applications, but their performance is somewhat limited when it comes to running intense applications, such as cutting edge games or graphical modeling programs, as compared to that of their high-end counterparts.
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to Cyrix's 6x86, AMD's K6, and IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233MHz[3]. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium II's (Slot 1) interface. The Celeron was used in many low end machines and, in some ways, became the standard for non gaming computers.

Celeron (P6)
Covington
The first Celeron (codenamed Covington) was essentially a 266 MHz Deschutes Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (Frequencies 33 to 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in slot 1 SEPP format.
The Mendocino Celeron, launched August 24th, 1998, was the first mass-market CPU to utilise on-die L2 cache. Where as Covington had no secondary cache at all, Mendocino included 128 KiB of L2 cache running at full clock speed. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clockspeed. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors "Celeron-A" regardless of speed.
The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) speed from the stock 66 MHz to the 100 MHz spec of the Pentium II. At this speed, the Mendocino Celeron rivaled the fastest x86 processors available.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock frequency as the CPU. All other CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KiB or 1 MiB), but they carried the performance penalty of slower cache speed, typically running at FSB speed (60 to 100 MHz) for motherboard mounted L2 cache. The implementation of the Pentium II's 512 KiB of L2 cache was unique at the time (and later copied by AMD's Athlon), being comprised of moderately high-speed L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half processor speed and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked faster and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The "Mendocino" Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock speeds reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is that SMP (symmetric multiprocessing) mode was available, and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with speeds from 266, 300, 333, 366, 400, 433, and 466, 500, 533, 566, 600 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.
The next generation Celeron was the Coppermine-128 (sometimes known as the "Celeron II"). These were a derivative of Intel's Coppermine Pentium III and were released on March 29th, 2000[12]. Like the Mendocino, the Celeron-128 used 128 KiB of on-chip L2 cache and was (initially) restricted to a 66 MHz bus speed, but the big news was the addition of SSE instructions, due to the new Coppermine core. Other than half the L2 cache (128 KiB instead of 256 KiB) and a slower FSB (66 to 100 MHz instead of 100 to 133 MHz), the Coppermine Celeron was identical to the Coppermine Pentium III.
All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 666, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rate increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement[13]. All Celeron-128 CPUs from 800 MHz and faster use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.
In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.
Tualatin-256
These Celeron processors, released initially at 1200 MHz (1.2 GHz) on October 2nd, 2001[14], were based on Pentium III Tualatin core and made with a 0.13 micrometer process for the FCPGA2 socket 370 . They were nicknamed "Tualeron" — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1000 MHz and 1100 MHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same speed they replaced)[15]. A 1300 MHz chip, launched January 4, 2002[16], and finally a 1400 MHz chip, launched May 15, 2002 (the same day as the Netburst Williamette 1.7 GHz Celeron launch)[17], marked the end of the Tualatin-256 line.
With regards to core functionality, Tualatin-256 was again quite similar to its Pentium III sibling. The most significant difference was the slower 100 MHz bus, it and had only 256 KiB of L2 cache (where as the Pentium III had either 256 KiB or 512 KiB of L2 cache). Furthermore, the Tualeron's L2 cache had a higher latency which boosted manufacturing yields for this budget CPU.
Despite offering much improved performance over the Coppermine Celeron it superceded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor[18]. Intel later responded by releasing the Netburst Williamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with their replacement Pentium 4-based Celerons.
In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.
Celeron (NetBurst)
Willamette-128
These Celerons were for socket 478 and were based on the Willamette Pentium 4 core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the "Celeron 4". Their L2 cache (128 KiB) is half that of the Pentium 4 Williamette's 256 KiB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use RDRAM, DDR SDRAM, or traditional SDRAM. Williamette Celerons were launched May 15, 2002, initially at 1.7GHz, and offered a noticeable performance improvement over the older Tualatin Celeron 1300 MHz part, being able to finally best the Duron 1.3 GHz, which at the time was AMD's top competing budget processor. On June 12th, 2002, Intel launched the last Williamette Celeron, a 1.8GHz model.
In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531.
Northwood-128
These socket 478 Celerons are based on the Northwood Pentium 4 core, and also have 128 KiB of L2 cache. The only difference between the Northwood-128 and the Willamette-128 Celeron is the fact that it was built on the new 0.13 micrometre process which shrunk the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the Willamette-128 to 1.52 V for the Northwood-128. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The Northwood-128 family of processors were initially released as a 2.0 GHz Model (a 1.9GHz model was announced earlier, but never launched) on September 18th, 2002. Since that time Intel has released at total of 10 different speed grades ranging from 1.8GHz to 2.8GHz, before being surpassed by the Celeron D. Although the Northwood Celerons suffer considerably from their small L2 cache, some speed grades have been favored in the enthusiast market, because like the old 300A, they can run well above their rated speeds.
In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532.

Intel Celeron

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:34:00 +0000

By : http://en.wikipedia.org

Celeron

Produced:April 1998
Manufacturer:Intel
CPU Speeds:266 MHz to 3.60 GHz
FSB Speeds:66 MHz to 200 MHz
Process:(MOSFET channel length)0.25 µm to 0.065 µm
Instruction Set:x86, x86-64
Microarchitecture:P6, NetBurst, Core
Sockets:
· Slot 1
· Socket 370
· Socket 478
· LGA 775
Cores:
· Covington
· Mendocino
· Coppermine-128
· Tualatin-256
· Willamette-128
· Northwood-128
· Prescott-256

Celeron

Celeron is a brand name given by Intel Corp. to a large number of different x86 microprocessor models that they produced and marketed as a budget/value CPU line. The Celeron family complements Intel's higher-performance (and more expensive) product lines (currently Core 2 Duo and formerly Pentium). Introduced in April 1998, the first Celeron was based on the Pentium II core. Later versions were based on the Pentium III, Pentium 4,Pentium M, and Core 2 Duo. These processors are suitable for most applications, but their performance is somewhat limited when it comes to running intense applications, such as cutting edge games or graphical modeling programs, as compared to that of their high-end counterparts.
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to Cyrix's 6x86, AMD's K6, and IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233MHz[3]. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium II's (Slot 1) interface. The Celeron was used in many low end machines and, in some ways, became the standard for non gaming computers.

Celeron (P6)
Covington
The first Celeron (codenamed Covington) was essentially a 266 MHz Deschutes Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (Frequencies 33 to 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in slot 1 SEPP format.
The Mendocino Celeron, launched August 24th, 1998, was the first mass-market CPU to utilise on-die L2 cache. Where as Covington had no secondary cache at all, Mendocino included 128 KiB of L2 cache running at full clock speed. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clockspeed. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors "Celeron-A" regardless of speed.
The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) speed from the stock 66 MHz to the 100 MHz spec of the Pentium II. At this speed, the Mendocino Celeron rivaled the fastest x86 processors available.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock frequency as the CPU. All other CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KiB or 1 MiB), but they carried the performance penalty of slower cache speed, typically running at FSB speed (60 to 100 MHz) for motherboard mounted L2 cache. The implementation of the Pentium II's 512 KiB of L2 cache was unique at the time (and later copied by AMD's Athlon), being comprised of moderately high-speed L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half processor speed and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked faster and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The "Mendocino" Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock speeds reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is that SMP (symmetric multiprocessing) mode was available, and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with speeds from 266, 300, 333, 366, 400, 433, and 466, 500, 533, 566, 600 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.
The next generation Celeron was the Coppermine-128 (sometimes known as the "Celeron II"). These were a derivative of Intel's Coppermine Pentium III and were released on March 29th, 2000[12]. Like the Mendocino, the Celeron-128 used 128 KiB of on-chip L2 cache and was (initially) restricted to a 66 MHz bus speed, but the big news was the addition of SSE instructions, due to the new Coppermine core. Other than half the L2 cache (128 KiB instead of 256 KiB) and a slower FSB (66 to 100 MHz instead of 100 to 133 MHz), the Coppermine Celeron was identical to the Coppermine Pentium III.
All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 666, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rate increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement[13]. All Celeron-128 CPUs from 800 MHz and faster use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.
In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.
Tualatin-256
These Celeron processors, released initially at 1200 MHz (1.2 GHz) on October 2nd, 2001[14], were based on Pentium III Tualatin core and made with a 0.13 micrometer process for the FCPGA2 socket 370 . They were nicknamed "Tualeron" — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1000 MHz and 1100 MHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same speed they replaced)[15]. A 1300 MHz chip, launched January 4, 2002[16], and finally a 1400 MHz chip, launched May 15, 2002 (the same day as the Netburst Williamette 1.7 GHz Celeron launch)[17], marked the end of the Tualatin-256 line.
With regards to core functionality, Tualatin-256 was again quite similar to its Pentium III sibling. The most significant difference was the slower 100 MHz bus, it and had only 256 KiB of L2 cache (where as the Pentium III had either 256 KiB or 512 KiB of L2 cache). Furthermore, the Tualeron's L2 cache had a higher latency which boosted manufacturing yields for this budget CPU.
Despite offering much improved performance over the Coppermine Celeron it superceded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor[18]. Intel later responded by releasing the Netburst Williamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with their replacement Pentium 4-based Celerons.
In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.
Celeron (NetBurst)
Willamette-128
These Celerons were for socket 478 and were based on the Willamette Pentium 4 core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the "Celeron 4". Their L2 cache (128 KiB) is half that of the Pentium 4 Williamette's 256 KiB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use RDRAM, DDR SDRAM, or traditional SDRAM. Williamette Celerons were launched May 15, 2002, initially at 1.7GHz, and offered a noticeable performance improvement over the older Tualatin Celeron 1300 MHz part, being able to finally best the Duron 1.3 GHz, which at the time was AMD's top competing budget processor. On June 12th, 2002, Intel launched the last Williamette Celeron, a 1.8GHz model.
In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531.
Northwood-128
These socket 478 Celerons are based on the Northwood Pentium 4 core, and also have 128 KiB of L2 cache. The only difference between the Northwood-128 and the Willamette-128 Celeron is the fact that it was built on the new 0.13 micrometre process which shrunk the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the Willamette-128 to 1.52 V for the Northwood-128. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The Northwood-128 family of processors were initially released as a 2.0 GHz Model (a 1.9GHz model was announced earlier, but never launched) on September 18th, 2002. Since that time Intel has released at total of 10 different speed grades ranging from 1.8GHz to 2.8GHz, before being surpassed by the Celeron D. Although the Northwood Celerons suffer considerably from their small L2 cache, some speed grades have been favored in the enthusiast market, because like the old 300A, they can run well above their rated speeds.
In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532.

Intel Centrino

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:32:00 +0000

By : http://en.wikipedia.org

Centrino

Components of the Centrino platform. From right, clockwise: Intel PRO/Wireless network adapter, Intel mobile processor, Intel mobile chipset (southbridge and northbridge).
Centrino, a platform-marketing initiative from Intel, covers a particular combination of CPU, mainboard chipset and wireless network interface in the design of a laptop personal computer. Intel claimed that systems equipped with these technologies should deliver better performance, longer battery life and broad wireless network interoperability. The chips were developed at Intel's Haifa, Israel R&D center and since their introduction in 2003, over US$5 billion worth have been sold.[citation needed]
To qualify for a Centrino label, laptop vendors must use all three Intel qualified parts, otherwise using only the processor and chipset will carry the Intel Core label instead.

Implementations
Carmel platform (2003)
Intel used Carmel as the code name for the first-generation Centrino platform introduced in March 2003.
The Carmel platform consists of:
an Intel Pentium M processor (code-named Banias or later Dothan) with a 400 MT/s FSB, Socket 478 and
an Intel 855 series chipset (code-named Odem or Montara with Intel Extreme Graphics 2), DDR-266 and
an Intel PRO/Wireless 2100 or later 2200 (IEEE 802.11b) mini-PCI Wi-Fi adapter (code-named Calexico or Calexico2).
Industry-watchers initially criticized the Carmel platform for its lack of an IEEE 802.11g-solution, because many independent Wi-Fi chip-makers like Broadcom and Atheros had already started shipping 802.11g products. Intel responded that the IEEE had not finalized the 802.11g standard at the time of Carmel's launch, and that it did not want to launch products not based on a finalized standard.
In early 2004, after the finalization of the 802.11g standard, Intel permitted an Intel PRO/Wireless 2200BG (code-named Calexico2) to substitute for the 2100. At the same time, they permitted the new Dothan Pentium M to substitute for the Banias Pentium M. Initially, Intel permitted only the 855GM chipset, which did not support external graphics. Later, Intel allowed the 855GME and 855PM chips, which did support external graphics, in Centrino notebooks.
Despite criticisms, the Carmel platform won quick acceptance among OEMs and consumers. Carmel could attain or exceed the performance of older Pentium 4-M platforms, while allowing for notebooks to operate for 4 to 5 hours on a 48 W-h battery. Carmel also allowed notebook-manufacturers to create thinner and lighter notebooks because its components did not dissipate much heat, and thus did not require large cooling systems.
Sonoma platform (2005)
Intel used Sonoma as the code name for the second-generation Centrino platform, introduced in January 2005.
The Sonoma platform consists of:
an Intel Pentium M processor (code-named Dothan) with a 533 MT/s FSB, Socket 479 and
an Intel Mobile 915 Express series chipset (code-named Alviso with Intel's GMA 900), DDR2-533 and
the Intel PRO/Wireless 2200 or 2915ABG mini-PCI Wi-Fi adapter (code-named Calexico2).
The Mobile 915 Express chipset, like its desktop version, supports many new features such as DDR2, PCI Express, Intel High Definition Audio, and SATA. Unfortunately, the introduction of PCI Express and faster Pentium M processors causes notebooks built around the Sonoma platform to have a shorter battery-life than their Carmel counterparts; Sonoma notebooks typically achieve between 3.5-4.5 hours of battery-life on a 53 W-h battery.
Napa platform (2006)
The code-name Napa designates the third-generation Centrino platform, introduced in January 2006 at the Winter Consumer Electronics Show. The platform initially supported Intel Core Duo processors but the newer Core 2 Duo processors were launched and supported in this platform from July 27th 2006 onwards.
The Napa platform consists of:
Processors - Socket M
an Intel Core Solo, Core Duo (code-named Yonah) processor, or
an Intel Core 2 Duo (code-named Merom) processor with a 667 MT/s FSB for Napa Refresh platform.
an Intel Mobile 945 Express-series chipset (code-named Calistoga with Intel's GMA 950), including ICH7M southbridge, and
RAM supported for DDR2-533 and DDR2-667 SODIMM.
the Intel PRO/Wireless 3945ABG mini-PCIe Wi-Fi adapter (code-named Golan), and
Some newer models (as of 1st quarter 2007) of the Napa Refresh platform contain the newer 4965AGN (a/b/g/draft-n) wireless cards.
Intel uses Centrino Duo branding for laptops with dual-core ("Core Duo") and ("Core 2 Duo") processors and retains the Centrino name for laptops with single core ("Core Solo") processors. Some of the initial Core Duo laptops, are still labeled as Intel Centrino rather than Centrino Duo.
[edit] Santa Rosa platform (2007)
The code-name Santa Rosa refers to the fourth-generation Centrino platform, which was released on Wednesday 9 May 2007.
The Santa Rosa platform consists of:
Processors - Socket P
an Intel Core 2 Duo (code-named Merom) second generation processor with 800 MT/s FSB, or
an Intel Core 2 Duo (code-named Penryn) 45nm processor scheduled for release in 1H 2008 [1] for Santa Rosa Refresh platform.
an Intel Mobile 965 Express chipset (code-named Crestline) with Intel's GMA X3100 graphics technology and ICH8M southbridge, 800 MT/s front side bus with Dynamic Front Side Bus Switching to save power during low utilization, and
Intel Dynamic Acceleration (IDA), better Windows Vista Aero support. [2]
RAM supported for DDR2-533 and DDR2-667 SODIMM.
EFI-compliant firmware, a successor to BIOS.
optional NAND flash-memory caching branded as Intel Turbo Memory (code-named Robson)
the Intel Wireless WiFi Link 4965AGN (a/b/g/draft-n) mini-PCIe Wi-Fi adapter (code-named Kedron).
Wireless-N technology boasts a 5X speed increase, along with a 2X greater coverage area, and supports 2.4 GHz and 5 GHz signal bands, with enough bandwidth for high definition audio and video streams. [1]
Santa Rosa platform come with dynamic acceleration technology. It allows single threaded applications to execute faster. When a single threaded application is running the CPU can turn off one of the CPU cores and overclock the active core. In this way the CPU maintains the same Thermal Profile as it would when both cores are active. Many expect Santa Rosa to perform well as a mobile gaming platform due to its ability to switch between single threaded and multithreaded tasks. Other power savings come from an Enhanced Sleep state where both the CPU cores and the chipset will power down.
The wireless chipset update was originally intended to include WWAN Internet access via HSDPA (3.5G), (code-named Windigo) co-developed with Nokia After announcing a working partnership, both later retracted the deal citing the lack of a clear business case for the technology.
Support for WiMAX (802.16) was originally scheduled for inclusion in Santa Rosa but appears to have been delayed until Montevina in 2008. There have, however, been reports that WiMax may still be introduced in 2007.
The Santa Rosa platform is branded as "Centrino Pro" when combined with the enhanced security technologies Intel introduced with vPro and will be called "Centrino Duo" when they are not used.
Montevina platform (2008)
The code-name Montevina refers to the fifth-generation Centrino platform, scheduled for release in Q2 2008. Montevina will support Penryn, Intel's 45nm die-shrink version of its current generation of 65nm Core 2 processors.
The code-named Penryn 45nm chip is planned to consume no more than 29W, compared to Merom's 34W TDP, the debut of SSE4.1, which will add 47 new instructions to SSSE3.
Montevina comprises the Cantiga chipset (with ICH9M southbridge) and with front side bus speed increase to 1067 MT/s front side bus. The graphics core is expected to be clocked at 475MHz which will contain ten unified shaders, up from the GMA 3000's eight.
Reports have suggested RAM support for DDR3-800 in preference to the less power-efficient DDR2-800 SODIMM.
NAND flash-memory caching branded as Intel Turbo Memory (code-named Robson 2).
LAN controller (code-named Boaz). Wireless Modules
the Intel Wireless WiFi Link mini-PCIe adapter (code-named Shiloh), and the add-on card WiMAX (802.16) (code-named Dana Point), or
the Intel combo WiFi/WiMAX Link mini-PCIe adapter (code-named Echo Peak).
Intel has reportedly invested US$300 million in Centrino advertising. Because of the ubiquity of the marketing campaign, many consumers mistakenly refer to Pentium M and Intel Core processors as "Centrinos". Many consumers have received the impression that only Centrino provides wireless connectivity in a notebook. This has resulted in increased demand for Intel's PRO/Wireless chipsets.
The Centrino marketing program has been widely assumed to be responsible for the success of Intel notebook PCs. However, findings of the Japanese FTC in March of 2005 indicate that the financial incentives associated with the Centrino program were used as illegal, anti-competitive practices by Intel to induce its customers not to buy notebook chips from Intel's long time rival AMD. In the quarter immediately following the JFTC ruling, AMD boasted more than 60 notebook computer design wins which was a strong resurgence from the drastic share reductions seen in 2003 and 2004.

Intel Core 2

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:31:00 +0000

By : http://en.wikipedia.org
Core 2

Produced:
From 2006
Manufacturer:Intel
CPU Speeds:1.06 GHz to 3.0 GHz
FSB Speeds:533 MT/s to 1333 MT/s
Process:(MOSFET channel length)0.065 µm to 0.045 µm
Instruction Set:x86, MMX, SSE, SSE2, SSE3, SSSE3, x86-64
Microarchitecture:Intel Core microarchitecture
Sockets:
· Socket T (LGA 775)
· Socket M (µPGA 478)
· Socket P (uPGA 478)
Cores:
· Allendale
· Conroe
· Merom
· Kentsfield

Intel Core 2

The Core 2 brand refers to a range of Intel's mobile and desktop 64-bit dual-/quad-core x86 CPUs with the Core microarchitecture, which evolved from the 32-bit dual-core Yonah mobile processor. The Yonah comprised two interconnected single cores (the Pentium M branded microprocessor derivatives) coupled as a single die silicon chip (IC). The Core 2 marked a relegation of the Intel's Pentium brand to a lower-end market, and a reunification of Intel's notebook and desktop brand names, previously divided into the Pentium M and Pentium 4 lines.
The Core 2 brand was launched on July 27, 2006, comprising Duo (dual-core), Quad (quad-core), and Extreme (dual- or quad-core CPUs with higher speeds and unlocked multiplier) branches. The brand covers processors based on various cores; "Conroe" and "Allendale" (dual-core for higher- and lower-end desktop use, respectively), "Merom" (dual-core for notebooks), "Kentsfield" (quad-core for desktops), and their variants named "Penryn" (dual-core for notebooks), "Wolfdale" (dual-core for desktops) and "Yorkfield" (quad-core for desktops). Although the "Woodcrest", "Clovertown" and the upcoming "Tigerton" core CPUs for servers and workstations are also based on Core architecture, they are marketed under the Xeon brand. The first Core 2 Duo processors were fabricated on 300 mm wafers using a 65 nm manufacturing process.
Unlike the NetBurst architecture of Pentium 4 or Pentium D branded processors, the Core architecture does not stress extremely high clock speeds, but rather improvements in the processor's usage of both available clock cycles and power. This translated into more efficient decoding stages, execution units, caches, and buses, etc, reducing the Core 2 CPU's power consumption, while enhancing their processing capacity. With a TDP of up to only 65 W, the Core 2 dual-core Conroe consumed only half the power of some of the higher end dual-core Pentium D branded desktop chips with a TDP of up to 130 W (a high TDP requires many noisy cooling fans or a more expensive noiseless cooling system) and was more capable compared to them.
Intel Core 2 processors featured Intel 64 (also known as EM64T), Virtualization Technology (except T5500 or lower end E4x00), Execute Disable Bit, and SSE3. Core 2 also introduced SSSE3, Trusted Execution Technology, Enhanced SpeedStep, and Active Management Technology (iAMT2).
Typically for CPUs, the Core 2 Duo E4000/E6000, Core 2 Quad Q6600, Core 2 Extreme X6800, QX6700 and QX6800 CPUs were affected by bugs, but apparently minor.
Current processor cores
Conroe
The first Intel Core 2 Duo processor cores, code-named Conroe and given the Intel product code 80557, were launched on July 27, 2006 at Fragapalooza, a yearly gaming event in Edmonton, Alberta, Canada. These processors are built on a 65 nm process and are intended for desktops, replacing the Pentium 4 and Pentium D. Intel has claimed that Conroe provides 40% more performance at 40% less power compared to the Pentium D. All Conroe processors are manufactured with 4 MiB L2 cache; however, for marketing purposes, the E6300 and E6400 versions based on this core have half their cache disabled, leaving them with only 2 MiB of usable L2 cache.
The lower end E6300 (1.86 GHz) and E6400 (2.13 GHz), both with a 1066 MT/s FSB, were released on July 27, 2006. Traditionally, CPUs of the same family with less cache simply have the unavailable cache disabled, since this allows parts that fail quality control to be sold at a lower rating. As yields improve, they may be replaced with versions that only have the cache amount needed on the die, to bring down manufacturing cost. At launch time, Intel's prices for the Core 2 Duo E6300 and E6400 processors were US$183 and US$224 each in quantities of 1000. Conroe CPUs have improved capabilities over previous models with similar processor speeds. According to reviews, the larger 4 MiB L2 cache vs. the smaller 2 MiB L2 cache at the same frequency and FSB can provide a 0–9% performance gain with certain applications and 0–16% performance gain with certain games.The higher end Conroe processors are labeled as the E6600 and E6700 Core 2 Duo models, with the E6600 clocked at 2.4 GHz and the E6700 clocked at 2.67 GHz. The family has a 1066 MT/s front side bus, 4 MiB shared L2 cache, and 65 watts TDP. These processors have been tested against AMD's current top performing processors (Athlon 64 FX Series), which were, until this latest Intel release, the fastest CPUs available. Conroe chips also experience much lower heat output compared to their predecessors — a benefit of the new 65nm technology. At launch time, Intel's prices for the Core 2 Duo E6600 and E6700 processors were US$316 and US$530, respectively, each in quantities of 1000.
E6320 and E6420 Conroe CPUs at 1.86 and 2.13 GHz respectively were launched on April 22, 2007 featuring a full 4 MiB of cache and are considered Conroes.
Intel released four additional Core 2 Duo Processors on July 22nd, 2007. The release coincided with that of the Intel Bearlake (x3x) chipsets. The new processors are named Core 2 Duo E6540, E6550, E6750, and E6850. Processors with a number ending in "50" have a 1333 MT/s FSB. The processors all have 4 MiB of L2 cache. Their clock frequency is similar to that of the already released processors with the same first two digits (E6600, E6700, X6800). An additional model, the E6540, was launched with specifications similar to the E6550 but lacking Intel Trusted Execution Technology and vPro support. These processors are slated to compete with AMD's Stars processor line and are therefore priced below corresponding processors with a 1066 MT/s FSB.
Conroe XE
The Core 2 Extreme was officially released on July 29, 2006. However some retailers appeared to have released it on July 13, 2006, though at a higher premium. The less powerful E6x00 models of Core 2 Duo were scheduled for simultaneous release with the X6800, which are both available at this time. It is powered by the Conroe XE core and replaces the dual-core Pentium Extreme Edition processors. Core 2 Extreme has a clock speed of 2.93 GHz and a 1066 MT/s FSB, although it was initially expected to be released with a 3.33 GHz and 1333 MT/s. The TDP for this family is 75–80 watts. At full load the X6800 does not exceed 45 °C (113 °F), and with SpeedStep enabled the average temperature of the CPU when idle is essentially that of the ambient atmosphere.
At launch time, Intel's price for the Core 2 Extreme X6800 was US$999 each in quantities of 1000. Like the desktop Core 2 Duo, it has 4 MiB of shared L2 cache available. This means that the only major difference between the regular Core 2 Duo and Core 2 Extreme is the clock speed and unlocked multiplier, usual advantages of the "Extreme Edition." The unlocked upward multiplier is of use to enthusiasts which allow the user to set the clockspeed higher than shipping frequency without modifying the FSB unlike mainstream Core 2 Duo models which are downward unlocked only.
Allendale
There was contention as to whether the previously-available low-end Core 2 Duo desktop processors (E6300, at 1.86 GHz and E6400, at 2.13 GHz, both with 2 MiB L2 cache) are specimens of the Allendale core. Prior to Q1 2007, all E6300 and E6400 processors released were Conroe (4 MiB L2 cache) cores with half their L2 cache disabled. The Allendale core, manufactured with 2 MiB L2 cache in total, offers a smaller die size and therefore greater yields.
Quoted from The Tech Report:
You'll find plenty of sources that will tell you the code name for these 2MB Core 2 Duo processors is "Allendale," but Intel says otherwise. These CPUs are still code-named "Conroe," which makes sense since they're the same physical chips with half of their L2 cache disabled. Intel may well be cooking up a chip code-named Allendale with 2MB of L2 cache natively, but this is not that chip.
Another difference between the premium E6000 series (Conroe core) or (Allendale core) and the E4000 series (Allendale core) is the front side bus clock rating. The E4000 series are rated to run on a quad-pumped 200 MHz front side bus ("800 MT/s") while the E6000 series are rated to run on a quad-pumped 266 MHz front side bus ("1066 MT/s"). The E4000 series also lack support for Intel VT-x instructions.
The currently available Core 2 Duo E4300 only uses an Allendale core, released on January 21, 2007. The Allendale processors use a smaller mask with only 2 MiB of cache, thereby increasing the number of chips per wafer. Allendale processors are produced in the LGA775 form factor, on the 65 nm process node. It is unclear and a matter of contention whether the E6300 and E6400 models are still Conroe processors with half their L2 cache disabled or Allendale processors. It is possible that the E6300 and E6400 models can be both Allendale and Conroe, differentiated by the L2 and B2 steppings respectively.
Initial list price per processor in quantities of one thousand for the E4300 was US$163. A standard OEM price was US$175, or US$189 for a retail package. Price cuts were enacted on April 22, 2007, when the E4400 was released at $133 and the E4300 dropped to $113. Allendale processors with half their L2 cache disabled were released in mid-June 2007 under the Pentium Dual-Core brand name.
On July 22nd, 2007, an E4500 Allendale was launched, phasing out the E4300 model. This was accompanied by a price cut for the E4400 model.
Merom
Merom, the first mobile version of the Core 2, was officially released on July 27, 2006 but quietly began shipping to PC manufacturers in mid-July alongside Conroe.Merom is Intel's premier line of mobile processors, with largely the same features as Conroe, but with more emphasis on low power consumption to enhance notebook battery life. Merom-based Core 2 Duo provides 20% more performance yet maintains the same battery life as the Yonah-based Core Duo. Merom is the first Intel mobile processor to feature Intel 64 architecture.
The first version of Merom is "drop-in" compatible with Napa platform for Core Duo, requiring at most a motherboard BIOS update. It has a similar thermal envelope of 34 W and the same 667 MT/s FSB rate. Merom features 4 MiB L2 cache (budget T5xxx models have only 2 MiB L2 cache).
A second wave of Merom processors featuring an 800 MT/s FSB and using the new Socket P was launched on May 9, 2007. These chips are part of Santa Rosa platform. Low voltage versions were also released on May 9, 2007.
Merom (מרום) is the Hebrew word for a higher plane of existence or a level of heaven, BaMerom (במרום) means "in the heavens". The name was chosen by the Intel team in Haifa, Israel, who designed this processor.
See the Merom section of "List of Intel Core 2 microprocessors" for a list of Merom processors.
Kentsfield
The Kentsfield was the first Intel desktop quad core CPU branded as Core 2 (and Xeon for lower-end servers and workstations). The top-of-the-line Kentsfields were Core 2 Extreme models numbered QX6xx0, while the mainstream ones branded Core 2 Quad were numbered Q6xx0. All of them featured two 4 MB L2 caches. The mainstream Core 2 Quad Q6600, clocked at 2.4 GHz, was launched on January 8, 2007 at US$851 (reduced to US$530 on April 7, 2007, and to US$266 on July 22, 2007). July 22, 2007 marked the release of the next Core 2: Quad Q6700 and Extreme QX6850 Kentsfields at US$530 and US$999 respectively, and also price reduction of Core 2: Quad Q6600 and Extreme QX6800 Kentsfields to US$266 and US$999 respectively.
Kentsfield, like the Pentium D Presler, comprised two separate silicon dies. Each of Kentsfield's two dies was dual-core with the Core architecture, as did each die constituting alone every Core 2's dual-core only CPU. Hence, the max. power consumption (TDP) of the Kensfield (QX6800 - 130 watts, QX6700 - 130 W[19], Q6600 - 95 W[20]) was approx. double of its similarly clocked Core 2 Duo counterpart. For example, the QX6700 consisted of two E6700 chips connected together by a 1066 MT/s FSB on one MCM, resulting in lower costs but less bandwidth to the northbridge. The Kentsfield was one socket processor sitting in a LGA775 socket, as well as Core 2 Duo (AMD Quad FX consisted of two dual-core processors in two separate sockets on one motherboard with a 2 x 125 W= 250 W TDP).
A quad-core CPU, like the Kentsfield, processes very well with multi-threaded applications (typical for video editing, ray-tracing, or rendering), where its processing ability may approach double that of each of its halves comprising the equally clocked dual-core CPU. Similarly, Pentium D Presler had two dice in one package. A two-die CPU, however, can rarely double the processing ability of each of its constituent halves (e.g. the Kentsfield rarely doubles the ability of the Conroe), due to a loss of performance resulting from connecting them (i.e. sharing the narrow memory bandwidth, and operating system overhead of handling twice as many cores and threads).
Single or dual-threaded applications alone, including most games, do not benefit from the second pair of cores of a quad-core CPU over an equally clocked dual-core CPU. For example, with no increase in FSB speed and a mild reduction in processor frequency of the quad-core Extreme QX6700 over the older dual-core Extreme X6800, overall performance of the Kentsfield (QX6700) for those applications does not improve. Nevertheless, the simultaneous use of several processor-intensive single/dual-threaded applications on a quad-core CPU will generally lead to a dramatic overall performance increase over an equally clocked dual-core CPU. A quad-core CPU is useful also to run the both client and server processes of a game without noticeable lag in either thread, as each instance (up to four) could be running on a different core.
Kentsfield XE
The first Kentsfield, named Core 2 Extreme QX6700 (product code 80562) and clocked at 2.67 GHz, was released on November 2, 2006 at US$999. It was the first x86 quad-core processor ever, featured the Kentsfield XE core, and complemented the Core 2 Extreme X6800 dual-core processor based on the Conroe XE core. The CPUs with the Kentsfield XE core had the highest and unlocked multipliers like their Extreme predecessors. On April 8, 2007, a new top Kentsfield XE - the Core 2 Extreme QX6800 - was released within the 135 W TDP thermal envelope, and clocked at 2.93 GHz. It went to high end OEM-only systems at US$1,199.. On July 22, 2007, the new champ Core 2 Extreme QX6850 arrived, clocked at 3.0 GHz, with a faster 1.33 GHz FSB, and at US$999 - a typical price for a top Kentsfield XE CPU.
The formerly available Core 2 Extreme QX6700 was relaunched on July 22nd, 2007 as the Core 2 Quad Q6700, clocked at 2.66 GHz, but it consumes less power than QX6700. The price of the Q6600 has been dropped to US$266 on July 22nd, 2007.
Merom XE
Merom XE is a laptop CPU designed for ultra-high end laptops. It will be released in two models, the X7900 and the X7800. These will feature an 800 MHz FSB. The X7800 will be clocked at 2.6 GHz and will cost around $795.The processor will feature a 44WT TDP and will require the new Intel Centrino (Santa Rosa) platform. The X7900 will be clocked at 2.8 GHz, but its cost is unknown, but expect it to be more than 1000 dollars per CPU in packs of 1000.
Penryn
The successor to the Merom core currently used for the Core 2 Duo T5000/T7000 series mobile processors, code-named Penryn, will debut the 45 nanometer process that will also be used for the Conroe sequel, Wolfdale (see below). Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is expected to be Nehalem.
Important advances include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).
Penryn is intended to be paired with a new chipset, Bearlake, which will include an increase in bus speed (connection to the northbridge, etc.) for certain models to 1333 MT/s and will include support for DDR3 SDRAM; Intel believes that DDR3 is particularly useful in the power- and heat-constrained environments within mobile equipment.
Penryn will also be released in a quad-core version for desktop replacement notebooks.
Wolfdale and Yorkfield
Wolfdale will be the desktop version of Penryn, with two cores sharing 6 MiB of L2 cache and 1333 MHz FSB. Two Wolfdale dies on a single module will make up a Yorkfield chip, the successor to the Kentsfield processor. Each die will share 6 MiB L2 cache, for a total of 12 MiB, and this chip will also have a 1333 MHz FSB. These processors are expected to become available in late 2007 or early 2008, and the platform will support DDR3. At the Intel Developer Forum 2007 a Yorkfield processor was compared with a Kentsfield processor.
Even further, the latest known codenames for future processors (perhaps based on a new post-Core microarchitecture) are Nehalem and Sandy Bridge (formerly known as Gesher), and little is known about either of them. Nehalem will be a 45 nm process debuting in 2008, followed by a 32 nm shrink codenamed Westmere (Nehalem-C), and Sandy Bridge will be 32 nm with a new microarchitecture debuting in 2010, provided that Intel stays on target with its roadmap. n 2011, Intel will launch its first processor based on a 22 nm process. Based on Intel's cycle alternating new architectures and die shrinks every two years, it is currently assumed that this will be a shrink of Sandy Bridge.
System requirements
Motherboard compatibility
Conroe, Conroe XE and Allendale all use Socket LGA775; however, not every motherboard is compatible with these processors.
Supporting chipsets are:
Intel: 865PE/G/GV/G, 945P/PL/G/GZ/GC, P65P/G, 975X, P/G/Q965, Q963, 946GZ/PL; X3x, P3x, G3x, Q3x
NVIDIA: nForce4 Ultra/SLI X16 for Intel, nForce 570/590 SLI for Intel and nForce 650i Ultra/650i SLI/680i LT SLI/680i SLI.
VIA: P4M800, P4M800PRO, P4M890, P4M900, PT880 Pro/Ultra, PT890.
SiS: 662, 671, 671fx, 672, 672fx
ATI: Radeon Xpress 200 and CrossFire Xpress 3200 for Intel
Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above mentioned chipsets do not support Conroe. This is because all Conroe-based processors require a new power delivery feature set specified in Voltage Regulator-Down (VRD) 11.0. This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it is replacing. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated BIOS to recognize Conroe's FID (Frequency ID) and VID (Voltage ID).
DDR2 memory modules
Unlike the previous Pentium 4 and Pentium D design, the Core 2 technology sees a greater benefit from memory running synchronously with the Front Side Bus (FSB). This means that for the Conroe CPUs with FSB of 1066 MT/s, the ideal memory speed is PC2-4200. In some configurations, using PC2-5300 can actually decrease performance. Only when going to PC2-6400 is there a significant performance increase. While expensive DDR2 memory models with tighter timings do improve performance, the difference in real world games and applications is negligible.
Optimally, the memory bandwidth afforded should match the bandwidth of the FSB closely. The AGTL+ PSB used by all NetBurst processors as well as current and medium-term (pre-CSI) Core 2 processors provide a 64-bit data path. Current chipsets provide for two DDR or two DDR2 channels.
Matched processor and RAM ratings
Processor Model
DDR or DDR2 rating
Memory channels
Bandwidth
T5200
PC2-4200 (DDR2-533)
Single channel
4.267 GB/s
T5n00 and T7n00
PC2-5300 (DDR2-667)
Single channel
5.333 GB/s
Socket P T7n00
PC2-3200 (DDR2-400)
Dual channel
6.400 GB/s
PC2-6400 (DDR2-800)
Single channel
6.400 GB/s
E4n00/Pentium E21n0/Celeron 4n0
PC3200 (DDR400) or PC2-3200 (DDR2-400)
Dual channel
6.400 GB/s
PC2-6400 (DDR2-800)
Single channel
6.400 GB/s
E6n00, E6n20, X6n00, Q6n00 and QX6n00
PC2-4200 (DDR2-533)
Dual channel
8.533 GB/s
PC3-8500 (DDR3-1066)
Single channel
8.533 GB/s
E6n50
PC2-5300 (DDR2-667)
Dual channel
10.667 GB/s
PC3-10600 (DDR3-1333)
Single channel
10.667 GB/s
On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit significantly from using a PC2-8500 memory, which runs exactly twice as fast as the FSB; this is not an officially supported configuration, but a number of motherboards offer it.
The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both the Core 2 and DDR memory. When using DDR memory, performance may be reduced because of the lower available memory bandwidth.
Chip bugs
The Core 2 Memory management unit (MMU) does not operate as previously specified or implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data.
Among the issues noted:
Write-protect or non-execute bit for a page table entry is ignored.
Floating point instruction non-coherencies.
Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel errata AI65, AI79, AI43, AI39, AI90, AI99 are said to be particulary serious.
Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt [2] and DragonFly BSD's Matthew Dillon [3]. Taking a contrasting view was Linus Torvalds, calling the issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better.
Pricing
The pricing for various models of Core 2, in lots of 1000 to OEMs, at the time the processors were released, can be found in the list of Intel Core 2 microprocessors. It should be noted that these prices are what it costs system builders such as Dell and HP to stock Core 2 processors. There are no set MSRPs for Core 2 CPUs in the retail channel — prices at retailers are usually very close to the aforementioned prices, but are dependent on what the supplier is charging to stock these CPUs as well as supply and demand.
Nomenclature and abbreviations
With the release of the new Core 2 processor, the abbreviation C2 has come into common use, as well variants C2D (the present Core 2 Duo), and C2Q, C2E to refer to the Core 2 Quad and Core 2 Extreme processors respectively. C2QX stands for the Extreme-Editions of the Quad (QX6700 or QX6800).

Intel Core

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:29:00 +0000

By : http://en.wikipedia.org

Intel Core

CoreProduced:2006 -
Manufacturer:Intel
CPU Speeds:1.06 GHz to 2.33 GHz
FSB Speeds:533 MT/s to 667 MT/s
Process:(MOSFET channel length)0.065 µm
Instruction Set:x86
Microarchitecture:P6 (Pentium M) derivative
Socket:Socket M
Core Name:Yonah

The Core brand refers to Intel's 32-bit mobile dual-core x86 CPUs derived from the Pentium M branded processor's microarchitecture (an interim step between the Intel P6 and Core microarchitecture), which emerged in parallel with the NetBurst (Intel P68) microarchitecture of the Pentium 4 brand, and was a precursor of the 64-bit Core microarchitecture. The Core comprised two branches: the Duo (dual-core) and Solo (Duo with one disabled core), which replaced the Pentium M brand of single-core mobile processor.
The Core brand was launched on January 5, 2006 by the release of the 32-bit Yonah core CPU - Intel's first dual-core mobile (low-power) processor. Its dual-core closely resembled two interconnected Pentium M branded CPUs packaged, as a single die (piece) silicon chip (IC). Hence, the 32-bit microarchitecture of Core branded CPUs - contrary to its name - had more in common with Pentium M branded CPUs than with the following 64-bit Core microarchitecture of Core 2 branded CPUs. Despite a major rebranding effort by Intel starting January 2006, some computers with the Yonah core continued to be marked as Pentium M.
In 2007, Intel began branding the Yonah core CPUs as Pentium Dual-Core intended for lower-end mobile only computers, unlike the 64-bit Core microarchitecture CPUs branded as Intel Core 2 (for higher-end computers) and also as Pentium Dual-Core (for lower-end desktops only). In short, the Core brand refers to processors with the "mobile" derivative of 32-bit Intel P6 microarchitecture (preceding the Core microarchitecture), whereas the Intel Core 2 brand refers to CPUs with the 64-bit Core microarchitecture.
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Yonah
Yonah was the code name for (the core of) Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer performance decreased slightly due to higher latency cache. Additionally, Yonah includes support for the NX bit.
The Intel Core Duo brand refers to the world's first low-power (less than 25 watts) Yonah dual-core microprocessor, with the previous low being AMD's Opteron 260 and 860 HE at 55 watts. Core Duo was released on 5 January 2006, with the other components of the Napa platform. It was the first Intel processor to be used in Apple Macintosh products (although the Apple Developer Transition Kit machines, non-production units distributed to some developers, used Pentium 4 processors).[1]
Contrary to early reports, the Intel Core Duo supports Intel VT x86 virtualization technology, except in the T2300E model and proprietary T2050/T2150/T2250 mounted by OEMs (cf. the Intel Centrino Duo Mobile Technology Performance Brief and Intel's Processor Number Feature Table). The Intel Pentium Dual Core processors may or may not have this feature. However, it seems some vendors, like HP, have chosen to disable this feature,with others making it available through a BIOS option.
Intel 64 (Intel's x86-64 implementation) is not supported by Yonah. However, Intel 64 support is integrated in Yonah's successor, the mobile version of Core 2, code-named Merom.
Intel Core Duo (product code 80539) consists of two cores on one die, a 2 MiB L2 cache shared by both cores, and an arbiter bus that controls both L2 cache and FSB access. Upcoming steppings of Core Duo processors will also include the ability to disable one core to conserve power.
Intel Core Solo (product code 80538) uses the same two-core die as the Core Duo, but features only one active core. This allows Intel to sell dies that have a manufacturing defect in one but not both of the cores. Depending on demand, Intel may also simply disable one of the cores to sell the chip at the Core Solo price -- this requires less effort than launching and maintaining a separate line of CPUs that physically only have one core. Intel used the same strategy previously with the 486 CPU in which early 486SX CPUs were in fact manufactured as 486DX CPUs but the FPU failed quality control and the connection was physically severed.
Technical specifications
Core Duo contains 151 million transistors, including the shared 2 MiB L2 cache. Yonah's execution core contains a 12 stage pipeline, forecast to eventually be able to run at a maximum frequency of 2.33–2.50 GHz. The communication between the L2 cache and both execution cores is handled by an arbitration bus unit, which reduces cache coherency traffic over the FSB, at the expense of raising the core-to-L2 latency from 10 clock cycles (in the Dothan Pentium M) to 14 clock cycles. The increase in clock frequency offsets the impact of the increased clock cycle latency. The power management components of the core features improved grained thermal control, as well as independent scaling of power between the two cores, resulting in very efficient management of power.
Core processors communicate with the system chipset over a 667 MT/s front side bus (FSB), up from 533 MT/s used by the fastest Pentium M. New T2050 & T2250 have also appeared in OEM systems as a low-cost option with a lower 533 MHz FSB and no Virtualization Technology. No official data on these processors is yet available from Intel.
Yonah is supported by the 945GM, 945PM, 945GT, 965GM, 965PM, and 965GT system chipsets. Core Duo and Core Solo use Socket M, but due to pin arrangement and new chipset functions are not compatible with any previous Pentium M motherboard.
The T2300E was later introduced as a replacement for the T2300. It has dropped support for Virtualization Technology. Early Intel specifications mistakenly claimed a halving of the Thermal Design Power.
Advantages and shortcomings
The Duo version of Intel Core (Yonah) includes two computational cores, providing performance per watt almost as good as any previous single core Intel processors. In battery-operated devices such as notebook computers, this translates to getting as much total work done per battery charge as with older computers, although the same total work may be done faster. When parallel computations and multiprocessing are able to utilize both cores, the Intel Core Duo delivers much higher peak speed compared to the single-core chips previously available for mobile devices.
The shortcomings of Intel Core (Yonah) are:
The same or even slightly worse "performance per watt" in single threaded or non-parallel applications compared to its predecessor.
32-bit processes only. 64-bit processes are not supported. (See the Intel Core 2 successor, which is a 64-bit processor.)
High memory latency due to the lack of on-die memory controller (further aggravated by system-chipset's use of DDR-II RAM)
Limited Floating Point Unit (multiply/divide) throughput for non-parallel computations or single-threaded processes; this is due to the smaller number of floating-point units in each CPU core compared to some previous designs.
The Yonah platform requires all main-memory transactions to pass through the Northbridge of the chipset, increasing latency compared to the AMD's Turion platform. (Intel's Non-Core2 Based Pentium processors have this same performance bottleneck.) However, application tests showed Intel Core's L2-cache system is quite effective at overcoming main-memory latency; despite this limitation, Intel Core (Yonah) sometimes managed to outperform AMD's Turion.
The Sossaman processor for servers, which is based on Yonah, also lacks Intel 64-bit support. For the server market, this had more severe consequences, since all major server operating systems already supported x86-64, and Microsoft Exchange Server 2007 even requires a 64-bit processor to run.
According to Mobile Roadmaps from 2005, Intel's Yonah project originally focused more on reducing the power consumption of its p6+ Pentium M-based processor and aimed to reduce it by 50% for Intel Core (Yonah). Intel continued recommending Pentium NetBurst-based processors for mobile high performance applications (although these were less power efficient) until the Yonah project succeeded in extracting higher performance from its lower-power-consumption design. The Intel Core Duo's inclusion of two highly-efficient cores on one chip can provide better performance than a Pentium NetBurst core, but with much better power-efficiency. Intel no longer recommends its Pentium Netburst-based processors for mobile devices.
On July 27, 2006, Intel's Core 2 processors were released. By 2Q 2007, Intel expected 90% of its laptop CPU production to be converted to the heavily-revised Intel Core 2 processors. The original Intel Core (Yonah) product had an unusually short lifespan as a stepping stone to the 64-bit Intel Core 2.
Non-Core Yonah variants
There were two variants and one derivative of the Yonah, which did not bear the "Intel Core" brand name. A dual-core (server) derivative, code-named Sossaman, was released on 14 March 2006 as the Xeon (branded) LV (low-voltage). The Sossaman differed from the Yonah only in its support for dual-socket configurations (two CPUs - i.e. four cores - on board, like AMD Quad FX), and implementation of 36-bit memory addressing (PAE mode). A single-core variant, code-named Yonah-1024, was released as the Celeron (branded) M 400 series CPUs. It was largely identical to the Core Solo branded Yonah, except that it only had half the L2 cache and did not support SpeedStep. Another dual-core variant of the Core Duo branded Yonah was released as the Intel Pentium Dual-Core branded T2060, T2080, and T2130 mobile CPUs.
The successor to Core is the mobile version of the Intel Core 2 line of processors using cores based upon the Intel Core microarchitecture, released on July 27, 2006. The release of the mobile version of Intel Core 2 marks the reunification of Intel's desktop and mobile product lines as Core 2 processors were released for desktops and notebooks, unlike the first Intel Core CPUs that were targeted only for notebooks (although some small form factor and all-in-one desktops, like the iMac, also used Core processors).
Unlike the Intel Core, Intel Core 2 is a 64-bit processor, supporting Intel 64. Another difference between the original Core Duo and the new Core 2 Duo is an increase in the amount of Level 2 cache. The new Core 2 Duo has doubled the amount of on-board cache to 4 MiB. Both chips have a 65 nm process technology architecture and support a 667-1333 MHz front-side-bus (FSB).

pentium D and Pentium EE

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:26:00 +0000

By : http://en.wikipedia.org
Pentium D

Pentium D

Produced:
From 2005 to 2007
Manufacturer:Intel
CPU Speeds:2.66 GHz to 3.73 GHz
FSB Speeds:533 MT/s to 800 MT/s
Process:(MOSFET channel length)0.09 µm to 0.065 µm
Instruction Set:MMX, SSE, SSE2, SSE3, x86-64
Microarchitecture:NetBurst
Socket:LGA 775
Cores:
· Smithfield
· Presler
The Pentium D brand refers to only two dual-core 64-bit processors (with NetBurst microarchitecture), which production ceased on March 9, 2007. The first one, codenamed Smithfield, was released by Intel on May 25, 2005 and established the 8xx-series produced using a 90 nm process. The Smithfield comprised of two single-core dice in one package (called a Multi-Chip Module). Nine months later, Intel introduced its successor, codenamed Presler[2] of the 9xx-series, produced using a "65 nm process, but without offering significant upgrades in design(i.e. "by fitting two single core Cedar Mill chips into one LGA package"[4]) still resulting in a relatively high power consumption [5].
By 2005, the processors hit the clock speed limit, due to thermal and power barriers at 4 GHz, with the Presler reaching a 130 W TDP (a high TDP requires many noisy cooling fans or a more expensive noiseless cooling system). Dual-core CPUs on a single die offered a solution to this problem. So, the dual die Presler became the last processor branded Pentium D also ending the NetBurst microarchitecture.
The dual-core Pentium D branded processors provided a significant performance improvement over a single-core only CPUs, when processing applications that have been written specifically for multiple CPUs or cores. The benefiting programs included most 3D rendering and video encoding (incl. compressing) applications (software). As of 2006, most business applications and games used only a single thread, which delivered largely the same performance whether run alone on the Pentium D or older Pentium 4 branded CPU at the same clock rate. However, applications rarely run alone on computers under Microsoft Windows, Linux, BSD-family, operating systems. In such multitasking enviroments, when an antivirus software is runing in the background of other program, or where several CPU-intensive application software are running simultaneously, each core of a Pentium D branded processor can handle a different application, improving the overall performance over its single-core Pentium 4 counterpart.
Smithfield
The Smithfield was the first x86 dual-core microprocessor intended for desktop computers. Intel first launched Smithfield on April 16, 2005 as the 3.2 GHz Hyper-threading enabled Pentium Extreme Edition 840. On May 26, 2005, Intel launched the mainstream Pentium D branded processor lineup with initial clock speeds of 2.8, 3.0, and 3.2 GHz with model numbers of 820, 830, and 840 respectively. In March 2006, Intel launched the last Smithfield processor, the entry-level Pentium D 805, clocked at 2.66 GHz with a 533 MT/s bus. The relatively cheap 805 was found to be highly capable for overclocking; running the processor in a stable state at over 3.5 GHz was easy and possible just with a standard air cooling. Running it at over 4 GHz was possible with water cooling, and at this stage the 805 outperformed the top-of-the-line processors (May 2006) from both major CPU manufacturers (the AMD Athlon 64 FX-60 and Intel Pentium Extreme Edition 965) in many benchmarks
The 805 and 820 models were rated at a 95 watt TDP. All other models were rated at 130 watts - a 37% power consumption increase.
The Smithfield was made of two 90 nm-process cores found also in Pentium 4 branded Prescotts. Each core was on a single die with 1 MB of Level 2 (L2) cache. Two separate dice (cores) next to each other in one package constituted the Smithfield. While it was capable of Hyper-threading, that feature was disabled in all Pentium D 8xx-series Smithfields, while only the Pentium Extreme Edition 840 Smithfield had it distinctively on. The Smithfield did not support VT - Intel's virtualization feature formerly called Vanderpool.
All Pentium D processors supported Intel 64 (EM64T), XD Bit, and fitted the LGA775 form factor. The only motherboards guaranteed to work with the Pentium D (and Extreme Edition) branded CPUs were those based on the 945-, 955-, and 975-series Intel chipsets, as well as the nForce 4 SLI Intel Edition and ATI Radeon Xpress. The Pentium D 820 did not work with the nForce 4 SLI Intel Edition chipset due to some power design issues, though they were rectified in the X16 version. The 915- and 925-series chipsets did not work at all with the Smithfields, as they did not support more than one core (to prevent motherboard manufacturers from using them for Xeon branded motherboards, as it happened with the 875P chipset). The 865- and 875-series chipsets supported multiprocessing. Motherboards with them might be Pentium D compatible with an updated BIOS.
A week after its launch, Intel officially denied a report in Computerworld Today Australia that the Pentium D branded CPUs included "secret" digital rights management features their hardware that could be utilized by Microsoft Windows and other operating systems, but was not publicly disclosed. While Intel admitted that there were some DRM technologies in the 945- and 955-series chipsets, it stated that the extent of the technologies was exaggerated, and that the technologies in question had been present in Intel's chipsets since the 875P.
Presler
The newest generation of Pentium D branded processors was the Presler identified by the product code 80553, and made of two 54 nm-process cores found also in Pentium 4 branded Cedar Mill CPUs. The Presler single package also comprised two single-core dice next to each other (like the Smithfield) increasing its processing capability over single-core CPUs branded Pentium 4. The Presler was supported by the same chipsets as the Smithfield. It was produced using 65 nm technology similar to the Yonah. The Presler communicated with the system using an 800 MT/s FSB, and its two cores communicated also using the FSB, just as in the Smithfield. The Presler also included VT (Virtualization Technology, aka Vanderpool, although limited to the 9x0 models, and not in the 9x5 models), Intel 64, XD bit and EIST (Enhanced Intel SpeedStep Technology)[*]. The Presler was released in the 1st quarter of 2006 with a 2x2 MB Level 2 cache. Its models included 915, 920, 925, 930, 935, 940, 945, 950, 955, 960 and 965 (with a respective 2.8, 2.8, 3.0, 3,0, 3.2, 3.2, 3.4, 3.4, 3.46, 3.6 and 3.73 GHz clock frequency).
The Presler for models 915, 920, 925, 930, 940, 950 stepping C1, and 915, 925, 935, 945, 950, 960 stepping D0 were rated at a 95 watt TDP. All other models were rated at 130 watts - a 37% increase in power consumption[9].
[*] - The first batch of Presler processors (revision B1) had the EIST feature turned off by a microcode update because of stability issues. That affected only its power consumption, when idle, and thermal dissipation. Chips with working EIST started shipping in Q2 2006. They had a different S-Spec number which can be found in Intel errata documentation, or at here
Pentium Extreme Edition
Smithfield

Pentium Extreme Edition was introduced at the Spring 2005 Intel Developers Forum, not to be confused with the "Pentium 4 Extreme Edition" (an earlier, single-core processor occupying the same niche). The processor was based on the dual-core Pentium D branded Smithfield, but with Hyper-threading enabled, thus any operating system saw 4 logical processors (2 physical x 2 virtual cores). It also had an unlocked multiplier to allow overclocking. It was initially released as Intel Pentium Extreme Edition 840 at 3.20 GHz, in early 2005, at a price point of $999.99 (OEM version) or $1,200 (Retail). The only chipsets that worked with the Extreme Edition 840 were the Intel's 955X, NVIDIA's nForce4 SLI Intel Edition, and ATi Radeon Xpress 200. Using a Pentium Extreme Edition branded CPU with an Intel 945-series chipset will disable Hyper-threading effectively turning the processor into a Pentium D branded equivalent.
Presler
The Pentium Extreme Edition based on the dual-core Pentium D branded Presler was introduced as the 955 model, at 3.46 GHz, and used a 1066 MT/s FSB compared to the 800 MT/s in the non-extreme edition. A second version, the 965 at 3.73 GHz followed in March 2006. Many overclockers, however, have been able to overclock the core to 4.26 GHz using air cooling simply by raising the unlocked CPU multiplier.
The Presler Extreme Edition would only run combined with the Intel 975X chipset. The i975X featured the ICH7R southbridge and supported all Socket T (LGA775) Pentium 4, Pentium D and Pentium Extreme Edition branded processors.
The Pentium D brand was succeeded on July 27, 2006 by the Core 2 branded line of microprocessors with the Core architecture released as dual- and quad-core CPUs branded Duo, Quad, and Extreme.
Implementation
In a single-processor scenario, the CPU-to-north bridge link is point-to-point and the only real requirement is that it is fast enough to keep the CPU fed with data from memory.
When assessing the Pentium D, it is important to note that it is essentially two CPUs in the same package and that it will face the same bus contention issues as a pair of Xeons prior to the Dual Independent Bus architecture introduced with the Dual-Core Dempsey Xeons. To use a crude analogy one could say that instead of using a single cable between CPU and north bridge, one must use a Y-splitter. Leaving aside advanced issues such as cache coherency, each core can only use half of the 800 MT/s FSB when under heavy load.

Pentium Dual Core

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:21:00 +0000

By : http://en.wikipedia.org/

Intel Pentium Dual-Core

The Pentium Dual-Core brand refers in only 2007to lower-end x86-architecture microprocessors from Intel. They were based on either the 32-bit Yonah or 64-bit Allendale processors (with very different microarchitectures) targeted at mobile or desktop computers respectively.
The first processors using the brand appeared in notebook computers in early 2007. Those processors, named Pentium T2060, T2080, and T2130, had the 32-bit Pentium M-derived Yonah core, and closely resembled the Core Duo T2050 processor with the exception of having 1 MB L2 cache instead of 2 MB. All three of them had a 533 MHz FSB connecting CPU with memory. According to CNet Asia, "Intel developed the Pentium Dual-Core at the request of laptop manufacturers.
Subsequently, on June 3, 2007, Intel released the desktop Pentium Dual-Core branded processors known as the Pentium E2140 and E2160. Those processors support the Intel64 extensions, being based on the newer, 64-bit Allendale core with Core microarchitecture. These closely resembled the Core 2 Duo E4300 processor with the exception of having 1 MB L2 cache instead of 2 MB. Both of them had an 800 MHz FSB. They targeted the budget market above the Intel Celeron (Conroe-L single-core series) processors featuring only 512 kB of L2 cache. Such step marked a change in the Pentium brand, relegating it to the budget segment rather than its former position as the mainstream/premium brand.
In 2006, Intel announced a plan to return the Pentium brand from retirement to the market, as a moniker of low-cost Core architecture processors based on single-core Conroe-L, but with 1 MB cache. The numbers for those planned Pentiums were similar to the numbers of the latter Pentium Dual-Core CPUs, but with the first digit "1", instead of "2", suggesting their single-core functionallity. Apparently, a single-core Conroe-L with 1 MB cache was not strong enough to distinguish the planned Pentiums from other planned Celerons, so it was substituted by dual-core CPUs bringing the "Dual-Core" add-on to the "Pentium" moniker.

pentium 4

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:15:00 +0000

by : http://en.wikipedia.org/wiki/Pentium_4"

Intel Pentium 4

Produced:From 2000 to 2007
Manufacturer:Intel
CPU Speeds:1.3 GHz to 3.8 GHz
FSB Speeds:400 MT/s to 1066 MT/s
Process:(MOSFET channel length)0.18 µm to 0.065 µm
Instruction Set:x86 (i386), x86-64
Microarchitecture:NetBurst
Sockets:
· Socket 423
· Socket 478
· LGA 775
Cores:
· Willamette
· Northwood
· Prescott
· Cedar Mill

The Pentium 4 brand refers to Intel's mainstream desktop and mobile single-core CPUs (released in 2000) with the seventh-generation NetBurst architecture, which was the company's first all-new design since the Intel P6 of the Pentium Pro branded CPUs of 1995. The NetBurst's 32-bit x86 instruction set was extended by the 64-bit x86-64 in 2004. The NetBurst differed from the Intel P6 - of CPUs branded Pentium II, Pentium III, etc. - by featuring a very deep instruction pipeline to achieve very high frequencies (up to 4 GHz) limited only by max. power consumption reaching up to 100 W.
Pentium 4 branded CPUs introduced the SSE2 and SSE3 instruction sets to accelerate calculations, transactions, media processing, 3D graphics, and games. They also integrated Hyper-Threading (HT), a feature to make one physical CPU working as two logical and virtual CPUs, and more. The Intel's Pentium 4 branded flagship also came in a low-end version branded Celeron (often referred to as Celeron 4), and a high-end derivative branded Xeon intended for servers and workstations. In 2005, the Pentium 4 was superseded by the Pentium D and Pentium Extreme Edition brands of dual-core CPUs.

In benchmark evaluations, the advantages of the NetBurst architecture were not clear. With carefully optimized application code, the first P4 did outperform Intel's fastest Pentium III, as expected. But in legacy applications with many branching or x87 floating-point instructions, the P4 would merely match or even fall behind its predecessor. Furthermore, the NetBurst architecture dissipated more heat than any previous Intel or AMD processor.
As a result, the Pentium 4's introduction was met with mixed reviews: Developers disliked the Pentium 4, as it posed a new set of code optimization rules. For example, in mathematical applications AMD's much lower-clocked Athlon easily outperformed the Pentium 4, which would only catch up if software were re-compiled with SSE2 support. Computer-savvy buyers avoided Pentium 4 PCs due to their price-premium and questionable benefit. In terms of product marketing, the Pentium 4's singular emphasis on clock frequency (above all else) made it a marketer's dream. The result of this was that the NetBurst architecture was often referred to as a marchitecture by various computing websites and publications during the life of the Pentium 4.
The two classical metrics of CPU performance are IPC (instructions per cycle) and clock-frequency. While IPC is difficult to quantify (due to dependence on the benchmark application's instruction mix), clock-frequency is a simple measurement yielding a single absolute number. Unsophisticated buyers would simply associate the highest clock-rating with the best product, and the Pentium 4 was the undisputed Megahertz champion. As AMD was unable to compete by these rules, it countered Intel's marketing advantage with the 'Megahertz myth campaign.' AMD product marketing used a "PR-rating" system, which assigned a merit value based on relative-performance to a baseline machine.
At the launch of the P4, Intel stated NetBurst was expected to scale to 10 GHz (over several fabrication process generations). However, the NetBurst architecture ultimately hit a frequency ceiling far below expectation—the fastest retail Pentium 4 never exceeded 4 GHz. Intel had not anticipated a rapid upward scaling of transistor power leakage that began to occur as the chip reached the 90 nm process node and smaller. This new power leakage phenomenon, along with the standard thermal output, created cooling and clock scaling problems as clock speeds increased. Reacting to these unexpected obstacles, Intel attempted several core redesigns ("Prescott" most notably) and explored new manufacturing technologies. Nothing solved their problems though and in 2005-6 Intel shifted development away from NetBurst to focus on the cooler running Pentium M architecture. In March 2006, Intel announced the Intel Core microarchitecture, which puts greater emphasis on energy efficiency and performance per clock. The final NetBurst-derived products were released in 2006, with all subsequent product families switching exclusively to the Intel Core microarchitecture.
Processor cores
The Pentium 4 has an IHS (Integrated Heat Spreader) that prevents the CPU core from accidentally getting damaged when mounting and unmounting cooling solutions. Prior to the IHS, a CPU shim was sometimes used by people worried about damaging the core. Overclockers sometimes removed the IHS on Willamette and Northwood cores to allow for more direct heat transfer. However, in revisions since Prescott the IHS is directly welded to the processor core, meaning that the IHS cannot be removed without irreparably damaging the chip.
Willamette
Willamette, the first Pentium 4, suffered long delays in the design process. The project was originally started in 1998, when Intel saw the Pentium II as their permanent line. At that time, the Willamette core was only expected to operate at frequencies of around 1 GHz. However, development delays saw the introduction of the Pentium III and the radical differences in these architectures meant Intel could not market Willamette as a Pentium III. Thus, it was named Pentium 4, ending Intel's Roman-numeral nomenclature system.
In November 2000, Intel released the Willamette Pentium 4 at speeds of 1.4 and 1.5 GHz. Most industry experts regarded the initial release as a stopgap product, introduced before it was truly ready. According to these experts, the Willamette was released because the competing AMD Athlon Thunderbird was at that time outperforming the elderly Pentium III, and further improvements to the P-III were not yet possible. The cores were produced using a 0.18 micrometer (180 nm) process and initially used Socket 423 on motherboards, with later revisions moving to Socket 478. These variants were identified by the Intel product codes 80528 and 80531 respectively.
On the test bench, the Willamette was somewhat disappointing to analysts in that not only was it unable to outperform the Athlon and the highest-clocked Pentium IIIs in all testing situations, it was clearly not superior to even the low-end AMD Duron. Although introduced at a price of US$819 (in 1000 unit quantities), it sold at a modest but respectable rate, handicapped somewhat by the requirement of relatively expensive Rambus Dynamic RAM (RDRAM). The Pentium III remained Intel's top selling chip, with the Athlon also selling slightly better than the Pentium 4.
In January 2001, a still slower 1.3 GHz model was added to the range, but over the next twelve months, Intel gradually started pegging back AMD's lead. April 2001 brought the 1.7 GHz P4, the first one to provide performance clearly superior to the old Pentium III. July saw 1.6 and 1.8 GHz models and in August 2001, Intel released 1.9 and 2.0 GHz Pentium 4s. In the same month, they released a new chipset that supported much cheaper PC133 SDRAM. While use of this RAM was much slower than RDRAM, the fact that PC133 was much cheaper caused the Pentium 4's sales to massively improve, displacing the Pentium III virtually overnight to become the top-selling processor on the market.
The 2.0 GHz was the first P4 to provide a serious challenge to the rival Athlon Thunderbird, which until then had been unquestionably the fastest x86 CPU on the market. Many observers concluded that the Thunderbird was still faster overall, but the performance gap was sufficiently narrow that it was not unreasonable for partisans of either camp to claim superiority. For Intel, this was a very significant achievement. The firm had held the x86 CPU performance crown for nearly 16 years straight, with only two brief exceptions prior to the release of the AMD Athlon.
The Willamette code name is derived from the Willamette River and Willamette Valley region of Oregon, where a large number of Intel manufacturing facilities are located.
Northwood
In October 2001, the Athlon XP regained a clear lead for AMD, but in January 2002, Intel released Pentium 4s with their new Northwood core at 1.6, 1.8, 2.0 and 2.2 GHz. Northwood (product code 80532) combined an increase in the secondary cache size from 256 KiB to 512 KiB (increasing the transistor count to 55 million, up from 42 million) with a transition to a new 130 nm (0.13 micrometer) fabrication process. By making the chip out of smaller transistors, chips can run at higher clocks or at the same speed while producing less heat. Unfortunately for many consumers, the new core also made upgrades impossible due to the requirement of a new socket (Socket 478), although later adapters were made for Socket 423 to use the Northwood processors.
With Northwood, the P4 came of age. The battle for performance leadership remained competitive (as AMD introduced faster versions of the Athlon XP) but most observers agreed that the fastest Northwood P4 was usually a fraction ahead of its rival.This was particularly so in the summer of 2002, when AMD's changeover to a 130 nm production process was delayed and the P4s in the 2.4 to 2.8 GHz range were clearly the fastest chips on the market.
A 2.4 GHz P4 was released in April 2002, and the bus speed increased from 400 MT/s to 533 MT/s for a 2.26 GHz, 2.4 GHz, and 2.53 GHz part in May, 2.6 and 2.8 GHz parts in August, and a 3.06 GHz Pentium 4 arrived in November.
The 3.06 GHz processor supported Hyper-Threading (first appeared in Xeon), enabling multiple threads to be run together by duplicating some parts of the processor in order to let the operating system believe that there are two logical processors. HyperThreading was present in all Northwood CPUs, but was disabled in the core in all but the 3.06 GHz model.
In April 2003, Intel launched new 800 MT/s FSB variants, ranging from 2.4 to 3.0 GHz. The key difference on these new versions was that they all supported Hyper-Threading, and ran their system buses at 800 MT/s. This was supposedly to compete better with AMD's Hammer line of processors. However, only Opteron was launched, and motherboard manufactures initially refused to build Opteron-based motherboards with an AGP controller, thus preventing the Opteron from encroaching on the Pentium 4's territory. AMD did boost the Athlon XP's bus speed from 333 MT/s to 400 MT/s, but it wasn't enough to hold off the new 3.0 GHz P4– and the FSB wasn't the problem; the 333 MT/s to 400 MT/s transition yielded little to no performance increase. A 3.2 GHz variant was launched in June and a final 3.4 GHz version was launched in early 2004.
Overclocking early stepping Northwood cores yielded a startling phenomenon. When VCore was increased past 1.7 V, the processor would slowly become more unstable over time, before dying and becoming totally unusable. This is believed to have been caused by the physical phenomenon known as Electromigration, where the internal pathways of the CPU become degraded over time due to excessive electron energy. This was also known as Sudden Northwood Death Syndrome.

Mobile Pentium 4
The Mobile Intel Pentium 4 Processor was released to address the problem of putting a full Pentium 4 desktop chip into a laptop, which some manufacturers were doing. The Mobile P4 still used 70 W of power, which let it bridge the gap between the full Pentium 4 (using about 82 W), and the Mobile Pentium 4 M (using about 35 W).
Mobile Pentium 4 M
Also based on the Northwood core, the Mobile Intel Pentium 4 Processor - M was released on April 23, 2002 [3] and included Intel's SpeedStep and Deeper Sleep technologies, but not Hyper-Threading. Intel's naming conventions made it difficult at the time of the processor's release to identify the processor model.There was the Pentium III mobile chip (or the PIII-M), the Mobile Pentium 4 M (or the P4-M), the Mobile Pentium 4 (or the Mobile P4), and then just the Pentium M which itself was based on the Pentium III.
Gallatin (Extreme Edition)
In September 2003, at the Intel Developer Forum, the Pentium 4 Extreme Edition (P4EE) was announced, just over a week before the launch of Athlon 64, and Athlon 64 FX (AMD64 FX). The design was mostly identical to Pentium 4 (to the extent that it would run in the same motherboards), but differed by an added 2 MiB of Level 3 cache. It shared the same Gallatin core as the Xeon MP, though in a Socket 478 form factor (as opposed to Socket 603 for the Xeon MP) and with an 800 MT/s bus, twice as fast as that of the Xeon MP. An LGA 775 version is also available.
While Intel maintained that the Extreme Edition was aimed at gamers, some viewed it as an attempt to steal the Athlon 64's launch thunder, nicknaming it the "Emergency Edition". Many condemned Intel for cannibalizing the Xeon line, but because of this, no such complaints were aimed at AMD, who retaliated by doing the same with their Athlon 64 FX.
The effect of the added cache was somewhat variable. In office applications, the Extreme Edition was generally a bit slower than the Northwood, owing to higher latency added by the L3 cache. Some games benefited from the added cache, particularly those based on the Quake III and Unreal engines. However, the area which improved the most was multimedia encoding, which was not only faster than the Pentium 4, but also both Athlon 64s.
A slight performance increase was achieved in late 2004 by increasing the bus speed from 800 MT/s to 1066 MT/s. Only one Gallatin-based chip at 3.46 GHz was released before the Extreme Edition was migrated to the Prescott core. The new 3.73 GHz Extreme Edition had the same features as a 6x0-sequence Prescott 2M, but with a 1066 MT/s bus. In practice however, the 3.73 GHz Extreme Edition almost always proved to be slower than the 3.46 GHz version.
The 'Pentium 4 Extreme Edition' should not be confused with a similarly-named later model, the 'Pentium Extreme Edition', which is based on the dual-core Pentium D.
Prescott
On February 1, 2004, Intel introduced a new core codenamed "Prescott." The core uses a 90 nm process for the first time, and "[it] is also a major reworking of the Pentium 4's microarchitecture - major enough that some analysts are surprised Intel didn't opt to call this processor the Pentium 5".[4] Although a Prescott clocked at the same rate as a Northwood, benchmarks show that a Northwood performed slightly better than a Prescott in gaming applications. However, with video editing and other multimedia software, the Prescott's extra cache and SSE3 instructions give it a clear clock-for-clock advantage over the Northwood. The Prescott architecture allows it to be easily set at higher clock-rates. (See Overclocking.) 3.8 GHz was the fastest Prescott-based processor ever mass-produced.
Upon release, the Prescott turned out to generate approximately 40% more heat clock-for-clock than the Northwood, and almost every review of it was negative, earning it the soubriquet PresHot. A shift in socket type (from Socket 478 to LGA775) was expected to reduce the heat to more acceptable levels, but in fact proved to have the opposite effect, with power requirements increasing by a further 10%. However, the LGA775 reference cooler and mounting system were somewhat better designs, so average temperatures were slightly lowered. Subsequent revisions to the processor by Intel engineers were expected to reduce average temperatures, but this never happened outside of the lowest speed grades. Prescott Pentium 4s were given the product codes 80546 (Socket 478) and 80547 (LGA775).
Finally, the thermal problems were so severe, Intel decided to abandon the Prescott architecture altogether, and attempts to roll out a 4 GHz part were abandoned, as a waste of internal resources. Also of concern was the fact that a review showed that in games, it took a 5.2 GHz Prescott core to soundly beat the performance of an Athlon FX-55 that clocked at 2.6 GHz.[5] Considering Intel boasted at launch the Pentium 4 architecture was intended to support up to 10 GHz operation, this can be seen as one of the most significant, certainly most public, engineering shortfalls in Intel’s history. This also meant that while Northwood ultimately achieved clockspeeds 70% higher than Willamette did, Prescott only managed a 12% rise over Northwood.
The Pentium M instead became the internal reference layout for Intel’s design teams, and P4 development was essentially abandoned. To this extent, the little-funded Israeli design team that produced the Pentium M core took over the much larger desktop development project.
Why the Prescott ended up in such a disaster can be attributed to internal politics at Intel as much as to poor design. The engineering group was not able to meet the marketing departments desire for ever higher clock speeds, to differentiate their products from AMD. The processor design was not able to clock at the higher speeds required for increased performance and the power consumption was simply untenable. The engineering group kept this information from people in other departments at Intel until it was too late. The termination of the P4 project, when it finally came, had consequences for many members of the management team at the desktop division, but not so much in the engineering or manufacturing groups.
Originally, two Prescott lines were released: the E-series, with an 800 MT/s FSB and Hyper-Threading support, and the low-end A-series, with a 533 MT/s FSB and Hyper-Threading disabled. Initially there were big problems with people who installed Windows XP Service Pack 2 on systems with these processors as an incompatibility with the BIOS, processor and SP2 coding led to systems unable to boot. Microsoft and Intel worked on a solution; Users with this problem can find out how to install SP2 on a Prescott machine.
LGA775 Prescotts use a rating system, labeling them as the 5xx series (Celerons are the 3xx series, while Pentium Ms are the 7xx series). The LGA775 version of the E-series uses model numbers 5x0 (520-560), and the LGA775 version of the A-series uses model numbers 5x5 and 5x9 (505-519). The fastest, the 570J and 571, is clocked at 3.8 GHz. Plans for 4 GHz processors were axed by Intel in favor of dual core processors, although some European retailers claim to be selling a Pentium 4 580, clocked at 4 GHz.
The 5x0J series (and its low-end equivalent, the 5x5J and 5x9J series) introduced the XD Bit (eXecute Disable) or Execute Disabled Bit [6] to Intel's line of processors. This technology, first introduced to the x86 line by AMD and called NX (No eXecute), can help prevent certain types of malicious code from exploiting a buffer overflow to get executed.
Intel also released a series of Prescotts supporting Intel 64, Intel's implementation of the x86-64 64-bit extensions to the x86 architecture. These were originally released as the F-series, and only sold to OEMs, but they were later renamed to the 5x1 series and sold to the general public. Two low-end Intel64-enabled Prescotts, based on the 5x5/5x9 series, were also released with model numbers 506 and 516.
5x0, 5x0J, and 5x1 series Prescotts have incorporated Hyper-Threading in order to speed up some processes that use multithreaded software, such as video editing. The 5x1 series also supports 64 bit computing.
Prescott 2M
Intel, by the first quarter of 2005, released a new Prescott core with 6x0 numbering, codenamed "Prescott 2M". It features Intel 64, the XD Bit, EIST (Enhanced Intel SpeedStep Technology), Tm2 (for processors at 3.6GHz and above), and 2 MiB of L2 cache. However, any advantage introduced by the added cache is mostly negated due to higher cache latency, and the double word size if using Intel 64 mode. Rather than being a targeted speed boost the double size cache is intended to provide the same space and hence performance for 64-bit mode operations.
6xx series Prescott 2Ms have incorporated Hyper-Threading in order to speed up some processes that use multithreaded software, such as video editing.
On 14 November 2005, Intel released Prescott 2M processors with VT (Virtualization Technology, codenamed "Vanderpool") enabled. Intel only released two models of this Prescott 2M category: 662 and 672, running at 3.6 and 3.8 GHz, respectively.
Cedar Mill
The final revision of the Pentium 4 was Cedar Mill, released in early 2006. This was simply a straight shrink of the 600-series core to 65 nm, with no real feature additions. Cedar Mill had a lower heat output than Prescott, with a TDP of 86 W. It has a 65 nm core and features a 31-stage pipeline (just like Prescott), 800 MT/s FSB, Intel 64, HyperThreading and Virtualization Technology. As with Prescott 2M, Cedar Mill also has 2 MiB of L2 cache. It was released as Pentium 6x1 and 6x3 (product code 80552) at frequencies from 3.0 GHz up to 3.6 GHz. None of the 6x1 range (631, 641, 651, and 661) have Virtualization Technology support. As of March 2007 it has not been possible to source 6x3 nor has Intel any records of this product line on their homepage.
Overclocking Record
In 2007, a frequency of 8.32 GHz was reached by an Italian overclocking team known as SFERA OC Team, using a Pentium 4 641 with a FSB of 520 MHz and a multiplier of 16. This is considered the highest clock frequency ever realized on a consumer CPU.
Successor
The original successor to the Pentium 4 was Tejas, which was scheduled for an early-mid-2005 release. However, it was cancelled a few months after the release of Prescott due to extremely high power consumption (a 2.8 GHz Tejas consumed 150 W of power, compared to around 80 W for a Northwood of the same speed, and 100 W for a comparably clocked Prescott) and development on the NetBurst architecture as a whole ceased, with the exception of the dual-core Pentium D/Extreme Edition and Cedar Mill.
Since May 2005, Intel has released dual-core processors based on the Pentium 4 under the names Pentium D and Pentium Extreme Edition. They represent Intel's shift towards parallelism and their intent to eventually make the bulk of their main processor line dual-core. These came under the code names Smithfield and Presler for the 90 nm and 65 nm parts respectively.
The ultimate successors to Pentium 4 are the Intel Core 2 processors using the "Conroe" core based upon the Intel Core microarchitecture, released on July 27, 2006. Intel Core 2 processors have, so far, only been released as dual and quad core processors. Single Core counterparts are present in the Intel Core line, primarily for the OEM market.

pentium III

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:07:00 +0000

By : http://en.wikipedia.org/

Pentium III

Pentium III

Produced:
From early 1999 to 2003
Manufacturer:Intel
CPU Speeds:450 MHz to 1.4 GHz
FSB Speeds:100 MHz to 133 MHz
Process:(MOSFET channel length)0.25 µm to 0.13 µm
Instruction Set:x86 (686)
Microarchitecture:P6
Sockets:
· Slot 1
· Socket 370
Cores:
· Katmai
· Coppermine
· Coppermine-T
· Tualatin

The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors (with the sixth-generation Intel P6 microarchitecture) introduced on February 26, 1999 and containing 9.5 million transistors. The brand's initial processors were very similar to the earlier CPUs branded Pentium II. The most notable difference was the addition of the SSE instruction set (to accelerate media processing and 3D graphics), and the introduction of a controversial serial number embedded in the chip during the manufacturing process.
Similarly to the Pentium II it superseded, the Pentium III was also accompanied by the Celeron brand for lower-end CPU versions, and the Xeon for high-end (server and workstation) derivatives. The Pentium III was eventually superseded by the Pentium 4, but its Tualatin core also served as the basis for the Pentium M CPUs, which used many ideas from the Intel P6 microarchitecture. Subsequently, it was the P-M microarchitecture of Pentium M branded CPUs, and not the NetBurst found in Pentium 4 processors, that formed the basis for Intel's energy-efficient Intel Core microarchitecture of CPUs branded Core 2, Pentium Dual-Core, Celeron (Core), and Xeon.
//
Pentium III cores
Katmai
The original version, Katmai (Intel product code 80525), was very similar to the Pentium II (using a 0.25 µm fabrication process), the only differences being the introduction of SSE, and an improved L1 cache controller (which was the cause of the minor performance improvements over the latter PIIs). It was first released at speeds of 450 and 500 MHz. Two more versions were released: 550 MHz on May 17, 1999 and 600 MHz on August 2, 1999. On September 27, 1999 Intel released the 533B and 600B running with 533/600 MHz but using a 133 MHz FSB, all others use a 100 MHz FSB.
The Katmai used the same slot based design as the Pentium II but with the newer SECC2 cartridge that allowed direct CPU core contact with the heatsink. There've been some early models of the Pentium III with 450 and 500 MHZ with SECC cartridge being delivered for OEM-use only.
A notable stepping for enthusiasts was SL35D. This version of Katmai was officially rated for 450 MHz, but often contained cache chips for the 600 MHz model and thus usually was capable of running at 600 MHz.
Coppermine
The second version, Coppermine, or 80526, had an integrated full-speed 256-bit 256 KiB L2 cache with lower latency, named Advanced Transfer Cache by Intel, which improved performance significantly over Katmai. Under competitive pressure from AMD’s Athlon processor, Intel also re-worked the chip internally, and finally fixed the well known instruction pipeline stalls. The result was a remarkable 30% increased performance in some applications where these stalls happened.
It was built on a 0.18 μm process. Pentium III Coppermines running at 500, 533, 550, 600, 650, 667, 700, and 733 MHz were first released on October 25, 1999. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz (1 GHz). Both 100 MHz FSB and 133 MHz FSB models were made.
A 1.13 GHz version was released in mid-2000 but famously recalled after a collaboration between HardOCP and Tom's Hardware discovered various instabilities with the operation of the new CPU speed grade. The Coppermine core was unable to reliably reach the 1.13 GHz speed without various tweaks to the processor's microcode, aggressive cooling, additional voltage (1.75 V vs. 1.65 V), and specifically validated platforms.Intel only officially supported the processor on its own VC820 i820-based motherboard, but even this motherboard displayed instability in the independent tests of the hardware review sites. In benchmarks that were stable, performance was shown to be sub-par, with the 1.13 GHz CPU equalling a 1.0 GHz model. Tom's Hardware attributed this performance deficit to relaxed tuning of the CPU and motherboard to improve stability.Intel needed at least six months to resolve the problems and re-released 1.1 GHz and 1.13 GHz versions in 2001.
A common misconception is that a modified version of the Coppermine was developed for Microsoft's Xbox game console. The Xbox does not actually use a Pentium III processor per se. It technically runs a Mobile Celeron 733 (Coppermine-128) in a Micro-PGA2 package. Given the fact that the Mobile Celeron 733 has the same 8-way associative cache used in Pentium III chips, it isn't a stretch to just call the Xbox CPU a "Pentium III with half the cache." Still, that statement isn't entirely correct.
Although the codename Coppermine makes it sound as if the chip was fabricated with copper interconnects, Coppermine in fact used aluminum interconnects.
Later in Coppermine's life, Intel implemented a heatspreader to improve contact between the CPU and the heatsink. The heatspreader itself didn't improve thermal conductivity, since it added another layer of metal and thermal paste between the CPU and the heatsink. But it greatly assisted in holding the heatsink flat against the CPU. Earlier Coppermine CPUs with bare cores made for challenging heatsink mounting.[3] If the heatsink was not flat against the core, heat transfer efficiency was crippled. Some heatsink makers also began using pads on their coolers, similar to what AMD did with the "Thunderbird" Athlon. The enthusiast community went so far as to create shims to assist in maintaining a flat interface.
Coppermine-T
This core was supposed to be an intermediate step between Coppermine and Tualatin, with support for lower-voltage system logic present on the latter but core power within previously defined voltage specs of the former so it could work in older system boards. It existed in Intel's processor roadmap in 2000 but was cancelled on the way to production.
Intel did issue S-Spec production codes (e.g. SL5QK) for some late-model Coppermines that would work with low voltage system bus operation (GTL) at 1.25 V AGTL as well as normal 1.5 V AGTL+ signal levels, and would auto detect differential or single-ended clocking. These processors were probably intended for dual-processor motherboards. However core voltage was the same as other Coppermines.
Note: Some sources identified Coppermine cD0-stepping to be Coppermine-T. This is incorrect because cD0-stepping was merely a revision to the original Coppermine rather than a new core by itself. Intel was unlikely to have it placed in the roadmap as a new core codename. Stepping (version numbers) of processors could be compared to minor versions of software.
Tualatin
The third version, Tualatin (80530), was really just a trial for Intel's new 0.13 µm process. As the Pentium 4 had a much bigger die size than the Pentium III, Intel would get more usable Pentium IIIs out of a wafer, and this would allow them to introduce the 0.13 µm Pentium 4 (Northwood) once the process was achieving optimal yields. Tualatin performed quite well, especially in variations which had 512 KiB L2 cache (called the Pentium III-S). The Pentium III-S variant was mainly intended for servers, especially those where power consumption mattered, i.e., thin blade servers.
Pentium III Tualatins were released during 2001 until early 2002 at speeds of 1.0, 1.13, 1.2, 1.26, 1.33 and 1.4 GHz. Overclockers discovered that 1.7-1.8 GHz was about the maximum frequency the Tualatin could achieve using air cooling.
Tualatins can usually be visually distinguished from Coppermine-based Pentium IIIs by the metal integrated heatspreader (IHS) fixed on top of the package. However the very last models of Coppermine Pentium IIIs also featured the IHS - the heatspreader is what distinguishes the FC-PGA2 package from the FC-PGA - both are for Socket 370 motherboards.Because the IHS slightly reduces heat transfer efficiency, some overclockers would remove it to allow direct core-to-heatsink contact. This was even more dangerous with the smaller 130 nm core than it had been with the 180 nm Coppermine, with a risk of cracking or chipping the core, and the difficulty in making good flat contact between the top of the core and the heatsink. However, it did potentially improve cooling which could allow higher overclocking results. Like with Coppermine, as a measure of protection several companies manufactured aftermarket shims to aid in flat heatsink mounting.
The Tualatin core was named after the Tualatin Valley and Tualatin River in Oregon, where Intel has large manufacturing and design facilities.
Pentium III's SSE implementation
Since Katmai was built in the same 0.25 µm process as Pentium II "Deschutes", it had to implement SSE using as little silicon as possible. To achieve this goal, Intel implemented the 128-bit architecture by double-cycling the existing 64-bit data paths and by merging the SIMD-FP multiplier unit with the x87 scalar FPU multiplier into a single unit. To utilize the existing 64-bit data paths, Katmai issues each SIMD-FP instruction as two μops. To compensate partially for implementing only half of SSE’s architectural width, Katmai implements the SIMD-FP adder as a separate unit on the second dispatch port. This organization allows one half of a SIMD multiply and one half of an independent SIMD add to be issued together bringing the peak throughput back to four floating point operations per cycle — at least for code with an even distribution of multiplies and adds.
The issue was that Katmai’s hardware-implementation contradicted the parallelism model implied by the SSE instruction-set. Programmers faced a code-scheduling dilemma: Should the SSE-code be tuned for Katmai's limited execution resources, or should it be tuned for a future processor with more resources? Katmai-specific SSE optimizations yielded the best possible performance from the Pentium III family, but was suboptimal for later Intel processors, such as the Pentium 4 and Core.
Core specifications
Katmai (0.25 µm)
L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 512 KiB, external chips on CPU module at 50% of CPU-speed
MMX, SSE
Slot 1 (SECC, SECC2)
Front side bus: 100, 133 MHz
VCore: 2.0 V, (600 MHz: 2.05 V)
First release: May 17, 1999
Clockrate: 450-600 MHz
100 MHz FSB: 450, 500, 550, 600 MHz
133 MHz FSB: 533, 600 MHz (B-models)
Coppermine (0.18 µm)
L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, SSE
Slot 1 (SECC2), Socket 370 (FC-PGA)
Front side bus: 100, 133 MHz
VCore: 1.6V, 1.65V, 1.70V, 1.76V (cD0, see below)
First release: October 25, 1999
Clockrate: 500 - 1133 MHz
100 MHz FSB: 500, 550, 600, 650, 700, 750, 800, 850, 900, 1000, 1100 MHz (E-Models)
133 MHz FSB: 533, 600, 667, 733, 800, 866, 933, 1000, 1133 MHz (EB-Models)
Coppermine cD0-stepping or Coppermine-T (0.18 µm)
L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, SSE
Socket 370 (FC-PGA, FC-PGA2)
Front side bus: 100 and 133 MHz
VCore: 1.75 V
First release: June 2001
Clockrate: 600 - 1133 MHz
100 MHz FSB: 600, 700, 750, 800, 850, 900, 1000, 1100 MHz
133 MHz FSB: 733, 800, 866, 933, 1000, 1133 MHz
Tualatin (0.13 µm)
L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 or 512 KiB, fullspeed
MMX, SSE, Hardware prefetch
Socket 370 (FC-PGA2)
Front side bus: 133 MHz
VCore: 1.45, 1.475 V
First release: 2001
Clockrate: 1000 - 1400 MHz
Pentium III (256 KiB L2-Cache): 1000, 1133, 1200, 1333, 1400 MHz
Pentium III-S (512 KiB L2-Cache): 1133, 1266, 1400 MHz

pentium II

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 12:03:00 +0000

By : http://en.wikipedia.org/

Pentium II

Pentium II
Produced: From mid 1997 to early 1999
Manufacturer:Intel
CPU Speeds:233 MHz to 450 MHz
FSB Speeds:66 MHz to 100 MHz
Process:(MOSFET channel length)0.35 µm to 0.25 µm
Instruction Set:x86
Microarchitecture:P6
Sockets:
· Slot 1
· MMC-1
· MMC-2
· Mini-Cartridge
· Others
Cores:
· Klamath
· Tonga
· Deschutes
· Dixon

The Pentium II is an x86 architecture microprocessor by Intel, introduced on May 7, 1997. It is based on a modified version of the P6 core first used for the Pentium Pro.
Pentium II is largely based upon its predecessor, Pentium Pro. However, there are some significant changes to the design of the processor.
Unlike previous Intel processors such as the Pentium and Pentium Pro, the Pentium II was packaged in a slot-based form-factor rather than a socket. The chip and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side, sometimes using its own fan
This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled backside bus. This separate cache was slower (running at half of the processor speed) than that in the Pentium Pro, but the smallest cache size was increased to 512 KiB from the 256 KiB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yields, allowing Intel to introduce the Pentium II at a mainstream price level. This arrangement also allowed Intel to easily vary the amount of L2 cache, thus making it possible to target different market segments with cheaper or more expensive processors and accompanying performance levels.
Intel notably improved 16-bit code execution performance on Pentium II, an area in which Pentium Pro was at a notable handicap. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The Pentium II went to 32 KiB of L1 cache, double that of Pentium Pro, as well. Pentium II is also the first P6-based CPU to implement the Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX.
Pentium II is basically a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, and multimedia applications. Combined with the larger L1 cache and improved 16-bit performance, the slower and cheaper L2 cache's performance impact was minimized. General processor performance maximized while costs were cut.
The original Klamath Pentium II (Intel product code 80522) ran at 233 and 266 MHz, were produced in a 0.35 µm fabrication process. A 300 MHz version was released later in 1997.These CPUs worked with a 66 MHz front side bus and initially were used on motherboards equipped with the aging Intel 440FX Pentium Pro chipset. The Deschutes core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced in a more suitable 0.25 µm fabrication process. The 333 MHz variant was the final Pentium CPU used with the legacy 66 MHz front side bus. Support for a 100 MHz front side bus speed heralded solid performance improvements. During 1998, Pentium IIs running at 266, 300, 350, 400, and 450 MHz were also released. Pentium II-based systems using the Intel 440LX chipset were the first to utilize the new generation RAM-standard, SDRAM (which replaced EDO RAM), and the AGP graphics bus.
The Pentium II Xeon was a high-end version intended for use on servers. Principally, it used a different type of slot (Slot 2), case, board design and used expensive full-speed custom L2 cache, which was again off-die. Versions were produced with 512 KiB, 1 MiB or 2 MiB L2 caches by varying the number of 512 KiB chips incorporated on the boardThe 0.25 μm "Tonga" core was the first mobile Pentium II and had all of the features of the desktop models. A mobile version with 256 KiB of on-die, full speed cache was produced late in the Pentium II's lifecycle. This "Dixon" core was the fastest type of Pentium II produced
In early 1999, the Pentium III superseded the Pentium II.
Models Core
Desktop
Klamath (80522)
L1 cache: 16 + 16 KiB (Data + Instructions)
L2 cache: 512 KiB, external chips on CPU module with 50% of CPU-speed
Slot 1 (GTL+)
MMX
Front side bus: 66 MHz
VCore: 2.8 V
Fabrication: 0.35 µm
First release: May 7, 1997
Clockrate: 233, 266, 300 MHz
Deschutes (80523)
L1 cache: 16 + 16 KiB (Data + Instructions)
L2 cache: 512 KiB, external chips on CPU module with 50% of CPU-speed
Slot 1 (GTL+)
MMX
Front side bus: 66, 100 MHz
VCore: 2.0 V
Fabrication: 0.25 µm
First release: January 26, 1998
Clockrate: 266 - 450 MHz
66 MHz FSB : 266, 300, 333 MHz
100 MHz FSB: 350, 400, 450 MHz
Mobile
Tonga (80523)
mobile Pentium II
L1 cache: 16 + 16 KiB (Data + Instructions)
L2 cache: 512 KiB, external chips on CPU module with 50% of CPU-speed
MMC-1, MMC-2, Mini-Cartridge (GTL+)
MMX
Front side bus: 66 MHz
VCore: 1.6 V
Fabrication: 0.25 µm
First release: June 7, 1997
Clockrate: 233, 266, 300 MHz
Dixon (80524)
mobile Pentium II PE ("Performance Enhanced")
L1 cache: 16 + 16 KiB (Data + Instructions)
L2 cache: 256 KiB, on-die, full CPU speed
BGA1, MMC-1, MMC-2, μPGA1 (GTL+)
MMX
Front side bus: 66, 100 MHz
VCore: 1.5, 1.55, 1.6 V, 2.0 V
Fabrication: 0.25 µm
First release: January 25, 1999
Clockrate: 266 - 400 MHz

Pentium Pro

noreply@blogger.com (jazz filling) — Mon, 11 Aug 2008 11:51:00 +0000

By :http://en.wikipedia.org

Pentium Pro

Pentium Pro
Pentium Pro with 256 Kib L2-Cache
Produced:November 1, 1995
Manufacturer:Intel
CPU Speeds:150 MHz to 200 MHz
FSB Speeds:60 MHz to 66 MHz
Process:(MOSFET channel length)0.35 µm to 0.50 µm
Instruction Set:x86
Microarchitecture:P6
Socket:Socket 8

The Pentium Pro is a sixth-generation x86 architecture microprocessor (P6 core) produced by Intel and was originally intended to replace the original Pentium in a full range of applications, but later, was reduced to a more narrow role as a server and high-end desktop chip. The Pentium Pro was capable of both dual- and quad-processor configurations. It was introduced in a stunningly large, rectangular Socket 8 form factor in November 1995. Intel has since discontinued it in favor of the newer high-end Xeon processor lines.
The Pentium Pro (given the Intel product code 80521), was the first generation of the P6 architecture, which would carry Intel well into the next decade. The design would scale from its initial 150 MHz start, all the way up to 1.4 GHz with the "Tualatin" Pentium III. The core's various traits would continue after that in the derivative core called "Banias" in Pentium M and Intel Core (Yonah), which itself would evolve into Core architecture (Core 2 processor) in 2006 and onward.
//
Performance
Performance with 32-bit code was excellent and well ahead of the older Pentium at the time, by 25-35%; however, the Pentium Pro's 16-bit performance was approximately only 20% faster than a Pentium at running 16-bit code. It was this, along with the Pentium Pro's high price, due in part to the full speed L2 cache, that caused the rather lackluster reception for the chip among many home PC enthusiasts, given the dominance at the time of the 16-bit Windows 3.1x and MS-DOS. Windows 95 had already been released at the time of the introduction of the Pentium Pro, but some parts of Windows 95 itself (for example, USER) were still mostly 16-bit. To truly gain the full advantages of Pentium Pro's architecture, one was forced to run a fully 32-bit OS. Microsoft's only truly 32-bit OS at the time was Windows NT 3.51.
Despite the name, the Pentium Pro was actually a completely new architecture, very different from Intel's earlier Pentium processor. The Pentium Pro (P6) core featured an array of advanced RISC technologies, although it wasn't the first x86 CPU with such approach -- before it, the NexGen Nx586 processor already utilized internal x86 translation to its own proprietary RISC86TM instruction set. Perhaps the most obvious sign that things had changed was that the CPU's "front end" decoded the old IA32 instructions into micro-instructions which the Pro's RISC core then processed. The core of Pentium Pro featured several new technologies, including: speculative execution, superpipelining, an advanced L2 cache, register renaming, out of order execution, and a wider 36-bit address bus (usable by PAE).
After the microprocessor was released a bug was discovered in the floating point unit, commonly called the "Pentium Pro and Pentium II FPU bug" and by Intel as the "flag erratum". The bug occurs under some circumstances during floating-point to integer conversion when the floating-point number won't fit into the smaller integer format causing the FPU to deviate from its documented behaviour. The bug is considered to be minor and occurs under such special circumstances that very few, if any, software programs are affected.
An innovation in cache
Likely Pentium Pro's most noticeable addition was its on-package L2 cache. At the time, manufacturing technology did not feasibly allow L2 cache to be integrated into the processor core. Intel instead placed the L2 die separately in the package which still allowed it to run at the same clock speed as the CPU core. Additionally, unlike motherboard-based cache which shared the main system bus with the CPU, the Pentium Pro's cache had its own backside bus (called dual independent bus by Intel). Because of this, the CPU could read main memory and cache concurrently, greatly reducing a traditional bottleneck. The cache was also "non-blocking", meaning that the processor could issue more than one cache request at a time (up to 4), reducing cache-miss penalties. (This is an example of MLP, Memory Level Parallelism.) These properties combined to produce a L2 cache that was immensely faster than the motherboard-based caches of older processors. This cache alone gave the CPU an advantage in input/output performance over older x86 CPUs. In multiprocessor configurations, Pentium Pro's integrated cache skyrocketed performance in comparison to architectures which had each CPU sharing a central cache.
However, this far faster L2 cache did come with some complications. All versions of the chip were expensive, those with more than 256 KiB being particularly so. The Pro's "on-package cache" arrangement was unique. The processor and the cache were on separate dies in the same package and connected closely by a full-speed bus. The two dies — both of which were very large by the standards of the day — had to be bonded together early in the production process, before testing was possible. This meant that a single, tiny flaw in either die made it necessary to discard the entire assembly, which was one of the reasons for the Pentium Pro's relatively low production yield and high cost.
Available models
Pentium Pro clock speeds were 150, 166, 180 or 200 MHz with a 60 or 66 MHz external bus clock. Some users chose to overclock their Pentium Pro chips, with the 200 MHz version often being run at 233 MHz, and the 150 MHz version often being run at 166 MHz. The chip was popular in symmetric multiprocessing configurations, with dual and quad SMP server and workstation setups being commonplace.
The Pentium Pro was succeeded by the Pentium II, which was essentially a cost-reduced and re-branded Pentium Pro with the addition of MMX and enhanced 16-bit code performance. Costs were reduced by using standard SRAM cache chips running at half-speed, which increased production yields.
Eventually a 333 MHz Pentium II Overdrive processor for Socket 8 was produced by Intel as an upgrade option for owners of Pentium Pro systems, which had 512 KiB of high speed cache. However it only supported dual-processor operation, which did not make it a usable upgrade for high end quad-processor systems.
Pentium Pro / 6th generation competitors
AMD K5 and K6
Cyrix 6x86 and MII
IDT WinChip
Intel Pentium (co-existed with Pentium Pro for several years)