According to Everything USB, “Dubbed SuperSpeed USB, USB 3.0 promises a major leap forward in transfer speeds and capability, while maintaining backwards compatibility with USB 2.0 devices.”

What are the differences with this release of the standard:

• Higher transfer rates (up to 4.8Gbps)
• Increased maximum bus power
• New power management features
• Full-duplex data transfers
• Support for new transfer types
• Backward USB 2.0 compatibility
• New connectors and cables

So, if you were to design and verify a Superspeed USB 3.0 core on your next chip integration.  Where would you get your IP core, and where would you get your Verification IP (VIP)? After looking around, this is what we found.

VIP SuperSpeed USB

The Cadence SuperSpeed USB Verification IP (VIP) provides a mature, highly capable compliance verification solution for the USB 3.0 Protocol. Used on multiple production designs, the SuperSpeed USB VIP is applicable for IP, SoC, and system-level verification.…more

USB 3.0 Verification IP

For the SuperSpeed USB design verification needs, Perfectus announced Genie-SSU Verification-IP, fully compliant to the SuperSpeed USB 3.0 with features that far superior than any other solution available in the market….more

USB 3.0 Verification IP provides an smart way to verify the USB 3.0 component of a SOC or a ASIC. It provides backward compatibility support for earlier versions 1.0 and 2.0 of USB specifications….more

USB 3.0 Verification IP

Truechip’s USB 3.0 Verification IP provides an effective & efficient way to verify the components interfacing with USB 3.0 interface of an ASIC/FPGA or SoC….more

Verification IP for USB 3.0

Supports USB 3.0 and USB 2.0 standards Host, Device and Hub emulation…more

USB3.0_nVS

The USB 3.0 nVS is a comprehensive Verification IP solution for pre-silicon functional verification of USB designs. The USB 3.0 nVS builds upon the widely used nVS for PCI Express and the USB 2.0 nVS….more

USB-Xactor Test Environment

Your Solution to Superspeed USB 3.0 Compliance Validation. Complete solution for core through chip-level verification Superspeed USB3.0 and 2.0 OTG…more

USB 3.0 Verification IP

Sibridge Technologies’ USB3.0 Verification IP is the Industry’s most comprehensive protocol validation solution for predictable verification of USB based designs…more

Interlaken is the name of a very picturesque town in Switzerland (pictured), but it’s also the name of the next communications protocol that will be driving a cloud near you! Maybe the fact that Interlaken, the town, sits between two huge lakes in the Alps is what inspired the name of the protocol. Think of the lakes as huge pools of data that needs to move from one lake to another. You get the idea.

Chip-to-chip bandwidth is one of the major bottlenecks in cloud computing as the amount of data that needs to be moved around increases incessantly. Cisco and Cortina Systems recognized the need in 2006 and announced the protocol.  The two companies joined with Silicon Logic Engineering (now part of Open-Silicon) in 2007, and put out an Interlaken Technology White Paper.

The whitepaper summarizes the protocol, “Interlaken is an interconnect protocol optimized for highbandwidthand reliable packet transfers. It uses bundles of serial links to create a logical connection between components with multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment.”

So, if you were to design and verify an Interlaken core on your next chip integration.  Where would you get your IP core, and where would you get your Verification IP (VIP)? After looking around, this is what we found.

Interlaken Controller IP Core

Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI…more

Interlaken IP Core

Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 150Gbps…more

Altera’s Interlaken intellectual property (IP) continues to scale with today’s demand for more bandwidth and higher performance needs…more

Interlaken Controller IP Core

Flowgic’s Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.2. Interlaken IP core is designed for flexibility, robustness, scalability and is available in 64(10-20 Gb/s), 128(20-40Gb/s), 256(40-80Gb/s) and 384(80-120Gb/s) bit datapath variants…more

Interlaken IP Core

The Interlaken is a high speed, narrow, channelized and highly configurable chip-to-chip interface protocol. It offers programmable burst sizes, per-channel backpressure, source-asynchronous nature and scalability…more

3G to 600G Interlaken ILK and ILA IP Core

Tamba offers industry’s lowest latency, power, and size solution for the Interlaken communication protocol. The Universal Interlaken IP Core can be customized from 1 Gbps to 600 Gbps and targeted to both FPGA and ASIC platforms…more

XCI4FIC 100G Interlaken Fabric Interface Core

The Xelic 100G Interlaken Fabric Interface Core (XCI4FIC) provides the flexible transport of channelized signals for both segment mode and packet mode transmission formats with configurable lane number support. Flow control is provided for both in-band and out-of-band methods with optional automatic and override insertion capability…more

Interlaken VIP

The Interlaken Verification IP is compliant with 1.2 specifications and verifies Interlaken interfaces of designs Interlaken Interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment…more

Rockfish Technologies

INTERLAKEN ASIC IP

The Optimized Interlaken Protocol IP block from Rockfish Technology supports all the published extensions and interoperability recommendations from the Interlaken Alliance including…more

Rockfish Technologies

INTERLAKEN VERIFICATION IP

The Vermilion BFM bridges the gap between the user’s testbench and an Interlaken Device Under Test (DUT). Vermilion BFM Egress Interlaken Framing Layer Features…more

Date: Thursday, March 21, 2013
Time: 1100 - 1230
Location / Room: Chartreuse

Automatically computing abstractions of large circuits combined with powerful SAT and SMT solvers is key to the success of formal verification techniques. The papers of this session present significant improvements in abstraction techniques and SAT/SMT-based optimizations. SAT- and SMT-abstractions are guided by unsatisfiable cores. Three papers address the issue of reducing the size of interpolants generated during the construction of abstractions. The second paper proposes a new abstraction technique demonstrating a significant improvement in gate-level abstractions.

For more information, go here.

Came across a great panel discussion from DAC 2012 that’s really worth a watch. Hosted by David Murray of Duolog, the panel includes Mike Stellfox of Cadence, Harry Foster of Mentor Graphics, Paul Martin of ARM, and Warren Stapleton of AMD.

The main thrust of the conversation is centered on SoC integration efficiency and how SoC verification has become a major component or driver of it.

Take a look here:

Closely related to this topic are the tools that Duolog provide to increase SoC integration efficiency. You can try these tools out for free on the cloud here:

	Duolog’s Weaver tool has a unique rules-based integration methodology that offers an intuitive, highly automated, scalable solution for IP integration and system assembly.
	Duolog’s Bitwise tool manages HW/SW register, memory-map and interface definitions for IPs, subsystems or SoCs. Bitwise automatically generates specifications for register and memory-map information.
	Duolog’s Spinner tool specifies the complete I/O layer, auto-generates multiple design views and enables seamless integration of the I/O fabric with the rest of the system.

We are very proud to announce that this advanced verification IP (VIP) is now available for hands-on trials on the Xuropa Platform: HERE.

The VIP has a unique in that it combines MIPI Alliance physical interface (M-PHY) with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device. This makes it easier for mobile device manufacturers to leverage the large USB hardware and software ecosystem in the mobile environment.

The VIP is production-proven, used by Global Unichip.  “Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol,” said James Cheng, senior vice president, Global Unichip. “By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage.”

To trial this verification IP for yourself, click on the image below and try it out on the Xuropa Platform - hands-on with no downloads or installation.

If you’re interested in more Verification IP on the Xuropa Platform:

• VIP AMBA AHB UVC (includes APB)
• VIP CAN UVC
• VIP SATA PureSpec
• VIP AMBA AXI 3&4 UVC (includes APB)
• MIPI DSI VIP
• OCP Assertion Based VIP
• VIP PCI Express 3.0 PureSpec
• VIP AMBA4 ACE UVC (includes AXI 4)
• VIP Ethernet 40G/100G UVC
• VIP HDMI 1.3 UVC
• VIP I2C UVC
• VIP AMBA4 Stream
• VIP JTAG UVC
• VIP LIN UVC
• AMBA AXI Assertion Based VIP
• VIP SuperSpeed USB
• MIPI SLIMbus VIP
• AMBA4 ACE Assertion Based VIP
• VIP SAS UVC
• MIPI UniPro VIP
• VIP PCI UVC
• AMBA AHB Assertion Based VIP
• MIPI CSI VIP
• MIPI PHY VIP
• MIPI DigRF v4 VIP

According to the research collected by Markets and Markets,  the cloud computing market in the health care sector is expected to grow to $5.4 billion by 2017.

While privacy and security are still cited as reasons to be cautious, users of the cloud are finding security models and technology that they can use today in the cloud.

Here is the key paragraph that relates to every industry out there:

“Most IT organizations in the health care sector don’t have the talent required to move their systems safely to cloud-based platforms, and they may not understand the compliance and security issues as well as they should. However, the default of “do nothing” is not acceptable considering that the IT backlog is growing again — and budgets are not. It’s time to get creative and innovative around the use of new technology, including cloud computing.”

Budget is an issue in every IT organization, and the cloud offers direct and in direct ways to either control spend, or do more with less.

Horan expects AWS revenues to grow from an estimated $2.1 Billion in 2012 (up 77%) to $10 Billion by 2016.  Using Rackspace as a data point and extrapolating from there, Horan estimates that AWS could have a market cap of $101,000,000,000 by 2018.

The differences between customer base, channel, and market could not be more stark when comparing AWS and Amazon retail, but there has been little pressure to date to make any changes.  With an estimated market share of between 75-80% of cloud workloads running on AWS, there appears to be no pressing need to change.

However, we’re in the very early days of cloud computing with plenty of growth yet to come.  This will provide the environment for competition to build, and with that the pressure make the split.

Read more here.

Over 75,000 people to attend DreamForce with phenomenal keynote speakers, including fellow Brit Richard Branson. Here’s a preview video from Denis Pombriant and Brent Leary. Enjoy!

As I and many others often say, as the cost of computing continues to asymptotically approach zero, migration to the cloud becomes inevitable. Many concerns are thrown up into the face of progress, such as security and reliability. But these continue to get resolved as real world solutions are applied to real world situations.

One challenge of migrating to the cloud and between clouds is still very real however - how do you quickly and securely move a ton of data to the cloud? And by a “ton”, let’s say a Petabyte.

Well, Mover.io is changing all that. According to an article in Venture Beat, they’re already moving petabytes of data to and between clouds. It will be interesting to see how this company develops and solves one of the most pressing challenges of moving applications from the data center to the cloud.

Here are the main points:

Myth #1: The public cloud is the most inexpensive way to procure IT services

As our own analysis has shown, when your workloads are running constantly and you already have a private cloud or data center, you’re better sticking with what you have than moving to the cloud.  One of the key benefits of the cloud is flexibility and agility, not necessarily cost.

Myth #2: Baby steps in virtualization are the only way to reach the cloud

Not sure about this one.  I wonder how many IT departments would really make it a step-function move to virtualization without first moving a targeted group or portion of the data center first.

Myth #3: Critical applications do not belong in the cloud

An excellent point.  There is no reason a mission critical job should not be migrated to the cloud - if you need the compute to meet an immediate need, then why not?  The question is, “which cloud, and how?”.

Myth #4: All cloud security requirements are created equally

Not sure if I’d use this particular title.  Essentially - make sure you understand what are the real threats and manage the migration accordingly, mitigating risks appropriately.

Myth #5: There is only one way to do cloud computing

In such a nascent field, how could there possibly be only one way to execute a cloud strategy?