<?xml version='1.0' encoding='UTF-8'?><?xml-stylesheet href="http://www.blogger.com/styles/atom.css" type="text/css"?><feed xmlns='http://www.w3.org/2005/Atom' xmlns:openSearch='http://a9.com/-/spec/opensearchrss/1.0/' xmlns:blogger='http://schemas.google.com/blogger/2008' xmlns:georss='http://www.georss.org/georss' xmlns:gd="http://schemas.google.com/g/2005" xmlns:thr='http://purl.org/syndication/thread/1.0'><id>tag:blogger.com,1999:blog-4597498589834570435</id><updated>2026-04-14T04:11:50.609+05:30</updated><category term="parasitic extraction"/><category term="Static Timing analysis"/><category term="STA"/><category term="VLSI"/><category term="Manufacturing Effects"/><category term="Delay"/><category term="scripting language"/><category term="setup check"/><category term="Setup violation"/><category term="command"/><category term="hold Violation"/><category term="hold check"/><category term="metal"/><category term="Fabrication Step"/><category term="Interview Question"/><category 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term="Etching"/><category term="Example of Setup and hold"/><category term="Fall delay"/><category term="Latched based STA"/><category term="Maximum Delay"/><category term="Metal Layer"/><category term="Minimum Delay"/><category term="Negative Unate"/><category term="OpenSTA"/><category term="Physical Design"/><category term="Positive Unate"/><category term="Primetime"/><category term="Resume"/><category term="Rise Delay"/><category term="Standard Delay Format"/><category term="Synopsys"/><category term="capacitor"/><category term="capture path"/><category term="clock"/><category term="combinational circuit"/><category term="launch path"/><category term="lib"/><category term="pmos"/><category term="AND"/><category term="AOI Cells"/><category term="Active Region"/><category term="And-Or-Inverter"/><category term="Back Annotation"/><category term="Block based model"/><category term="CMP"/><category term="Conformal"/><category term="DRC"/><category term="DTA"/><category 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charge"/><category term="Adding Buffer"/><category term="Addition"/><category term="Anisotropic"/><category term="Anisotropy"/><category term="Annealing"/><category term="Antenna voilation"/><category term="Area Constraints"/><category term="Assessment"/><category term="Associative"/><category term="Awards"/><category term="BCD"/><category term="Bash Shell"/><category term="Basic Electronics"/><category term="Basic gates"/><category term="Best case analysis"/><category term="Binary Arithmetic"/><category term="Binary Number"/><category term="Block scope"/><category term="Blockage"/><category term="Boolean Function"/><category term="Boolean Property"/><category term="Boundary nets"/><category term="CMOS circuit"/><category term="CRP"/><category term="CRPR"/><category term="CVD"/><category term="Cell Section"/><category term="Cell instance"/><category term="Cell type"/><category term="Channel Stop Implants"/><category term="Chemical Vapor Deposition"/><category term="Clock Skew"/><category term="Clock gating path"/><category term="Combinational Logic"/><category term="Commutative"/><category term="Context Independent"/><category term="Conversion"/><category term="Coupled Capacitance"/><category term="Critical"/><category term="Cross talk"/><category term="Cshell"/><category term="DSPF"/><category term="Data path"/><category term="Decoupled Capacitance"/><category term="Delay variation"/><category term="Demorgan&#39;s"/><category term="Density Variation"/><category term="Design Rule Check"/><category term="Detailed Standard Parasitic Format"/><category term="Device Isolation"/><category term="Die"/><category term="Die-to-die"/><category term="Difference between different parasicitic formats"/><category term="Diode insertion"/><category term="Dishing"/><category term="Distributed RC model"/><category term="Division"/><category term="Driver strength"/><category term="Dry Etch"/><category term="Duality Principle"/><category term="Dynamic Timing analysis"/><category term="END Point Detection"/><category term="ETM verification"/><category term="Effective Channel Length"/><category term="Electron Spinning"/><category term="Employee"/><category term="Enclosed Area"/><category term="Enclosure"/><category term="Equation methods"/><category term="Erosion"/><category term="Etch Profile"/><category term="Etch rate"/><category term="Exclusive"/><category term="Extension"/><category term="External Skew"/><category term="Face to Face"/><category term="Fanout"/><category term="Feedback"/><category term="Field Oxide"/><category term="Field Poly"/><category term="File extension"/><category term="Front end"/><category term="Full Flat Design Flow"/><category term="GBA"/><category term="Gate Of Equivalence"/><category term="Gate Poly"/><category term="HLS"/><category term="HVH"/><category term="Hierarchical Design"/><category term="How to generate SPEF"/><category term="How to read SPEF"/><category term="How to write SDC"/><category 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Experience Summary."/><category term="Jumper"/><category term="KCL"/><category term="KVL"/><category term="LTSPICE"/><category term="Late Path"/><category term="Linux"/><category term="Lithography"/><category term="Loading effect"/><category term="Logical Hierarchy"/><category term="Low Power"/><category term="Lucy Wyndham"/><category term="Lumped Capacitor Delay"/><category term="Lumped RC model"/><category term="MEASURED_FROM"/><category term="Max path"/><category term="Maximum Borrow Time"/><category term="Maximum capacitance"/><category term="Maximum transition time"/><category term="Mealy Model"/><category term="Metal Stack"/><category term="Metal layer Orientation"/><category term="Metal1"/><category term="Min Spacing"/><category term="Min Width"/><category term="Minimum Capacitance"/><category term="Modelling"/><category term="Moore Model"/><category term="Mu"/><category term="Multi-cycle"/><category term="Multiplication"/><category term="Mx"/><category term="MxMyMz"/><category term="My"/><category term="Mz"/><category term="N select Layer"/><category term="N type impurity"/><category term="N well"/><category term="N+ Impurities"/><category term="NOR"/><category term="NOT"/><category term="Negative Borrow Time"/><category term="Negative Skew"/><category term="Net Delay"/><category term="Nets"/><category term="Noise Margin"/><category term="Nomenclature"/><category term="Number System"/><category term="OCV"/><category term="OR"/><category term="Octal number"/><category term="Operating Condition"/><category term="Over Etch"/><category term="Oxidation"/><category term="P select layer"/><category term="PBA"/><category term="PT"/><category term="PVD"/><category term="Path"/><category term="Physical Hierarchy"/><category term="Physical library"/><category term="Pi network"/><category term="Planar Dielectric."/><category term="Plasma effect"/><category term="Poly Contact"/><category term="Poly Design Rule"/><category term="Port delay"/><category term="Positive Skew"/><category term="Post Layout STA"/><category term="Power Constraints"/><category term="Pre-Layout STA"/><category term="Process"/><category term="Process Skew"/><category term="Process Variation"/><category term="Programming Logic"/><category term="Property of interconnects wires"/><category term="Pulse Skew"/><category term="QTM. Interface Logic Models"/><category term="Quick Timing Models"/><category term="RLC model"/><category term="RSPF"/><category term="RTL engineer"/><category term="Random"/><category term="Realization of Basic gates"/><category term="Residue"/><category term="Routing Grid"/><category term="Routing Orientation"/><category term="SBPF"/><category term="SDC format"/><category term="SI"/><category term="SPF"/><category term="STAR-RCXT"/><category term="Sanjay Goyal"/><category term="Selectivity"/><category term="Semiconductor Industry"/><category term="Short Term Courses"/><category term="Signal Integrity"/><category term="Simulation"/><category term="Single Cycle path"/><category term="Skew"/><category term="Stage Delay"/><category term="Swapping Cell"/><category term="Symbol Library"/><category term="Synchronous Circuits"/><category term="System Unate"/><category term="Systematic"/><category term="T network"/><category term="THICKNESS"/><category term="TIMINGCHECK"/><category term="TOP_OF_CHIP"/><category term="Technical Resume"/><category term="Technology library"/><category term="Template STA script"/><category term="Thinkness variation"/><category term="Time Borrowing"/><category term="Timing Budgeting"/><category term="Timing Models"/><category term="Timing Waveform"/><category term="Timing path"/><category term="Tphl"/><category term="Tplh"/><category term="Transition Delay"/><category term="True Story"/><category term="Twin Tub"/><category term="Type of Clock Skew"/><category term="Type of Timing Analysis"/><category term="Uncertain Region"/><category term="Undefined Region"/><category term="Uniformity"/><category term="V1"/><category term="V2"/><category term="VHV"/><category term="VIH"/><category term="VIL"/><category term="VLSI Institute"/><category term="VOH"/><category term="VOL"/><category term="Vds"/><category term="Vgs"/><category term="Via rules"/><category term="Wafer"/><category term="Wet Etch"/><category term="Within-die"/><category term="Workplace"/><category term="XNOR"/><category term="XOR"/><category term="acronyms"/><category term="adder"/><category term="antenna"/><category term="antenna effects"/><category term="antenna ratio"/><category term="asynchronous"/><category term="asynchronous path"/><category term="author article"/><category term="back-end"/><category term="block diagram"/><category term="block level constraints"/><category term="capacitance"/><category term="clock reconvergence Pessimism"/><category term="clock reconvergence pessimism removal"/><category term="conditional path delay"/><category term="current mobility"/><category term="cycle Stealing"/><category term="db"/><category term="ddc"/><category term="decoder"/><category term="def"/><category term="deposition"/><category term="early path"/><category term="equation"/><category term="false"/><category term="full adder"/><category term="gate"/><category term="grdgenxo"/><category term="hdl"/><category term="high level synthesis"/><category term="input-output delay"/><category term="inter-die"/><category term="interconnect delay"/><category term="intrinsic transconductance"/><category term="layer"/><category term="lef"/><category term="lexical"/><category term="map"/><category term="max width"/><category term="max_capacitance"/><category term="max_fanout"/><category term="maximum Clock Frequency"/><category term="milkyway database"/><category term="min_capacitance"/><category term="modelling of variation"/><category term="nxtgrd"/><category term="on-chip-variation"/><category term="over budgeted"/><category term="pass transistor"/><category term="pchannel"/><category term="physical Vapor Deposition"/><category term="physical constraint"/><category term="plib"/><category term="positional Number system"/><category term="read_sdc"/><category term="report_timing"/><category term="rules"/><category term="saif"/><category term="saturation current"/><category term="saturation region"/><category term="single via"/><category term="slib"/><category term="special cells"/><category term="stacked Via"/><category term="substraction"/><category term="subthreshold current"/><category term="subtractor"/><category term="svf"/><category term="transmission gate"/><category term="under budgeted"/><category term="user input"/><category term="variation"/><category term="vcd"/><category term="velocity saturation"/><category term="verilog"/><category term="verilog file"/><category term="via"/><category term="via array"/><category term="vlsi aspirant"/><category term="wire load model"/><category term="worst case analysis"/><category term="write_sdc"/><title type='text'>VLSI Concepts</title><subtitle type='html'>An online information center for all who have Interest in Semiconductor Industry.</subtitle><link rel='http://schemas.google.com/g/2005#feed' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/posts/default'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default?redirect=false'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/'/><link rel='hub' href='http://pubsubhubbub.appspot.com/'/><link rel='next' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default?start-index=26&amp;max-results=25&amp;redirect=false'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><generator version='7.00' uri='http://www.blogger.com'>Blogger</generator><openSearch:totalResults>138</openSearch:totalResults><openSearch:startIndex>1</openSearch:startIndex><openSearch:itemsPerPage>25</openSearch:itemsPerPage><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-8263731365141826213</id><published>2025-04-23T09:16:00.000+05:30</published><updated>2025-04-23T09:16:07.165+05:30</updated><title type='text'>Pranjal Joshi – From Code to Chips: How a CSE Girl Found Her Place in the VLSI Industry</title><summary type="text">Pranjal Joshi’s story is not the typical “CSE-to-software-success” arc. After completing her Computer Science Engineering degree, she joined a reputed software company—something most of her peers celebrated. But for Pranjal, the spark just wasn’t there.
Day after day of routine coding left her feeling disconnected. It wasn’t the kind of impact she had envisioned making. “Is this really what I </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/8263731365141826213/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2025/04/Pranjal Joshi story.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8263731365141826213'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8263731365141826213'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2025/04/Pranjal Joshi story.html' title='Pranjal Joshi – From Code to Chips: How a CSE Girl Found Her Place in the VLSI Industry'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://img.youtube.com/vi/Z8kYQhVR2pc/default.jpg" height="72" width="72"/><thr:total>0</thr:total><georss:featurename>Noida, Uttar Pradesh, India</georss:featurename><georss:point>28.5355161 77.3910265</georss:point><georss:box>0.22528226382115335 42.234776499999995 56.845749936178848 112.5472765</georss:box></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-6027604914655586885</id><published>2024-10-23T10:56:00.001+05:30</published><updated>2024-10-28T07:33:26.853+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="SDC"/><category scheme="http://www.blogger.com/atom/ns#" term="Synopsys Design Constraints"/><title type='text'>Advance SDC Techniques for Efficient Timing Closure - Part 1</title><summary type="text">Introduction to Advanced SDC TechniquesSDC is an industry-standard format used to specify the timing, design, and operational constraints for ASIC and FPGA designs. It’s crucial for various EDA tools like synthesis, static timing analysis (STA), and place-and-route.Note:- Basic Of SDC&amp;nbsp;(Our Previous Blog)
Key Concepts:

  Clock Definition: Specifies the clock waveforms and timing </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/6027604914655586885/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2024/10/advance-sdc-techniques-part1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6027604914655586885'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6027604914655586885'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2024/10/advance-sdc-techniques-part1.html' title='Advance SDC Techniques for Efficient Timing Closure - Part 1'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total><georss:featurename>Noida, Uttar Pradesh, India</georss:featurename><georss:point>28.5355161 77.3910265</georss:point><georss:box>0.22528226382115335 42.234776499999995 56.845749936178848 112.5472765</georss:box></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-6785316733704888880</id><published>2024-03-20T17:58:00.007+05:30</published><updated>2024-03-20T17:58:00.134+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Electron Spinning"/><category scheme="http://www.blogger.com/atom/ns#" term="Semiconductor Physics"/><title type='text'>Semiconductor Physics: Electron Spinning in an ATOM</title><summary type="text">Electron Spinning in an ATOMWe have discussed in our previous article (Semiconductor Physics:- Electron Configuration In Atom, about the atoms (and analogy) and the basic idea of electron movement. If you remember, we have finished our article just introducing the spining of electrons in 3D dimensions and about the quantum numbersn - principal quantum number – This is same number as we know </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/6785316733704888880/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2024/03/semiconductor-physics-electron-spining.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6785316733704888880'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6785316733704888880'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2024/03/semiconductor-physics-electron-spining.html' title='Semiconductor Physics: Electron Spinning in an ATOM'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEjKzP-Y-bEeIbo4TLs_fswL6Qyprm_l-t2-xvkpB1iwSTlJu9XMXeXv3B0ZDJ0uorR7xYvxA1rxrKZOaXFqi8PtBeaOG-TcxWHnpJi5t5CWOGfjJhZxfE38636jAxmo6bbh5LSXoHz3Boe_-ehGKsmsfIkwwfCBQmYKUzu9OYHN1QVuysM1Xk2mTEVs8TY=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-2119763577731768017</id><published>2024-03-16T16:39:00.001+05:30</published><updated>2024-03-16T16:48:41.819+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Semiconductor Physics"/><title type='text'>Semiconductor Physics:- Electrons configuration in Atom</title><summary type="text">Electrons configuration in Atom as per Quantum Mechanics&amp;nbsp;To understand the movement of electrons in a semiconductor device, we need to understand the electronic configuration of an atom and how it interacts with the crystal lattice. We already know that atom consists of Neutrons (neutral charge) and Protons (positive charge) inside a nucleus &amp;amp;&amp;nbsp; Electrons (negative charge) revolved </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/2119763577731768017/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2024/03/semiconductor-physics-electron-configuration.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2119763577731768017'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2119763577731768017'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2024/03/semiconductor-physics-electron-configuration.html' title='Semiconductor Physics:- Electrons configuration in Atom'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEjeN99IrqO2RyTytvabXirN6wyCt0rJZqA_dtDj2M8qP7A7v_xp6TGsG60rWRovLATmwgPyi1bjcwLwRlbizLhJQoyYozR_MJB5sCQNPBofZh3ViAeqSRSDh9gRXCruxCdUnQZMo2sHZXuV24r8D3DiKHKM55kKn6pihU3-uitAJkrC05if9CJwXxA7rzc=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-7686409841027789472</id><published>2022-02-03T20:39:00.001+05:30</published><updated>2022-02-03T20:39:21.279+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="hdl"/><category scheme="http://www.blogger.com/atom/ns#" term="lexical"/><category scheme="http://www.blogger.com/atom/ns#" term="verilog"/><title type='text'>Verilog HDL - Lexical Conventions</title><summary type="text">
&amp;nbsp;

  HDLs provide ways to represent the digital circuits in the textual form. Verilog HDL is a HARDWARE DESCRIPTION LANGUAGE to model the digital circuits, this source code is written in a text file with the extension [ *.v ].&amp;nbsp; 

  Any source code is created with the combination of characters and words which are called KEYWORDS and SYNTAX/SEMANTICS. These are globally called lexical </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/7686409841027789472/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/02/verilog-hdl-lexical-convention.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7686409841027789472'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7686409841027789472'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/02/verilog-hdl-lexical-convention.html' title='Verilog HDL - Lexical Conventions'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-8520842904535459762</id><published>2022-01-28T18:19:00.010+05:30</published><updated>2022-01-28T18:19:00.197+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="SHELL"/><category scheme="http://www.blogger.com/atom/ns#" term="task"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><title type='text'>Unix For VLSI Industry - Part 4a- TASK 1 - SHELL Scripting</title><summary type="text">
   SHELL Scripting Task - 1
  
  In the previous articles or say Assignment 1 and  Assignment 2, I have captured few of the practice question related to debugging of SHELL Scripting. We know very well how much this is important from Industry point of view. By now you are very much expert in the UNIX Command and specially writing any Kind of Script using the SHELL Scripting. I am now going to </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/8520842904535459762/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-scripting-task-1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8520842904535459762'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8520842904535459762'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-scripting-task-1.html' title='Unix For VLSI Industry - Part 4a- TASK 1 - SHELL Scripting'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-7156209333923845861</id><published>2022-01-25T14:19:00.005+05:30</published><updated>2022-01-25T14:19:00.189+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Assignment"/><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="Debugging"/><category scheme="http://www.blogger.com/atom/ns#" term="File"/><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="SHELL"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><title type='text'>Unix For VLSI Industry - Part 3b - Assignment 2 - SHELL Scripting</title><summary type="text">
   SHELL Scripting Debugging Assignment - 2
  
  In the previous assignment, I have captured few of the practice question related to debugging part. We know very well how much this is important from Industry point of view. Like I said in last article - Understanding the Scripting syntax and using them in automation - these are 2 different things. Debugging the existing code OR say enhancing that</summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/7156209333923845861/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-debugging-assignment-2.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7156209333923845861'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7156209333923845861'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-debugging-assignment-2.html' title='Unix For VLSI Industry - Part 3b - Assignment 2 - SHELL Scripting'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-7596868485842672019</id><published>2022-01-22T15:00:00.012+05:30</published><updated>2022-01-22T15:00:00.201+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Assignment"/><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="Debugging"/><category scheme="http://www.blogger.com/atom/ns#" term="File"/><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="SHELL"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><title type='text'>Unix For VLSI Industry - Part 3a - Assignment 1 - SHELL Scripting</title><summary type="text">
   SHELL Scripting Debugging Assignment - 1
  
  Understanding the Scripting syntax and using them in automation - these are 2 different things. A lot of times people use google to check the syntax and they have some logic to capture them but when they compile - they face a lot of error. And that&#39;s the point they stuck because debugging itself is a Skill and which always come by experience or </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/7596868485842672019/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-debugging-assignment-1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7596868485842672019'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/7596868485842672019'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-debugging-assignment-1.html' title='Unix For VLSI Industry - Part 3a - Assignment 1 - SHELL Scripting'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4448158884417637021</id><published>2022-01-20T18:01:00.019+05:30</published><updated>2022-01-20T18:01:00.214+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Assignment"/><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="File"/><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="SHELL"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><title type='text'>Unix For VLSI Industry - Part 2b - Assignment 2 - SHELL Scripting</title><summary type="text">
   SHELL Scripting based Assignment

  Shell Scripting is going to easy your daily work - specially repeated work. In the previous Article we have discussed the UNIX command and first assignment - Now it&#39;s time to use the scripting language to automate our work around the Unix command. There are other scripting languages also like TCL / PERL and Python but in this article we will talk about the </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4448158884417637021/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-scripting-assignment.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4448158884417637021'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4448158884417637021'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/shell-scripting-assignment.html' title='Unix For VLSI Industry - Part 2b - Assignment 2 - SHELL Scripting'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEg7podxap-IGQQujQbjr5QCZZc_itFUfXkrNplQXPj2MuGv7nsiLo3gS4tOeHG0DrzWYO95FDBqQImyQKnV9mPgo_g_L0OYtv34L7jZBr1SFOO1PhJEs8r61h43MhcWTAKWoRJvnX3o_wP0_t368WJ0rCRsoIpMS8iDSLJwUxuC5xF0PtB6XhwRd98M=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4358535587496697144</id><published>2022-01-18T16:07:00.003+05:30</published><updated>2022-01-18T19:49:42.209+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Assignment"/><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="File"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><title type='text'>Unix For VLSI Industry - Part 2a - Assignment 1</title><summary type="text">
  Unix and VLSI And Our Education System (or say the skills in Freshers) are at 3 different levels right now, even though people know that without Unix it&#39;s impossible to even work in VLSI industry. Unfortunatly, It&#39;s been so many years but it&#39;s not in curriculum of any engineering college. Same thing I have highlighted in my previous article. 
  
  In the previous part, we have discussed few </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4358535587496697144/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/unix-assignment-1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4358535587496697144'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4358535587496697144'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/unix-assignment-1.html' title='Unix For VLSI Industry - Part 2a - Assignment 1'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEj68irp9nPKTqsoO9CyZg3EsYAUD1Dwv08RvPkSXykgm6m8r7WUCxTSMG9CQfDfB08NRFDpPp9yvTbOMsvhmeLXKyoNV8unat6bggqwbTzQUAjtewjEIjxR2XFTYkV4O8Hh4cZOk1zod5t1Ss1vWaiz7tC_io4gmEpF-xIL3qvkLpCIPplwjm8T26FN=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-9036333374159120908</id><published>2021-12-24T19:19:00.002+05:30</published><updated>2022-01-17T17:29:01.789+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="TCL"/><title type='text'>TCL Practice Task S2_1 (Scripting Language)</title><summary type="text">
While working on industry grade EDA tools, it is important to understand the working of commands. However most important are switches used along with the commands. These switches are designed in such a way that it acquire sufficient information from the end user (user that is using the command). As a end user you can control the command also or say you can instruct the program to execute the </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/9036333374159120908/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2021/12/tcl-practice-task-5.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/9036333374159120908'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/9036333374159120908'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2021/12/tcl-practice-task-5.html' title='TCL Practice Task S2_1 (Scripting Language)'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4267174577593039162</id><published>2021-12-15T18:28:00.026+05:30</published><updated>2022-02-03T20:14:11.761+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Basic Electronics"/><category scheme="http://www.blogger.com/atom/ns#" term="KCL"/><category scheme="http://www.blogger.com/atom/ns#" term="KVL"/><category scheme="http://www.blogger.com/atom/ns#" term="LTSPICE"/><category scheme="http://www.blogger.com/atom/ns#" term="Simulation"/><title type='text'>LTSPICE Based Self-Practice Questions</title><summary type="text">We have seen a lot of students facing problems while working on several basic concepts. To understand those concepts, it&#39;s very much required to do some testing and simulation and assess yourself how much you are able to grasp the concepts.

Below are few questions which you can try over LTSPICE yourself and understand the different design concpets. It will help you in VLSI Industry, the real </summary><link rel="related" href="www.vlsi-expert.com/ltspice-simulation-question.html" title="LTSPICE Based Self-Practice Questions"/><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4267174577593039162/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2022/01/ltspice-simulation-question.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4267174577593039162'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4267174577593039162'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2022/01/ltspice-simulation-question.html' title='LTSPICE Based Self-Practice Questions'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEjv4pFbzaADrR6Eura7J27VYWdgE5w0OXPzsYoohKMOBEvXSz_J8_lQSDgqJqiX-KfDm-matisQ67fuMpRZxXbS8bARj6XAHn0-k_F4AAHZ0f3OlfkkwTkgir_rN2KwdPB36mx7RMIqisb2tZf9fjtXOZ2O95Lb7X6Af35Iwm642r0vQkJzeRPm5gE7=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4782324974046201811</id><published>2021-06-06T09:32:00.002+05:30</published><updated>2022-01-17T17:28:46.559+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Latch"/><category scheme="http://www.blogger.com/atom/ns#" term="Latched based STA"/><category scheme="http://www.blogger.com/atom/ns#" term="Static Timing analysis"/><title type='text'>Latch Based Timing Analysis - Part 2 (Capture and Launch Edges)</title><summary type="text">
  In the last article (Latch Based Timing Analysis - Part 1) of this series, we have discussed general differences and correlation between Latch and Flipflop from Timing analysis point of view. We have discussed, how in case of Latches, Edges are also important and what&#39;s the significance of those edges.
Just to summarize or say refresh your memory, below are few points along with respective </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4782324974046201811/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2021/06/latch-based-timing-analysis-part-2.html#comment-form' title='1 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4782324974046201811'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4782324974046201811'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2021/06/latch-based-timing-analysis-part-2.html' title='Latch Based Timing Analysis - Part 2 (Capture and Launch Edges)'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi0pTpQXzoFLNvC0QFi29vJ_P41SkrW_JNq6tqV4XkxCMO53pLTd1WtWDlQAaMbhxodHA3XRN1rQX-Zd6e9J9Hi6fKTDK9es22VoSmxSuHApvsrrwW5LsKQgbP0XceGyPQxZfgHp01gnMk/s72-c/Latch+Waveform+2.PNG" height="72" width="72"/><thr:total>1</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-6326559777558747155</id><published>2021-05-31T00:09:00.010+05:30</published><updated>2021-05-31T00:48:55.848+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="high level synthesis"/><category scheme="http://www.blogger.com/atom/ns#" term="HLS"/><title type='text'>High Level Synthesis - Part 1 - Introduction</title><summary type="text">
High Level Synthesis is the technology of 21st Centuary. Lot of industry is working in this area and unfortunatly you will find very less information abou this. We as in VLSI Expert, always try to fill such gaps. These series of articles are going to give you an indept knowledge from basic to advance. Author of this article is Mr. Rishabh Jain (Senior Member Technical Staff, Mentor Graphics Pvt.</summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/6326559777558747155/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2021/05/high-level-synthesis-intro.html#comment-form' title='2 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6326559777558747155'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6326559777558747155'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2021/05/high-level-synthesis-intro.html' title='High Level Synthesis - Part 1 - Introduction'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7zoBqorZKWVs5FDA-rr5JTpxbTVXXWcko1CXcMxdyAbOaQWiQ1oQobNte3d4Ma-gAdEKFwC93OQnVqpsmSj-KnTVyUUmzxhRbcVa0D0IJRkK-VPgxxoL-ZiqPEiTOq1sj-9PsOL6SqWI/s72-c/Figure+3.png" height="72" width="72"/><thr:total>2</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4158108949503024222</id><published>2021-04-28T20:32:00.003+05:30</published><updated>2021-04-28T20:40:08.491+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Best case analysis"/><category scheme="http://www.blogger.com/atom/ns#" term="Operating Condition"/><category scheme="http://www.blogger.com/atom/ns#" term="Static Timing analysis"/><category scheme="http://www.blogger.com/atom/ns#" term="worst case analysis"/><title type='text'>Static Timing Analysis based on Operating Conditions</title><summary type="text">
Understanding of operating condition-based analysis is very important, if you really want to be expert in Static Timing Analysis. PVT (like Process, Voltage and Temperature) corners, Interconnect corners, Design Corners are all inter-related and these numbers are increases day by day. These are few topics where people have a lot of confusion (and there was time even I was at the same stage). </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4158108949503024222/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2021/04/Operating-condition-mode.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4158108949503024222'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4158108949503024222'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2021/04/Operating-condition-mode.html' title='Static Timing Analysis based on Operating Conditions'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgc1t7_WkYW6t-eu_cnB6uhIj0fL0psrK5z67WywbweXszEKvbCkuN53OvCXTZyR_iOi45nA6_NxwB2M2p36mxhtuAZQusekVUg2HPec23YBzRdai7W6qmqp0OepRCsEExg_1tLNobQ4Xc/s72-c/Circuit1.png" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-4662215115293553962</id><published>2019-12-23T20:44:00.001+05:30</published><updated>2021-06-06T06:47:30.542+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Flip-flop"/><category scheme="http://www.blogger.com/atom/ns#" term="Latch"/><category scheme="http://www.blogger.com/atom/ns#" term="Latched based STA"/><title type='text'>Latch based Timing Analysis - Part 1</title><summary type="text">This series we are starting for Latch based Timing Analysis. In case of Latch, there are lot of basic concepts which are similar to Flipflop based Timing but still we get confuse a lot of time, I am going to try my best to clarify that.

Let&#39;s first try to understand Flipflop Vs Latch when we are doing Timing analysis. You will see everything is almost same.


In the above circuit you can see </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/4662215115293553962/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/12/latch-based-timing-analysis-part-1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4662215115293553962'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/4662215115293553962'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/12/latch-based-timing-analysis-part-1.html' title='Latch based Timing Analysis - Part 1'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiG7g8LLwUU4E0JLIcsvzPkTvRTYmaLX7e_XhcNtcakO1GsxcsgG4YkQtKoS1org4t4j98szdO5cOmbfj3-ZaFHgumkUL_YYcVc66XiCScjOIPfg0Nbh_LDxwI4utAmzy939qC0tl9bm_c/s72-c/Latch+Vs+Flipflop+1.PNG" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-1807599552708701471</id><published>2019-12-14T18:57:00.001+05:30</published><updated>2019-12-14T18:57:34.848+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term=".sdf file"/><category scheme="http://www.blogger.com/atom/ns#" term="circuit diagram"/><category scheme="http://www.blogger.com/atom/ns#" term="Delay"/><category scheme="http://www.blogger.com/atom/ns#" term="SDF"/><category scheme="http://www.blogger.com/atom/ns#" term="SDF Constructs"/><title type='text'>How To Read SDF (Standard Delay Format) - Part5</title><summary type="text">
In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things
 SDF different sections and different construct - In PART 2
 Cell Section details - In PART 3
 Delay Details in SDF - In PART 4
Now. it&#39;s the time to discuss about the SDF using an example. 

Lets discuss the below circuit. 

As a part of SDF, if you remember, we have discussed in PART 2 - that there is </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/1807599552708701471/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/12/standard-delay-format-5.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/1807599552708701471'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/1807599552708701471'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/12/standard-delay-format-5.html' title='How To Read SDF (Standard Delay Format) - Part5'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-laVviWsQh8mcy7U_EPgQKg3L9qhgnZfpZ0Rcvu3rgA5ydy6MBbgou6SZ4dXs41l0HVc1BojP4Jq5nM6qU1il8hUfhgEyKZDpilFrKM28ZoClM1h2R_kOpTftCV9UEVSUkayGhrbRF7M/s72-c/example1.PNG" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-2224904163010027894</id><published>2019-12-12T18:34:00.000+05:30</published><updated>2019-12-12T18:34:10.297+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term=".sdf file"/><category scheme="http://www.blogger.com/atom/ns#" term="Absolute delay"/><category scheme="http://www.blogger.com/atom/ns#" term="conditional path delay"/><category scheme="http://www.blogger.com/atom/ns#" term="Delay"/><category scheme="http://www.blogger.com/atom/ns#" term="Incremental Delay"/><category scheme="http://www.blogger.com/atom/ns#" term="input-output delay"/><category scheme="http://www.blogger.com/atom/ns#" term="interconnect delay"/><category scheme="http://www.blogger.com/atom/ns#" term="Net Delay"/><category scheme="http://www.blogger.com/atom/ns#" term="Port delay"/><category scheme="http://www.blogger.com/atom/ns#" term="Sample SDF file"/><category scheme="http://www.blogger.com/atom/ns#" term="SDF"/><title type='text'>How To Read SDF (Standard Delay Format) - Part4</title><summary type="text">
In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things
 What is SDF and what information it contain? 
 Construct of SDF (2 Section – Header and CELL) 
 Header Section contain general information about the Tool which is used to create/generate the SDF and the Design related information (like Design name, Process, Voltage, Temperature of the design for which </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/2224904163010027894/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/12/standard-delay-format-4.html#comment-form' title='1 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2224904163010027894'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2224904163010027894'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/12/standard-delay-format-4.html' title='How To Read SDF (Standard Delay Format) - Part4'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjvqkahBdYryLrJvFHBZYWGRF2o96LJjfXkKkqDdlF7f4h56cl5hVGKt-e2jbOXShCANkCT8fGtY8oq-S5dRYt-U5h5Xn90GSUiF4O2YQYJzef8dbxCmi57VYE12gWcj7MPRj9urHZeVTY/s72-c/sdf+delay+table.PNG" height="72" width="72"/><thr:total>1</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-111434617586134579</id><published>2019-11-07T12:08:00.002+05:30</published><updated>2019-11-07T12:11:03.091+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="EDA tools"/><category scheme="http://www.blogger.com/atom/ns#" term="group_count"/><category scheme="http://www.blogger.com/atom/ns#" term="max_paths_count"/><category scheme="http://www.blogger.com/atom/ns#" term="OpenSTA"/><category scheme="http://www.blogger.com/atom/ns#" term="Primetime"/><category scheme="http://www.blogger.com/atom/ns#" term="STA"/><category scheme="http://www.blogger.com/atom/ns#" term="Static Timing analysis"/><title type='text'>STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 2</title><summary type="text">
In the previous part (STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 1) we have discussed about the switch -group_count for 1 circuit. As per our initial understanding -group_count is correspond to &quot;The number of paths to report in each path group&quot;. But when we have checked practically, we have noticed different behavior (Summarized in the below table).



  </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/111434617586134579/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/11/sta-group-count-command-2.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/111434617586134579'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/111434617586134579'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/11/sta-group-count-command-2.html' title='STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 2'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-laVviWsQh8mcy7U_EPgQKg3L9qhgnZfpZ0Rcvu3rgA5ydy6MBbgou6SZ4dXs41l0HVc1BojP4Jq5nM6qU1il8hUfhgEyKZDpilFrKM28ZoClM1h2R_kOpTftCV9UEVSUkayGhrbRF7M/s72-c/example1.PNG" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-5171218609716946408</id><published>2019-11-04T16:55:00.000+05:30</published><updated>2019-11-04T16:55:13.359+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="EDA tools"/><category scheme="http://www.blogger.com/atom/ns#" term="group_count"/><category scheme="http://www.blogger.com/atom/ns#" term="max_paths_count"/><category scheme="http://www.blogger.com/atom/ns#" term="OpenSTA"/><category scheme="http://www.blogger.com/atom/ns#" term="Primetime"/><category scheme="http://www.blogger.com/atom/ns#" term="report_timing"/><category scheme="http://www.blogger.com/atom/ns#" term="STA"/><category scheme="http://www.blogger.com/atom/ns#" term="Static Timing analysis"/><title type='text'>STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 1</title><summary type="text">
As, I have shared last time that in this series of articles, we are going to discuss about the different command of STA Tools along with the concepts. We have used OpenSTA which is an open source tool and can be downloaded from OpenSTA. It’s commands are similar to Primetime (Industry standard tool).  By using OpenSTA you can understand the working of tool properly. Here, I have made some of the</summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/5171218609716946408/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/11/sta-group-count-command-1.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/5171218609716946408'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/5171218609716946408'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/11/sta-group-count-command-1.html' title='STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 1'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-laVviWsQh8mcy7U_EPgQKg3L9qhgnZfpZ0Rcvu3rgA5ydy6MBbgou6SZ4dXs41l0HVc1BojP4Jq5nM6qU1il8hUfhgEyKZDpilFrKM28ZoClM1h2R_kOpTftCV9UEVSUkayGhrbRF7M/s72-c/example1.PNG" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-8169527459466834049</id><published>2019-10-16T14:27:00.001+05:30</published><updated>2019-10-16T14:27:49.619+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Awards"/><category scheme="http://www.blogger.com/atom/ns#" term="Employee"/><category scheme="http://www.blogger.com/atom/ns#" term="Workplace"/><title type='text'>10 Employee Awards To Boost Morale At The Workplace</title><summary type="text">




Employees function as
the backbone of any company and making sure that employee satisfaction is at
its highest is incredibly important for the smooth functioning of a
corporation. Employees who come in day in and day out are generally dedicated
to improving the manner in which the company works. They are one of the main
reasons why the company has been able to function as intended. For </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/8169527459466834049/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/10/10-employee-awards-to-boost-morale.html#comment-form' title='1 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8169527459466834049'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/8169527459466834049'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/10/10-employee-awards-to-boost-morale.html' title='10 Employee Awards To Boost Morale At The Workplace'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>1</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-6309776186398162592</id><published>2019-09-24T18:45:00.002+05:30</published><updated>2019-10-30T17:05:01.895+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="command"/><category scheme="http://www.blogger.com/atom/ns#" term="EDA tools"/><category scheme="http://www.blogger.com/atom/ns#" term="OpenSTA"/><category scheme="http://www.blogger.com/atom/ns#" term="Primetime"/><category scheme="http://www.blogger.com/atom/ns#" term="STA"/><title type='text'>STA Tool Command - report_timing -group (OpenSTA-path_group)</title><summary type="text">
We are going to start a new series where we are going to discuss about the different command of STA Tools along with the concepts. I have received a lot of requests about the tool understanding and their features. After discussing with them - I have figured out - problem is not HandsOn but it&#39;s all about mapping of different concepts (fundamental &amp;amp; Basics) with the Tool commands. So, in this</summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/6309776186398162592/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/09/sta-path-group-command.html#comment-form' title='1 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6309776186398162592'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/6309776186398162592'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/09/sta-path-group-command.html' title='STA Tool Command - report_timing -group (OpenSTA-path_group)'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi-laVviWsQh8mcy7U_EPgQKg3L9qhgnZfpZ0Rcvu3rgA5ydy6MBbgou6SZ4dXs41l0HVc1BojP4Jq5nM6qU1il8hUfhgEyKZDpilFrKM28ZoClM1h2R_kOpTftCV9UEVSUkayGhrbRF7M/s72-c/example1.PNG" height="72" width="72"/><thr:total>1</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-2092701544194695399</id><published>2019-05-24T20:00:00.000+05:30</published><updated>2019-05-24T20:00:14.487+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Bash Shell"/><category scheme="http://www.blogger.com/atom/ns#" term="Cshell"/><category scheme="http://www.blogger.com/atom/ns#" term="Fresher"/><category scheme="http://www.blogger.com/atom/ns#" term="Linux"/><category scheme="http://www.blogger.com/atom/ns#" term="unix"/><category scheme="http://www.blogger.com/atom/ns#" term="VLSI basics"/><title type='text'>Unix For VLSI Industry - Part 1</title><summary type="text">
Unix is universal and lot of Industry is using this. But still in our education system, it&#39;s not part of curriculum. And that&#39;s the reason lot of Students faces issues during Interview or after joining companies. Today, I am going to capture few of the commands, I have used in my career and I wish it will help everyone. From Interview point of view, if you will practice to all these - I am sure </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/2092701544194695399/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/05/unix-intro.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2092701544194695399'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/2092701544194695399'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/05/unix-intro.html' title='Unix For VLSI Industry - Part 1'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-420991888882288707</id><published>2019-05-14T00:35:00.035+05:30</published><updated>2022-02-03T20:15:26.370+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="Assignment"/><category scheme="http://www.blogger.com/atom/ns#" term="pass transistor"/><category scheme="http://www.blogger.com/atom/ns#" term="transmission gate"/><title type='text'>Transmission | Pass Gate - Assignment</title><summary type="text">
  Transmission gate or say Pass transistor (NMOS pass transistor and PMOS pass transistor) are one of the concept which is usually asked by Interviewer and most of the time candidates become confused. I will explain the concepts some other time but right now if you know then practice is very important or you should know what all they can ask and how they can twist the questions. 
  
  Please try</summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/420991888882288707/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2019/05/transmission-gate-assignment.html#comment-form' title='0 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/420991888882288707'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/420991888882288707'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2019/05/transmission-gate-assignment.html' title='Transmission | Pass Gate - Assignment'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/a/AVvXsEiUDi9thhAlFIBZwPNNgsaMLoBCvgu5yyeaFc5TbU3ELE8y2iUTJIXfu1raGTsdkythS7pOg_vGZAQ9A-ZQ44KNgjTIZpFVQkUNWdgGwr0i225Q_SzEsui4A1ONGxnRDrJC9fxy719p54fmk98xb6rbg9xd0uOmsrpUT4nmGZ49MmjYwk62W82mgZ3j=s72-c" height="72" width="72"/><thr:total>0</thr:total></entry><entry><id>tag:blogger.com,1999:blog-4597498589834570435.post-1009220789454388229</id><published>2018-11-29T19:38:00.000+05:30</published><updated>2018-11-29T19:38:31.714+05:30</updated><category scheme="http://www.blogger.com/atom/ns#" term="automation"/><category scheme="http://www.blogger.com/atom/ns#" term="practice"/><category scheme="http://www.blogger.com/atom/ns#" term="program"/><category scheme="http://www.blogger.com/atom/ns#" term="scripting language"/><category scheme="http://www.blogger.com/atom/ns#" term="task"/><category scheme="http://www.blogger.com/atom/ns#" term="TCL"/><category scheme="http://www.blogger.com/atom/ns#" term="VLSI"/><title type='text'>TCL Practice Task 4 (Scripting Language)</title><summary type="text">During the automation using TCL, sometime we have to ask inputs from the user even before running the program. One of the option is &quot;Template&quot; and other option is command line input. In the command line input, we uses switches which can help user to give input.
Example -file_name &quot;name_of_file&quot; . Here -flie_name is the switch and &quot;name_of_file&quot; is the input from the user. This type of program is </summary><link rel='replies' type='application/atom+xml' href='http://www.vlsi-expert.com/feeds/1009220789454388229/comments/default' title='Post Comments'/><link rel='replies' type='text/html' href='http://www.vlsi-expert.com/2018/11/tcl-practice-task-4.html#comment-form' title='2 Comments'/><link rel='edit' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/1009220789454388229'/><link rel='self' type='application/atom+xml' href='http://www.blogger.com/feeds/4597498589834570435/posts/default/1009220789454388229'/><link rel='alternate' type='text/html' href='http://www.vlsi-expert.com/2018/11/tcl-practice-task-4.html' title='TCL Practice Task 4 (Scripting Language)'/><author><name>VLSI Expert</name><uri>http://www.blogger.com/profile/01205530113106138349</uri><email>noreply@blogger.com</email><gd:image rel='http://schemas.google.com/g/2005#thumbnail' width='16' height='16' src='https://img1.blogblog.com/img/b16-rounded.gif'/></author><thr:total>2</thr:total></entry></feed>