Around this time back in 2004, I was discussing the possibility of joining Verilab's just-opened Austin office. My goals were pretty basic - I was unhappy in my job at a local startup, and was looking for a change. I figured I'd get some experience with international travel, and maybe learn a thing or two more about verification. Little did I know then where that journey would take me.
I made some great friends and learned a ton along the way, but after 9 years, I decided that it was again time to try something new. So back in August, I joined Cadence as a Sr. Architect. In my new role I'll be working across multiple groups and divisions at Cadence, and I may be popping up at various locations around the world as I ramp up on my position and Cadence products and services. I look forward to getting a chance to meet more of you face to face than I may have had an opportunity to do while at Verilab.
You may be wondering - why Cadence? Did something happen to turn me to the Dark Side of the Force? Possibly. But another explanation is that I was presented with an opportunity to make a positive impact on the EDA industry in collaboration with a group of people I have a lot of respect for. Is everything perfect here? No. But if it was, what would be the point of coming into work every day?
For my friends at other EDA companies, I hope we can still stay in touch. Things should be easier now. Many of you always harbored deeply-seated suspicions that I was on the Cadence payroll due to my never-ending passion surrounding Specman (except for folks at Cadence, who thought I was on the payroll of some other EDA firm, go figure!). And though those suspicions about Cadence were ill-founded in the past, they are certainly true now. So we all now know where we stand on the matter ;).
My writing on Cool Verification has been pretty limited over the last couple of years. I hope to keep going with the site, though it's possible my interests may change moving forward.
There are some significant challenges coming over the months and years ahead. If we're still designing and verifying chips using today's techniques 10-15 years in the future, we'll be in a world of hurt. It's exciting to have a chance to work on defining the future, and I'm looking forward to collaborating with all of you both inside and outside of Cadence to do so.
Every year at DAC, I'm amazed at how many engineers miss out on events attended by some of the most influential names in EDA. One example already this year was the Phil Kauffman award presentation earlier this evening, attended by Aart De Geus, Wally Rhines, Lip-Bu Tan, and Kathryn Kranen among others. Another example each year is the pavilion panel put on by the Women in Electronic Design Automation. This year's panel topic is "The Road to Success!". Here's the synopsis:
Don’t go it alone! How many times have you heard it? A lively panel of luminaries discuss how alliances are critical to our success, and cover networking and negotiating skills for achieving personal satisfaction and professional visibility. Also hear various perspectives on the importance of nonsense, and how to consciously incorporate humor and joy into your work life. An informative and inspiring event for both women and men, in electronics and EDA, at any stage in your career.
Moderator: Sashi Obilisetty - Synopsys, Inc., Mountain View, CA Panelists: Soha Hassoun - Tufts Univ., Medford, MA Jan Willis - Calibra Consulting, London, United Kingdom Kavita Snyder - Blue Pearl Software, Inc., Santa Clara, CA
The panel will be held Monday, June 3 from 1:30 to 2:30pm at the Pavilion (booth 509). Stick around after the panel to hear an interview with Nanette Collins, the 2013 Marie R. Pistilli Women in EDA Award recipient.
Earlier this evening, Gary Smith held his annual night-before-DAC talks at the Austin Convention Center . During his presentation, Gary laid out his vision of the EDA industry over the next 10-15 years. There were many interesting points in the presentation (see Richard Goering's writeup for more details). One comment in particular stood out:
"Not as many RTL guys are moving up into ESL. They're really not capable of grasping the software end of it. So what we're getting is a lot of brand new engineers, young guys... They're young guys, they can do the software, they can do the hardware..."
My question to Gary during the session was to ask whether or not he was suggesting that ESL was being held back by senior design engineers, and that the migration to ESL might simply have to wait until a new crop of engineers with a background that included both hardware and software might be required to fully make the move to the newer design style.
Gary pointed out that when synthesis started making inroads into digital design, only 40% of blocks were being synthesized, and that number increased over time as newly designed blocks replaced blocks that were being reused. He feels the same trend is likely to occur here.
What do you think? Is ESL simply going to have to wait until there start to be a critical mass of IP blocks written in that style before it really takes off? Or is the issue simply one of training, where a differently-trained group of engineers will eventually be required to really get the ball rolling?
What, if anything, is holding back the adoption of ESL?
Last year, the folks at Oski effectively locked one of their engineers in a room for the duration of DAC to see if they could formally verify a design module they had not previously seen. This year, they're focusing less on the drama and more on providing DAC visitors tip and tricks on how to use formal verification techniques on your next project by presenting episodes of their new video series "Decoding Formal" throughout the day.
Stop by and visit Oski at booth #718. Each hour, starting at 9:30am, they will show a new video from the series. Come back at 5:15pm on Monday, June 3 and again on Tuesday, June 4 to compete for prizes in the live "Decoding Formal" trivia challenge.
You can also play the challenge online at http://www.surveymonkey.com/s/DecodingFormal
Good luck!