ee-diary

True Advantages for Electrical & Electronics Engineers in the Future

2026-10-15T11:13:40.167+05:45

True Advantages for Electrical & Electronics Engineers in the Future

The Physical Reality Constraint (Physics Can't Be Prompted): AI can write Python scripts or Verilog templates, but it cannot escape the laws of physics. Signal integrity, electromagnetic interference (EMI), thermal dissipation, parasitic capacitance, and power delivery networks require human intuition and hands-on validation. An AI model can suggest a circuit topology, but debugging why a switching regulator is oscillating or why a PCB trace is acting as an antenna requires physical debugging skills (like using oscilloscopes and spectrum analyzers).
The Custom Silicon & Semiconductor Boom: As general-purpose Moore's Law slows down, the tech industry relies entirely on Domain-Specific Architectures (ASICs, FPGAs, TPUs, and neuromorphic chips) tailored specifically for AI workloads. Electrical and microelectronics engineers are the only ones capable of designing, verifying, and taping out these specialized chips.
Edge AI and Embedded Integration: The future of AI is at the edge—running local models on microcontrollers, IoT sensors, and autonomous drones. Bridging high-level machine learning frameworks with low-level microcontrollers (like ESP32s, STM32s, or RISC-V cores) requires engineers who understand both firmware and hardware peripherals (ADCs, I2C, SPI, power management).
Power Infrastructure & Energy Crisis: AI data centers and electric vehicle infrastructure demand unprecedented amounts of electrical power. Power electronics engineers—those designing high-efficiency DC-DC converters, inverters, grid ties, and battery management systems—are facing a massive talent shortage. AI cannot generate megawatt-scale power grids or high-frequency switch-mode power supplies out of thin air.

What Electrical & Electronics Engineers Should Focus On

To stay indispensable and dominate the next decade of technology, EEs should focus on these key pillars:

1. Hardware-Software Co-Design & Embedded AI (TinyML)

Focus: Learn how to deploy lightweight machine learning models onto resource-constrained microcontrollers and edge devices.
Why: Knowing how to interface sensors, optimize C/C++ firmware, and manage memory constraints lets you build smart, autonomous hardware products that pure software engineers cannot touch.

2. Advanced Power Electronics & Energy Systems

Focus: Master switch-mode power supply (SMPS) design, wide-bandgap semiconductors (SiC and GaN transistors), battery management systems (BMS), and thermal management.
Why: Everything from AI server racks to electric vehicles and renewable energy grids requires aggressive power optimization.

3. High-Speed Digital Design & FPGA/ASIC Development

Focus: Deepen your knowledge of HDL (Verilog/SystemVerilog), high-speed PCB layout techniques (controlled impedance, differential routing), and FPGA prototyping.
Why: Custom acceleration hardware is the backbone of modern AI infrastructure.

4. AI-Assisted Engineering Tools

Focus: Embrace AI design assistants (like automated routing tools, SPICE optimizers, and AI-driven debugging) as force multipliers rather than threats.
Why: Engineers who know how to leverage AI tools to automate tedious schematic capture or documentation tasks while applying rigorous engineering judgment will vastly outperform those who ignore them.

F8205A Spice Model | Proteus Library & Simulation Test

2026-10-14T21:21:05.743+05:45

The FS8205A is a dual N-channel enhancement-mode MOSFET integrated circuit, commonly utilized in battery protection circuits, power management systems, and load switching applications due to its low on-resistance and high-speed switching capabilities. It is specifically designed to act as a compact, efficient switch for protecting lithium-ion battery packs against overcharge, over-discharge, and over-current conditions.

Download F8205A Spice Model

The model uses only standard SPICE3 elements (M, R, C, D, .MODEL with LEVEL=1) and plain .SUBCKT/.ENDS, so it should work in ngspice, LTspice, KiCad (which uses ngspice) and Proteus. The parts that differ are the symbol and pin-order setup, not the model itself.

Download F8205A Proteus Library with Spice Model

Regarding the F8205A SPICE model, it is a critical component for virtual prototyping in circuit simulator software like Proteus, KiCAD, Altium designer, LTspice, Ngspice etc, allowing engineers to simulate the electrical behavior of the MOSFET within a circuit before physical implementation. Here this F8205A spice model was integrated into Proteus for test simulation. The test simulation can verify thermal performance, switching losses, and transient responses, ensuring the design meets reliability standards under various load conditions.

FS820A Bidirectional Switch Behavior Test Circuit

A bidirectional switch, in the context of dual MOSFETs like the FS8205A, refers to a configuration where two MOSFETs are connected in a back-to-back (common-source or common-drain) arrangement to control current flow in both directions. In a standard single MOSFET, the internal body diode inherently allows current to flow from source to drain even when the device is "off." By placing two MOSFETs in series with opposing body diodes, the circuit gains the ability to completely block current in both directions when the gates are pulled low.

This behavior is of paramount importance for several reasons:

Battery Protection: In lithium-ion battery management systems (BMS), a bidirectional switch is essential to independently disconnect the battery from the charger (to prevent overcharging) and from the load (to prevent over-discharging). A single MOSFET would fail to stop current flow in one of these directions due to its body diode.
True Isolation: It provides a reliable "off" state that is immune to voltage fluctuations on either side of the switch. This is critical for safety-critical applications where you must ensure that no current can leak into or out of a power source.
Verification in Simulation: Verifying this in Proteus is vital because it allows you to test the "blocking" capability under various fault conditions. You can simulate a scenario where the battery voltage is higher than the charger voltage (or vice versa) and confirm that the dual MOSFET configuration successfully prevents current flow. Without this verification, you risk designing a protection circuit that remains "leaky" or fails to engage during a critical over-voltage or under-voltage event.

By using the FS8205A SPICE model in Proteus, you can probe the voltage across the common node and the current through the pair to ensure that both MOSFETs are correctly biased to achieve the desired bidirectional blocking state.

Schematic. V3 feeds the 10 Ω resistors (still labeled RL) into S2 (pins 6/7). S1 (pins 2/3) is grounded, D is open, V1 drives G1 (pin 4) through R1, and V2 drives G2 (pin 5) through R2. That is the setup I described.

Plot. The gate timing is: G1 is on 5–10 ms and 15–20 ms, and G2 is on 10–20 ms.

The current follows:

Window	Gates	What the plot shows	Expected
0–5 ms	both off	almost no current	blocked
5–10 ms	G1 only	positive halves only, about +40 mA	positive half passes through the body diode (DB2)
10–15 ms	G2 only	negative halves only, about −40 mA	negative half passes through DB1
15–20 ms	both on	full sine, about ±100 mA	1 V / 10.05 Ω ≈ 100 mA

The 5–10 ms and 10–15 ms windows are mirror images, so the two FETs are matched.

About the 40 mA. My earlier estimate of 28 mA was too low. I used the datasheet's 0.72 V diode drop, but that is specified at a higher current. At 40 mA the diode drops only about 0.55 V, which gives (1 − 0.55) / 10 ≈ 45 mA, matching the plot.

The small negative blips at the negative peaks. You see them in 0–5 ms and 5–10 ms, not in the other windows or on the positive peaks. They are not a model error. When S2 swings below −0.8 V, the "off" gate (G2, tied to ground through 100 Ω) has VGS = +0.8 V or more relative to its source, so M2 turns on weakly. A real FET with Vth = 0.8 V does the same. To remove them, use a smaller sine amplitude (about ±0.5 V). The diode-clipped windows then show almost no current, which also demonstrates blocking cleanly. For a figure for your blog, I'd keep ±1 V and note the effect in the caption.

DW01A/DW01P Spice Model | Download battery protection device spice model

2026-10-13T16:31:35.977+05:45

DW01A/DW01P lithium-ion battery protection IC is designed to protect the 3.7V li-ion battery from over-voltage (charging) or under-voltage (discharging). I made a spice model of DW01A IC and tested it via simulation in Proteus. This can be downloaded from the link below.

Download DW01A Spice Model

DW01A Spice Model Test Bench Circuit

The test bench circuit for checking the DW01A IC is used below.

The test bench circuit with the simulation waveforms demonstrate that the SPICE model for the DW01A/DW01P lithium-ion battery protection IC is working as expected.

Explanation of the Test Bench Circuit

The DW01A is a single-cell lithium-ion/polymer battery protection IC designed to protect against overcharge, over-discharge, and over-current conditions.

Power Supply & Inputs: Pin VCC (5) and Pin GND (6) provide the IC operating voltage (driven here by the Vin generator).

Over-Charge / Over-Discharge Control Outputs:

Pin OD (1) controls the discharge protection MOSFET.
Pin OC (3) controls the charge protection MOSFET.
Both outputs are pulled up via resistors R1 and R2 to observe their logic states clearly.

Current Sense: Pin CS (2) monitors the voltage drop across the protection circuit to detect over-current conditions (tied to ground in this test configuration).

How the Waveforms Show the Model is Working

The graph plots the input voltage ramp against the internal protection states over a 20-second simulation period:

1. Normal Operating Region (4.3V > Vin > 2.3V):

Initially, when Vin is within safe voltage limits, both U1(OD) and U1(OC) are high (≈5V), meaning both charging and discharging switches are enabled.

2. Over-Charge Protection Trigger (Vin > 4.3V):

At approximately t = 1.45s, Vin rises above the over-charge detection threshold (typically around 4.3V).
The waveform for trace U1(OC) immediately drops to 0V, signaling the charging MOSFET to turn off and block further charging.

3. Over-Discharge Protection Trigger (Vin):

At approximately t = 1.45s, Vin rises above the over-charge detection threshold (typically around 4.3V).
The waveform for trace U1(OC) immediately drops to 0V, signaling the charging MOSFET to turn off and block further charging.

As Vin returns to normal operating ranges, the outputs recover accordingly, confirming that the SPICE model accurately reproduces the protection thresholds and gate-drive behavior of the DW01A.

The expected DW01A expected charging profile and the OC (Over Charge), OD (Over Discharge) and CS (Current Sese) is shown below.

The DW01A/DW01P datasheet provides the internal functional circuit diagram of DW01A which is shown below.

3.7V Li-Ion battery circuit model for simulation

2026-10-11T18:17:48.603+05:45

I wanted to share circuit schematic of a 3.7V Li-Ion battery simulation model for simulation.

The 3.7V Li-ion battery model implemented as a hierarchical subcircuit shown above uses a clever combination of analog behavioral sources, a specialized capacitor, and switches to dynamically mimic the charge, discharge, and terminal voltage characteristics of a real lithium-ion cell.

Li-Ion Battery Proteus Library | Download Free

Watch the following video that operation of the Li-Ion battery circuit model in action.

Here is a breakdown of how the key components inside the subcircuit work together:

1. Energy Storage & Capacity (C1)

Component: [C1] (Capacitor valued at 1F with model ACTVCAP and attribute VMAX="3.7").
Function: In this model, capacitance represents electrical charge (Ampere-hours or Coulombs) rather than standard electrostatic capacitance. The voltage across this capacitor corresponds directly to the state-of-charge (SoC) / open-circuit voltage of the battery.

2. State-of-Charge & Current Integration (ACS1 & AVS1)

Components: [ACS1] (Current Source) and [AVS1] (Voltage Source) configured with algebraic expressions.
Function: These controlled sources act as an integrator/translator network. ACS1 senses the terminal current and injects/extracts equivalent charge into the charge-storage capacitor [C1] based on the capacity scaling attributes (such as the SDR / discharge rate parameters passed from the parent sheet).

3. Internal Resistance (R1)

Component: [R1] (Resistor valued at 0.7mΩ).
Function: Represents the internal equivalent series resistance (ESR) of the battery. When current flows into or out of the battery, this resistor causes the instantaneous voltage sag or charge-overvoltage observed at the terminals [B1:+] / [B1:-].

4. Voltage Protection / Limits (S1, D1, D2, V2)

Components: Voltage-controlled switch [S1], diodes [D1], [D2], and pulse/bias source [V2].
Function: This circuitry handles boundary conditions—such as cutting off discharge when the cell voltage drops too low or regulating behavior near full charge limits (4.2V max / 2.5V / 3.0V cutoffs)—preventing the behavioral capacitor from unphysically over-charging or over-discharging.

Summary

In short, instead of representing a battery as a simple ideal DC voltage source with a series resistor, this Li-Ion subcircuit models the nonlinear discharge curve and charge capacity of a real chemistry cell dynamically as you draw current from or feed current into it in the root schematic.

See also the spice version or spice model of Li-Ion Battery:3.7V Li-Ion Battery Spice Model | Download Free

SimulIDE Circuit Simulation Software: Introduction with amplifier simulation

2026-10-11T14:41:37.178+05:45

The following video shows how to use SimulIDE circuit simulation software with BJT amplifier design and simulation.

QUCSS introduction with RC Filter Tutorial

2026-10-11T13:43:26.809+05:45

I tried QUCS-S electronics circuit simulator/software for the first time, and I recorded a video on it. The video shows the UI interface, what kind of tools and libraries are available. The using the help menu, an RC low pass filter is created and simulated (AC analysis and Transient analysis).

How to connect 5V relay with ESP32-S3 for Motor Control?

2026-10-07T18:38:59.261+05:45

The following circuit diagram shows how to connect 5V relay module with ESP32-S3 to control a DC motor.

Here is a complete breakdown of how your circuit is wired, how each component interacts, and how the MicroPython firmware controls everything.

1. How the ESP32-S3 is Powered

Power Supply (B1 / VCC): The ESP32-S3 board is powered by a 5V DC source connected to its VCC / 5V pin.
Ground (GND): The system shares a common ground rail (GND), connecting the battery, motor, relay module, and microcontroller together to ensure a complete return path for current.

2. How the ESP32-S3 is Connected to the Relay

Control Signal (GP5):

GPIO pin 5 on the ESP32-S3 is wired to the IN pin of the relay module.
The ESP32-S3 acts as the brain: it outputs either a HIGH (3.3V) or LOW (0V) signal on GP5 to command the relay.

Relay Power:

The relay module's power pins are connected to +5V (V) and GND (G) so that its internal transistor/optocoupler and electromagnetic coil have enough power to operate.

3. How the Motor and Relay Switch are Connected

A relay acts as an electrically operated switch that isolates the low-voltage control circuit (ESP32-S3) from the high-power circuit (12V motor):

High-Power Source (BAT1): A 12V battery powers the load. Its positive terminal is connected to the relay's R_COM (Common, pin 5) terminal.
Motor Control Path:

One side of the 12V DC motor is connected to the relay's R_NO (Normally Open, pin 7) terminal.
The other side of the motor is connected directly to GND.

Switching Action:

Relay OFF: The switch inside the relay is open, so no current flows from R_COM to R_NO. The motor stays OFF.
Relay ON: When commanded, the relay coil energizes, pulling the internal switch closed between R_COM and R_NO. This completes the 12V circuit, allowing current to flow from the battery through the relay and into the motor, turning it ON.

4. How the Input Switch is Connected

Pushbutton (SWITCH):

Connected between GP40 (on the right side of the ESP32-S3) and GND.
When pressed, it pulls GP40 to 0V (LOW). When released, the internal pull-up resistor keeps GP40 at 3.3V (HIGH).

5. Explanation of the MicroPython Code (main.py)


from machine import Pin
from time import sleep

# Configure Relay pin on GP5 (Connected to Active-Low Relay Module IN)
# For Active-Low: LOW (0) turns the relay ON, HIGH (1) turns it OFF
relay = Pin(5, Pin.OUT)

# Configure Switch/Button pin on GP40 (Right side of the ESP32-S3 board)
switch = Pin(40, Pin.IN, Pin.PULL_UP)

print("Starting ESP32-S3 Active-Low Relay & Switch Control...")

while True:
    # Read switch state (0 when pressed)
    if switch.value() == 0:
        print("Switch pressed on GP40 -> Motor ON (Relay LOW)")
        relay.value(0)  # Active-Low: LOW turns relay ON
    else:
        print("Switch released on GP40 -> Motor OFF (Relay HIGH)")
        relay.value(1)  # Active-Low: HIGH turns relay OFF
        
    sleep(0.1)  # Polling delay / debounce

This MicroPython script continuously runs an infinite loop (while True) that monitors the state of a pushbutton switch connected to input GP40 (held HIGH by an internal pull-up resistor), and controls an active-low relay module wired to output GP5. When the switch is pressed, it pulls GP40 to 0 (LOW), causing the script to output 0 (LOW) on GP5, which energizes the active-low relay to close its contacts and turn the motor on; conversely, when the switch is released, GP40 returns to 1 (HIGH), prompting the script to output 1 (HIGH) on GP5 to de-energize the relay and turn the motor off, with a short 0.1-second sleep delay included in each cycle to prevent excessive CPU usage and debounce the switch.

If you want the ESP32-S3 Devkit Proteus library and 5V relay library for simulation, click on the download link below:

You can find other proteus models in the following download link:

Free Electronics Download Hub | Proteus, PIC, STM32 & PCB Files

MT3608 Module | Proteus Library | Model Download Free

2026-10-07T01:42:16.725+05:45

Here you can download MT3608 Module Proteus Library (animated model) for proteus simulation. MT3608 module is a step-up converter or boost converter that you can use to step up voltage from 2V to 24V. This can be used with Arduino and in other electronics circuit design and simulation.

Download and Install

MT3608 Module | Proteus Library | Model Download Free

How to install?
Download and Unzip the file. A folder is created with two files MT3608.MDF and MT3608_Module.lib.
Copy the MT3608.MDF into Model folder and MT3608_Module.lib. into the Library Folder

Testing MT3608 module in Proteus

Once you have downloaded the MT3608 module you can test the module in the in proteus using the following setup. The diagram shows how to connect the module to the power supply B1 which is 3.7V and this converter takes this voltage and then boost it to 15V. The potentiometer resistance is set configured via properties, so that the output of this module is 15V or any other voltage between 2V to around 24V. And across the module output we have connected a 12V lamp, so 15V output is enough for 12V lamp, and you can also set to 12V using the potentiometer resistance value. So, this is for demonstration you can also connect a variable resistor here and then check the voltage across the output because this regulator so that whatever the resistance you connect here the output voltage Should remain mostly the same. See How boost converter (MT3608) circuit works? and also MT3608 Boost Converter IC Testing and Simulation for more detailed internal circuit operation information.

About MT3608 Boost Converter Module

The MT3608 boost converter module is a small, low-cost DC-DC step-up power supply module based on the MT3608 switching regulator IC. It can increase a low input voltage, typically around 2–24 V DC, to a higher adjustable output voltage of up to approximately 28 V, using an onboard potentiometer for voltage adjustment. The module is commonly used in battery-powered projects, Arduino and ESP circuits, LED drivers, and other applications where a higher voltage is required from a lower-voltage source. It is compact and efficient for low-power applications, although the available output current depends on the input/output voltage and thermal conditions.

MT3608 Module Video Demonstration

The following video shows how to use the MT3608 proteus simulation model.

If you want only MT3608 IC spice model then you can download it from Download and Test MT3608 spice model in ngspice electronics circuit simulator.

If you are interested in other voltage converter module, see AMS1117 Modules Proteus Simulation Models | Free Download.

I also suggest trying out the 3.7V Rechargeable Li-Ion Battery Proteus Library and boosting its voltage to higher voltage like 5V for powering up Arduino Proteus Model or use it to drive motors using motor driver module.

How boost converter (MT3608) circuit works?

2026-10-06T22:48:13.427+05:45

This is a note on how boost converter IC like MT3608 internal circuit works. For example, the MT3608 IC has 6 pins IN, SW, EN, FB, VSS and NC. Other voltage converter IC have similar pins. The VSS is the ground pin, and NC is No Connection pin which means no connection is required. EN is enable which needs to be held high to enable the chip and IN pin is the input dc supply pin which we want to step up. So, the main pins actually are the SW and FB. The FB is the feedback input pin, which samples the output signal and feed backs into the circuit. The SW pin is the switching pin which connects to the junction of diode and inductor of a boost converter.

Now, below the circuit diagram shows the internal circuit schematics of boost converter/step up converter IC like MC3608.

Note that the above circuit also shows the external circuit component besides the internal IC circuit. Compare the first and this 2nd circuit to find out which are external components.

So here I am going to tell the overall operation of this step up or boost converter. The input voltage 3.7V which is to be stepped up is connected across the VIN+ and VIN- pins. The capacitor C1 acts as noise filter which is connected across the battery. The EN and the IN pins of the internal boost converter IC is connected to the 3.7V dc power source. The 22uH inductor is also connected to the +ve side of the voltage input pin. After the inductor is the diode which is facing towards the output voltage node. Between the diode and inductor is connection to the switch SW pin of the internal boost converter IC. At the output we have a noise decoupling capacitor C2 of 22uF. RL is the load and the boosted voltage appears across the VOUT+/VOUT-.

Power On Sequence with Initial Condition

At t = 0 everything is at zero: $V_{out}$ = 0, $I_L$ = 0, all capacitors $C_{comp}$, $C_d$ and $C_{d1}$ are discharged, $V_{err}$ = 0, and $Q$ = 0.

VIN below 1 V. Both EN (Enable) and UVLO (Under Voltage Lock Out) comparators outputs are low since $V_{in}$ is below 1V, lower than both comparator reference voltages are 1V and 1.9V, so it does not exceed both comparator reference voltages. So, the output of AND gate $V_{on}$= 0V (Logic 0), The NAND output $V_{on}$ is 5V (Logic 1), so $V_{rst}$ = 5V (Logic 1) and $Q$ is held at 0. The switch cannot turn on whatever the clock does.
The converter is still not isolated. Even with Q1 off, there exist direction path from input to output, that is, $V_{in}\rightarrow L \rightarrow D \rightarrow V_{out}$ is a direct path from the battery. It is an LC circuit with $Z_0 = \sqrt{\frac{L}{C}} = \sqrt{\frac{22\,\mu\text{H}}{22\,\mu\text{F}}} = 1\,\Omega$ and $f_0 = \frac{1}{2\pi\sqrt{LC}} = 7.2\,\text{kHz}$. The inrush peaks near $\frac{V_{\text{in}} - V_f}{Z_0}$, which is a few amps in the ideal limit (less after the battery resistance and ESR). COUT can overshoot to about $2(V_{in}-V_{fb})$, roughly 6.5 V, before the diode blocks. This is normal for a boost converter and is not caused by the controller.
VIN above 1.9 V. In this case, $V_{on}$= 5V (Logic 1), so RESET releases as long as $V_{or} $= 5V (Logic 1) and $V_{dc}$ = 5V (Logic 1).
Vref starts from V1, a pulse source. If its rise time is non-zero, that is soft start. At first $V_{fb} ≈ 0$, so $V_e = V_{ref}-V_{fb} > 0$(note:$V_{err} = 100\times V_e$)$, C_{comp}$ charges and $V_{err}$ rises.
While Verr is still low, $V_{sum}$ is already above $V_{err}$, so $V_{pwm}$ = 0. The only thing keeping Q1 on is the 60 ns delay on $\bar{Q}$. The first pulses are therefore a few tens of ns wide, which is the minimum on time.
Verr climbs, the pulse width grows, $I_L$ builds, and $C_{OUT}$ is pumped up toward 15 V. As $V_{fb}$ approaches $V_{ref}$, $Ve \rightarrow 0$ and the loop settles.

Error Amplifier with Compensation Network

Once the circuit is powered up, the error amplifier compares the sampled feedback output $V_{fb}$ with $V_{ref}$=0.6V signal. The output signal $V_{err}$ is given by,

$$V_{err}= A_v(V_{ref}-V_{fb})$$

where $A_v$ is voltage gain, set to 100 in this circuit, $V_{ref}$=0.6V is voltage reference and $V_{fb}$ is the output feedback signal which is defined as,

$$V_{fb}= V_{in} \frac{R_2}{R_1+R_2}$$

If $V_{ref} > V_{fb}$ then $V_{err}$ is +ve, this allows to create PWM signal that turns on/off the N-channel MOSFET switch with some duty cycle.
If $V_{ref} \leq V_{fb}$ then $V_{err}$ is -ve, this leads to PWM signal with duty cycle 0, that is no PWM signal, and the MOSFET switch is off.

The following graph shows the $V_{err}$,$V_{ref}$,$V_{fb}$ signals waveform for $ V_{out}$=12V and $ V_{in}$=3.7V.

The error signal $V_{err}$ is then compared with sawtooth signal $V_{sum}$ and PWM signal with duty cycle proportional the $V_{err}$ magnitude is created.

Loop Compensation Network

PWM Comparator

The PWM signal $V_{pwm}$ generated by the PWM comparator by comparing magnitude of $V_{err}$ and $V_{sum}$ signals, where $V_{sum}$ is the signal generated by adding $V_{saw}$ signal and $V_{cs}$ signal.

$$V_{sum}= V_{cs} + V_{saw}$$

$$V_{pwm}= [ V_{err} > V_{sum}]$$

OR Gate

It forces Vor high for about 42 ns after turn-on. This is leading-edge blanking and a minimum on-time, so the turn-on spike or a very low Verr cannot end the pulse instantly.

Delayed Vqbar	Vpwm	Vor (Output)
0	0	0
0	1	1
1	0	1
1	1	1

NAND Gate

It has three inputs $V_{on}$, $V_{or}$ and $V_{dc}$ and one output $V_{rst}$. The $V_{dc}$ forces a reset at the end of the maximum-duty window, which limits D.

Since it is a 3-input NAND gate, the output is low (0) only when all three inputs are high. Otherwise, it is high.

Vdc	Vor	Von	Vrst (Output)
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

D Flip Flop

The function of the D flip flop is to turn on/off the MOSFET switch at the frequency set by the incoming clock which for MT3608 is 1.2MHz.

In this switching power supply controller, the DFF acts as the primary PWM latch:

CLK Input: Driven by the clock oscillator(CLK), the rising edge of the clock initiates a new switching cycle by setting the Q output HIGH, which turns on the power MOSFET gate drive.
DATA Input: Tied to a fixed high/low state or power rail to determine the state to be clocked through.
RESET Input: Driven by the NAND gate output (VRST). When the current limit, maximum duty cycle, or PWM comparator trips, VRST goes high, immediately resetting Q LOW to terminate the power pulse before the next clock cycle.
$Q$ and $ \bar{Q}$: Outputs: Q drives the gate driver path, while $ \bar{Q}$ feedback to logic/blanking circuits via the RC network($R_d$, $C_d$)

Truth Table for a Standard D-Type Flip-Flop (with Asynchronous Reset)

RESET	CLK	D	$Q$ (Next State)	$ \bar{Q}$ (Next State)	Description
1	X	X	0	1	Asynchronous Reset (Forces Q low immediately, active state in your circuit)
0	$\uparrow$ (Rising)	0	0	1	Latches a Logic 0
0	$\uparrow$ (Rising)	1	1	0	Latches a Logic 1
0	0 or 1	X	Q (prev)	$ \bar{Q}$ (prev)	Hold State (No change between clock edges)

MOSFET Switch

It regulates the input voltage $V_{in}$ to the output determined by duty cycle determined by the PWM comparator. The 10Ω resistor is gate resistor $R_g$ to limit current into the gate and $R_{pd}$ 100kΩ is pull-down to keeps the N-channel MOSFET switch Q1 off if the gate drive state is undefined.

Current Sense Amplifier

The current sense amplifier senses the voltage across the current-sense resistor $R_s$ ($V_{sense} = I_L R_s$) with a gain $A_{cs}$(=40).

The output of the current sense op-amp passes through a low-pass RC filtering/delay network formed by $R_{d1}$ and $C_{d1}$. The resulting waveform $V_{cs}$ as a function of the amplifier output $V_{ampout}$ and amplifier output voltage equation are below

Capacitor Voltage Equation:

$$V_{cs}(t) = V_{ampout}(0) + (V_{ampout}(\infty) - V_{ampout}(0)) (1 - e^{-\frac{t}{R_{d1}C_{d1}})$$

Amplifier Output Voltage Equation:

$$V_{\text{amp\_out}} = A_{\text{cs}} \cdot (I_L \cdot R_S) = 40 \cdot I_L \cdot R_S$

Summed Signal Equation:

This summed signal is compared with the PWM comparator output:

$$V_{sum}=V_{cs}+V_{saw}$$

See related blog posts:

MT3608 Boost Converter IC Testing and Simulation

2026-10-05T12:52:26.314+05:45

So, I tried to build MT3608 Boost Converter IC model in Proteus. What I have built is the sub-circuit of the MT3608 Boost Converter. The diagram of the sub-circuit is shown below.

The following graphs show signals at various circuit nodes.

Graph 1: loop and regulation

Vout: shows whether it reaches 12 V and how it overshoots.
Vf: should settle at 0.6 V.
Verr: should settle between 0 and 5 V. At 220 Ω I expect about 3 V, and it should no longer sit at 1 V.

Graph 2: PWM decision (zoomed, a few cycles)

Vsum (the ramp plus the current-sense term)
Verr, overlaid on it, so you can see exactly where Vsum crosses it
Vpwm (the comparator output)

Zoomed in:

Graph 3: logic chain

CLK (V2)
RD/CD node (the delayed Q!)
Vor (the OR gate output). Confirm which node your current "Vor" probe is on, because I suspected earlier it was the RD/CD node.
Duty-cycle source (V4)
NAND output (the reset to U5)
Q1 gate (after R1)

Reading this graph left to right shows whether the delays you set are doing what you expect: CLK sets Q, Vpwm (via Vor and the NAND) resets it, and the gate follows.

Graph 4: power stage (zoomed)

SW (Q1 drain)
I(L1): tells you CCM or DCM and the peak current
I(D1): confirms DCM ringing (it should hit zero before each turn-on) and shows any reverse recovery
I(Q1) or the voltage across RS: confirms the peak current stays under your limit

Analysis:What your plots shows

No runaway: peak inductor current is about 0.13 A, versus several amps before. Soft start has fixed the startup problem.
Inductor ramp: I(L1) rises at about 0.8 A/µs, which matches Vin/L = 3.7 V / 4.7 µH. The model is behaving like a real inductor.
Diode: I(D1) overlaps I(L1) while SW is high and is near zero during the on-time, as it should be.
Operating mode: the inductor current has decayed to about zero right when Q1 turns on again, so you are at the DCM/CCM boundary. The small dip in Vsw just before each turn-on (4.9 V to 4.7 V) is the start of DCM ringing.
Cycle timing: the period is about 0.83 µs, matching 1.2 MHz.

What to check

On-time (gate high) should equal the interval from CLK to Vsum crossing Verr, plus your ~10–20 ns delays.
At 220 Ω, I(L1) peak should be about 0.4 A with Verr about 3 V. If Verr is correct but the output is still low, the problem is in the power stage rather than the loop.
The Q1 gate should never be high at the same time as a long Vpwm-low period, which would mean the reset isn't working.

If you add the I(L1) and I(D1) probes, I can also confirm my earlier explanation of the sub-0 V SW dip. Send me the zoomed plots once the rail is fixed and I'll go through them with you.

See further:

Download and Test MT3608 spice model in ngspice electronics circuit simulator

2026-10-03T22:17:10.376+05:45

This is note on how to download and test MT3608 spice model using free ngspice electronics circuit simulator.

MT3608 Step Up/Boost Converter IC

MT3608 is a popular boost converter IC, inexpensive with high efficiency.

MT3608 Spice Model | Download Free

Key Specifications

Specification	Value
Input Voltage Range	2V to 24V DC
Output Voltage Range	Adjustable, from 5V up to 28V DC
Maximum Peak Current	2 Amps (1A or less recommended for continuous use without a heat sink)
Switching Frequency	1.2 MHz (Allows the module to use tiny components)
Peak Efficiency	Up to 93% – 97%

Testing MT3608 spice file

Here we will use ngspice free electronics simulator to check whether the MT3608.LIB spice circuit works or not.

Download ngspice simulator if you don't already have.

Double click on the ngspice.exe application.

There are two ways to test the MT3608 spice model in ngspice simulator.

Use the mt3608_test.cir testbench file which incorporates MT3608 spice model
Use MT3608_testbench.cir testbench file and include MT3608 spice model separately

The required files are below.

MT3608.LIB


* ============================================================
* MT3608 - behavioral model (peak-current-mode boost, 1.2 MHz)
* SPICE3F5-compatible: NO B (arbitrary) sources. Uses only
* R, C, E, G, H, V (DC/PULSE) and S (SW model) elements.
* Built from the Aerosemi datasheet block diagram (Figure 3).
* Simulated OK in ngspice: 5V->12V/200mA gives 11.99V, 1.2MHz.
*
* Pin order (SOT23-6):  1=SW  2=GND(VSS)  3=FB  4=EN  5=IN  6=NC
* ============================================================
* NOTE: pin order matches the netlist Proteus emits for this part: IN FB EN SW VSS
.SUBCKT MT3608 IN FB EN SW VSS
*---- internal rails / thresholds (VSS = IC ground pin)
V5     v5   VSS DC 5
V25    v25  VSS DC 2.5
V50M   v50m VSS DC 0.05
V1V    v1v  VSS DC 1
*---- UVLO and EN as a series-switch AND gate: ok = 5 V when both true
S_UV   v5   n1  IN   VSS M_UV
S_EN   n1   ok  EN   VSS M_EN
R_OK   ok   VSS 100k
*---- 0.6 V reference with soft start: ramps 0.2 V -> 0.6 V over ~1.5 ms
* (starts above the FB level at power-up so the error amp is not driven negative at the DC operating point)
V_REF  refv VSS PULSE(0.2 0.6 20u 1.5m 1n 1 2)
*---- error amplifier (gm stage) + internal compensation
* node vc is the amplifier output = comparator + input
G_EA   VSS  vc  refv FB  100u
R_O    vc   VSS 10Meg
R_C    vc   cc  20k
C_C    cc   VSS 1n
*---- clamp Vc to 0..1 V (1 V / 0.25 V/A = 4 A limit)
S_CH   vc   v1v vc   VSS M_CH
S_CL   vc   VSS VSS  vc  M_CL
*---- current sense (0.25 V per A) and slope ramp, stacked in series
V_SN   sn   VSS DC 0
H_CS   csa  VSS V_SN 0.25
V_RMP sum csa PULSE(0 0.05 2n 832n 1n 0.1n 833.33n)
*---- oscillator: clock (set) and max-duty dead window
V_CLK  clk  VSS PULSE(0 5 2n 1n 1n 40n 833.33n)
V_DMN  dmn  VSS PULSE(5 0 2n 1n 1n 748n 833.33n)
*---- PWM comparator + control logic: SR latch built from switches
* set: clock pulse charges q;  reset: any of four parallel switches discharges q
S_SET  v5   q   clk  VSS M_SET
C_Q    q    VSS 10p
* current-limit reset: only effective after the leading-edge blanking delay (bl high)
S_R1   q    mid sum  vc  M_RSA
S_R1B  mid  VSS bl   VSS M_BL
R_MID  mid  VSS 1Meg
E_QB   qb   VSS q    VSS 1
R_BL   qb   bl  3k
C_BL   bl   VSS 20p
S_R2   q    VSS dmn  VSS M_RSD
S_R3   q    VSS v50m vc  M_RSA
S_R4   q    VSS v25  ok  M_RSA
*---- power MOSFET M1 (80 mOhm) in series with the sense source
S_M    SW   sn  q    VSS M_SW
*---- misc
* small parasitic cap on SW so the node never floats in DCM (helps convergence)
C_SW   SW   VSS 30p
.MODEL M_UV  SW(Ron=1    Roff=1G    Vt=1.93 Vh=0.05)
.MODEL M_EN  SW(Ron=1    Roff=1G    Vt=0.95 Vh=0.55)
.MODEL M_CH  SW(Ron=10   Roff=1G    Vt=1.0005 Vh=0.0005)
.MODEL M_CL  SW(Ron=10   Roff=1G    Vt=0.0005 Vh=0.0005)
.MODEL M_SET SW(Ron=1k   Roff=1G    Vt=2.5  Vh=0.1)
.MODEL M_BL  SW(Ron=1 Roff=1G Vt=2.5 Vh=0.1)
.MODEL M_RSA SW(Ron=10   Roff=1G    Vt=0    Vh=0.001)
.MODEL M_RSD SW(Ron=10   Roff=1G    Vt=2.5  Vh=0.1)
.MODEL M_SW  SW(Ron=0.08 Roff=20Meg Vt=2.5  Vh=0.5)
.ENDS MT3608

* ============================================================

MT3608_test.cir

* MT3608 5V to 12V Boost Converter Testbench

* --- Power Supply and Enable ---
Vin vin 0 DC 5
Ven en  0 DC 5

* --- MT3608 IC Pin Order: IN FB EN SW VSS ---
X1 vin fb en sw 0 MT3608

* --- Boost Power Stage ---
L1 vin sw 22u
D1 sw vout D1N5819
Cout vout 0 22u
Rload vout 0 60  ; 200mA load at 12V (12V / 60 ohms)

* --- Feedback Network (12V Output, Vref = 0.6V) ---
R1 vout fb 190k
R2 fb   0  10k

* --- Diode Model ---
.model D1N5819 D (IS=1e-5 RS=0.1 N=1.05)

* ============================================================
* MT3608 Subcircuit Model
* ============================================================
.SUBCKT MT3608 IN FB EN SW VSS
V5     v5   VSS DC 5
V25    v25  VSS DC 2.5
V50M   v50m VSS DC 0.05
V1V    v1v  VSS DC 1
S_UV   v5   n1  IN   VSS M_UV
S_EN   n1   ok  EN   VSS M_EN
R_OK   ok   VSS 100k
V_REF  refv VSS PULSE(0.2 0.6 20u 1.5m 1n 1 2)
G_EA   VSS  vc  refv FB  100u
R_O    vc   VSS 10Meg
R_C    vc   cc  20k
C_C    cc   VSS 1n
S_CH   vc   v1v vc   VSS M_CH
S_CL   vc   VSS VSS  vc  M_CL
V_SN   sn   VSS DC 0
H_CS   csa  VSS V_SN 0.25
V_RMP sum csa PULSE(0 0.05 2n 832n 1n 0.1n 833.33n)
V_CLK  clk  VSS PULSE(0 5 2n 1n 1n 40n 833.33n)
V_DMN  dmn  VSS PULSE(5 0 2n 1n 1n 748n 833.33n)
S_SET  v5   q   clk  VSS M_SET
C_Q    q    VSS 10p
S_R1   q    mid sum  vc  M_RSA
S_R1B  mid  VSS bl   VSS M_BL
R_MID  mid  VSS 1Meg
E_QB   qb   VSS q    VSS 1
R_BL   qb   bl  3k
C_BL   bl   VSS 20p
S_R2   q    VSS dmn  VSS M_RSD
S_R3   q    VSS v50m vc  M_RSA
S_R4   q    VSS v25  ok  M_RSA
S_M    SW   sn  q    VSS M_SW
C_SW   SW   VSS 30p
.MODEL M_UV  SW(Ron=1    Roff=1G    Vt=1.93 Vh=0.05)
.MODEL M_EN  SW(Ron=1    Roff=1G    Vt=0.95 Vh=0.55)
.MODEL M_CH  SW(Ron=10   Roff=1G    Vt=1.0005 Vh=0.0005)
.MODEL M_CL  SW(Ron=10   Roff=1G    Vt=0.0005 Vh=0.0005)
.MODEL M_SET SW(Ron=1k   Roff=1G    Vt=2.5  Vh=0.1)
.MODEL M_BL  SW(Ron=1 Roff=1G Vt=2.5 Vh=0.1)
.MODEL M_RSA SW(Ron=10   Roff=1G    Vt=0    Vh=0.001)
.MODEL M_RSD SW(Ron=10   Roff=1G    Vt=2.5  Vh=0.1)
.MODEL M_SW  SW(Ron=0.08 Roff=20Meg Vt=2.5  Vh=0.5)
.ENDS MT3608

* --- Simulation Control Commands ---
.control
  tran 100n 3m
  run
  plot v(vout) v(sw)
.endc

.end

MT3608_test.cir Code

******
** ngspice-47 : Circuit level simulation program
** Compiled with KLU Direct Linear Solver
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2026, The ngspice team.
** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
** Creation Date: Aug 11 2026   13:49:23
******
ngspice 1 -> cd D:\ngspice
Current directory: D:\ngspice
ngspice 2 -> ngspice mt3608_test.cir
ngspice: no such command available in ngspice
ngspice 3 -> source mt3608_test.cir

Note: No compatibility mode selected!


Circuit: * mt3608 5v to 12v boost converter testbench

Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

Initial Transient Solution
--------------------------

Node                                   Voltage
----                                   -------
vin                                          5
en                                           5
x1.v5                                        5
x1.v25                                     2.5
x1.v50m                                   0.05
x1.v1v                                       1
x1.n1                                  4.99995
x1.ok                                   4.9999
x1.refv                                    0.2
x1.vc                             -3.74045e-05
fb                                    0.237415
x1.cc                             -3.74045e-05
x1.sn                                        0
x1.csa                                6.25e-08
x1.sum                                6.25e-08
x1.clk                                       0
x1.dmn                                       5
x1.q                               2.49999e-08
x1.mid                             2.49996e-08
x1.bl                              2.49999e-08
x1.qb                              2.49999e-08
sw                                           5
vout                                   4.74829
h.x1.h_cs#branch                             0
v.x1.v_sn#branch                       2.5e-07
l1#branch                            0.0791622
e.x1.e_qb#branch                             0
v.x1.v_dmn#branch                            0
v.x1.v_clk#branch                            0
v.x1.v_rmp#branch                            0
v.x1.v_ref#branch                            0
v.x1.v1v#branch                   -1.00004e-09
v.x1.v50m#branch                             0
v.x1.v25#branch                              0
v.x1.v5#branch                     -5.0004e-05
ven#branch                                   0
vin#branch                          -0.0791622


No. of Data Rows : 649376
Warning: No job (tran, ac, op etc.) defined:
run simulation not started
ngspice 4 -> 
x0 = 0.00126429, y0 = 13.6533    x1 = 0.00197857, y1 = 6.82667
dx = 0.000714286, dy = -6.82667
dy/dx = -9557.33    dx/dy = -0.000104632

x0 = 0.00157143, y0 = 10.9333

Steps to test the MT3608_test.cir spice model/library in ngspice.

To test the MT3608.LIB spice model of MT3608 boost converter IC, you can use the MT3608_test.cir test bench file provided above. You first have to place that file into a folder and use the ngspice.exe command window to cd to that folder. From there use the command source MT3608_test.cir in the command window to run the simulation.

CD to the folder where the MT3608_test.cir is located.

CD D:\ngspice

Then execute the following command:

source MT3608_test.cir

This is as shown below:

The following shows the transients graph created by the ngspice simulator:

This is a good result. The plot shows the output (yellow) and SW (red) from the mt3608_test.cir, the model is behaving like a real boost converter in that testbench.

What the plot shows

0 to 0.2 ms: the output sits at about 5 V and nothing switches. This is expected. With 5 V in, FB is 5 V / 20 = 0.25 V, which is above the starting reference of 0.2 V. The converter stays idle until the reference ramp passes 0.25 V.
0.2 to 1.6 ms: the output follows the reference ramp upward (about 5.4 V per ms), with SW switching continuously. There is no stall and no restart problem.
About 1.6 ms: one small overshoot to about 12.3 V, which is roughly 2.5%.
After about 2.2 ms: it settles at 12.0 V and stays there, with visible ripple. This is with a 200 mA (60 Ω) load, 22 µH, and your generic 1N5819.

That is the soft-start, regulation and load behavior.

If you have download seperate spice simulation model file like MT3608.LIB, it maybe easier to create the testbench file seperate from the spice model file that you want to test. This is because multiple spice model of similar function that you are looking for can be separately easily tested with separate testbench file like MT3608_testbench.cir.

To test the simultion model this way, you have to run the following:

cd D:/ngspice

source MT3608_testbench.cir

optional commands:

run

plot v(vout)

See further:

3.7V Li-Ion Battery Spice Model | Download Free

2026-10-01T13:59:45.990+05:45

Here I want to share spice simulation model for 3.7V Li-Ion rechargeable battery which you can download for free from the link below.

Li-Ion Battery Spice Model | Download Free

Below is proteus simulation video of Battery Model that uses the Prospice SPICE3F5 spice file. It illustrates how the Li-Ion rechargeable works with a LED as load connected to it. For charging +5V DC power supply is used.

This video demonstrates how a SPICE-based lithium-ion battery works. The battery is connected to a single pole, triple throw switch, allowing it to be linked to a 5-volt DC power source, connected to a load (in this case, an LED), or disconnected from both so it’s idle. When connected to the 5-volt supply, the battery charges. The SPICE model battery starts with an initial charge, which lets it power a load when the simulation begins. Charging continues until it reaches its maximum voltage of 4.2 volts; if it exceeds this, the battery stops functioning and the simulation must be restarted. Once fully charged, switching to the OFF position keeps the battery’s voltage intact. Connecting the charged battery to the LED causes the voltage to drop as the LED lights up. The LED stays on until its forward voltage of 2.2 volts is reached, begins to dim below 2.1 volts, and eventually turns off—though the battery continues discharging even after that point.

Note that the video shows simulation model simulated in proteus and that the spice simulation models (SPICE3F5, PSPICE) do not include battery animation and cannot animate like shown in the video. It is purely shown to demonstrates and validate the Li-Ion Battery spice model. Because SPICE-based models do not support Proteus visual animations, animation requires an MDF (Model Description Format) file instead. If you need fully animated battery models for your Proteus simulations, you can download them using the link below.

3.7V Rechargeable Li-Ion Battery Simulation in Proteus

If you want to build your own simulation capable proteus models or library, then see the following tutorials.

You can also use the free SPICE Converter web application on this website. This tool can convert various SPICE formats, like PSPICE ,ngspice, LTspice and the SPICE3F5 spice model, into each other. If you’re using LTSpice, simply upload the PSPICE or SPICE3F5 model, and the converter will transform it into an LTSpice-compatible file.

What are Transfer Function and Script Expression Syntax rules in Proteus

2026-09-30T10:48:23.668+05:45

Transfer function expression and Script are used in Proteus to model behavior of a component for simulation. The behavior of Primitives like current sources ACS (ACCS, AVCS), voltage sources AVS (AVCVS, ACCVS), VSWITCH etc. are modelled using Transfer function. Similarly, Script is used to define numerical values to mapped values and also write evaluation equations. So, what are the syntax rules to write the transfer function and script in Proteus Professional.

The following rules and syntax guidelines for writing transfer functions (property expressions) and writing scripts are based on the Proteus ISIS manual:

1. Rules for Transfer Function Syntax (Property Expression Evaluation)

Transfer functions/expressions are used in parameterized circuits to calculate component values dynamically.

Syntax & Functions

Expressions must use one of three specific keywords followed by a mathematical formula in parentheses:

EVAL(...) – Evaluates the expression directly without rounding.
E12(...) – Evaluates the expression and rounds the result to the nearest standard E12 series value.
E24(...) – Evaluates the expression and rounds the result to the nearest standard E24 series value.

Spacing, Operators, and Variables

Spaces allowed between operators and variables? Yes. Spaces are permitted between numbers, variables (sheet properties), and arithmetic operators (e.g., E12(1/(2*PI * IMP * FREQ)) or E24( 3 + 4 * 5 )).
Supported Operators: Mathematical expressions can include addition (+), subtraction (-), multiplication (*), division (/), and standard parentheses () for overriding operator precedence.
Unit Suffixes: Standard engineering multipliers (like k for thousands) can be attached directly to numbers inside the expression (e.g., 20k is automatically treated as 20000).
Variables: Expressions can reference named sheet properties (e.g., PI, FREQ, IMP).
Limitations:
- The evaluator only supports numeric values; text/string expressions are not allowed.
- Standard mathematical functions (such as sin, cos, sqrt) are not supported.

2. Rules for Writing User Properties and Scripts

User Property Syntax

Properties consist of a keyword and a value separated by an equals sign:

\text{KEYWORD}=\text{value}

Rule on Spaces: Keywords should generally consist of letters, numbers, and underscores only. Under no circumstances should keywords contain spaces, commas, double quotes, or equals signs.
Hidden Properties: If a property assignment is wrapped in curly brackets {...}, it will be defined but hidden from display on the schematic (e.g., {PRIMITIVE=DIGITAL}).
Property Substitution: Enclosing a property name in chevrons inside an assignment (e.g., PACKAGE=<C1_PACKAGE>) acts as a literal text substitution macro referencing a sheet property.

Script Block Syntax

Scripts are entered as multiline text blocks on a sheet.

Command Names: Script block definitions begin with an asterisk (*), such as *DEFINE.
Structure:
Plaintext
*DEFINE PI=3.142 FREQ=10k
Each assignment following the command header is written on a single line.

3.7V Rechargeable Li-Ion Battery Proteus Library | Free Download

2026-09-29T09:31:33.172+05:45

I do a lot of circuit simulation in Proteus, and the main reason is to understand how the circuit works. One of the Proteus libraries I have always wanted is a Li-Ion battery simulation part because Li-Ion batteries are so widely used in circuits these days. However, Proteus does not have an animated part for a rechargeable Li-Ion battery. I wanted a Li-Ion battery that could charge and discharge and show the state of the battery voltage through LED bars. So, I tried to make one, and this is what I wanted to write a note about here.

A rechargeable lithium-ion battery is widely used in portable electronics, IoT devices, embedded systems, and battery-powered projects. In this tutorial, we will simulate a 3.7V rechargeable Li-Ion battery in Proteus and observe how its voltage changes during charging, discharging, and idle conditions.

The simulation demonstrates how the battery can be connected either to a load for discharging or to a power source for charging.

3.7V Li-Ion Battery Simulation

The Proteus circuit uses a 3.7V rechargeable battery, a load resistor, a charging power supply, and a switch that allows us to select between three operating conditions:

Discharge: The battery supplies current to the load.
Idle: The battery is disconnected from both the load and charging source.
Charge: An external power supply charges the battery.

The battery's initial state of charge is set to approximately 20%, allowing us to observe both charging and discharging behavior during the simulation.

Starting the Simulation at 20% Charge

Initially, the switch is placed in the middle position. In this position, the battery is disconnected from both the load and the charging circuit.

When the simulation starts, the battery shows an initial charge level of approximately 20%.

This provides a convenient starting point for demonstrating how the simulated battery responds when a load or charging source is connected.

Discharging the Battery

The switch can now be moved to the discharge position, connecting the 3.7V battery to the load resistor.

Once connected, current flows from the battery through the load. The battery voltage gradually decreases as energy is delivered to the load.

In the simulation, the battery's visual charge indicator also decreases gradually, providing an easy way to observe the change in battery state.

The discharge process is relatively slow because the battery model allows parameters such as the discharge rate to be configured. A more realistic lithium-ion discharge profile can also be incorporated into the model.

As the battery becomes heavily discharged, the voltage and available current become very low. The current does not necessarily become exactly zero immediately; the simulation can take some time to reach the lower limit of the battery model.

Charging the Battery

Next, the switch is moved to the charging position.

This connects the battery to the external power supply. Current now flows into the battery, increasing its stored charge and terminal voltage.

In this particular simulation, the charging process is faster than the previous discharge process. The battery quickly approaches its fully charged condition.

Once the battery reaches the configured full-charge level, the charging current stops.

This demonstrates an important feature of the battery model: the battery does not continue accepting charging current indefinitely after reaching its defined full-charge condition.

Disconnecting the Battery

The switch can then be returned to the middle position.

The battery is now disconnected from both the load and the charging source. No significant current flows through the external circuit.

However, the energy stored in the battery remains available.

This is useful for demonstrating that the battery's charge is retained while it is not connected to a load.

Discharging After Charging

If the switch is moved back to the discharge position, the stored energy is delivered to the load again.

The battery begins discharging from its new, higher state of charge rather than from the original 20% level.

As the simulation continues, the battery voltage gradually decreases, and the charge indicator drops.

Because the battery was previously charged to a higher level, it can continue supplying the load for a longer period before reaching the lower-voltage region.

At very low voltage, the discharge current becomes small, and the battery approaches its fully discharged condition.

Recharging the Battery

The battery can then be connected to the charging source again.

The simulation demonstrates that the battery can be charged, disconnected, discharged, and recharged repeatedly.

This makes the model useful for understanding the basic behavior of a rechargeable lithium-ion battery without requiring physical battery hardware.

What This Proteus Simulation Demonstrates

The simulation provides a simple way to visualize several important battery behaviors:

Initial battery state of charge
Battery discharge through a load
Battery voltage reduction during discharge
Configurable charging and discharging rates
Battery charging from an external source
Full-charge behavior
Charge retention while disconnected
Repeated charge/discharge cycles
Lithium-ion battery discharge-profile modeling

The model can also be modified to experiment with different load resistances, charging voltages, charging rates, discharge rates, and battery profiles.

Download the 3.7V Rechargeable Li-Ion Battery Proteus Model

If you want to experiment with this rechargeable lithium-ion battery model yourself, you can download the Proteus simulation model from the link below.

Li-Ion Battery Proteus Library | Download Free

It can be useful for electronics students, hobbyists, and engineers who want to experiment with rechargeable battery behavior directly inside Proteus before building a physical circuit.

You might be interested in these free Proteus model libraries

Conclusion

This Proteus simulation provides a simple visual demonstration of how a 3.7V rechargeable Li-Ion battery behaves during charging, discharging, and idle conditions.

By changing the battery parameters and load conditions, you can further investigate different charging and discharge characteristics and develop more realistic battery models for your Proteus simulations.

How to build Ramp Signal Generator with 2N3904/2N3906 Transistors

2026-09-23T07:09:48.624+05:45

Below shows circuit diagram with animation of how to build a Ramp Signal Generator with 2N3904/2N3906 Transistors, resistors and capacitor.

The following picture shows the ramp signal waveform on digital oscilloscope.

How Ramp Signal Generator built with 2N3904/2N3906 Transistors works?

Main Equation

The capacitor charging current is governed by the constant current equation:

I_C = C1 \cdot \frac{dV_{ramp}}{dt} \implies \frac{dV_{ramp}}{dt} = \frac{I_C}{C1}

Because $I_C$ is constant, the voltage rate of change $\frac{dV_{ramp}}{dt}$ is constant, generating the linear ramp (sawtooth waveform) shown on the oscilloscope.

Oscillation Condition

Oscillation requires a loop gain $A\beta > 1$ during the discharge phase and a regenerative switching threshold defined by the Programmable Unijunction Transistor (PUT) equivalent circuit ( $Q2$ and $Q3$ ).

Specifically, $Q2$ and $Q3$ conduct and rapidly discharge $C1$ when:

V_{ramp} \ge V_G + V_{EB(Q2)}

where the gate voltage $V_G$ set by the $R4/R5$ divider is:

V_G = V_{B1} \cdot \left(\frac{R5}{R4 + R5}\right)

V_G = V_{B1} \cdot \left(\frac{R5}{R4 + R5}\right)

V_G = V_{B1} \cdot \left(\frac{R5}{R4 + R5}\right)

V_G = V_{B1} \cdot \left(\frac{R5}{R4 + R5}\right)

V_G = V_{B1} \cdot \left(\frac{R5}{R4 + R5}\right)

Circuit Operation

Linear Ramp Charging (Q1 Constant Current Source)
- PNP transistor $Q1$ , biased by the divider network $RV1$ and $R2$ , holds a fixed voltage across emitter resistor $R3$ .
- This supplies a constant charging current $I_C \approx \frac{V_{B1} - V_B - V_{EB}}{R3}$ directly into $C1$ .
- As $C1$ charges, $V_{ramp}$ rises linearly from near $0\text{ V}$ .
Triggering & Rapid Discharge (Q2/Q3 Thyristor Pair)
- $Q2$ (PNP) and $Q3$ (NPN) form a discrete SCR/PUT switch with its gate biased to $V_G = 2.5\text{ V}$ via $R4$ and $R5$ (given $R4 = R5 = 10\text{ k}\Omega$ ).
- Once $V_{ramp}$ reaches $\approx 3.1\text{ V}$ ( $V_G + 0.6\text{ V}$ ), $Q2$ 's emitter-base junction becomes forward-biased.
- Collector current from $Q2$ turns on $Q3$ , which pulls $Q2$ 's base lower, turning $Q2$ on harder (positive feedback loop).
- This instantly dumps all charge stored in $C1$ to ground, producing the sharp falling edge of the sawtooth.
Reset & Cycle Repeat
- Once $C1$ fully discharges, current drops below the hold current threshold of the $Q2/Q3$ pair, turning them off.
- $C1$ resumes charging from the constant current source $Q1$ , repeating the cycle continuously.

RAKwireless WisBlock LoraWAN IoT Solution User Guide(RAK4631+RAK19007+RAK5802)

2026-09-22T09:48:02.234+05:45

RAKwireless WisBlock is a modular hardware platform for building IoT sensor nodes. It is more industrial, modular alternative to building an IoT node from an Arduino board plus separate LoRa, RS485, sensor, and power circuits. It is built from several plug-in modules: WisBlock Base + Core + IO + Sensors

RAKwireless WisBlock RAK19007 is a WisBlock Base Board 2nd Gen that connects RAK4631 WisBlock Core, WisBlock RAK5802 RS485 ModBus IO, and WisBlock Modules as shown below.

So, one way of select the parts is as follows:

1. RAK19007(WisBlock Base Board)

2. RAK4631(WisBlock Core)

3. RAK5802(RS485 ModBus I/O module)

Various sensors like soil temperature, soil moisture, soil electrical conductivity(EC), soil pH, NPK sensor etc, can be connected to the RAK5802(RS485 ModBus I/O module). We can use sensors provided by RAKwireless WisBlock or we can use other brand sensors like:

SenseCAP S2105 / RK520-02 (FDR) - Soil Temperature/Moisture/EC sensor
Sensirion SHT35/45 + Radiation Shield RK400-01 - Air Temperature/Moisture sensor
Dual-Reed Tipping Bucket Atlas Scientific Industrial pH + EZO Modbus - Soil pH sensor
Sensirion SHT45 Industrial

All the aforementioned parts, RKwireless WisBlock and sensors(not to forget the solar power or power supply which can be connected to the RAK19007 base board) constitute IoT Sensor Node. The function of the IoT Sensor Node is to acquire signal from sensors and transit the sensor data via LoRaWAN RF signal (eg AS923 (920–923 MHz)).

The IoT sensor node is then connected to a LoRaWAN Gateway like Milesight UG65 gateway(AS923) which is illustrated before.

Because of the different frequency spectrum allocation for different countries user has to make sure the Mightsight gateway and the RAKwireless operates in the frequency band in the country where this IoT architecture solution is going to be implemented.

AMS1117 Modules Proteus Simulation Models | Free Download

2026-09-17T19:39:31.787+05:45

The AMS1117 is a highly popular series of low-dropout (LDO) linear voltage regulators, frequently sold as pre-assembled, breadboard-friendly breakout AMS1117 modules. These modules include necessary input/output filter capacitors and header pins, making them ready to use.

Here you can freely download the AMS117 (3.3V, 5V and ADJ all in single file) module model for proteus simulation from the link below.

AMS1117 Modules Proteus Simulation Models | Download Free

1. AMS1117-3.3V Module

Purpose: Steps down a higher input voltage (typically 5V to 12V) to a steady 3.3V output.
Common Use Cases: Powering 3.3V microcontrollers and wireless modules like the ESP8266, ESP32, and STM32.
Key Constraint: Because it is an LDO, dropping voltage from 12V to 3.3V at high currents creates significant heat. It runs most efficiently when powered by a 5V input.

2. AMS1117-5.0V Module

Purpose: Steps down a higher input voltage (typically 6.5V to 12V) to a fixed 5.0V output.
Common Use Cases: Powering standard Arduino Uno/Nano boards, 5V sensors, relays, and TTL logic circuits.
Key Constraint: It requires a minimum input voltage (dropout voltage) of about 6.2V to 6.5V to reliably maintain a stable 5V output.

3. AMS1117-ADJ (Adjustable) Module

Purpose: Allows the user to customize the output voltage anywhere from 1.25V to 13.8V (depending on the input voltage).
How it works: Unlike the fixed modules, the ADJ version includes an onboard potentiometer (trimmer) or a specific resistor network connected to the Adjust pin to tune the output.
Common Use Cases: Prototyping custom or non-standard voltage rails (like 1.8V or 2.5V) and variable bench power supplies.

Video Tutorial: How to Install AMS1117 Proteus Simulation Model

The following video demonstrates how to install and use the AMS1117 3.3V,5V and ADJ version of the modules in Proteus.

These free AMS1117 Proteus Simulation Models are custom-designed virtual components that allow users to test 3.3V, 5V, and adjustable breakout boards directly inside Proteus Design Suite. Because the standard Proteus library often lacks these exact pre-assembled module footprints, these free downloadable models bridge the gap between software design and physical hardware prototyping.

See other Proteus Simulation Models:

Designing a DSBSC Balanced Modulator Using 2N3904 Transistors

2026-09-15T19:15:23.308+05:45

Here I wanted to show a RF balanced modulator circuit that can produce DSB-SC AM signal at the transistor level with all the bias included. This might be helpful if you want to build your own RF balanced modulator at home. One can use readily available transistors like 2N3904 and the correct biasing is already set-up so that you don't have to worry about how to calculate those bias resistors values. This is single supply modulator which uses Gilbert mixer/modulator topology. The capacitors are mostly coupling capacitors and bypass capacitor which can be easily integrated on DIY PCB.

1. Circuit Overview

This circuit is a transistor-level balanced modulator (built using a discrete transistor topology similar to the core of an MC1496 IC). Its primary function is to multiply a Carrier Signal by a Modulating (Message) Signal to produce a Double Sideband Suppressed Carrier (DSBSC) output, commonly used in communications and RF applications.

2. Component breakdown & Subcircuits

A. Power Supply & Biasing

Power Rail: The circuit is powered by a +12V rail and referenced to GND.
Biasing Resistors:

R11, R12, R1, and R2 establish the DC operating points and collector load currents for the differential transistor stages.
R13 is tied between the common nodes GA1 and GA2 to balance the cross-coupled differential stages.
R9, R10, and R14 provide emitter degeneration/bias return paths to GND for the output differential pair (Q7, Q8) and diode network.

B. Signal Inputs & Coupling

Carrier Input (VC):

Generated by CARRIER SIGNAL.
AC-coupled via C4 (0.01µF) into the upper switching quad (Q2, Q3, etc.).
R15 (47Ω) acts as a source termination/damping resistor for the carrier input path.

Modulating Input (VS):

Generated by MODULATING SIGNAL.
AC-coupled via C1 (1µF) and C3 (1µF) into the lower differential amplifier pair.
Potentiometer RV1 (50kΩ) along with resistors R6, R7, and R8 forms an adjustable bridge/balancing network used to null out DC offsets and carrier feedthrough.

C. The Modulator Core (Transistor Array Q1 – Q8)

Transistors Q1 through Q8 (2N3904 NPNs):

Arranged in a Gilbert cell / balanced modulator configuration.
The lower transistors act as a transconductance amplifier driven by the modulating signal, while the upper cross-coupled quad (Q1-Q4) acts as a reversing switch controlled by the carrier signal. This four-quad multiplication process achieves the frequency translation (modulation).

D. Output Stage & Diode Network

Diode D1 (1N4148): Used in conjunction with biasing resistor R9 for temperature compensation or voltage clamping within the DC bias loop.
Output (VO):

AC-coupled via output capacitor C5 (1µF) to block DC bias while passing the resulting modulated RF/IF output spectrum.

Summary of Operation

During the circuit operation, the following things happens:

The Modulating Signal varies the tail currents of the differential pair.
The Carrier Signal switches the upper quad transistors on and off at the carrier frequency.
The multiplication of these two signals creates sum and difference frequencies (upper and lower sidebands) at the output VO, while suppressing the original carrier frequency component due to the symmetry of the balanced design.

How does AN612 - SSB Balanced Modulator Work

2026-09-13T17:38:01.507+05:45

AN612 Overview

AN612 is a Panasonic-manufactured IC for SSB (Single Sideband) balance modulator circuits, mainly used in CB (Citizens Band) transceivers.

Description (translated): The AN612 is a semiconductor integrated circuit designed for the balance modulator circuit of SSB-mode CB transceivers.

Features

Low operating voltage
High carrier suppression — the key job of a balanced modulator is to cancel out the carrier wave and pass only the sidebands; this IC does that well
Compact 7-lead plastic SIL package (Single In-Line)

Package

7-pin SIL (Single In-Line) plastic package, with dimensions given in mm (roughly 18.5 mm tall body, 6.3 mm max width). Pins are numbered 1–7 down one edge.

What's inside (Schematic)

The equivalent circuit is a fairly dense double-balanced modulator/mixer topology:

Q1–Q4 and diodes D1–D5 form a bias/reference network tied to pin ④ (ground) and pin ⑤
Q9–Q12 form a cross-coupled differential pair — this is the classic Gilbert-cell-style balanced mixer core that multiplies the carrier and signal inputs
Q13–Q16 and Q17/Q18 form the output buffer stage feeding pins ⑥ and ⑦
Pins ① (signal in), ② and ③ (carrier in), ④ (GND), ⑤ (bias reference), ⑥/⑦ (differential output) are the functional I/O

This is essentially a double-balanced modulator (Gilbert-cell mixer) — you feed in an audio/IF signal and an RF carrier, and it outputs the double-sideband suppressed-carrier (DSB-SC) signal, which then typically goes to a crystal/mechanical filter to produce SSB.

Absolute Maximum Ratings (Ta = 25°C)

Item	Symbol	Rating	Unit
Supply voltage	V_CC	14.4	V
Circuit voltage	V1-4	+7 / 0	V
Supply current	I_CC	15	mA
Circuit current	I5	+1 / −2	mA
Circuit current	I7	+2 / −2	mA
Power dissipation	P_D	220	mW
Operating temp	T_opr	−20 to +70	°C
Storage temp	T_stg	−55 to +125	°C

Electrical Characteristics (Ta = 25°C, V6 = 12.0V unless noted)

Item	Symbol	min	typ	max	Unit
Total circuit current	I_tot	6.5	9.5	12.5	mA
Zener voltage	V_ZD	—	6.15	—	V
Signal input terminal voltage	V1-4	—	3.1	—	V
Carrier input terminal voltage	V3-4	—	3.4	—	V
Output terminal voltage	V7-4	—	8.6	—	V
Output voltage (balanced modulator AC), at V6=9.0V	V_O(BM)	−6	−3	0	dBm
Carrier suppression ratio	SC	40	50	—	dB

The 50 dB typical carrier suppression is the headline spec — that's how cleanly it nulls out the carrier so only the sidebands come through, which is exactly what you want feeding into an SSB filter.

Test circuits

Test Circuit 1 just powers the IC (V_CC = 12V) to measure static bias voltages/currents at each pin.

Test Circuit 2 is the actual modulator test setup: two signal generators — SG1 at 10 kHz/170 mVrms (the "audio" signal) and SG2 at 11 MHz/50 mVrms (the "carrier") — are injected, VCC = 9V, and the output is measured on a spectrum analyzer. This is how they verify the −3 dBm typical output and 50 dB carrier suppression.

2N5179 Proteus Model | Download Free

2026-09-10T05:49:30.128+05:45

The 2N5179 is a popular low-noise NPN RF transistor ( $f_T \approx 1.4\text{ GHz}$ ) used in VHF/UHF amplifiers, mixers, and RF modulators.

Proteus does not include the 2N5179 in its default library out-of-the-box, but you can create a fully functional, free 2N5179 component in Proteus by attaching a SPICE .LIB definition to a generic NPN transistor. If you want to make your own transistor simulation model for proteus, see the tutorial making Transistor part with spice simulation model in Proteus

Here is how you can download for free, extract, and load your custom 2N5179 Proteus model so the simulation runs smoothly.

1.Download and Extract the ZIP File:

Prerequisite.

Download the ZIP archive containing both 2N5179.pdsprj and 2N5179.lib. Right-click the downloaded file and select Extract All... to unpack the files into a single folder on your PC.

2N5179 Proteus Model | Download Free

Verification: Open the extracted folder and confirm both 2N5179.pdsprj and 2N5179.lib are present in the same location.

2.Open via Project Directory (Portable):Option A: Recommended Method.

Double-click 2N5179.pdsprj to open the project directly inside Proteus. Because the .lib file lives in the same folder, Proteus automatically loads the SPICE parameters relative to the project.

Verification: Press F12 (or click the Play button at the bottom left) to start the simulation. The circuit should run without throwing a "Model 2N5179 not found" SPICE error.

3.Copy Library to Proteus Global Models:Option B: Permanent Installation.

To use the 2N5179 transistor in any future Proteus schematic without keeping the .lib file next to every new project:

Copy 2N5179.lib.
Paste it into your local Proteus LIBRARY directory:
- Default Path: C:\ProgramData\Labcenter Electronics\Proteus 8 Professional\LIBRARY\
  (Note: ProgramData is a hidden system folder—paste the path directly into your Windows File Explorer address bar).

Verification: Open a fresh Proteus schematic, place an NPN component, set its value to 2N5179, add the SPICE directive .INCLUDE "2N5179.lib", and run the simulation.

You can download more Proteus simulation models, electronics design software from the

See other Proteus tutorials:

Circuit Design and Analysis with ChatGPT, Claude, Gemini and Deepseek

2026-09-09T11:39:51.162+05:45

I have been using Proteus ProPilot AI assistant feature that uses Gemini API based AI in Proteus v9.1 to help me in analyzing a FM reactance modulator circuit. At first, it recognized the circuit as FM reactance modulator but later it did. I then tried to analyze the circuit with different free AI chats like ChatGPT, Gemini, Claude and Deepseek AI. Here is what I found.

The following shows the FM reactance modulator circuit schematic that I was working on.

Following shows the analog signal waveform graph and the Fourier (FFT) graph.

As you can see the analog waveform of the FM signal from this frequency modulator does not show clearly the squishing and crushing(compression and expansion) form of a typical FM signal. This could be because the frequency deviation is too small or the FM signal is simply absent! From the Fourier graph it is clear that the FM signal spectra are absent, only the modulating signal at 1khz is visible.

So how to correct this reactance modulator to build FM transmitter and what is the problem? I asked the 4 popular AI copilots- ChatGPT, Claude, Propilot Gemini, google chat Gemini and Deepseek.

1. Propilot Gemini-3.5-Flash Circuit Analysis

I have analyzed your schematic, the transient waveforms, and the Fourier analysis graph. Here is a detailed breakdown of what is happening in your circuit and why your FFT graph is not showing the expected results.

1. Is there an FM signal?

Yes, there is a frequency-modulated (FM) signal, but its carrier frequency is around 130 kHz rather than 100 kHz.

By measuring the period of the output signal VFM at different points of the modulating signal VM (which is a 1 kHz sine wave with a ±4 V amplitude), we can clearly see the frequency modulation taking place:

At t = 2.1 ms (where ≈VM +2.35 V): The period of VFM is μ7.753 s, which corresponds to a frequency of 129.0 kHz.

At t = 2.4 ms (where ≈VM +2.35 V): The period of VFM is μ7.780 s, which corresponds to a frequency of 128.5 kHz.

At t = 2.7 ms (where ≈VM -3.80 V): The period of VFM is μ7.446 s, which corresponds to a frequency of 134.3 kHz.

This clear shift in frequency in response to the modulating voltage confirms that frequency modulation is working successfully.

2. Why is the carrier frequency 130 kHz instead of 100 kHz?

The project file is named reactanceModulator90mhz.pdsprj, which suggests it was originally designed for a 90 MHz RF carrier (FM broadcast band) for building a two transistor FM transmitter. However, the component values in the schematic have been scaled up to bring the carrier frequency down to the 100 kHz range to make the SPICE simulation run much faster.

The resonant tank is formed around Q1 using L2 (1 mH) and C1 (1 nF). The theoretical resonant frequency of this combination is:

When accounting for the loading of the reactance stage Q2 and the coupling capacitor C3 (10 nF), the actual center frequency shifts down to approximately 130 kHz.

Additionally, the output Pi-filter formed by L1 (1 mH), C5 (4.7 nF), and C6 (4.7 nF) has a cutoff frequency of:

Because the carrier frequency (130 kHz) is above the filter's cutoff frequency (73.4 kHz), the output signal VFM is attenuated down to about ≈0.5 V peak.

3. Why does the FFT / Fourier Graph show almost nothing?

If you look at your FOURIER ANALYSIS graph, the vertical axis scale is extremely small (maximum value of only μ300 V), and the spectrum is completely flat.

This is caused by a simulation window mismatch:

Oscillator Startup Delay: In the ANALOGUE ANALYSIS transient graph, the oscillator takes about μ3.5 s to start up. Before this time, the output is completely flat (0 V).

Fourier Window: If your Fourier graph's fundamental frequency is set to 100 kHz, Proteus performs the Fourier transform over a time window of only μ10 s starting at t = 0 s. Because the oscillator is off or just starting up during this window, the Fourier transform analyzes a mostly flat signal, resulting in a near-zero spectrum.

How to fix the FFT Graph:

To display the FM spectrum clearly around 130 kHz, you need to configure the Fourier graph to analyze a stable portion of the simulation:

Right-click on the FOURIER ANALYSIS graph and select Edit Properties.

Change the Start Time to a point after the oscillator has fully stabilized (e.g., 1ms or 2ms).

Set the Stop Time or Time Span to cover at least one or two full cycles of the modulating signal (e.g., from 2ms to 4ms) to capture the sidebands.

Press Spacebar to re-simulate the graph. You should then see a clear peak around 130 kHz with its corresponding FM sidebands!

2. Google Gemini Circuit Analysis:

Based on the schematic and simulation graphs provided, here is the analysis of your FM reactance modulator circuit and the reasons why it is failing to produce an FM signal.

1. Why There is No FM Signal (The Main Flaws)

Missing RF Phase-Shift Feedback: For a transistor to act as a reactance modulator for FM transmitter, it must inject a current into the oscillator tank that is $90^\circ$ out of phase with the tank voltage. This requires an RC or CR phase-shifting network connected from the oscillator tank (Q2) back to the base of the modulator transistor (Q1). In your circuit, the base of Q1 has no RF connection to the oscillator tank; it only receives the audio input ($V_{in}$). Without this RF feedback, Q1 cannot simulate a variable capacitor or inductor.
Incorrect Role of $C_1$: Capacitor $C_1$ is connected directly between the collector and base of Q1. This creates a Miller effect (increasing the input capacitance to audio) rather than acting as the required RF phase-shifter from the tank circuit.
Massive Impedance Mismatch ($R_1 = 220\text{ k}\Omega$): The input resistor $R_1$ is far too large. Combined with the $10\text{ k}\Omega$ and $27\text{ k}\Omega$ biasing resistors, the audio modulating signal is heavily attenuated before it ever reaches the base of Q1.

2. Waveform & FFT Graph Interpretation

The Waveform Graph (Top Right): You can see the low-frequency audio signal (the large green sine wave) and the high-frequency carrier (the blue band) simply superimposed on top of each other. This is linear mixing/additive leakage, not frequency modulation. The carrier frequency remains completely constant and is not stretching or compressing with the audio wave.
The FFT Graph (Bottom Right): The FFT plot is completely blank (flat line at zero). This usually happens in SPICE simulators if:
- The simulation time step ($\Delta t$) is too large to resolve the high-frequency carrier.
- The FFT window parameters (start time/end time) were set to a region before the oscillator stabilized, or the sampling rate is mismatched.

3. Component & Circuit Analysis

Oscillator Section (Q2): This is configured as a Colpitts-style oscillator using $L_1$, $C_5$, and $C_6$. The base bias network ($R_4 = 10\text{ k}\Omega$, $R_5 = 4.7\text{ k}\Omega$) correctly provides about 1.60V to the base, which is standard for a 5V supply line.
Modulator Section (Q1): Q1 has a radio-frequency choke ($L_2 = 100\,\mu\text{H}$) at its collector to block RF from the power supply rail. However, because its collector is decoupled from the tank via a simple $10\text{ nF}$ capacitor ($C_3$) without a loop back to its own base, it is behaving like a standard audio amplifier rather than a reactance modulator.

How to Fix the Circuit

To turn Q1 into a functioning reactance modulator:

Remove $C_1$ from between the collector and base of Q1.
Add a Phase-Shift Network: Connect a small capacitor (e.g., $10\text{ pF}$ to $47\text{ pF}$) from the oscillator tank node to the base of Q1. Then, ensure there is a resistor (or the internal resistance of the base network) from the base of Q1 to ground. This creates the $90^\circ$ phase shift needed to make Q1 "look" like a capacitor to the tank circuit.
Reduce $R_1$: Drop $R_1$ from $220\text{ k}\Omega$ down to around $1\text{ k}\Omega$ to $10\text{ k}\Omega$ so your modulating audio signal actually has enough amplitude to shift the bias of Q1.

Would you like help redrawing or calculating the exact RC phase-shift component values needed to match the resonant frequency of your Colpitts oscillator ($L_1$, $C_5$, $C_6$)?

3. Claude AI Circuit Analysis:

Circuit Topology

This is a two‑transistor "indirect FM" generator:

Q1 (2N3904) — the reactance modulator. Audio Vm is AC‑coupled through R1 (220k)/C2 (100nF) into Q1's base bias node (R3=27k from Vcc, R2=10k to ground, emitter degeneration R6=470Ω bypassed by C4=100nF). C1 (1nF) runs from that base node to Q1's collector — this is the classic 90°‑phase‑shift feedback element that makes Q1's collector look like a variable reactance whose value tracks the audio signal. L2 (1mH) is Q1's collector RF choke to Vcc. The resulting variable reactance is AC‑coupled via C3 (10nF) onto Q2's collector node.
Q2 (2N3904) — a common‑base Colpitts oscillator. Base is bootstrapped to AC ground by CC1 (10nF) and biased by R4 (10k)/R5 (4.7k). Collector load is RC (2.2k); the tank (L1=1mH with C5=C6=4.7nF forming the capacitive divider) hangs off the collector through CC2 (10nF). The divider's center tap feeds back to the emitter through CB (1µF) with RE (560Ω) setting emitter bias — a textbook Colpitts feedback loop, and the output is tapped right at the tank.

So the intent is clear: Q1's audio‑dependent reactance loads Q2's tank and pulls its resonant frequency up and down = FM.

The actual problem: the tank isn't resonant anywhere near RF

Compute the oscillator's tank frequency from the values on the schematic:

C5, C6 in series: Ceq = 4.7nF/2 = 2.35 nF
f = 1/(2π√(L1·Ceq)) = 1/(2π√(1mH × 2.35nF)) ≈ 103.8 kHz

That's not FM broadcast (88–108 MHz) — it's off by roughly a factor of 1000. The values used (L1 = 1 mH, C5/C6 = 4.7 nF) belong in an audio/low‑IF LC filter, not a VHF tank. For a real ~100 MHz Colpitts you'd want something like L1 ≈ 0.1–0.2 µH with C5/C6 ≈ 15–30 pF each — inductance and capacitance both need to drop by ~3–4 orders of magnitude.

This single scaling error explains everything you're seeing:

Scope: the dashed cyan trace (CH A, audio Vm) is a normal low‑frequency sine. The solid-looking blue band (CH B, output) isn't a clean RF carrier — it's an oscillation running around ~100 kHz that's too fast for the timebase you're viewing it at, so it renders as a filled block instead of resolved cycles. It also sits close enough to the audio rate that the "carrier" and "modulation" aren't well separated — you don't get the ~1000:1 carrier‑to‑audio ratio real FM needs.
FFT: all the energy is bunched right at the left edge (near 0 Hz) with nothing across the rest of the spectrum. If the FFT's frequency axis is scaled for an expected 88–108 MHz signal, a real oscillation at ~104 kHz is indistinguishable from DC on that scale — which is exactly the flat trace with one spike at the origin that you're getting. There's no carrier peak and no FM sidebands because there's no RF carrier to have sidebands.

Secondary issues (worth fixing once the frequency is right)

L2/C1 form their own resonance. L2 (1mH) with C1 (1nF) resonate at ≈159 kHz — close to Q2's tank frequency. L2 is meant to be a simple non‑resonant RF choke for Q1's collector; instead you have two similar‑frequency LC networks that will pull/interact rather than giving one clean carrier.
Reactance‑modulator phase‑shift ratio. The "reactance" behavior of Q1 depends on Xc1 (from C1) being much larger or smaller than the base‑bias resistance it works against (R3‖R2 ≈ 7.3k). At the current (wrong) frequency, Xc1 ≈ 1.5k — same order of magnitude as 7.3k, not a clean 90° condition, so Q1 would present a mixed resistive/reactive load (amplitude modulation and damping) rather than a pure reactance, even before the tank issue is fixed.
Coupling point. C3 injects Q1's reactance at Q2's collector rather than directly across the L1/C5/C6 tank. It still works because CC2's impedance is low relative to RC, but injecting directly across the tank nodes gives stronger, more predictable frequency deviation once you're actually tuned to RF.

Bottom line: the topology (reactance modulator driving a Colpitts oscillator for FM transmitter design) is correct in concept, but the tank component values are sized for a ~100 kHz circuit, not a ~100 MHz one. The scope and FFT are correctly showing you a low‑frequency oscillation near DC — there is no missing "FM" behavior, there's simply no RF carrier being generated. Rescale L1/C5/C6 (and ideally L2, C1) into the µH/pF range for the target FM frequency and you should see a real carrier appear in the FFT with audio‑rate sidebands moving as Vm changes.

4. ChatGPT AI Circuit Analysis

Yes. From the schematic and the two graphs, the main problem is not simply the waveform display. The circuit as drawn does not have the elements/configuration required to produce a useful FM carrier.

I can identify several major issues.

1. The LC values are far too large for an FM circuit

The most important values I see are approximately:

Component	Value shown	Problem
L1	1 mH	Far too large for an FM carrier tank
C5	4.7 µF	Far too large
C6	4.7 µF	Far too large
L2	1 mH	Extremely large as an RF choke/tank component
C1	1 µF	Far too large
C3	10 µF	Far too large for RF coupling
CC1	10 µF	Far too large for RF coupling
CC2	10 µF	Far too large for RF coupling
C4	100 µF	Suitable as a low-frequency bypass, but not RF
C8	1 µF	Much too large for RF bypass
Q1/Q2	2N3904	Can work at VHF, although not ideal for a high-quality FM oscillator

For an FM transmitter around, say, 100 MHz, the tank components would normally be in the approximate range of:

L: tens to hundreds of nH
C: a few pF to perhaps a few tens of pF

—not mH and µF.

2. Your output LC network resonates at only about 3.3 kHz

This is a very important clue.

You have:

L1 = 1 mH
C5 = 4.7 µF
C6 = 4.7 µF

C5 and C6 appear effectively in series across L1, giving approximately:

C_{eq}=\frac{4.7\times4.7}{4.7+4.7}\approx2.35\ \mu F

Therefore,

f_0=\frac{1}{2\pi\sqrt{LC}}

gives approximately:

f_0=\frac{1}{2\pi\sqrt{1mH\times2.35\mu F}}

\boxed{f_0\approx3.28\ kHz}

That's audio frequency, not FM RF.

So your output tank is not capable of producing a 88–108 MHz FM carrier.

For example, if you wanted approximately 100 MHz with a 100 nH inductor:

C=\frac{1}{(2\pi f)^2L}

which gives approximately:

\boxed{C\approx25\ pF}

That's the scale of components you need.

3. There is no actual variable-reactance element

This is probably the biggest conceptual problem.

For frequency modulation, a reactance-modulated FM oscillator needs something whose effective reactance changes with the modulation voltage.

For example:

Audio signal
     │
     ▼
┌──────────────┐
│ Varactor     │
│ diode        │
└──────┬───────┘
       │ changes C
       ▼
 RF LC resonator
       │
       ▼
 FM carrier

Your schematic contains:

Q1 = 2N3904
Q2 = 2N3904
L1
L2
capacitors

but I don't see a varactor diode or equivalent transistor reactance network.

Consequently, there is nothing that makes the LC resonant frequency move according to the audio signal.

A fixed LC circuit gives approximately:

f_c=\frac{1}{2\pi\sqrt{LC}}

For FM you need:

f(t)=\frac{1}{2\pi\sqrt{L C(t)}}

where:

C(t)=C_0+\Delta C(t)

Your circuit doesn't appear to provide that $C(t)$ .

4. Q2 is not configured as an RF oscillator

This is another serious issue.

Look at Q2.

Its base is biased through:

R4 = 10 kΩ
R5 = 4.7 kΩ

but CC1 = 10 µF is connected from the base node to ground.

At RF frequencies, 10 µF is effectively an extremely low impedance.

So the base is essentially AC-grounded.

More importantly, the signal from Q1 through C3 appears to be connected to the collector side of Q2, rather than providing the appropriate RF feedback to its base.

An oscillator requires positive feedback.

Something conceptually like:

             ┌─────────────┐
             │             │
             ▼             │
       ┌──────────┐        │
       │ transistor│───────┘
       └────┬─────┘   feedback
            │
            ▼
          LC tank

Your Q2 stage doesn't provide an obvious RF feedback path capable of sustaining oscillation.

Therefore, Q2 is not going to spontaneously generate a stable FM carrier just because L1/C5/C6 are connected at its output.

5. C5/C6 = 4.7 µF completely destroys the intended RF tank

This deserves special attention.

For an RF oscillator, capacitors such as:

4.7\mu F

are enormously larger than what you'd normally use in a 100-MHz resonator.

At 100 MHz, the reactance of 4.7 µF would theoretically be:

X_C=\frac{1}{2\pi fC}

X_C\approx0.00034\Omega

So at RF, it behaves almost like a short circuit.

Your C5/C6 therefore do not behave as useful RF tuning capacitors.

6. The coupling capacitors are also wrong for RF

You have:

C3 = 10 µF
CC1 = 10 µF
CC2 = 10 µF

These are commonly useful for audio-frequency coupling, but not as the primary coupling components in a 100-MHz circuit.

For an FM RF circuit, you would typically see values such as:

1 pF
2.2 pF
5 pF
10 pF
22 pF
47 pF
100 pF

depending on the circuit.

7. Your waveform is therefore not the expected FM waveform

The upper graph appears to show a dense/high-frequency-looking signal, but it does not show the characteristic FM behavior clearly.

Remember that FM doesn't necessarily look dramatically different in the time domain.

For:

v(t)=A_c\cos(2\pi f_ct+\beta\sin(2\pi f_mt))

the amplitude should remain approximately constant.

What changes is the instantaneous frequency.

So for a low-frequency modulating sine wave, you should see:

low frequency       high frequency       low frequency

  /\    /\             /\/\/\/\/\/\         /\    /\
 /  \  /  \           /\/\/\/\/\/\/\       /  \  /  \

The carrier cycles become closer together and farther apart while their amplitude remains approximately constant.

Your graph doesn't demonstrate that clearly.

8. The FFT should show an FM carrier and sidebands

This is another way to diagnose the problem.

Suppose you use:

f_c=100\ MHz

and:

f_m=1\ kHz

For FM, the spectrum should contain:

f_c

and sidebands at:

f_c\pm f_m

f_c\pm2f_m

f_c\pm3f_m

etc.

So conceptually:

Amplitude

             │
             │       │
             │   │   │   │
             │   │   │   │
─────────────┴───┴───┴───┴────────── frequency
             fc- fm fc fc+fm

With larger modulation index, more sidebands become significant.

Your FFT appears essentially flat/empty, which strongly suggests that there isn't a meaningful RF oscillation at the output—or the FFT/probe/time-window settings aren't appropriate.

9. There is another major issue: your simulation timestep/sample rate

If you're trying to simulate a 100-MHz FM signal in Proteus, you need to be careful with the simulation settings.

For example:

f_c=100MHz

means:

T_c=10ns

You need several simulation points within each 10-ns carrier cycle.

If your transient simulation timestep is, for example:

1\mu s

you cannot see a 100-MHz carrier correctly.

The simulator would effectively skip over the RF waveform.

For an RF simulation, use an appropriately small timestep, potentially in the sub-nanosecond to few-nanosecond range, depending on the frequency and what you're trying to resolve.

10. There may also be a unit-entry problem in Proteus

This is actually something I would check first.

If your intention was something like:

L1 = 100 nH
C5 = 4.7 pF
C6 = 4.7 pF

but you entered:

L1 = 1 mH
C5 = 4.7 µF
C6 = 4.7 µF

then the resulting circuit is off by many orders of magnitude.

Likewise, perhaps you intended:

C5 = 4.7 pF
C6 = 4.7 pF
CC2 = 10 pF
CC1 = 10 pF
C3 = 10 pF

rather than µF.

The circuit should look more like this conceptually

For a proper reactance-modulated FM oscillator:

                    +VCC
                      │
                      │
                  RF oscillator
                      │
                 ┌────┴────┐
                 │         │
                 │    LC tank
                 │         │
                 └────┬────┘
                      │
                    RF OUT
                      │
                     ...
                      
              Variable capacitance
                      │
                ┌─────┴─────┐
Audio ─────────►│  Varactor │
                │   diode   │
                └───────────┘
                      ▲
                      │
                 reverse bias

The audio voltage changes the varactor capacitance:

V_m(t)\rightarrow C(t)

which changes:

f_c(t)=\frac{1}{2\pi\sqrt{L C(t)}}

and therefore produces FM.

What I would change in your particular circuit

If your objective is something like 100 MHz FM, I would not try to fix this by merely changing one component.

I'd redesign the RF section.

Replace the output tank

Instead of:

L1 = 1 mH
C5 = 4.7 µF
C6 = 4.7 µF

use something approximately in the range of:

L1 ≈ 100 nH
C ≈ 20–30 pF

for a 100-MHz region, then provide a varactor diode for modulation/tuning.

Replace RF coupling capacitors

Instead of:

10 µF

use values in the pF range where appropriate.

Add the actual reactance modulator

For example:

                 +Vbias
                   │
                   R
                   │
Audio ── C ────────┤
                   │
                 Varactor
                   │
                   ├──── LC oscillator
                   │
                  GND

The exact topology matters, so I wouldn't simply insert a varactor randomly.

Most important diagnosis

I'd rank the problems like this:

Problem	Severity
No clear variable-reactance/varactor element	🔴 Critical
No proper RF oscillator/feedback around Q2	🔴 Critical
L1 = 1 mH	🔴 Critical
C5/C6 = 4.7 µF	🔴 Critical
10 µF RF coupling capacitors	🔴 Critical
Output LC resonates around 3.3 kHz	🔴 Critical
Q1/Q2 topology doesn't implement a clear FM modulator	🔴 Critical
Transient timestep may be inappropriate for RF	🟠 Important
FFT configuration/window may be inappropriate	🟠 Important

So the absence of FM is expected from the circuit as currently drawn. The fundamental problem is that it is neither a correctly tuned RF oscillator nor a complete reactance-modulated FM oscillator.

If you give me the intended carrier frequency (e.g. 10.7 MHz, 88–108 MHz, or 100 MHz) and the input modulation frequency/amplitude, I can redesign this exact two-transistor circuit with specific L, C, resistor and varactor values that you can enter directly into Proteus.

5. DeepSeek AI Circuit Analysis

Based on the component list you provided, this appears to be a **reactance modulator** circuit, which is a type of FM (Frequency Modulation) generator often used in low-power FM transmitters. The circuit typically uses a transistor (Q1, 2N3904 FM transmitter) as a variable reactance (capacitance or inductance) that changes the frequency of an oscillator (Q2, 2N3904) in response to an audio signal.

However, you're reporting **no FM signal** at the output. Let's analyze the circuit step by step and identify why it might not be producing FM.

## 🔍 Circuit Analysis (Based on Typical Reactance Modulator Topology)

### **Key Components:**

- **Q1 (2N3904):** Acts as the **reactance device** – its base-emitter capacitance varies with the audio signal applied to its base (via R1, C1). This changes the effective capacitance in the oscillator tank circuit.

- **Q2 (2N3904):** Acts as the **oscillator** (likely a Colpitts or Hartley type). Its tank circuit includes L1 and various capacitors (C2–C6 etc.). The reactance from Q1 is injected into this tank to modulate the frequency.

- **L1 (1mH):** Main inductor in the oscillator tank.

- **R1 (220k), R2 (1k), R3 (2k), R4 (10k):** Bias resistors for Q1 and Q2.

- **C1 (10nF):** Coupling capacitor for audio input.

- **C2 (2nF), C3–C6 (10nF, 4.7nF):** Part of tank and coupling networks.

- **C7–C426 (all 10nF):** Likely **decoupling capacitors** or part of a very long delay line or filter bank – this is highly unusual and suggests either a **schematic error**, **simulation artifact**, or **excessive bypassing** that kills the RF signal.

## ⚠️ Why No FM Signal?

### 1. **Excessive Decoupling Capacitors (C7–C426)**

- There are **hundreds of 10nF capacitors** connected to the power supply or ground. This massive capacitance will **short out any high-frequency (RF) signal** to ground, killing oscillation.

- In practice, you only need a few decoupling caps (e.g., 10nF + 100µF). This many caps will create a **low-pass filter** with an extremely low cutoff frequency, effectively **killing the RF carrier**.

### 2. **Missing Biasing or Incorrect Component Values**

- Q2 (oscillator) may not be properly biased. Check:

- **R2 (1k)** – is it providing base current?

- **R3 (2k), R4 (10k)** – correct voltage divider?

- Q2 needs to be in active region for oscillation.

- **L1 (1mH)** is large – typical FM tank inductors are in the **nH to µH** range for 88–108 MHz. 1mH would resonate at very low frequencies (kHz), not FM band.

### 3. **No Antenna or Output Coupling**

- There’s no output coupling capacitor or antenna shown – the signal might be trapped inside the tank.

### 4. **Q1 Reactance Not Tuned Properly**

- Q1’s collector is likely connected to the tank via a small capacitor. If that coupling is missing or too weak, modulation won't occur.

### 5. **Power Supply Issues**

- If VCC is not clean or too low, oscillation won't start.

## 📊 Waveform & FFT (Expected vs. Observed)

| Parameter | Expected | Observed (if no FM) |

|-----------|----------|----------------------|

| **Waveform** | Sine wave with frequency deviation | **Flat line (no oscillation)** or random noise |

| **FFT** | Single carrier peak with sidebands | **No peak** or only DC/low-frequency noise |

If you see **no peak** in FFT above noise floor, the oscillator is **not running**.

## 🛠️ Troubleshooting Steps

1. **Remove all unnecessary capacitors (C7–C426)** – keep only one or two 10nF for decoupling.

2. **Check Q2 biasing** – ensure Vce ≈ ½ VCC and base-emitter is forward-biased (~0.7V).

3. **Verify tank resonance** – using L=1mH, C≈10nF gives:

f = \frac{1}{2\pi\sqrt{LC}} \approx \frac{1}{2\pi\sqrt{1e-3 \cdot 10e-9}} \approx 50.3 \text{ kHz}

That’s **not FM band** – you’ll get audio-range oscillation, not RF.

→ Use L ≈ 100nH and C ≈ 10pF for ~100 MHz.

4. **Inject a small audio signal** (e.g., 1kHz, 100mV) at C1 and check if frequency shifts.

5. **Probe the collector of Q2** with an oscilloscope – you should see a sine wave if oscillating.

## ✅ Final Verdict

**No FM signal** is likely due to:

- **Massive decoupling (hundreds of 10nF caps)** killing RF.

- **Wrong L1 value** (1mH too large for FM).

- **Missing or incorrect biasing** for Q2.

- **No output stage** to radiate or couple the signal.

**Fix:**

- Reduce caps to a few 10nF + 1x 100µF for power.

- Change L1 to ~100nH.

- Adjust tank capacitors (C2–C6) for ~100 MHz.

- Add a 10pF coupling cap from Q2 collector to an antenna.

After these changes, you should see a clean FM signal in both time-domain (sine wave) and frequency-domain (carrier with sidebands).

Comparison & Conclusion

Propilot Gemini and Google Gemini completely misunderstood the circuit. This is an FM reactance modulator circuit but these AI did not identify the circuit correctly. So there rest of the answer would be wrong anyway.
Claude AI, ChatGPT AI and DeepSeek AI all identified the circuit as Reactance Modulator
Claude AI correctly pointed out that this reactance modulator is designed for 100kHz and not an FM circuit.
ChatGPT incorrectly calculated the carrier frequency given the component values.
DeepSeek incorrectly specified capacitors and resistors names and values that are not used as the reason for the circuit failure

Insofar, because of the trunked reasoning, I continued my questions to Claude AI and ChatGPT. The Gemini AI was giving initial complete incorrect answer, so I did not brother to further analyze the circuit. Similarly, I did not analyze the circui further with DeepSeek AI because although it identified the circuit correctly as FM reactance modulator, it did not correctly identify the components their names and values. I think this is because DeepSeek underlying image/video analysis is not good.

Why Your Reactance FM Modulator Is Clipping

2026-09-08T11:47:46.420+05:45

This note on FM reactance modulator explains how severe output distortion—manifested as clipping, spurious amplitude modulation, and low-frequency breakthrough—occurs in an FM generator when the transistor in the reactance modulator stage is driven into hard cutoff.

The following shows circuit diagram of Frequency Modulator using Reactance Modulator for FM signal generation.

The reactance modulator is formed by the transistor Q1 with its biasing resistors(R3,R2,R6), RF choke(L2) and the feedback coupling capacitor (C1). The transistor Q2, along with its biasing resistors(R4,RC,R5,RE), bypass capacitor CB, LC tank circuit(L1,C5,C6) and coupling capacitors(CC1,CC2) forms the Colpitts oscillator.

Sometimes one can get distorted FM signal as shown below.

Instead of producing clean Frequency Modulation, the FM modulator circuit is now suffering from severe clipping, spurious Amplitude Modulation (AM), and low-frequency breakthrough.

Such distortion at the output of the transistor like in this reactance modulator circuit, is due to mismatch of the signal waveform amplitude entering the base of the transistor. If we assume the transistor to be a water flow controller, the base water hose pipe size must fit the water flow controller (the transistor) input port pipe size, otherwise the water (the input signal) cannot flow properly into the water flow controller and there will be distortion. Something like this:

The picture illustrates severe clipping by transistor with water pipe size mismatch example.

So, the reason for the severe clipping is that the transistor Q1 is driven into hard cutoff. The dc bias voltage at the Q1 base is,

$V_B = V_{CC} \frac{R_2}{R_2+R_3} = 5V \frac{10k\Omega}{10k\Omega+27k \Omega} \approx 1.35V$

The ac input impedance into the base of Q1 is,

$R_{in,ac}=R_2 || R_3 \approx 7.3k \Omega$

and so, the ac voltage peak into the base is,

$V_{in,ac} = V_p \frac{R_{bin}}{R_{bin}+R_1} = 2V \frac{7.3k \Omega}{{7.3k \Omega}+10k \Omega} \approx 0.84V$

The ac signal is riding on the dc bias voltage so, the voltage peak of the input signal during the +ve half cycle is

$V_+ = V_B + V_{in,ac} = 1.35V + 0.84V /approx 2.19V $

and during the -ve half cycle it is,

$V_- = V_B + V_{in,ac} = 1.35V - 0.84V /approx 0.51V $

So, the ac signal input into the base swings between 0.51V and 2.19V. However, when a signal is fed into the base of the transistor, to turn it on, the signal amplitude must be higher than the Vbe(0.65V). If it is less than that, the signal will be cutoff. Similarly, when the base is at 2.19V, the Q1 is driven into high conduction generating high emitter current.

The Solution

The solution to this problem is hinted by the water pipe size mismatch example. That is like resizing the water pipe, we need to increase the size of the resistor R1 to attenuate the input signal before it reaches the base, and/or, decrease the amplitude of the input signal.

So here, the input signal amplitude was set to 200mV from 2V and the R1 value changed to 10k to 100k.

The resulting output fm signal waveform after the changes is shown below.

Summary

Here it is explained how severe output distortion—manifested as clipping, spurious amplitude modulation, and low-frequency breakthrough—occurs in an FM generator when the transistor $Q_1$ in the reactance modulator stage is driven into hard cutoff. Calculated via DC biasing ( $V_B \approx 1.35\text{ V}$ ) and AC input impedance voltage division ( $V_{in,ac} \approx 0.84\text{ V}$ ), the input signal at $Q_1$ 's base swings between $0.51\text{ V}$ and $2.19\text{ V}$ . Because the negative peak drops below the transistor's base-emitter threshold ( $V_{BE} = 0.65\text{ V}$ ), the device periodically cuts off and heavily distorts the modulating drive to the $Q_2$ Colpitts oscillator stage. Analogous to fixing an oversized water hose that overwhelms a flow controller, this waveform distortion is resolved by attenuating the modulating signal—specifically by reducing the input voltage amplitude from $2\text{ V}$ down to $200\text{ mV}$ and increasing the input series resistor $R_1$ from $10\text{ k}\Omega$ to $100\text{ k}\Omega$ to yield a clean FM output.

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