FPGA Projects, Verilog Projects, VHDL Projects - FPGA4student.com

FPGA Course: Learn the Fundamentals of VHDL and FPGA

noreply@blogger.com (FPGA4student) — Sat, 3 Oct 2020 21:13:00 -0700

This article introduces one of the most popular FPGA courses on Udemy. The FPGA course, which taught students how to start with VHDL and FPGA programming, got 3934 students with 4.4 rating.

The instructor agreed to provide FPGA4student readers with the opportunity to get the course with 91% OFF. The coupon link to the course is HERE.

The course details are described below.

How will you learn?

You will learn by doing the real programming. All the code and examples are explained in tutoring videos. After you adjust the existing code or you create your own, you will run simulations to verify it. If you are interested to run your code on a real hardware (not required, but much more fun), we recommend Altera or Xilinx boards.

What will you learn?

Learn the Essentials of VHDL and FPGA Development is course that will teach you the fundamentals and basics of VHDL design. In this course you will be working through various projects that will require you to go through the entire FPGA development process. You will be guided through the coding of the actual VHDL to the synthesis using either Xilinx’s development tool, Vivado or Altera development tool Quartus. There are 8 projects in this course:

Buttons & LEDs
A project that is designed to teach students the very basics of VHDL as well as how to make specific pins on an FPGA inputs (buttons) and outputs (LEDs).
Blinky LEDs
Students will learn how to create a counter in VHDL in order to simultaneously turn multiple LEDs on and off in unison.
LED Brightness
This project will have students create 3 VHDL designs, a PWM design to control the brightness of the LEDs, a counter to vary the duty cycle, and a top level design to pull everything together.
UART Demonstration
Students will be introduced to softcore processors and use them to display a “Hello World” message on a serial port terminal.
UART I/O
In the project students will build upon the ability to transmit messages using the softcore processor to read messages. Students will learn how to interpret messages coming from the computer to the FPGA in order to read the status of various peripherals on the board.
AD Processing
This project will have students perform an analog to digital conversion. As an example, they sense the temperature.
SPI Interface (Arty A7 Only)
In this project students will learn how to work with SPI interface. They will load existing designs onto the external flash memory chip to have the FPGA configure itself through the SPI interface.
I2C Interface (DE10 Nano Only)
In this project students will learn how to work with I2C. They will load an embedded Linux operating system onto the DE10 Nano development board. They will then run a program that interfaces with the onboard accelerometer to display the g forces the sensor reads.

All of the required background and knowledge to complete each project will be explained prior to completing the project. There are demonstration videos and walk-throughs for each project so that you can have a deep understanding of how the project works.

About the instructor

Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involve circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout, and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.

Recommended FPGA projects for students:

1. What is FPGA? How does FPGA work?

2. Basys 3 FPGA OV7670 Camera

3. How to load text file or image into FPGA

4. Image processing on FPGA using Verilog

5. License Plate Recognition on FPGA

6. Alarm Clock on FPGA using Verilog

7. Digital Clock on FPGA using VHDL

8. Simple Verilog code for debouncing buttons on FPGA

9. Traffic Light Controller on FPGA

10. Car Parking System on FPGA in Verilog

11. VHDL code for comparator on FPGA

12. Verilog code for Multiplier on FPGA

13. N-bit Ring Counter in VHDL on FPGA

14. Verilog implementation of Microcontroller on FPGA

15. Verilog Carry Look Ahead Multiplier on FPGA

16. VHDL Matrix Multiplication on FPGA Xilinx

17. Fixed Point Matrix Multiplication on FPGA using Verilog

18. Verilog Divider on FPGA

19. VHDL code for Microcontroller on FPGA

20. VHDL code for FIR Filter on FPGA

21. Verilog code for Digital logic components on FPGA

22. Delay Timer Implementation on FPGA using Verilog

23. Single-Cycle MIPS processor on FPGA using Verilog

24. FIFO Verilog Implementation on FPGA

25. FIFO VHDL Implementation on FPGA

26. Verilog D Flip Flop on FPGA

27. Comparator Design on FPGA using Verilog

28. D Flip Flop on FPGA using VHDL

29. Full Adder Design on FPGA using Verilog

30. Full Adder Design on FPGA using VHDL

31. Counters on FPGA with Verilog Testbench

32. RISC Processor Design on FPGA using Verilog

33. Verilog test bench for inout ports on FPGA

34. PWM Generator on FPGA using VHDL

35. Tic Tac Toe Game on FPGA using Verilog

36. VHDL code for ALU on FPGA

37. Verilog code for ALU on FPGA

38. Counter design on FPGA with VHDL test bench

39. Pipelined MIPS Processor on FPGA in Verilog (Part-1)

40. Pipelined MIPS Processor on FPGA in Verilog (Part-2)

41. Pipelined MIPS Processor on FPGA in Verilog (Part-3)

42. Verilog Decoder on FPGA

43. Verilog Multiplexers on FPGA

44. N-bit Adder Design on FPGA in Verilog

45. VHDL ALU on FPGA using N-bit Verilog Adder

46. VHDL Shifter on FPGA

47. Lookup Table VHDL example code on FPGA

48. Coprocessor VHDL Implementation on FPGA

49. Affordable Xilinx FPGA boards for beginners
50. Affordable Altera FPGA boards for beginners

Digilent Inc to become Hardware Sponsor for FPGA4Student

noreply@blogger.com (FPGA4student) — Thu, 2 Jul 2020 18:59:00 -0700

July 3, 2020: Digilent Inc to become a Hardware sponsor for FPGA4student from FPGA boards to a wide range of FPGA peripherals such as camera, sensors, wifi module, bluetooth module, etc.

This is obviously a great news for students and professionals around the world visiting FPGA4student on daily basic. On behalf of our visitors and followers, FPGA4Student would like to send millions thanks to Digilent Inc for the generous support.

Digilent Nexys A7 FPGA Board

FPGA4student also would like to thank Digilent for the great suggestion over the use of two FPGA boards (Nexys A7 and Arty S7). These two boards perfectly fit our upcoming projects, which are dedicated for students and FPGA hobbyists. Following are the Digilent hardware that would be using along with these FPGA boards for our upcoming projects also listed below.

1. Pmod DA2: Two 12-bit D/A Outputs

2. Pmod OLEDrgb: 96 x 64 RGB OLED Display with 16-bit color resolution

3. Arty S7 Pmod Pack (Pmod VGA: Video Graphics Array, Pmod MIC3: MEMS Microphone,Pmod AMP2: Audio Amplifier)

4. Nexys 4 DDR Pmod Pack

5. Zybo Pmod Pack (Pmod ALS: Light Sensor, Pmod BT2: Bluetooth , Pmod RTC: Real-time Clock, PMOD-TMP3 Temperature Sensor)

6. Pmod WiFi: WiFi Interface 802.11g

7. Pcam 5C: 5 MP Fixed Focus Color Camera Module

FPGA Interfacing with PCamera 5C

Following are exciting FPGA projects to be published on FPGA4STUDENT:

1. OLED RGB Interfacing with FPGA

2. On-Screen Display with DDR Memory Controller + VGA Controller

3. Computer interfacing with FPGA via USB-UART interface

4. Signal Generator with FPGA (+DAC PMOD and displaying waveform on PC via USB Oscilloscope)

5. Ethernet Interfacing with FPGA

6. Microphone interfacing with FPGA (Audio Output)

7. Real-Time Clock/Calendar with FPGA (displaying on OLED/VGA)

8. Temperature Sensor Interfacing with FPGA (displaying on OLED)

9. Bluetooth Interfacing with FPGA

10. Light Detection with FPGA

11. I2C interface on FPGA

12. SPI interface on FPGA

13. HDMI Interfacing with FPGA

14. Wifi Interfacing with FPGA

15. Real Time Image processing on FPGA (with Digilent PCAM 5C)

Recommended FPGA projects for students:

1. What is FPGA? How does FPGA work?

2. Basys 3 FPGA OV7670 Camera

3. How to load text file or image into FPGA

4. Image processing on FPGA using Verilog

5. License Plate Recognition on FPGA

6. Alarm Clock on FPGA using Verilog

7. Digital Clock on FPGA using VHDL

8. Simple Verilog code for debouncing buttons on FPGA

9. Traffic Light Controller on FPGA

10. Car Parking System on FPGA in Verilog

11. VHDL code for comparator on FPGA

12. Verilog code for Multiplier on FPGA

13. N-bit Ring Counter in VHDL on FPGA

14. Verilog implementation of Microcontroller on FPGA

15. Verilog Carry Look Ahead Multiplier on FPGA

16. VHDL Matrix Multiplication on FPGA Xilinx

17. Fixed Point Matrix Multiplication on FPGA using Verilog

18. Verilog Divider on FPGA

19. VHDL code for Microcontroller on FPGA

20. VHDL code for FIR Filter on FPGA

21. Verilog code for Digital logic components on FPGA

22. Delay Timer Implementation on FPGA using Verilog

23. Single-Cycle MIPS processor on FPGA using Verilog

24. FIFO Verilog Implementation on FPGA

25. FIFO VHDL Implementation on FPGA

26. Verilog D Flip Flop on FPGA

27. Comparator Design on FPGA using Verilog

28. D Flip Flop on FPGA using VHDL

29. Full Adder Design on FPGA using Verilog

30. Full Adder Design on FPGA using VHDL

31. Counters on FPGA with Verilog Testbench

32. RISC Processor Design on FPGA using Verilog

33. Verilog test bench for inout ports on FPGA

34. PWM Generator on FPGA using VHDL

35. Tic Tac Toe Game on FPGA using Verilog

36. VHDL code for ALU on FPGA

37. Verilog code for ALU on FPGA

38. Counter design on FPGA with VHDL test bench

39. Pipelined MIPS Processor on FPGA in Verilog (Part-1)

40. Pipelined MIPS Processor on FPGA in Verilog (Part-2)

41. Pipelined MIPS Processor on FPGA in Verilog (Part-3)

42. Verilog Decoder on FPGA

43. Verilog Multiplexers on FPGA

44. N-bit Adder Design on FPGA in Verilog

45. VHDL ALU on FPGA using N-bit Verilog Adder

46. VHDL Shifter on FPGA

47. Lookup Table VHDL example code on FPGA

48. Coprocessor VHDL Implementation on FPGA

49. Affordable Xilinx FPGA boards for beginners

50. Affordable Altera FPGA boards for beginners

How to Read Image in VHDL

noreply@blogger.com (FPGA4student) — Sat, 11 Aug 2018 08:44:00 -0700

In DSP projects, it is required to read image files and load them into VHDL implementations of the image processing algorithms for functional simulations. In addition, there are many cases that images are loaded into FPGAs during synthesis for onboard verifications.

This VHDL tutorial is to tell you how to read images in VHDL in a way that the images can be loaded into the block memory of the FPGA during synthesis or simulation.

Since VHDL cannot read image files such as BMP, JPG, TIF, etc. directly, images are required to be converted into binary text files so that VHDL can read them using the TEXTIO VHDL package.

To convert images into binary text files, you can use Matlab or C. Once the image binary text files are ready, you can copy it to the project folder.

Then, in VHDL, the binary text files can be read using the following function:

-- by FPGA4student.com
impure function init_mem(mif_file_name : in string) return mem_type is
    file mif_file : text open read_mode is mif_file_name;
    variable mif_line : line;
    variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
    variable temp_mem : mem_type;
begin
    for i in mem_type'range loop
        readline(mif_file, mif_line);
        read(mif_line, temp_bv);
        temp_mem(i) := to_stdlogicvector(temp_bv);
    end loop;
    return temp_mem;
end function;

It is noted that you need to include the TEXTIO package in the VHDL code by "use std.textio.all". Then, to load the image data in the binary text files into the block memory, you just need to add the following line to the VHDL code:

signal ram_block: mem_type := init_mem(IMAGE_FILE_NAME);

Now, let's do an example code for reading images in VHDL. For simplicity, let's assume that the following is the content of the binary text file that we converted from a gray image.

Then, save the image binary file as "IMAGE_FILE.MIF" and put it to the project folder. Now, write a VHDL code to read this image binary text file and initialize it into a block memory during synthesis or simulation.

Below is the VHDL code for reading image files into FPGA. The code is synthesizable.

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use std.textio.all;
-- FPGA4student.com: FPGA/Verilog/VHDL projects for students
-- VHDL tutorial: How to Read images in VHDL
entity read_image_VHDL is
  generic (
    ADDR_WIDTH     : integer := 4;        
    DATA_WIDTH     : integer := 8;
    IMAGE_SIZE  : integer := 15;
    IMAGE_FILE_NAME : string :="IMAGE_FILE.MIF"
  );
  port(
    clock: IN STD_LOGIC;
    data: IN std_logic_vector ((DATA_WIDTH-1) DOWNTO 0);
    rdaddress: IN STD_logic_vector((ADDR_WIDTH-1) downto 0);
    wraddress: IN STD_logic_vector((ADDR_WIDTH-1) downto 0);
    we: IN STD_LOGIC;
    re: IN STD_LOGIC;
    q: OUT std_logic_vector ((DATA_WIDTH-1) DOWNTO 0));
end read_image_VHDL;

architecture behavioral of read_image_VHDL is

TYPE mem_type IS ARRAY(0 TO IMAGE_SIZE) OF std_logic_vector((DATA_WIDTH-1) DOWNTO 0);

impure function init_mem(mif_file_name : in string) return mem_type is
    file mif_file : text open read_mode is mif_file_name;
    variable mif_line : line;
    variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
    variable temp_mem : mem_type;
begin
    for i in mem_type'range loop
        readline(mif_file, mif_line);
        read(mif_line, temp_bv);
        temp_mem(i) := to_stdlogicvector(temp_bv);
    end loop;
    return temp_mem;
end function;

signal ram_block: mem_type := init_mem(IMAGE_FILE_NAME);
signal read_address_reg: std_logic_vector((ADDR_WIDTH-1) downto 0) := (others=>'0');
  
begin
  process (clock)
  begin
   if (rising_edge(clock)) then
      if (we = '1') then
        ram_block(to_integer(unsigned(wraddress))) <= data;
      end if;
      if (re = '1') then
        q <= ram_block(to_integer(unsigned(rdaddress)));
      end if;
    end if;
  end process;

end behavioral;

To verify if the image binary text file is read properly, let's write a testbench to test it in a simulation. Following is the testbench for reading image in VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- FPGA4student.com: FPGA/Verilog/VHDL projects for students
-- VHDL tutorial: How to Read images in VHDL
ENTITY tb_read_image_vhdl IS
END tb_read_image_vhdl;
ARCHITECTURE behavior OF tb_read_image_vhdl IS 
    COMPONENT read_image_VHDL
    PORT(
         clock : IN  std_logic;
         data : IN  std_logic_vector(7 downto 0);
         rdaddress : IN  std_logic_vector(3 downto 0);
         wraddress : IN  std_logic_vector(3 downto 0);
         we : IN  std_logic;
         re : IN  std_logic;
         q : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal clock : std_logic := '0';
   signal data : std_logic_vector(7 downto 0) := (others => '0');
   signal rdaddress : std_logic_vector(3 downto 0) := (others => '0');
   signal wraddress : std_logic_vector(3 downto 0) := (others => '0');
   signal we : std_logic := '0';
   signal re : std_logic := '0';
  --Outputs
   signal q : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clock_period : time := 10 ns;

   signal i: integer;
BEGIN
 -- Read image in VHDL
   uut: read_image_VHDL PORT MAP (
          clock => clock,
          data => data,
          rdaddress => rdaddress,
          wraddress => wraddress,
          we => we,
          re => re,
          q => q
        );

   -- Clock process definitions
   clock_process :process
   begin
  clock <= '0';
  wait for clock_period/2;
  clock <= '1';
  wait for clock_period/2;
   end process;
   -- Stimulus process
   stim_proc: process
   begin  
                data <= x"00";
  rdaddress <= x"0";
  wraddress <= x"0";
  we <= '0';
  re <= '0';
                wait for 100 ns;
  re <= '1';  
  for i in 0 to 15 loop
  rdaddress <= std_logic_vector(to_unsigned(i, 4));
  wait for 20 ns;
  end loop;
      wait;
   end process;

END;

Now, it's time to run the simulation and check if the image binary text file is loaded correctly into the block memory. The following figure shows that the image was read properly into the block RAM of FPGAs.

To read the image data in the block memory for testing your image processing design, just provide read addresses and enable memory reading. The following simulation waveform shows the image data in the binary text file is read out correctly at the output port of the block RAM.

For reading images in Verilog, the tutorial can be found here.
Recommended VHDL projects:
1. What is an FPGA? How VHDL works on FPGA
2. VHDL code for FIFO memory
3. VHDL code for FIR Filter
4. VHDL code for 8-bit Microcontroller
5. VHDL code for Matrix Multiplication
6. VHDL code for Switch Tail Ring Counter
7. VHDL code for digital alarm clock on FPGA
8. VHDL code for 8-bit Comparator
9. How to load a text file into FPGA using VHDL
10. VHDL code for D Flip Flop
11. VHDL code for Full Adder
12. PWM Generator in VHDL with Variable Duty Cycle
13. VHDL code for ALU
14. VHDL code for counters with testbench
15. VHDL code for 16-bit ALU
16. Shifter Design in VHDL
17. Nonlinear Lookup Table Implementation in VHDL
18. Cryptographic Coprocessor Design in VHDL

19. Verilog vs VHDL: Explain by Examples

20. VHDL Code for Clock Divider on FPGA

21. Generate clock enable signal in VHDL
22. VHDL code for debouncing buttons on FPGA

23. VHDL code for Traffic light controller
24. VHDL code for a simple 2-bit comparator
25. VHDL code for a single-port RAM
26. VHDL code for Car Parking System using FSM
27. VHDL coding vs Software Programming

28. VHDL code for MIPS Processor
29. VHDL code for Moore FSM Sequence Detector
30. VHDL code for Seven-Segment Display on Basys 3 FPGA
31. VHDL code for OV7670 Camera on Basys 3 FPGA